GB2336075B - Method and apparatus for the phase alignment of data in high-speed parallel data buses using adjustable high frequency sampling clocks - Google Patents

Method and apparatus for the phase alignment of data in high-speed parallel data buses using adjustable high frequency sampling clocks

Info

Publication number
GB2336075B
GB2336075B GB9806748A GB9806748A GB2336075B GB 2336075 B GB2336075 B GB 2336075B GB 9806748 A GB9806748 A GB 9806748A GB 9806748 A GB9806748 A GB 9806748A GB 2336075 B GB2336075 B GB 2336075B
Authority
GB
United Kingdom
Prior art keywords
phase alignment
frequency sampling
speed parallel
high frequency
sampling clocks
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
GB9806748A
Other versions
GB9806748D0 (en
GB2336075A (en
Inventor
Con Cremin
J Noel Butler
Anne Geraldine O'connell
Una Quinlan
Eugene O'neill
Tadhg Creedon
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
3Com Technologies Ltd
Original Assignee
3Com Technologies Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 3Com Technologies Ltd filed Critical 3Com Technologies Ltd
Priority to GB9806748A priority Critical patent/GB2336075B/en
Publication of GB9806748D0 publication Critical patent/GB9806748D0/en
Publication of GB2336075A publication Critical patent/GB2336075A/en
Application granted granted Critical
Publication of GB2336075B publication Critical patent/GB2336075B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
    • H04L7/046—Speed or phase control by synchronisation signals using special codes as synchronising signal using a dotting sequence
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/14—Channel dividing arrangements, i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
GB9806748A 1998-03-30 1998-03-30 Method and apparatus for the phase alignment of data in high-speed parallel data buses using adjustable high frequency sampling clocks Expired - Fee Related GB2336075B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB9806748A GB2336075B (en) 1998-03-30 1998-03-30 Method and apparatus for the phase alignment of data in high-speed parallel data buses using adjustable high frequency sampling clocks

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB9806748A GB2336075B (en) 1998-03-30 1998-03-30 Method and apparatus for the phase alignment of data in high-speed parallel data buses using adjustable high frequency sampling clocks

Publications (3)

Publication Number Publication Date
GB9806748D0 GB9806748D0 (en) 1998-05-27
GB2336075A GB2336075A (en) 1999-10-06
GB2336075B true GB2336075B (en) 2002-12-04

Family

ID=10829505

Family Applications (1)

Application Number Title Priority Date Filing Date
GB9806748A Expired - Fee Related GB2336075B (en) 1998-03-30 1998-03-30 Method and apparatus for the phase alignment of data in high-speed parallel data buses using adjustable high frequency sampling clocks

Country Status (1)

Country Link
GB (1) GB2336075B (en)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB9810843D0 (en) 1998-05-21 1998-07-22 3Com Technologies Ltd Method for storing data in network devices
GB2343092B (en) 1998-10-22 2003-05-14 3Com Technologies Ltd Framing codes for high-speed parallel data buses
GB9824594D0 (en) 1998-11-11 1999-01-06 3Com Technologies Ltd Modifying tag fields in ethernet data packets
GB2344030B (en) 1998-11-17 2003-06-04 3Com Technologies Ltd Credit-based scheme for high performance communication between devices in a packet-based communication system
EP1277316A2 (en) 2000-04-28 2003-01-22 Broadcom Corporation Methods and systems for adaptive receiver equalization
GB2362289B (en) * 2000-05-10 2002-04-03 3Com Corp Distributed multicast routing in packet-based communication network devices
GB2362473B (en) 2000-05-18 2002-08-21 3Com Corp On-chip detector of clock glitches
US20030070033A9 (en) * 2001-02-09 2003-04-10 Zabinski Patrick Joseph Parallel and point-to-point data bus architecture
GB2397966B (en) 2003-02-01 2005-04-20 3Com Corp High-speed switch architecture
GB2401279B (en) 2003-04-29 2005-06-01 3Com Corp Switch module architecture
WO2008153652A2 (en) * 2007-05-25 2008-12-18 Rambus Inc. Reference clock and command word alignment
US9001842B2 (en) 2012-06-26 2015-04-07 International Business Machines Corporation Parallel receiver interface with receiver redundancy
US8861513B2 (en) 2012-06-26 2014-10-14 International Business Machines Corporation Fault tolerant parallel receiver interface with receiver redundancy

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0153107A2 (en) * 1984-02-10 1985-08-28 Prime Computer, Inc. Clock recovery apparatus and method for a ring-type data communications network
US4780889A (en) * 1986-09-17 1988-10-25 Alcatel Cit Device for relocking one or a number of identical or submultiple binary data signal trains on a synchronous reference clock signal
EP0424741A2 (en) * 1989-10-23 1991-05-02 National Semiconductor Corporation Method and structure for digital phase synchronization

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0153107A2 (en) * 1984-02-10 1985-08-28 Prime Computer, Inc. Clock recovery apparatus and method for a ring-type data communications network
US4780889A (en) * 1986-09-17 1988-10-25 Alcatel Cit Device for relocking one or a number of identical or submultiple binary data signal trains on a synchronous reference clock signal
EP0424741A2 (en) * 1989-10-23 1991-05-02 National Semiconductor Corporation Method and structure for digital phase synchronization

Also Published As

Publication number Publication date
GB9806748D0 (en) 1998-05-27
GB2336075A (en) 1999-10-06

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Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee

Effective date: 20030330