GB2336074B - Method and apparatus for the phase alignment of data in high-speed parallel data buses using a multi-phase low frequency sampling clock - Google Patents
Method and apparatus for the phase alignment of data in high-speed parallel data buses using a multi-phase low frequency sampling clockInfo
- Publication number
- GB2336074B GB2336074B GB9806747A GB9806747A GB2336074B GB 2336074 B GB2336074 B GB 2336074B GB 9806747 A GB9806747 A GB 9806747A GB 9806747 A GB9806747 A GB 9806747A GB 2336074 B GB2336074 B GB 2336074B
- Authority
- GB
- United Kingdom
- Prior art keywords
- phase
- low frequency
- sampling clock
- frequency sampling
- speed parallel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
- H04L7/0338—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals the correction of the phase error being performed by a feed forward loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M9/00—Parallel/series conversion or vice versa
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/14—Channel dividing arrangements, i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/04—Speed or phase control by synchronisation signals
- H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
- H04L7/046—Speed or phase control by synchronisation signals using special codes as synchronising signal using a dotting sequence
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB9806747A GB2336074B (en) | 1998-03-30 | 1998-03-30 | Method and apparatus for the phase alignment of data in high-speed parallel data buses using a multi-phase low frequency sampling clock |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB9806747A GB2336074B (en) | 1998-03-30 | 1998-03-30 | Method and apparatus for the phase alignment of data in high-speed parallel data buses using a multi-phase low frequency sampling clock |
Publications (3)
Publication Number | Publication Date |
---|---|
GB9806747D0 GB9806747D0 (en) | 1998-05-27 |
GB2336074A GB2336074A (en) | 1999-10-06 |
GB2336074B true GB2336074B (en) | 2002-12-04 |
Family
ID=10829504
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB9806747A Expired - Fee Related GB2336074B (en) | 1998-03-30 | 1998-03-30 | Method and apparatus for the phase alignment of data in high-speed parallel data buses using a multi-phase low frequency sampling clock |
Country Status (1)
Country | Link |
---|---|
GB (1) | GB2336074B (en) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2343092B (en) | 1998-10-22 | 2003-05-14 | 3Com Technologies Ltd | Framing codes for high-speed parallel data buses |
EP1277316A2 (en) | 2000-04-28 | 2003-01-22 | Broadcom Corporation | Methods and systems for adaptive receiver equalization |
JP4425426B2 (en) * | 2000-05-11 | 2010-03-03 | Necエレクトロニクス株式会社 | Oversampling clock recovery circuit |
GB2362473B (en) | 2000-05-18 | 2002-08-21 | 3Com Corp | On-chip detector of clock glitches |
DE10245210B4 (en) * | 2002-09-27 | 2009-05-28 | Infineon Technologies Ag | demultiplexer |
GB2397966B (en) | 2003-02-01 | 2005-04-20 | 3Com Corp | High-speed switch architecture |
GB2401279B (en) | 2003-04-29 | 2005-06-01 | 3Com Corp | Switch module architecture |
CN103930014B (en) * | 2012-05-24 | 2016-03-23 | 奥林巴斯株式会社 | Image data reception device and image data transmission system |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0153107A2 (en) * | 1984-02-10 | 1985-08-28 | Prime Computer, Inc. | Clock recovery apparatus and method for a ring-type data communications network |
US4780889A (en) * | 1986-09-17 | 1988-10-25 | Alcatel Cit | Device for relocking one or a number of identical or submultiple binary data signal trains on a synchronous reference clock signal |
EP0424741A2 (en) * | 1989-10-23 | 1991-05-02 | National Semiconductor Corporation | Method and structure for digital phase synchronization |
-
1998
- 1998-03-30 GB GB9806747A patent/GB2336074B/en not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0153107A2 (en) * | 1984-02-10 | 1985-08-28 | Prime Computer, Inc. | Clock recovery apparatus and method for a ring-type data communications network |
US4780889A (en) * | 1986-09-17 | 1988-10-25 | Alcatel Cit | Device for relocking one or a number of identical or submultiple binary data signal trains on a synchronous reference clock signal |
EP0424741A2 (en) * | 1989-10-23 | 1991-05-02 | National Semiconductor Corporation | Method and structure for digital phase synchronization |
Also Published As
Publication number | Publication date |
---|---|
GB9806747D0 (en) | 1998-05-27 |
GB2336074A (en) | 1999-10-06 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 20030330 |