JP3125348B2 - Parallel bit synchronization method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel bit synchronization system, and more particularly to a parallel bit synchronization system for a device for transmitting parallel data at high speed.

[0002]

2. Description of the Related Art In parallel data transmission in a conventional device of this type, the operation speed is relatively low, the propagation delay time by a transmission medium is sufficiently short with respect to a clock cycle, the phase synchronization of bits, the phase synchronization between bits, and the like. The shift did not matter. However, in recent years, devices requiring high-speed data transmission, such as broadband switching devices, have increased, and in such devices, phase synchronization between data and clock and synchronization between parallel bits are important issues. For example, 622 Mb
When transmitting ps data in 8-bit parallel,
Although parallel transmission of about 80 Mbps is required, the data width is only about 12 ns, which is about the same as the propagation delay time of the transmission medium. Therefore, phase adjustment of data and a clock signal for latching the data and phase adjustment between parallel bits are performed. Is required. Conventionally, such adjustment has to be performed manually.

[0003]

In this prior art,
There is a problem in that the phase synchronization between data and clock and the phase synchronization between parallel bits cannot be adjusted in a complicated device requiring high-speed data transmission that cannot be manually adjusted.

[0004]

According to the parallel bit synchronization method of the present invention, a transmitting side of a device for transferring parallel data of 2 bits or more includes a training data generating circuit for generating training data, and a normal mode based on a training mode signal. A selector circuit for switching between an output of the training data generating circuit and a receiving side of the device, which operates in a training mode to automatically synchronize the phase of the bit data and change the phase synchronization state when the training mode is released. A bit phase synchronizing circuit to be held, which is connected to the bit phase synchronizing circuit, operates during the training mode, automatically synchronizes the phase between each bit data, and holds the inter-bit phase synchronizing state when the training mode is released. And a phase synchronization circuit between bits.

The training data generation circuit may be a 2-bit or more parallel data generation circuit having a function of generating an identification pattern for identifying a data unit for each bit of the parallel data.

[0006]

Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention.

The transmitting section 1 has an n-bit training data generating circuit 10 and a selector 20 for selecting n-bit normal data 100 and an output signal 300 of the training data generating circuit 10 according to a training mode signal 200. Further, the receiving unit 2 having the output signal 400 of the selector 20 as an input includes the bit phase synchronizing circuit 30 and the inter-bit phase synchronizing circuit 40 having the output signal 500 as an input.

In the training data generation circuit 10, the bit phase synchronization circuit 30 can compare and adjust the phase of each bit of the arrival data and the clock, and the inter-bit phase synchronization circuit 40 can compare and adjust the phase between each bit. In order to be able to do so, a bit sequence that changes and a bit sequence that can identify the boundaries of data are generated.

In the training mode, the training data 300 is input to the bit phase synchronization circuit 30 of the receiver 2 via the selector 20. Bit phase synchronization circuit 30
Then, the phase relationship between the data and the clock is adjusted for each parallel bit so that the data can be latched without error.
Further, the output of the bit phase synchronization circuit 30 is input to the inter-bit phase synchronization circuit 40. In the inter-bit phase synchronizing circuit 40, a data delimiter (for example,
Frame, etc.), and the amount of delay of each bit is adjusted so that the time position of the delimiter between the bits, that is, the phase matches. The bit phase synchronization circuit 30 and the inter-bit phase synchronization circuit 40 store each phase adjustment information at the end of the training mode, for example, in the register
Since it holds with like, also for normal data 100 received through the selector 20 during the training mode is released, it can be normally bit phase synchronization and inter-bit phase synchronization.

[0010]

As described above, according to the present invention, the normal data and the training data are switched and output from the transmitting side by the training mode signal, and the receiving side operates in the training mode to automatically change the phase of the bit data. Synchronize and maintain the phase synchronization state when training mode is released, and operate in training mode to automatically synchronize the phase between each bit data and maintain the phase synchronization state between bits when training mode is released. Therefore, in the high-speed parallel data transmission, the phase of the data and the clock and the phase between the parallel bits can be automatically adjusted, so that there is an effect that the manual adjustment becomes unnecessary.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 transmission unit 2 reception unit 10 training data generation circuit 20 selector 30 bit phase synchronization circuit 40 bit phase synchronization circuit 100 normal data 200 training mode signal

Claims (1)

(57) [Claims] 1. A transmitting side of a device for transferring parallel data of 2 bits or more transmits each bit of arriving data and a clock of a clock.
Performs phase synchronization and phase comparison adjustment between parallel bits.
Training data generation circuit that generates training data that is a bit sequence for training, and training mode that synchronizes data and clock phases
Trained mode signal for designating a certain normal data at the output of the training data generating circuit
A selector circuit for switching and outputting training data, and the receiving side of the device operates in a training mode,
A bit phase synchronization circuit that synchronizes the phase of data and clock for each parallel bit and maintains a phase synchronization state when the training mode is released, and is connected to the bit phase synchronization circuit and operates during the training mode , Frame for each bit of
Detects and matches the time position of the frame between each bit.
Sea urchin, and a bit between the phase synchronizing circuit for holding the inter-bit phase synchronization state when the training mode is released while adjusting the amount of delay of each bit, the training mode by the training mode signal
Upon release, normal data transmission / reception via the selector
Parallel bit synchronization method and performing.