KR880001023B1 - Self-clocking data transmission system - Google Patents

Abstract

The system has a data transmitter coupled to receivers by true and complement data signal lines. The receivers may also send return data signals to the transmitter in sychronism with received signals. The transmitter uses the four possible binary states represented by the two bits of the true and complement lines. A transition is made to a zero state represented as 01, or to an one state as 10, when data is to be transmitted. The data receivers detect the bit state to recover a bit clock signal, and the one and zero status to recover and NRZ data signal.

Description

Self-Clocking Data Transmission System

1 is a schematic configuration diagram of a self-cloaking data transmission system embodying the present invention.

2 is a schematic structural diagram of a data transmitter for a data transmission system of FIG.

3 is a schematic structural diagram of a data receiver for a data transmission system of FIG.

4 is a waveform diagram showing a binary state used for encoding a data signal transmitted between a data transmitter and a receiver in the data transmission system of FIG.

FIG. 5 is a waveform diagram showing waveforms for various blocks of the data receiver in FIG.

6 is a schematic structural diagram of another data receiver for a data transmission system of FIG.

FIG. 7 is a waveform diagram showing waveforms of various blocks of the data transmission receiver shown in FIG.

* Explanation of symbols for main parts of the drawings

101: data transmitter 102: data receiver

103: data receiver 104: data receiver

201: Latch 203: Inverting gate

208: flip-flop 211: register

312: register 313: latch

320: register 321: decoder

322 gate

The present invention relates generally to data transmission systems, and more particularly to a self clocked transmission system of digital data signals.

One conventional self clocking data transfer technique, commonly referred to as "pola return to zero," uses various voltage levels in the bit intervals that protect the data signal. For example, the constant voltage level for the reference voltage level indicates a state of "1" and the negative voltage level for the reference voltage level indicates a state of "0". Another technique, commonly referred to as Manchester coding, puts a transition during each bit interval so that the direction of the transition determines the binary state of the bit. For example, a positive transition '1' bit during the bit interval and a negative transition represent a "0" bit.

In any case, in order to immediately receive a data signal transmitted by this conventional scheme, it is essential that the timing relationship between successive bits of the data signal be maintained accurately at the data transmitter and recognized immediately at the data receiver. Moreover, the correct reception at the data receiver depends on the reproduction of the clock signal and the precise definition of the bit spacing. Therefore, transmission systems using this reference scheme are very sensitive to speed and timing variations in the transmission of data signals. Also, in order to compensate for such changes, the receiving device must have expensive and complicated circuits.

It is therefore an object of the present invention to provide an improved method and apparatus for a self-clocking data transmission system that controls wide variations in the speed and timing of transmission.

It is an object of the present invention to provide an improved self-clocking data transmission system for bidirectional data transmission between one data transmitter and a plurality of data receivers.

It is an object of the present invention to provide an improved self-clocking data transmission system for data transmission between a plurality of addressable data receivers that are separated from one data transmitter.

It is an object of the present invention to provide an improved self clocking data transmission system for data transmission between a data transmitter and a plurality of data receivers for which data is desired to be transmitted from the transmitter.

In implementing the present invention a data signal having a plurality of binary bits is transmitted over two signal lines between one data transmitter and one or more four data receivers of a self-clocking transmission system. Two signal lines are available in two 2-bit states, and data signals are transmitted using them. According to the data transmission scheme of the present invention, the first state of the signal line is prepared before and after the data signal and the second state of the signal line which comes before the third state of the signal line for each bit of the data signal has a state of '1'. The fourth state of the signal line, generated for the bit and coming before the third state of the signal line, is generated for the bit with a state of "0." As a result, the transmitted data signal is not only self-clocking but independent of the transmission frequency. Therefore, it is possible to adjust a wide change in the time interval of successive bit intervals.

In the data transmission system of the present invention, a data transmitter is connected to one or more data receivers by two signal lines, and the data signal is transmitted through the above-described data transmission scheme. The data transmitter has circuitry that generates a state of two bits of signal lines for each bit of the data signal to be transmitted. The receiver has circuitry that responds to a third state of the signal line to prepare a clock signal. The receiver also has circuitry to store a state of "1" in response to the second state and a state of "0" in response to the fourth state. Therefore, the output signal of the first storage circuit reflects the binary state of consecutive bits of the transmitted data signal and is stored in the second storage circuit according to the clock signal. At the end of the transmission, the second storage circuit retains the received data signal. The data signal in the second storage circuit can be used to perform some proper function in the data receiver.

In FIG. 1, a block diagram of a self clocking data transmission system embodying the present invention is depicted. The data transmitter 101 is connected to the data receivers 102, 103 and 104 by two signal lines labeled "true data" and "complement data". The data receivers 102, 102 and 104 transmit a return data signal to the data transmitter, where the data receivers 103 and 104 use a shared signal line, referred to as "return data," and the data receiver 102 uses separate signal lines. The return data signal sent by the data receivers 102 to 104 via the return data signal line is transmitted in synchronization with the data signal received from the data transmitter 101 via the true data and complement data signal lines. Since data transmission is self-clocking and independent of the transmission frequency, the transmitter and receiver can be close together or far apart.

According to the present invention, data is transmitted from the data transmitter 101 to the data signalers 102 to 104 using four two bit binary states by tying true data and complement data signal lines together. For example, referring to FIG. 4, the first two bit binary states are called "word states " 4, where both the true data and completion data signal lines are in the state " 1 ". The word state 401 is prepared for the true data and completion data signal lines when data is not being transferred. When the data signal is transmitted, it transitions from the word state 401 to the zero state 402 represented by the binary state " 1 " or the original state 1 represented by the binary state " 10 ". In the word state, the completion data signal line is "1" and the true data signal line is "1". For every subsequent bit of the data signal to be transmitted, it first transitions to bit state 403, which is indicated by binary state " 0 " before transitioning to state 404 or zero state 402 of the original 1. The two bit binary states of the true data and complement data signal lines are shown in Table 1 below.

TABLE 1

Moreover, the transition between states 401 and 404 in Figure 4 is such that at any given time, the binary state of only one signal line is changed. Transition between original (1) state 404 and zero state 402 of transition between word state 401 and bit state 403 is not allowed. This is because the true data and complement data signal lines must be changed at the same time. By limiting the binary state of only one signal line at any time between the binary states 401 to 404, the effect of distortion and timing changes is minimized. In addition, as shown in the state diagram of FIG. 4, by transmitting the data signal, transmission via the true data and the complement data signal lines becomes self-clocked with each other and is independent of the transmission frequency. The time intervals between each state transition shown in FIG. 4 need not be the same and can vary dynamically. Therefore, according to the data transmission scheme of the present invention, the data transmission frequency may be completely asynchronous with an irregularly changing time interval between successive state transitions.

In summary, when data is not being transmitted, the true data and complement data signal lines are in the word state 401 (see waveform in FIG. 5). During the transmission of one data signal, two state transitions occur in each bit. It depends on the binary state of the bit to be transmitted for the first bit of the data signal and transitions from word state 401 to original state 404 or zero state 402. The state transitions to the next bit state 403. It then transitions to the original state 404 or zero state 402 for each successive bit of data honeymoon and then back to bit state 403. Bit state 403 may be used to generate a clock signal at the data receiver because a transition is made to bit state 403 for each bit of the transmitted data signal. The last state transition is made back from the original state 404 or zero state 402 to the word state 401 for the last bit of the data signal. After the last bit of the data signal has been transmitted, it returns to word state 402 to indicate that a complete data signal has been transmitted to data receivers 102-104.

Another signal line, called a return data signal line, may be provided to provide bidirectional transmission of the data signal between the data transmitter 101 and the data receivers 102-104 in FIG. This signal line brings a non-return-to-zero (NRZ) coded data signal from the data receiver. The data receiver may transmit the return data signal using a clock signal generated by detecting bit states of the true data and the complement data signal lines. In order to adjust the transmission of the return data signal, each data receiver may be provided with an independent return data signal line such as the data receiver 102, or the data receivers may be connected to one return data signal line such as the data receivers 103 to 104. If many data receivers are connected to the same return data signal line, it may be necessary to selectively specify a particular data receiver to transmit the return data signal. Various addressing methods may be used. For example, it may be possible to use a portion of a data signal transmitted by a data transmitter to provide an address or to transmit independent address signals and data signals.

In FIG. 2 a block diagram of the data transmitter in FIG. 1 is shown. When the transmitter wants to transmit data, a data strobe pulse (state of pure binary "1") is applied to the strobe input of latch 201 to carry a new set of input data. The input data set is shown here as an 8-bit binary signal. The latch 201 can be passed if there is a data strobe pulse and not otherwise. The data strobe signal via the inverting gate 202 clocks the Q output of the flip-flop 208 to the binary "1" state. This state of "1 '" corresponds to the + V voltage level with respect to ground. The state of binary " 1 " of the Q output of flip-flop 208 is coupled through OR gate 204 to create a binary " 1 " state of busy signal. The busy signal indicates that the data transmitter is currently busy transmitting a data signal.

The clock input of flip-flop 209 and the shift clock signal coupled to registers 203 and 211 determine the rate of data transmitted to the data receiver via the true data and complement data signal lines. The shift clock signal may be provided by a remote device such as a clock oscillator or a microcomputer. According to the present invention, the shift clock signal does not need to be periodic, and frequency and transition may be changed dynamically.

Once the flip-flop 208 is clocked once by the data strobe signal, the Q output of the flip-flop 208 is clocked in the binary "1" state at the next positive transition of the shift clock signal. The Q output from flip-flop 209 is connected to the parallel shift input of register 203 and the D input of register 211. Therefore, at the next forward transition of the shift clock signal, the data signal from the latch 201 is applied in parallel to the register 203 and " 1 " is applied to the first end of the shift register 211. The state of binary "1 " of the Q output of flip-flop 209 is used to reset the flip-flop 208, and keeps the busy signal at " 1 " through the OR gates 205 and 204. The shift clock signal is applied to the register 203 through the 205 and 207 and the inverting gate 206.

Each bit is applied to the inverting gate 216 and the AND gate 219 successively while the data signal in the next eight cycle pattern register 203 of the shift clock signal is shifted to the right. At the same time, one bit is sequentially shifted to the shift resist 211. The outputs of the shift register 211 are coupled at the OR gate 212 to enable the AND gate 214 and keep the busy signal at " 1 " through the OR gates 205 and 204.

Prior to applying the data signal to the latch 201, the true data and complement data signal lines are held at " 1 " by the OR gate 212 through the OR gate 218 and the inverting gate 215. When the state of the OR gate 218 changes from "0" to "1", the state of the true data and complement data signal lines will be determined by each bit of the data signal in the register 203. During the period of " 1 " of the first shift clock signal, the true data and complement data signal lines are held at " 1 " by the AND 213. During the period of " 0 " of the next shift clock signal, the AND gates 217 and 219 are connected to the OR gate 220 for the register 203 and the true data signal line and to the OR gate 221 for the data signal line. Allows you to apply consecutive bits. The true data signal line is "1" if the bit of the data signal is "1" and the complement data signal line is "1" if the bit of the data signal is "0". Typical waveforms of the true data and complement data signal lines are shown in FIG.

The data signal is transmitted through the complement data signal and the true data signal line, and at the same time, the return data signal is received through the return data signal line connected to the D input of the register 203.

Initially, the register 203, which receives the input data signal from the latch 201 in parallel, sequentially receives the return data signal while moving and transmitting the input data signal. When the last bit of the input data signal is transmitted, the output of the OR gate 212 changes from "1" to "0" and the shift clock signal passes through the OR gate 205 and the inverting gate 206 to the register 203. To prevent In addition, when the transfer is completed, the register 203 prepares a return data signal received from the data receiver at its output.

FIG. 3 shows a detailed circuit diagram of the data receivers 102-104 in FIG. For a typical data signal transmission, the waveform corresponding to the block shown in FIG. 3 is shown in FIG. 4, the transmitted data signal in FIG. 4 is " 11010001 " and the return data signal is " 1110101. " The data receiver in FIG. 3 includes a data latch formed by the NAND gates 305 and 306, which are connected to the NAND gate 303 which senses the state of "1" of the true data and complement data signal lines. Set by the NAND gate 304 which senses the state of " 0 " of the signal line. Completion of the true data and complement data signal lines is required to decode the 2-bit binary state, which is provided by the inverting gates 301 and 302. The outputs of the data latches 305 and 306 are reproduced NRZ data signals, and the D input and the parallel input of the register 312 are connected to the higher side.

The data receiver also includes a last bit latch formed by NAND gates 309 and 310. The last bit latches 309 to 310 are set by the bit state of the true data and complement data signal lines sensed by the NAND gate 307 and reset by the word state sensed by the NAND gate 308. The last bit latch output signal is applied to the parallel shift input of the NAND gate 314 and the register 312.

The reproduced bit clock signal is provided by the NAND gate 311 corresponding to the bit state of the signal line sensed by the NAND gate 307. In addition, the bit clock signal becomes " 1 " due to the word state of the signal line sensed by the NAND gate 308. FIG.

When the data signal is transmitted to the data receiver in FIG. 3, the register 312 is first loaded in parallel in response to the last bit latch output signal and thereafter the angle of the bit clock signal to move the reproduced NRZ data signal. It is clocked sequentially every forward transition. In the preferred embodiment, the data signal has eight bits, so the register 312 and latch 313 have eight stages. When 8 bits of the reproduced NRZ data signal are shifted to the register 312, the frame clock signal provided by the NAND gate 308 changes from " 0 " to " 1 " and allows the latch 313 to pass through the received NRZ. The data signal is coupled from the register 312 to the output of 313. Latch 313 is locked while frame 312 is shifting because the frame clock signal is " 0 ". The return data signal applied to the register 312 is also applied to the return data signal line by the NAND gates 314 to 316 while receiving the transmitted data signal.

The data receiver of FIG. 3 requires a separate return data signal line for each data receiver in the data transmission system. In order to connect many data receivers to the same return data signal line, the ability to selectively designate each data receiver needs to be provided. One way to optionally specify many data receivers is to send an address signal before transmitting a data signal. Various transmission schemes for providing an address signal prior to the data signal can be realized using the data transmission scheme of the present invention. For example, when the data transmission plan of FIG. 4 is used, the address signal and the data signal can be distinguished by the word states of the true data and the complement data signal. According to another plan, the address signal and the data signal can be separated by providing each bit state of the data signal between the word state of the signal line between each bit of the address signal. This scheme can be used to define varying lengths of addresses while maintaining a fixed length of data words. The end of the address signal is confirmed by the bit state of the signal line occurring after the first bit of the next data signal. A data receiver for receiving an 8-bit address signal and an 8-bit data signal transmitted according to this scheme is shown in FIG.

The data receiver shown in FIG. 6 is substantially the same as the data receiver of FIG. 3 except for the added address register 320, address decode 321 and gates 322 to 325. A waveform corresponding to a block shown in FIG. 6 for a typical address and data signal transmission is shown in FIG. 7 wherein the address signal transmitted is a "1010101" data signal and a "11010001" return data signal is "1110101". In FIG. 6, the address register 320 sequentially receives the NRZ data signals from the data latches 305 to 306 in response to the word states of the signal lines sensed by the NAND gate 308 and the inverting gate 322. FIG. Receive. Since the word state is provided between each bit of the address signal, the NAND gate 308 and the inverting gate 322 provide a clock pulse in response to the sensed word state. The 8-bit address signal received by the address register 320 is decrypted by the address discriminator 321 and this receiver is decrypted by the correct address discriminator 321 and the NAND if the receiver receives and decrypts the correct address. Gate 323 is made available.

The data signal following the address signal is sequentially moved to the register 312 as described with reference to FIG. The return data signal is applied to the NAND gate 315 which is made available by the address decoder 321 when the correct address is received and decrypted past the inverting gate 324. The return data signal is coupled from the NAND gate 315 to the open collector inverting gate 325 via the NAND gate 316 to use the shared return data signal line. The open collector inverting gate 325 is unavailable until an address signal is detected by the decoder 321 enabling the NAND gate 315. Since many data receivers are connected to the return data signal line, the open collector inverting gate 325 is used to interface each gate receiver to the return data signal line. Other suitable tri-state busing devices may be used to interface the data receiver to the return data signal line.

The NAND gate 323, which is made available by the address decoder 321 when all eight bits of the motorized data signal are sequentially moved to the register 312, is output to the outputs from the last bit latches 309 and 310. In response, the received data signal is clocked from the register 312 to the register 326.

According to another advantage of the present invention, the data receiver of FIG. 6 can send an interrupt signal to the return data signal line instantaneously to warn the data transmitter which can use the return data signal. In FIG. 6, the NAND gate 314 may connect the interrupt signal to the return data signal line by the outputs of the last bit latches 309 and 310. The output of the last bit latches 309 and 310 disables the NAND gate 314 only while the return data signal is being transmitted. Thus, the intercept signal can be connected to the return data signal line by any receiver at any time except during the time during which the selected data receiver is transmitting the return data signal. Since the data transmitter does not know which data receiver is generating the interrupt signal, the data transmitter will have to examine the data receiver after receiving the interrupt signal.

The data transmitter of FIG. 2 and the data receiver of FIG. 6 may consist of ordinary integrated circuits, such as CMOS, described in CMOS I.C.Book, published in 1978 by Motorola Bamdoche, Texas. Furthermore, the electric circuit devices corresponding to the data transmitter of FIG. 2 and the data receiver of FIG. 6 can be separately or in one integrated circuit device.

The data transmission scheme of the present invention can be advantageously used in many different data transmission systems. For example, the invention data transmission scheme can be used to send and receive data between microprocessors and peripherals such as auxiliary storage, keyboards, displayers and radio sets, as described in the application described above. Similarly, the inventive data transmission scheme can be used to control multiple radio transmitters located in branch offices geographically far from the central control pole. The data transfer plan is self-clocking and independent of changes in speed and timing, so it is not important for correct transmission to delays and skews caused by long distances.

In summary, the data transmission scheme and apparatus of the present invention provide reliable self-clocking bidirectional data transmission that is highly immune to speed and timing changes. The data transmission plan, invented by using two-bit binary state by tying true data and complement data signal lines, has the ability to separate the address and data signals while uniquely defining the data state and the binary state of the data signal bits. . The correctly selected two-bit binary state can change if the binary state of only one signal line changes for each state transition, as shown in FIG.

Claims (11)

Configured to serially transmit a data signal from a signal source by a first and a second binary signal sequence transmitted over the first and second signal lines, the data signal being in binary zero state or binary first state. Gates 212, 214, 215, and 218 which generate a first binary state in the first and second signal sequences before and after this data signal, including a plurality of bits with A second binary state of the second signal sequence and a second binary state of the first signal sequence are generated for each bit of the data signal and a second binary sequence of the second signal sequence is generated for a bit having a binary one state. A transmission system comprising gates 216, 217, and 219 for generating a second binary state of a second signal sequence and a first binary state of a first signal sequence for bits having a binary state. The gates 216, 217, 219 between successive bits of the data signal. 1 and the data transmitter, comprising a step of generating a second binary state of the second signal sequence. A clock signal generating means according to claim 1, wherein said gates (216, 217, 219) generate a binary state of a first and second signal sequence for each bit of a data signal in response to a clock signal. Data transmitter. 3. The apparatus of claim 2, comprising a latch 201 responsive to the strobe signal and means for providing a strobe signal to store a data signal, wherein the gates 216, 217, and 219 are angles of the first and second signal sequences. Responsive to a data signal stored in the means for generating a state. Receives a data signal from a first and second binary signal sequence transmitted in series through the first and second signal lines by a signal source, the data signal being a plurality of binary or binary states. The first and second signal sequences have a first binary state before and after the data signal; the first signal sequence has a second binary state; the second signal sequence has a binary state; A transmission system having a first binary state and a second signal sequence having a second binary state with respect to data signal bits in a binary one state, wherein the first and second signal sequences are continuous data signals. The first and second signal sequences have a second state between the bits and the first and second signal sequences have a second state between the successive data signal bits and the first and second signal sequences have a second state between the successive data signal bits. Gates 307 and 30 responsive to a second binary state of 8, 311) and an output signal having a binary zero state in response to the first binary state of the second signal sequence and the second binary state of the first signal sequence, and storing the first signal sequence of the first signal sequence. Gates 303 and 304 and latches 305 connected to the first and second signals to store an output signal having a binary one state in response to a second binary state of a binary state and a second signal sequence of And a register (312) connected to said gate to store an output signal of said gate (303, 304, 305, 306) in response to a clock signal. 5. A signal source for transmitting a return data signal having a plurality of binary bits by a return signal sequence on a return signal line and a corresponding binary state of the return signal sequence are generated for successive bits of the return data signal. And a gate (314, 315, 316) in response to a clock signal. 6. A data receiver as claimed in claim 5, wherein the gate (314, 316) generates a predetermined binary pulse signal on the return signal line to indicate that the return data signal is useful for transmission. A plurality of binary or two binary states between the receivers 102, 103, 104 and the transmitter 101 coupled by the first and second signal lines carrying the first and second binary signal sequences; A serial signal is transmitted in series and the transmitter is configured to generate a first binary state of the first and second signal sequences before and after the data signal and the signal source providing the data signal. 218) and generate a first binary state of the second signal sequence and a second binary state of the first signal sequence for the bits of each data signal for the bit having a binary zero state. A communication system comprising a second binary state of a second signal sequence and gates 216, 217, and 219 for generating a first binary state of a first signal sequence with respect to a bit having: Generating a second binary state of the first and second signal sequences between successive bits. The transmitter includes the data 216, 217, and 219, and the receiver includes a gate 307, 308, 311 and a second signal sequence in response to a second state of the first and second signal sequences to generate a clock signal. An output signal having a binary 1 state in response to a first binary state of and having a binary manufacturing state in response to a first binary state of a second signal sequence and a second binary state of a first signal sequence Storing consecutive binary states of the gates 303 and 304 and the data latches 305 and 306 and the gates 303 and 304 and the data latches 305 and 306 in response to the first and second signal sequences. And a register (312) connected to the gate (307, 308, 311) and the gate (303, 304) and the data latch (305, 306). 8. The apparatus of claim 7, wherein the transmitter comprises means for generating a clock signal and gates (316, 317, 319) for generating respective binary states of the first and second signal sequences for each bit in response to the clock signal. Data transmission system characterized in that it comprises. 10. The method of claim 8, comprising a return signal line carrying a return signal sequence transmitted between a receiver and a transmitter, the receiver including a signal source providing a return data signal having a plurality of binary bits and Gates 314, 315, and 316 responsive to clock signals of gates 307, 308, and 311 to generate corresponding binary states for successive bits of the return data signal, and the transmitter responds to the clock signal to return signals. And a register coupled to the return signal line to store a sequential binary state. The receiver always includes gates 314 and 316 for generating a pulsed binary state of the return signal line to indicate whether the return data signal is useful for transmission and the transmitter is configured to transmit the pulsed binary state to transmit the data signal. And means connected to the return signal line to detect and activate the transmitter. The data communication system according to claim 9 or 10, wherein a plurality of receivers are connected to the first and second signal lines and the return signal line.

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