JPH11298459A - High speed transmission system and high speed transmitter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce losses in a high frequency band in a transmission channel and to realize high speed data transmission by sending data at a transmitter side in a half rate clock that is frequency-divided by 1/2 in a transmission system for sending data and clock in parallel and operating a receiver at the half rate clock resulting from frequency division. SOLUTION: In this high speed transmission system, a transmitter side LSI 1 outputs data that is subjected to re-timing by a clock and a half rate clock frequency-divided by a 1/2 frequency divider circuit 8, and they are received by a receiver side LSI 2 via a transmission line 6. A receiver side flip-flop is subject to re-timing by a 2-shape clock that is positive and negative outputs of a differential buffer 9 inside of the receiver side LSI 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to high-speed signal transmission, and more particularly, to a semiconductor device and a transmission system related to an electronic device such as an ATM switch in communication.

[0002]

2. Description of the Related Art The prior art is described in Japanese Patent Application Laid-Open No. 7-15405, entitled "Digital Transmission Line Test System and Digital Transmission Line Test System". Hereinafter, this technique will be described. FIGS. 10A and 10B show a conventional transmission system. FIG. 10 shows a transmission system connected by three interfaces for separating and transmitting clock, data, and frame signals from the transmission side. As an actual circuit configuration, the transmission side L
In SI1, data from the internal logic synchronized with the frame signal is retimed by the last-stage flip-flop 3, and the clock and data for which this retiming is performed are performed.
The frame is output via the output buffer 4. The signal propagates through the transmission line 5, is input to the receiving-side LSI 11, and is re-timed by the first-stage flip-flop 10 via the input buffer 7.

The speeding up of the device is determined by the transmission speed of the three interfaces. Normally, data to be transmitted is NRZ (Not Return to Zero) within one cycle, and the transmission rate is represented by a data cycle (bit
/ S). The clock is RZ (Return to Zero)
o), the clock frequency (H
z) is twice. The transmission line 6 has a length of several tens of meters to transmit between the units of the device, and the waveform deterioration due to the loss in the high band in the transmission line 6 is greatest for the clock having the maximum frequency among the three interfaces. Affected. Therefore, the transmission speed is limited by the clock frequency.

[0004]

In the configuration of the prior art, the data and clock to be transmitted use the same type of transmission line, and the data always utilizes only half of the transmittable band.

Therefore, the limitation of the clock frequency, which is twice the frequency of the data, is a bottleneck for increasing the speed of the device.

An object of the present invention is to realize a high-speed apparatus by reducing waveform deterioration due to loss in a high band in a transmission line and enabling high-speed signal transmission.

[0007]

The object of the present invention is to transmit a frequency-divided clock from the transmission side and operate the circuit with the frequency-divided clock on the reception side to provide a transmission line with twice the frequency band of data. Achieved by not requiring.

[0008]

(Embodiment 1) Hereinafter, Embodiment 1 of the present invention according to the present invention will be described with reference to FIGS. 1, 2, 3, and 4. FIG. As shown in FIG. 1, the transmission system according to the present invention employs a transmitting LSI 1, a receiving LSI 2, a transmitting flip-flop 3, a receiving flip-flop 4, an output buffer 5, a transmission line 6, an input buffer 7, and a dividing circuit 8 , A differential buffer 9.

Usually, the data transmission speed is represented by a data period (bit / s), and corresponds to a frequency (の) of a frequency. Therefore, the frequency of the clock is twice the frequency of the data. In the transmission-side LSI 1, the data from the internal logic is re-timed by the last-stage flip-flop 3, and the re-timed clock is frequency-divided by 2 by the divide-by-2 circuit 8, and is output together with the data via the output buffer 5. Output. The transmission line 6 has a length of several tens of meters to transmit between the units of the device. However, since the clock propagating through the transmission line 6 is a half-rate clock divided by two, the loss in the transmission line in a high band is high. Waveform degradation is caused by the fact that the clock frequency is 1 /
2, it can be reduced.

The data and the half-rate clock transmitted through the transmission line 6 are input to the receiving LSI 2, the data is input to the receiving flip-flop 4 via the input buffer 7, and the half-rate clock is input to the differential buffer 9. The half-rate clock input to the differential buffer 9 outputs a two-phase clock having positive and negative outputs, and retiming of data is performed using the two-phase clock.

FIG. 3 is a timing chart in the transmission system of FIG. Data is alternately retimed at each rising edge of a differential half-rate clock.

FIG. 2 shows a system in which a half-rate clock is shifted by a flip-flop 10, which is a shift register, on a transmitting side to output a two-phase clock. As in FIG. 1, the clock propagating through the transmission line 6 is a half-rate clock.
Therefore, it can be reduced.

In this method, since there are two clock outputs, it is necessary to add an LSI pin. However, since only the rising edge of the clock is used on the transmitting side, the influence of the clock duty can be ignored.

FIG. 4 is a timing chart in the transmission system of FIG. By shifting the clock by one, retiming is performed alternately as in FIG.

(Embodiment 2) Hereinafter, Embodiment 2 of the present invention will be described with reference to FIGS. 5, 6, and 7. FIG. FIG. 5 shows a configuration in which, in the transmission system shown in the first embodiment of the present invention, the divide-by-2 circuit is configured by a 1-bit counter circuit, and the clock timing is delayed by half a cycle with respect to data.

The clock is divided into two by a 1-bit counter, which is a frequency dividing circuit, to obtain a half-rate clock. At this time, since both the data and the clock output are outputs from the same type of flip-flop, the variation in the delay time due to the influence of the LSI process, temperature variation, and power supply variation is the same variation. The skew between the data and the clock due to the above effects can be ignored.

In the half-rate clock to be transmitted in parallel, the data is retimed by the positive output of the clock and the half-rate clock is retimed by the negative output of the clock in the transmission-side LSI, so that the edge of the half-rate clock is logic Delay half a cycle. As a result, there is an advantage that the timing of the data and the half-rate clock does not have frequency dependency, and the relative fluctuation of the delay time due to the influence of the LSI process, temperature fluctuation, and power supply fluctuation can be ignored.

FIG. 6 shows a configuration in which the timing of the half-rate clock is delayed by the delay element 11 to the center of the data. In this configuration, the data and the rising edge of the half-rate clock are output with the same phase on the transmitting side, and the timing is adjusted by the delay element 11 on the receiving side.

FIG. 7 shows a PLL 13 which is a magnifying circuit on the receiving side.
Thus, the transmitted half-rate clock is multiplied to operate with the full-rate clock.

In the PLL 13, the clock is multiplied,
The skew is corrected by adjusting the phases of the rising edges of the divided clock and the multiplied clock. Therefore, by performing retiming at the center of the data using the negative output clock of the differential buffer 9, a timing margin can be secured. The multiplying circuit may be constituted by a differentiating circuit using EOR logic.

(Embodiment 3) Hereinafter, Embodiment 3 of the present invention will be described with reference to FIGS. FIG.
Is a configuration of an ATM switch using the high-speed data transmission method of the present invention, and includes a parallel / serial converter 14, a serial / parallel converter 15, a logic unit 16, a SW (switch) unit 17, an input / output LSI 18, an ATM SW LSI 19, 2
The transmission circuit 20 includes a frequency dividing circuit 8 and the receiving circuit 21 includes a differential buffer 9.

In an ATM switching system, in order to switch data such as voice and video from a plurality of ATM terminals, it is necessary to distribute and transmit signals to substrates corresponding to the number of ATM terminals. In order to cope with this, it is necessary to increase the speed and capacity of the switch. In the device, it is necessary to transmit data from each ATM terminal from the line unit to the switch unit. Actually, the data is transmitted from the input / output LSI 18 of the line unit to the switch side via the transmission line 6 of the board and backboard. Transmission to the ATM SW LSI 19 is performed. At this time, parallel / serial conversion is performed to reduce the number of parallel bits of data due to the limitation of the number of pins of the LSI, the board, and the backboard. High-speed transmission of serial-converted data is required, and the transmission speed of this serial transmission determines the speedup of the ATM switch.

FIG. 9 shows the appearance of the ATM exchange. Transmission is performed by the transmission line 6 from the board on which the input / output LSI 18 is mounted to the board on which the ATM SW LSI 19 is mounted via the backboard.

By applying the transmission method of the present invention,
As shown in the first embodiment of the present invention, high-speed transmission between LSIs is possible, thereby realizing high-speed ATM switching.

[0025]

As described above, according to the present invention, LS
By using a half-rate clock for clock transmission between I, waveform deterioration due to a loss in a high band in a transmission line can be reduced, so that high-speed data transmission becomes possible and the speeding up of the device can be realized. In addition, since the data and the half-rate clock are output from the same flip-flop on the transmission side, the effects of temperature, power supply, and process variation can be ignored. Further, the differential buffer on the receiving side outputs positive and negative
Since the operation is performed by the phase clock, high-speed transmission can be realized without increasing the number of pins of the LSI.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a high-speed transmission system using a differential clock according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of a high-speed transmission system using a shift register according to an embodiment of the present invention.

FIG. 3 is a time chart of a high-speed transmission method using a differential clock according to the embodiment of the present invention.

FIG. 4 is a time chart of a high-speed transmission method using the shift register according to the embodiment of the present invention.

FIG. 5 is a configuration diagram of a high-speed transmission system using reverse-phase transfer according to the embodiment of the present invention.

FIG. 6 is a configuration diagram of a high-speed transmission system using a delay element according to an embodiment of the present invention.

FIG. 7 is a configuration diagram of a high-speed transmission system using a PLL according to an embodiment of the present invention.

FIG. 8 is a configuration diagram of an ATM switch to which a high-speed transmission system according to an embodiment of the present invention is applied.

FIG. 9 is an external perspective view of an ATM switch to which the high-speed transmission system according to the embodiment of the present invention is applied.

FIGS. 10A and 10B are a configuration diagram and a time chart of a conventional transmission system.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Transmission side LSI, 2 ... Reception side LSI, 3 ... Transmission side flip-flop, 4 ... Reception side flip-flop,
5 output buffer, 6 transmission line, 7 input buffer,
8: 2 frequency dividing circuit, 9: Differential buffer, 10: Flip-flop for shift register, 11: Delay element, 12
... frequency divider, 13 ... PLL, 14 ... parallel / serial converter, 15 ... serial / parallel converter,
16: logic section, 17: SW section, 18: input / output LS
I, 19: ATM SW LSI, 20: transmitting circuit, 21: receiving circuit.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Mitsukuni Yokota 216 Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside the Information and Communications Division, Hitachi, Ltd. (72) Inventor Hiroaki Kasahara 216 shares in Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture In-house Hitachi Ltd. Information and Communication Division (72) Junya Obayashi 216 shares in Totsuka-cho, Totsuka-ku, Yokohama, Kanagawa Hitachi, Ltd. Information and Communication Division

Claims (7)

[Claims] 1. A transmission system for transmitting digital data to be transmitted together with a transmission clock for defining a transmission cycle of the data, and taking in the digital data on a receiving side by using the transmitted transmission clock. A high-speed transmission system in which a clock having a period equal to one-half of the digital data transmission period is transmitted as a transmission clock, thereby enabling clock transmission on a transmission line having a bandwidth equivalent to a data transmission line. 2. A transmission system for transmitting digital data to be transmitted together with a transmission clock for defining a transmission cycle of the data, and taking in the digital data on a receiving side using the transmitted transmission clock. A high-speed transmission method that eliminates the need for a clock transmission line that requires a wider bandwidth than the data transmission line by transmitting digital data that changes every cycle instead of the transmission clock. 3. A transmission method in which a plurality of parallel data and a clock are transmitted in parallel from a transmitting side and output, and data is retimed by a clock transmitted in parallel on a receiving side. By transmitting a half-rate clock obtained by dividing the clock by 2 and operating on the transmitting side using a two-phase clock of positive output and negative output of the differential buffer, waveform deterioration due to loss in a high band in the transmission line High-speed transmission system characterized by reducing noise. 4. The transmission method according to claim 3, wherein the transmission side transmits a half-rate clock obtained by dividing the clock by two and a two-phase half-rate clock obtained by shifting the half-rate clock. 3. A high-speed transmission method characterized by reducing waveform deterioration due to loss in a high band in a transmission line as in the case of (3). 5. The transmission method according to claim 1, wherein a half-rate clock transmitted from the transmission side is multiplied by a PLL on the reception side and operated as a full-rate clock. A high-speed transmission method characterized by reducing waveform deterioration due to high-bandwidth loss in a line. 6. A high-speed transmission method according to claim 1, wherein a parallel / serial conversion of a plurality of data is performed on a transmitting side, and a serial / parallel conversion is performed on a receiving side. Reduces the number of pins on the backboard,
And a serial / parallel conversion circuit and a parallel / serial conversion circuit capable of high-speed transmission of serial signals. 7. A high-speed transmission apparatus according to claim 1, further comprising an ATM switch for switching a high-speed signal by applying a parallel / serial conversion circuit.