DE1774945C3 - Electronic data processing system for mixing, sorting, arithmetic processing of data sets consisting of data fields and for rearranging individual data fields - Google Patents

Description

11. Electronic data processing system io table processing of data fields consist according to claim 9, characterized in that the data sets and for changing over a single delay device (528) with data fields.

The invention is based on an arrangement in which the data processing system with a memory channel corresponds to multiples of the entire group of times, and a second delay arrangement, consisting of a number of dynamic devices (530 ) See with a delay, synchronously circulating memory for Speizeit, which corresponds to the time of a time channel, chem of the data sets, with a format memory are provided, which together form the cyclic recording of format information, the specific storage device, the onein- data fields or . Parts of data fields select other bits at the output of the first circuit 20 and with a program memory, the instruction information delay device can be removed and the information which the processing method for the output of the first delay circuit via the AND gate (532) indicated by the format information with the input of the data field which prescribes or data field parts, is connected to a second delay device. see is.

12. Electronic data processing system »5 The invention is based on the object by according to claim 10, characterized in that the use of acting as a buffer dynamic between the output and the input of the see cyclic memories and one in two first delay devices (528, 530) Steps carried out processing, namely before AND gate (542) is (Fig. 15 b). reading and actual processing of each

13. Electronic data processing system 30 data set as well as by the provision of Fornach claim 1, characterized in that <let mat- and program information, which work synchronously the Vorabfühl- and transfer control device with the clock of the buffer storage arrangement, device (2746, 2756) static storage devices a continuous To achieve data flow.
(1802, 1808) , which are suitable for storing several program information according to the invention, which is achieved in that the data bar can be read from the memory arrangement and information fields are used to control the processing of data sets by a first reading device are to be read by a second reading device by the time delayed in relation to the transmission of the length of a data record that data fields in the processing device can be operated with a dependent function (FIG. 18b). 4 ° controlled by command and format information

14. Electronic data processing system data processing device for selection according to claim 13, characterized in that converting and arithmetic processing verdie static storage devices (1802,1808) is bound that order terms and have a matrix structure (Fig. 18b). data fields read out by the first reading device

15. Electronic data processing system 45 or data field parts of a Vorabfühl- and Überranach claim 13, characterized in that supply control is supplied, which is dependent on a program data selection control device with command and format information controllable to a comparison device (1804) and which controls the data processing device , resemble the characteristics maps of program data - that the format and program memory is provided with an identifier of the first data set preceding each information and data sets and a comparison result storage device reading device for addressing unites. Instruction information (1808) which the program data transmission or format information can be fed to the device as a function of the stored and that the format and program memory controls the comparison result (FIG. 18b). synchronous with the one storing the data records

16. Electronic data processing system 55 memory arrangement circulating dynamic memory after Claim 15, characterized in that contains arrangements. A particularly cheap ardie Program data selection control device one by one arises when in each one Comparison device for comparing two memories of the memory arrangement and the format data records for the purpose of group control or program memory, several data sets or and a partial comparison result storage device 60 format and command information temporarily according to Art containing the program data transmission of a time division multiplex system in several time channels device are stored depending on the stored.

The result of the comparison controls, and the same characteristics. The arrangement can be made in this way fields the addition of selected data information that have controllable delay elements tion fields in registers that are available to these fields of 65 time channel transfer facilities, consecutive data records are assigned which data records or data fields or data fields are, and unequal fields the transmission parts from one time channel to another over from Total sums that are stored in the registers.

5 6:

Further preferred and particularly favorable ones are to be mentioned in a sequence, this combines |

Versions are in the subclaims. Advantages with the advantages of the main memory, to i

give. for example, direct access to an ex- ■

The data processing system of the invention has heard selected information. I.

Considerable advantages over arithmetic machines 5 The main memory that is used in the data processing ι

can be used with static memories and especially core storage systems of the invention, such as: ··>

arithmetic machines. In comparison with a magnetic tape reel, it can be exchanged because there is no loading;:

Memory core much cheaper, data in one may be present, at the same time an access to J

Save track. Pie data manipulation to get all parts of the memory. This depends Ϊ

system of the invention can be a number of functions io together with the fact that the parts of the

meet at the same time, while a core memory to total memory are in a given order

can only fulfill a single function at a time. and data processing only ever in one part

The commands for a memory core must first be issued before the entire memory.

The costs of the total memory are thereby

the. Part of a core memory must then be reduced by 15, otherwise all information is direct

an address can be addressed. The commands should be stored so that they can be accessed

will have to be read and a register I _n the following description, the prin-

be convicted. This register is subject to other principles and embodiments of the invention in

Command. A core memory is therefore slow. Explained in connection with the drawings.

A core memory control system is very expensive and »0 in the drawings are

can with one memory core at a time only one Fig. la and 1b a representation of the sub-bit

to do. The entire memory only fulfills one task.

at a time and its working speed is F i g. 2 shows a representation of the sub-bit clocks,

in the range from 500 kHz to 1 MHz. The Datenbear- Figs. 3 and 4 show the derivation of the

The processing system of the present invention has a 25 sub-bit clock out of the bit clocks,

higher operating speed than a core memory F i g. 5 is a diagram showing the

compared to the size and does not require individual nesting of sub-bit times

Control systems, since individual control is necessary FIG. 6 shows an illustration of the format storage track;

is; the data is in the data processing system. Fig. 7 shows a rotating memory with four

arranged in a fixed order. The need 30 sectors;

for memory cores, direct synchro- F i g. 8 shows a character in binary code with four

elimination of the memory. fan nesting;

In the case of the calculators known today as shown in Fig. 9, the first two bits of 16 data

save the information in various registers;

chert, and a program controls the processing of 35 FIGS. 10 and 11 each schematically show a time data. Since the information and the result of the canal transfer device for the transfer of processing in different registers, data from one sub-bit time is stored in another sub-bit, elaborated programs are necessary to time;

Get results. In the data processing system, FIGS. 12, 13, 14a, 14b, 14c, 15a and 15b show

of the invention, the data are m specific series 40 block diagrams of further time channel transfer

result stored in memory tracks and therefore fault devices:

dig available, whereby the necessary program F i g. 16 shows a block diagram of an arrangement being reduced. The program has practically only for successive selection of the format addition or subtraction and a starting point control and program control data;
to determine. 45 Fig. 17 shows a block diagram of the data transfer

In the data processing system of the invention is processing system;

each field of a data record in a particular FIGS. 18a, 18b and 18c show a block diagram

Position saved. The program is in each case a picture of a circuit that can be used for sorting; g <

Field length pre-stored so that selected Fig. 19 shows a block diagram of a further di

Data can be processed directly and the data processing 50 sorting circuit

processing can be easily performed Fig. 20 is a block diagram of a buffer and Si

Programming is very simple, and storage turret assembly

Different programs can be very easily combined with one another. Figs. 21a and 21b together show a block B

be connected to each other. circuit diagram of the data processing system

The arithmetic operations of the data processing 55 FIG. 22 shows a block diagram of an arrangement Z.

processing system of the invention are m less time to read ahead of time and to prepare a

and carried out at a higher speed than the sort word; D.

with arithmetic operation methods known today. 23 is a block diagram of a field justifier; ί

travel. This also makes them considerably cheaper than Fig. 24 is a block diagram for the positioning system

known methods for arithmetic operations. 60 ren of errors · t

In magnetic tape systems where the data in FIG. 25 is a block diagram of a delay t B

Magnetic tracks are stored, there is an emergency line; & & ^

(Perhaps idle runs. The data processing Fig. 26 shows a block diagram of an arrangement

system of the invention allows the rollover or to synchronize a delay line with

Skipping of unwanted or unnecessary 65 rotating storage

agile areas of data The data processing data that are processed here are coded,

processing system of the invention thus receives the advantages Table I shows the binary code of the characters table Π

3es magnetic tape, whereby for example the sorting shows the alphanumeric binary code of the characters

1 774 945 (P 8th 7th Table II Table I. Alphanumeric binary code Binary code

sign 1 Code position
2 4 . 8th 1 1 1 2 1 1 3 1 1 1 4th 1 5 1 , 6th 1 7th 1 1 8th . 9 1 1 1 10 1 1 1 11th 1 1 1 1 12th 1 1 13th 1 1 14th 1 1 15th 1 1 1 16 or 0

sign 1 2 4th Code position
8 A 1 BCO B. 1 1 A. 1 1 ... C. 1 1 _t 1 ■ · D. . 1 1 E. 1 1 1 F. . 1 1 . 1 G 1 1 1 1 «· H 1 1 •. · I. 1 1 1 ... J 1 . 1 1 K 1 1 1 1 L. 1 1 1 *. . M. 1 1 1 1 N . 1 1 1 1 • ■ O 1 1 1 1 1 • ■ ■ P. Q 1 . 1 R. 1 . 1 S. 1 1 1 T 1 1 U 1 1 1 V _# 1 1 1st W. 1 1 1 1 X . 1 1 Y 1 1 1 Z 1 . 1 1

In the invention, each character is represented by a characteristic 8-bit position code, In the explanations of the present invention, terms such as the following are used:

Sub-bit time or sbt:

Time of a subordinate bit bit time or bt:

Time instant of a bit with a certain significance character-time or cht:

Time in which a character is displayed Record:

Sequence of related individual data sub-bit clock:

Control pulse number for subordinate bits Bit clock:

Control pulse train for the bits Character cycle:

Control signal sequence for consecutive Characters etc.

The bits of a character (letter, number) appear in a non-parallel system one after the other at a certain point in an arrangement. In order for this arrangement to process these bits correctly, this arrangement must be indicated to which bit position a bit which appears at a certain point belongs. A separate pulse generator generates a pulse for each bit position to define the bit position. This pulse generator generates 8 pulses within the time required for the 8 bit positions of a character to occur at a certain point in the arrangement. These pulses represent the bit cycle in their sequence, each individual pulse defines a certain bit time.

The time between the first pulse of a group

from 8 impulses to the first impulse of the following

The group of 8 pulses of the bit clock is the Sign time. The first impulse in a series of ach Bit clock pulse is the character clock pulse. In the explanations there is a »Fixed Dates ·

field «eight characters. This means that the first character impulse of a sequence of eight character impulses is equal to early a field clock pulse. The time between two Data field clock pulses is the data field time. Eit

509 610/1

71 *

Fixed-length data record contains 128 characters or 16 "fixed" data fields.

Since a time division multiplex system is used for the recording and the data manipulation, each Bit time divided into sub-bit times. In the present explanations is the number of bit positions multiplied by four since each bit time is divided into four sub-bit times. The bit time remains as before but it contains four independent bit positions. The four independent bit positions within a bit time are defined by the sub-bit clock. The time between two consecutive Sub-bit clock pulses is the sub-bit time.

If one assumes the bit repetition frequency of 1 MHz for the purpose of a more detailed explanation, the result is the following times:

Bit time four microseconds, sub-bit time one Microsecond, half character time 16 microseconds. A "field" has 1 to 8 character positions.

A word is a variable-length field and is always shorter than a record. A sector is larger than a data set. Up to four data records can be stored in a memory track, so that 512 characters are then stored within a memory track. In some examples it was assumed that two sets of data can be stored in each memory track.

Since the characters are nested 4 times, 16 data records with 2048 characters can be stored in one memory track get saved. 128 storage tracks can be accommodated on one surface of the storage disk. A storage disk thus has 256 storage tracks with 256 x 2048 = 524 288 characters on it two surfaces. A field impulse appears at the beginning of every eighth character. A field impulse relates always on the "fixed" field. A sector pulse appears at the beginning of each data record. Each Part of information that is transported over a data transmission path goes in a control signal transmission path a sequence of time impulses ahead, which have the task of transmitting to control. Each time pulse train also serves to synchronize the information that it precedes. The time pulses or the synchronization pulse trains are on the control lines while the impulses of the data are in the Dalen lines.

Fig. La shows the bit clock pulses in a Sign time, and

Fig. Ib shows the bit clock pulses and the sub-bit clock pulses generally their chronological order.

In the data processing system of the invention, the rotating memories are provided with a special one Clock memory track equipped to store the data to be stored on the other memory tracks in a to record the given relation to the beat. A special memory track contains the bit clock, a another special storage track contains the sub-bit clock.

The F i g. Figure 2 shows these bit clock and the sub-bit clock memory tracks. If no storage track is provided for the sub-bit clock, it is used by the Bit clock derived with delay circuits.

F i g. 3 shows the derivation of the sub-bit clock from the bit clock. As in Fig. 3 become delay means used to extract the sub-bit clock from the bit clock.

F i g. 4 shows the extraction of the bit clock from the sub-bit clock. As in FIG. 4 shown, a counter is used to extract the bit clock from the sub-bit clock.

Information can always be synchronized by one of these four sub-bit clocks at a time, d. i.e., a first group of information can be stored in sub-bit clocks 1 and 2, while a second group of information can be associated with sub-bit clocks 3 and 4.

ίο The sub-bit clocks can also be used for saving information in a storage track can be used. So the second data record is always with the Sub-bit clock 2 recorded. The sub-bit clock is also used to set delay times steer.

In the time division multiplex of the invention, the data sets are stored in dynamic memories.

As in Fig. 5, the bits of the characters of a data set are 1 in the sub-bit time I.

ao positioned. The bits of the characters of a data record 2 are positioned in sub-bit time 2. The bits of the characters of data record 3 and 4 are corresponding positioned in sub-bit time 3.

The four sub-bit times of a bit time can also

»5 can be used in a group control program. In such a case, there will be a sub-total positioned in sub-bit time 1, the group total is positioned in sub-bit time 2, the Sum is positioned in the sub-bit time 3, and

the main sum is positioned in sub-bit time 4.

This means that the bits of four different data records are available in one bit time.

F i g. 6 shows the format memory track. The format

defines the meaning of a word within a data set. Every word in a data record has a Format signal at the beginning and at the end. Since the format signal starts with the format signal at the beginning of a word for the end of the previous word

is identical, and because the beginning of a data record is identified by a special code character the format signal is at the end of the word to which it belongs. The formal signal needs to consist of just a single bit. This results in a system using 4 Snh-bit characters and in which 6 positions in an 8-bit code are used for the representation of the characters are, 4 x 6 = 24 bit positions are available, so that the formats for 24 different Types of records can be stored in a character time. In Fig. 6 show the solid lines Lines display format signals in sub-bit time 1, while the dashed lines display format signals show in sub-bit time 2. As shown, can

each format storage track on the length of a data record 24 formats corresponding to 4-fold nesting and save the 6 bit positions.

The format gives the signal at the end of the word and can also be the location number of the field

specify within the data set.

The format can be specified in the following ways. First, it can be used as a word-end signal directly associated with the data. In this case, there are no restrictions whatsoever with regard to the field length.

restrictions. Second, the "end of word" signal can be a single pulse in the format memory track stored in the manner already described, it will then be the same for all data records

713

I 774

Type used. Since the front memory track is prepared before starting a new task, this must be done Signal "end of word" can be set for a minimum field length, d. i.e., it must be for the maximum word length Provide sufficient space. It is Z. B. possible to have 8000 machine units (4 digits), but only 97 units were counted (2 digits). The "end of word" signal in the format memory track must therefore be set 4 digits (character positions) after the preceding word end signal. Third, instead of the end-of-word signal or an In <-

pulse, which represents the signal »end of word«, can also be stored on the format memory track Save field follow-up signal. Fourth, in the case of a "fixed" field length for each type of record, neither an end-of-word signal nor a format identifier is required.

The four types of format representations are shown in Table III. The data set exists in this Table III from the details A, B, C, D, E, F. ίο Each character of the information is separated by a χ and each free space represented by an ο.

First:

Max.

Table III
Formats

E F

XXX X X XXXX XXXX X X X

EEE E EEE

WWW W WWW

Min.

A. B. C. D. E. F. X X X X X X

EEEEEEE
WWWWWWW

Secondly:

Max. Xxx xx xxxx xxxx χ xx

E.
W.

Min. XOO xO xOOO xOOO χ xO

E.
W.

Data storage track
Format memory track

Data storage track
Format memory track

Third: pure format

IAIBI C I D | E | F.

Fourth: Fixed field length. All fields have the same length; z. B. 8 characters.

The field end signal is always in the sub-bit time, which also contains the associated field. Since the format is a sequence of end-of-word signals, there are it also indicates the length of the data record.

A sequence of data sets, the characteristics of which are arranged in ascending or descending order, becomes referred to as the data record stream. So that a simultaneous access to each data record on a dynamic Storage is possible, as many reading devices must be provided as there are data records can be stored on the memory. The distance between successive readers is equal to the fixed length of the data records and is called a sector. Belongs to every sector a sector clock pulse. The time between two consecutive sector clock pulses is the Sector time. In a system in which the data records are stored in an interleaved manner, reduced the number of necessary read and write devices corresponds to the number of in a bit time existing sub-bit times.

Fig. 7 shows a rotating memory with four

Sectors, each storage track within a sector carries four interleaved channels. The records are in their order, each data record is numbered.

Each of the data records is the same length or shorter than a sector. Data record 1 is in the sub-bit time etc. of sector 1 are stored.

Figure 8 shows four characters in their nested Positions.

9 shows the first two bits of 16 data records IV1 through 16 in their nested positions.

Table IV shows the nested positions of the records as shown in FIG.

Table IV Positions of nested records

record sector
number Sub-bit time track 1 1 I.
1 1 2 2 1 1 3 3 1 1 4th 4th 1 1 5 1 2 1 6th 2 2 1 7th 3 2 1 8th 4th 2 1 9 1 3 1 10 2 3 1 11th 3 3 1 12th 4th 3 1 13th 1 4th 1 14th 2 4th 1 15th 3 4th 1 16 4th 4th 1 17th 1 1 2 18th 2 1 2 19th 3 1 2 20th 4th 1 2

The time conversion device when transferring information from a memory location of a dynamic memory into another will now be described.

Fig. 10 shows an arrangement which is used as a time channel transfer device can be used to transfer data from one sub-bit time to another sub-bit time. The time conversion device 352 can at its input for the data via the control line 353 and at its output for the data are controlled via the control line 354. The data is passed to the time porter 352 via line 355 and leave the device via line 356.

The time slot transfer device of FIG. 11 consists of a flip-flop 363. The data bits are fed to the flip-flop 363 via the line 355. The supply of the bits is monitored by the AND element 364; this AND element receives its control signals via line 353. A data bit which passes through AND gate 364 brings flip-flop 363 in his seated position. The output control signal on line 354 is a pulse which is the AND gate 365 opens at a certain, desired instant in time to receive an output signal from the Bring flip-flop 363 on line 356 when said flip-flop is in its set position. The control signal for the AND gate 365 is also transmitted via the line 366 and the delay 367 fed to the reset input of the flip-flop 363, jm said flip-flop to its basic position bring. The flip-flop 363 then remains in its basic position until a new data bit is on the line 355 the AND gate 364 can pass in order to bring the flip-flop 363 into its set position. Fig. 12 is a block diagram of another Arrangement which can be used as a time slot transfer device.

The arrangement shown in FIG. 12 consists of three ring registers consisting, for example, of a delay line, each of which has a length which corresponds to the smallest delay time. Each of the three ring registers 422, 423 and 424 has an input AND element 425, 426 and 427. These AND elements 425, 326 and 427 are controlled by corresponding signals on lines 428, 429 and 431. The data are fed to AND gates 425, 426 and 427 via lines 432, 433 _{and (} } 434.

The output line is directly connected to the input line ao. Such a memory is also called Revolver called.

Information that is fed to one of these delay lines experiences a minimum delay, which corresponds to the length of the revolver. The delay time can be several times this Minimum delay time can be extended. The outputs of turrets 422, 423 and 424 are through the AND gates 435, 436 and 437 are controlled, which in turn send their control signals over the lines 438, 439 and 411 obtained.

Data leaving the arrangement shown in FIG. 12 can be on lines 442, 443 and 444 be removed.

Fig. 13 shows a further arrangement, which as Time slot transfer device can be used. This arrangement in FIG. 13 consists of a plurality of delay means, only three of which are shown. These three delay units 451, 452 and 453 are connected in series. The output line of the third delay unit 453 is via the line 454 to the input the first delay unit 451 connected. The input lines 455, 456 and 457 are through the AND gates 458, 459 and 461 are controlled, these AND gates 458, 459 and 461 receive their input control signals again via the lines 462 or 463 or 464. The AND gates 458, 459 and 161 control the inputs to the delay unit, which between the delay units 451 and 452 and between the delay units 452 and 453 and between the delay units 453 and 451 lie.

The output line 465 is controlled by the AND gate 466, this AND gate in turn receives its control signals over the line 467. Information on the line 457 is corresponding to the Delay time of the delay unit 453 is delayed and can of the arrangement over the line

can be removed, but it can also be returned via line 454 to the entire

Arrangement to go through again and thereby another delay in the amount of the sum of the delay times of the three delay units 4SI, 452 and 453. The information can run through such a revolver as often as required until the arrangement is via the AND gate

is removed. This means that information can be provided for additional times, multiples of the total

delay time of the three delay units 451, 452 and 453 are delayed.

The arrangement shown in FIG. 13 can also be used with only one input line and with three output lines if only the input lines 456 and 457 are replaced by the output lines 468 and 469 .

Each of the output lines must be controlled by an AND gate 471 and 472. These AND gates 471 and 472 receive their output control signals via lines 473 and 474.

14a, 14b, 14c show further arrangements, which can be used as time channel changing devices. These shown in FIG Arrangements consist of controlled ring registers made up of delay units. The length or the delay time of a delay unit depends on the shortest delay time at any one Position of a circuit in which it is used. The length of the delay unit must then be a sub-bit time shorter than the shortest necessary delay time. As a result, the information is transferred to a different sub-bit time after each cycle of the turret. Since the output of the arrangement is only controlled by a signal in a certain sub-bit time, the information has to make so many iterations until it is in the sub-bit time of the output signal. This results in the delay time of an item of information in the arrangement which is shown in FIG. 14a and Fig. 14b is shown from the sub-bit time it was in to the time it was fed to the turret became.

In order to predetermine this delay time, the information is fed to a time conversion device 482 via the line 481 in FIG. 14a. A selectable control signal on line 480 determines the sub-bit time in which the information is to be recorded. An output signal on line 483 translates the information into a desired sub-bit time. The information leaves this time conversion device 482 via the line 484 and is fed to the delay device 485. After the specific delay time of the delay device 485 , the information is in the next lower sub-bit time, based on the sub-bit time in which it was supplied to the entire arrangement. If this sub-bit time does not match that of the output control signal on line 486, which controls AND element 487 , the information is passed through AND element 488 and via line 491 to the input of delay device 485 returned. The AND gate 488 receives these Uber management task a signal via the line 489. Once the information in the same sub-bit time is as the output control signal on line 486, the information of the arrangement may according to FIG. Withdrawn 14a via line 492 will.

The arrangement according to FIG. 14b uses an AND element at the input instead of the time conversion device 482 from FIG. 14a and has a time conversion device instead of the AND element 487 from FIG. 14a. The arrangement of Fig. 14b operates in the same way as that shown in Fig. 14a.

14c is a schematic block diagram of another embodiment of the time converter. The arrangement according to FIG. 14c consists of a turret with a selective input control and with a selective output control. The information reaches the time conversion device 499 via the line 498. It can flow into the time conversion device 499 if the input control signal is in the input control line 500 in the same sub-bit time the time conversion device 499 u ^ '~ ^r the control of the output control signal
Line 501 removed and fed to turret 502 via line 6ü3. The sub-bit time in which the information leaves the time converter 499 and is fed to the turret 502 is determined by the control signal on the line 501 . The output line 504 of the revolver feeds the information to the time conversion device 505 . A selection control signal on line 506 selects the information from the turret, which consists of the delay device 502 and the return 507 .

The selection control signal on line 506 determines the sub-bit time in which the information is present. The information is fed to the time conversion device 505 and is taken from it again in a sub-bit time which is determined by the output control signal on the line 508 . As long as the sub-bit time of the information does not match that of the control signal on line 506 , it can pass through AND element 511 , which receives its control signals via line 510 .

From this AND element 511 , the information is returned to the turret 502 via the lines 507 and 509. As soon as the information is in the same sub-bit time as the control signal in line 506, this information can be taken from the arrangement via line 512. The output of the information is controlled by the output control signal on line 508.

FIGS. 15a and 15b are block diagrams of FIG further arrangements which can be used as a time conversion device. The orders in Figures 15a and 15b have revolvers with interleaved storage of the information and a controlled return time. Each of the in 15a and 15b of the arrangements shown consists of a delay device, which as a turret and is of the same type as the arrangements shown in FIGS. 14a and 14b. These Type of caching can be used in systems with interleaved information arrangements will. The length or the delay time of a delay means depends on the shortest delay time which is required in the overall arrangement in which this device is used will. The length of the delay means is one sub-bit time shorter than the shortest required delay time. As a result, the sub-bit time of an item of information is set each time the information circulates in changed by a sub-bit time on the turret. By controlling the output of the array in just one Sub-bit time then the information circulates in the turret until it reaches this relevant sub-bit time has reached. The delay that information experiences in such an arrangement is thus determined by the sub-bit time in which it is fed to the arrangement.

To set the delay time for information in

509 610/105

17 18

To be determined in advance, the information is stored in the, in which the control signal is in the line

15a and 15b appear via the line 513 and a 544 , the information is provided by the AND

Control unit 514 of a delay device 528, element 532 , or the AND element in FIG. 15b

fed. The control unit consists of a timer 542, the information comes from this AND element

Transfer device as shown in FIGS. 14 a and 14 b 5 back to the entrance of the revolver 528. As soon as

are shown, or from an AND gate, as in which the information has the same sub-bit line as that

15b is shown. A select control signal has control signal on line 544 , the

on line 429 determines the sub-bit time, in information to turret 528 about the control unit

which the information is to be transferred. The 543 can be removed.

Delay line 528 can be used in any for this purpose. The simultaneous processing of data in par-

usable type, e.g. B. an arrangement aHelen processing equipment is now loaded

that the bits inductively overwrite via a wire.

wear, or mechanically by transmission. The arrangement of Fig. 16 enables the format control of the wire to be selected from one end to the other after printing from one end to the other. 15 and program control data as a function of The information traverses the delay-identifying signals for groups of data line 528 and is offset in it by one field time. The arrangement of FIG. 16 enables a sub-bit time delay. Since the field - also the processing of selected fields, time in the assumed system is 256 microseconds which were determined by the format controller, the effective delay time is the same as the length of 256 microseconds minus 1 micro-program control determined. That for the program second, i.e. 255 microseconds. The signal belonging to the taxation appears within the delay of 255 microseconds. The informacyclic operation at the time the tion is carried out is carried out by a 1 microsecond delay operation on the field data within the cycle device 530 , see above that the total verses of a data set.

delay time 256 microseconds, i.e. one field The program data indicate which fields are

Time, is; the sub-bit time in which the information identified by the dynamic format data

stands, so does not change. The 1-micro-second draws were to be selected and soft ope-

Delay device 530 can be carried out as a return ration on the fields

delay. The information is 30 In FIG. 16, the data records are in the memory

continues this delay of 1 microsecond if 591 is saved. In the first cycle of surgery

they via the line 531 and the AND gate 532 become a selection unit 592 for the

the delay device 530 is supplied. From the format control program via the AND element

there the information is transmitted via line 533 593. The fields of the record are

again to the input of the delay line 528. 35 through the selector 594, which is controlled by the identifier

The delay line is controlled with its return field of the data set, selected

speaks four normal parallel revolvers because of this selection is made via the AND gate 593,

the fourfold nesting of the information. which is received by the selector 594 via the line 595

Any information that the control unit 514 is uncontrolled.

is taken, retains its sub-bit time in which it was supplied to the 40 A plurality of format information is in arrangement. stored the memory 596 and in which the passage of the information through the 1 The Micro first cycle of operation is transmitted through member 598 in the format memory 597 selectively via the AND-second delay unit 530, a control signal on the line 539 controlled, which is the format control program is also AND gate 532 is supplied from the. The additional 45 associated selection unit 592 is selected in the device 598 via the AND gate Delay by one microsecond. This AND gate receives its signal device 530 is necessary because the delay line from the selection unit 592 via the line 599, 528 is one microsecond shorter than the time. A plurality of programs are in the program for simple shifting of the information stored in gram memory 600. What you want the revolver is necessary. 50 in the first cycle of operation in the program-however, if the information in FIG. 15 b from memory 601 via the AND gate 602 , the delay line 528 exits and via which the program is sent by the selector 594 for the line 540 , it receives another identifier field of the data record by means of the AND sub-bit Time. Thus, information changes to a member 602, which receives its control signal via the line Umlauf from its original sub-bit time 2 in 55 603 , selected.

the sub-bit time 1 over. The delay by one The data stored in the data memory 591

Sub-bit time is determined by AND gate 542 in the second cycle of the operation via the

controls, which in turn sends its control signal via AND gates 605 and 606 to the comparator

Line 541 receives. device 604 transmitted. The transfer of the records

In the arrangements of FIGS. 15 a and 15 b, 60 leads to the comparison device 604 takes place as a function of

the output line 531 of the revolver the information of the format which determines the fields,

tion to the control unit 543. This control unit can The transmission takes place via the AND element 605,

consist of an AND element, as it is in the which from the format memory 597 via the line

14a, or else it is controlled from a timer 607. Furthermore, the transmission

Conversion device, which in Figs. 14b and 14c 65 control still via the AND gate 606 ,

is shown. A selection signal on line 544 which is received from program memory 601 via the

selects the information from the turret. As long as line 608 is activated. The comparison facility

The information is not in the same sub-bit time. 604 compares the data record that was just drawn.

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with data records which are stored in other sub-bit times and which are supplied via line 609. The data records that are stored in the memory 591 are also transferred to the output memory 611 via the AND gate 612 in the third operation cycle. This transfer of the data records to the output memory 611 takes place under the control of the comparison result of the comparison device 604 via the output unit 613 and the AND element 612, on which the comparison result takes effect via the line 614.

17 shows a schematic block diagram of the data processing system. 17 shows the connection between the central processing unit of a main memory system 755 and the input and output stations 756, 757, 758, 759 and 761, via which new data are entered from the button 762 or special input means 763 or via the data for the Printouts can be transferred to the printer 764. The multiple input 758 is required to feed data from several buttons to the central processing unit of the main memory system 755. The asynchronous input 757 transfers incoming data with a bit sequence frequency that differs from the bit sequence frequency of the central unit into that of the central unit of the main memory system 755. The input serial memory 756 is the main memory for data stored in the central unit of the RAM system 755 are to be processed. The output serial memory 7 ^ 1 is of the same type as the input memory 756. Both the input memory 756 and the output memory 761 operate at the bit rate of the central processing unit of the main memory system 755 Working memory system 755 is transferred to printer 764 by output compressor 759, which prepares the data for printing.

18a, 18b and 18c together form FIG. 18 and show a block diagram of a circuit arrangement used for sorting. It shows how a data record is selected from the memory tracks 1723 a and 1723 b by the controller 1729 for early reading as a function of the result of the comparison carried out in a comparison arrangement. FIG. 18 also shows the compilation of the sorting field group contained in the data record and its transmission via the field selector and the control (FIG. 18b) for the word order in the new order of the words for comparison arrangement (FIG. 18c), dit in turn controls the transmission of data records that have been selected.

Depending on the set and basic position of the flip-flop 1793 and 1794, the data records are read from the memory tracks 1723 α or 1723 & and ^{transmitted via the line 1732, the AND gates 1727a to 1727 a 1} and the OR gate 1731. A trigger 1795 initially does not allow any signals to pass because it does not receive any time pulses. The data record is therefore first fed via line 1796 to a signal decoder 1797 in order to determine the format of the data record. The 1797 signal decoder allows the signal following the "EI" character (end of the data record) to pass. As already mentioned, the "EI" character is at the beginning and at the end of every data record.

The following character indicates the format of the data record, i. H. the nature and order of the various Fields.

The format signals are fed to format control unit 1798 via line 1799. The format control unit 1798 has an output 1801 a to 1801 n for each possible type of format that occurs. The outputs are shown for four of the possible formats. The output lines 1801 u to

ίο 1801 π are with the controller 1802 for the field and Word order linked. In this controller 1802, it is specified for each type of data record which one Fields are to be selected and in which order these fields are put together to form a sort word group

t5 should be.

Up to four fields can be selected for each type of data record and in any order be put together.

At the beginning of each field, the output

ao lines 1803 a to 1803 d Signals for different characters, according to a program in which a special character is assigned to each field. The sequence of these characters can relate to the fields of the data records, ie the characters

s5 itself and its position in a sequence form a program code for identifying the fields and for classifying the selected fields in the desired sequence in the sort word group. The signals which are supplied by the character generator via the output lines 1803 a to 1803 d in accordance with the program and the sequence of field selection are compared in the comparison device 1804 with the identification signal of the following field of the following new data record.

The comparison starts when the signal occurs. The signal EF is identified by the decoder 1805, which generates a signal on line 1806 for the generation of field signals. The field signals are compared to the signals on lines 1803a through 1803ti. The field signal is generated in a generator which, with each signal »EF«, starting with the letter A, is incremented by one letter in the order of the alphabet, ie each incoming data record identifies its various fields by a character in alphabetical order . These field characters are then compared with those characters which are generated in the four different field positions in the control unit 1802 for the field selection and the field sequence. The field character generator can be of any type, such as B. punch cards or fixed character generator.

Depending on the desired arrangement of the fields within the sorting group, a signal is generated by the comparison arrangement 1804 whenever a match is found between the programmed character and the incoming character. This signal is fed to the signal unit 1808 via one of the lines 1807 a to 1807 a ^1. The signal unit 1808 receives over the lines 1809a to 1809a ¹ time pulses that occur synchronously with the time pulses of the dynamic memory. The signal unit 1808 generates signals which depend on the programmed position of the next incoming character and the arrival time of the signals in the relevant fields. The necessary delay in periods is given by the signal in

21 22 J

one of the lines 1809α to 1809a ¹ determined. There AND elements 1833a to 1833c and in the OR element |

it concerns the necessary delay of the 1834 intended. The conversion of the maps from |

Sorting fields for their compilation in the re a sub-bit time in another takes place after; |

in the correct time allocation, the sorting fields circulate the delay device 1823a %

to the other words of the sort field group. 5 to 1823 have left a ¹ . |

Because of the division of the sorting field group into four After a map in the correct sub-bit time %

Words is a maximum delay of 3 word and the correct word time has been transmitted, §j

periods of 8 characters each required. In dependence, it is via a line 1835 and an OR gate |

1836 supplies a buffer turret 1837 of the necessary word time delay. The M

the signal unit 1808 characterizing sub-bit Im- io buffer revolver 1837 can three groups of maps to if

pulse 1, 2, 3 or 4 via lines 1811a to 4 fields each with 8 characters, i.e. up to 32 characters, f

1811 d to the OR gate 1812. The flip-flop 1795 record. , %

is controlled via a line 1813, in which the return of the map groups from the %

selectively obtained data for the sorting field group gangway of the revolver 1837 to the entrance of the revolver %

the necessary word delays are supplied 15 1837 via lines 1838, 1839 and 1841. ■ ?.

the. The necessary word delay is provided by The feedback is provided by an AND element 1842 %

the sub-bit position in which the selected data is controlled, which its control signals from outputs ΐ

be transferred, determined, in the order: Sub- 1736α, 17366 and 1736α ¹ from comparison arrangement;

Bit-time 1, 2, 3, 4 results in word delay 0, 1, 2, 3. Entries 1728a, 17286 and 1728c via one line

In the following circuit of the arrangement * o 1743 is obtained, as will be described later. The "■ '-. The selected data will be made by as many characters comparisons of the map group as soon as there is an increase in the times that the character with the lowest is taken from a revolver 1844. The revolver has the highest value directly before the start of the next- 1844 can have 3 map groups of four fields each, * the following word time is. In order to achieve this, each of which can have up to 8 characters, a counter 1814 is always incremented, 25 nested in three sub-bit times ■ '■. Whenever a character return of the map groups from the output comes via the management 1732, which is not to be selected 1845, an AND gate 1846, an OR gate gears a number of delay lines 1815a 1848 and a line 1849. The return is controlled \ to 18151t via the AND gates 1816a to I8I6 / 1 30 via the AND gate 1846, st control to achieve the necessary character time delay. A new map group is reached via a line. As soon as a field information item, the 1851 and the OR gate 1848 are supplied. The new map group for the compilation of the sorting field group replaces the previous one in question. This member was deleted in 1846. An AND gate 1852, followed by closing an AND gate 1817 via which between the lines 1838 and 1851 to a flip-flop 1818 by signals on the lines is arranged, is for this purpose by a signal 1807a to 1807a ", the OR gate 1821 and which are controlled on a line 1853. This signal controls line 1822. The sorting field information also passes the AND element via line 1854, then one of the delay lines 1815a to 40 after it has been inverted 1815Λ in the inverter 1855.

As soon as the start of the selected word leaves the AND gates 1856a to 1856c through the delay system at the time of the first character of the comparison start signal Cpt on a line 1857 of the next word time and then enters a, the map groups are opened in their word time delay arrangement 1823a to 1823a ¹ 45 sub-bit times via the said AND gates to the comparison arrangements 1728a to 1728c supplied via an OR gate 1824 and a line 1825. As soon as the next following »EFe character arrives at the map groups are through their sub-bit-responsible decoder 1805, a signal times separated from one another via lines 1858 a on a line 1826 is fed to the counter 1814, to 1858c to the AND gates 1856a to 1856c to switch him on. 50 led. The map group I is the comparison

The selected fields of the data records are circuit I-1I 1728a and the comparison circuit

then fed together to the delay arrangement 1823a I-III 1728 ft. The map group II is

until 1823 J supplied in different time periods. via the AND gate 18566 of the comparison circuit

Since the AND gates 1827a to 1827d by the four MI 1728a and the comparison circuit H-III 1728c Sub-bit pulses are controlled, only that 55 can be supplied. The map group arrives via the

Characteristic map leave the delay device, the AND gate 1856 c to the comparison circuit H-III

stands in the corresponding sub-bit time and thus 1728 c and for comparison circuit I-III 17286. It

at the same time has the correct time position. The two map groups are each bit-by-bit in the

Characteristic maps are then via an OR gate 1828 comparison arrangements 1728 a to 1728 c with one another fed to the trigger 1829, where they were compared into a standard 60. Each of the comparison assemblies 1728a

Sub-bit time, namely sub-bit time 1, is transferred to 1728c has two outputs 1866a and 18666,

the. In a subsequent flip-flop 1831, 1866c and 1866rf, 1866e and 1866 /, accordingly

then the map is in that sub-bit time above the operating method of this comparison circuit. That

which leads to the data record group in which the comparison result of the three individual comparison scarfs belongs Data record is connected. By comparing the individual results, the

Sub-bit time are all four fields of a map comparison circuit via AND gates 1868 a to.

group transferred. The sub-bit time is found logically through the 1868 c and on lines 1867 a bis

set inputs of the flip-flops 1832a to 1832c, 1867c. The comparison result is through

71 *

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a signal combination E II and 5SC, as will be described below, released.

Depending on the program control on the associated lines, a signal is generated which indicates which of the three groups of characteristics has the highest or lowest significance. The line 1867 α is assigned to the map group I, the line 18676 is assigned to the map group II, the line 1867 c is assigned to the map group III. The result of the comparison process is stored in flip-flops 1869 a to 1869 c until the data record to be selected has been transferred. As soon as the signal E II of this data record appears in the line 1871 , the comparison result is deleted. One of the flip-flop 1869a to 1869c is then 1868a to 1868 c through the AND gates by the following comparison result, standing by c already in Comparative assemblies 1728 a to 1728, is brought into set position. After the comparison result has entered flip-flops 1869 a to 1869 c, the next operation takes place.

First, the selected data record is transferred from the memory track 1723 c / or 1723 b to another memory. The associated map group is then transferred from the storage turret 1844 .

The sorting field group is then replaced by the next following characteristic field group of the following data record in the storage track 1723a or 1723 ft.

Then a new map group of the data set following in second place on the storage track 1723a or 1723ft is obtained by selection.

The selected maps are then put together to form a map group.

Finally, the reloading of the storage tracks 1723a and 1723ft or 1763a to 1763d is initiated.

These five processes are controlled by the output lines 1736a to 1736 / .

The lines 1736d, 1736 e and 1736 / select in a signal unit Ϊ872 the sub-bit time for the delay of the characteristic diagrams belonging to the data set. So there is always only one sub-bit time pulse sequence at the outputs 1873 a to 1873 c of the signal unit 1872. These data reach an AND element 1874 via an OR element 1875 and a line 1876. As soon as a new comparison result occurs, a flip-flop 1877 is caused by pulses that are placed on lines 1736g, 1736 h and 1736: and pass through an OR gate 1878, a line 1879 and a pulse shaper 1881 , whereby the AND gate 1874 becomes permeable via a line 1882 , brought into set position.

The flip-flop 1877 is brought into the basic position by a signal on a line 1883 after a time period of four field lengths, the AND gate 1874 is blocked again. As a result, the map data can reach the line 1884 in the sub-bit time of the selected data set during the time of four field lengths, which corresponds to the time of a map group in the revolvers 1837 and 1844. The data are inverted in the reversing element 1855 and delete the characteristic diagram group of the selected data record in the turret 1844, in that this is not fed back to the input of the turret. At the same time, the AND element 1852 is opened via the line 1853 for the next following map group. This next map group is in the same sub-bit time as the deleted map group. The new map group goes into the revolver 1844.

This map group transferred to the revolver in 1844 was taken from the revolver in 1837 under the control of the AND element in 1842 . The AND element

In 1842 the reverse step becomes 1886 and the line

Controlled in 1843 . The transfer of a map group from the revolver 1837 to the revolver 1844 does not depend on a specific start time, because

ίο both turrets work synchronously. Only the start of the comparison depends on the temporal position of the map groups in the turrets.

18 likewise shows the control arrangement for read heads 1724 a to 1724 d of the storage tracks 1723 a and 1723 ft. The inFig. The control arrangement shown in FIG. 18 is shown in its entirety for group 3 data records. Line 1736c transmits a signal when a data record is to be selected from this group and transmitted.

In each of the storage tracks 1723 a and 1723 b there are two data records per data record group. Since each of the storage tracks has two read heads, reading of a data record can be started at the beginning of each sector. Each memory track consists of two sectors, and one data record is stored for each group in each sector, since this working method requires the length of two data records in order to be able to sort, namely between the premature reading to form the map type and the reading of the same data record in order to transfer this to other memories depending on the comparison arrangement (FIG. 18c). The control of these read heads is very easy.

Most operations use two separate read heads. The heads are on the same side of the memory tracks, but are assigned to different memory tracks, since each memory track has two data records stored in the three sub-bit times, interleaved. The flip-flops 1793 and 1794 (Fig. 18) control the transfer of data to the signal heads for data of group 3 of the data sets. The flip-flop 1793 indicates the pair of heads to be used. The flip-flop 1794 indicates the memory track. The flip-flop 1793 is toggled with each sector pulse. The signal heads are therefore always switched so that they can read the data records in their order.

As soon as a signal occurs on a line 1887 , switching from one position to the other is interrupted once per pulse. The data record in question is then read and the signal heads are then in front of the next data record. After two data sets have been read from a memory track, the flip-flop 1794 is switched over, and the conditions for the premature reading and transfer of data records related to the memory tracks are reversed. Since there is a separate control unit for each of the groups of data records, resetting the flip-flops 1793 and 1794 to the basic position is only possible while data from the same group of data records is being read out. This is achieved by a signal in the line 1736 c , which AND elements 1888 a to 1888 d to control the prior reading and AND elements 1889 a to 1889 d to control the transmission process is fed.

509610/105

713

25 26

The AND gates 1888α to 1888t / and 1889α memory tracks 2079α and 20790, each of which up to 1889 d receive sub-bit pulses of the data - a write head 2081 α or 2081 6 and two read record groups via line 1891 and the output heads 2082 a and 2083 a or 2082 6 and 20836 lines 1892a, 18926, 1893a, 18936 of the flip-flops. The data sets stored in the transmission memory 2074 1793 and 1794, which are stored in an appropriate 5, can both be combined in advance of the form. The OR gates will be read as well in an issue series 1894 a to 1894 d and 1895 a to 1895 d will be transferred for memory. This output series, the merging of the control signals of the three memories, is used in the second half 20656 of the input control units. This is indicated by arrows and output serial memory 2065. The transfer 1896a to 1896a ¹ . Lines 1897a io are made via the read heads 2082 α, 20826 and 2083 a to 1897 a "connect the OR gates 1894α to and 20836, which are controlled by the head shell arrangement 1894 d with the AND gates 1727a to 1727 d, 2084. The head switching arrangement lines 1898a to 1898a "connect the OR 2084 is controlled by a controller 2085 for the ^{reading and transmission of the prior elements 1895a to 1895 a 1} with the AND elements. Early 1726a to 1726 rf. The signals in the lines 15 read data records are the head switchgear 1896a to 1896a "are time impulses which are taken from the voltage 2084 via a line 2086. The selected data records from the signals offered by the signal heads to be transmitted into the output serial memory 2065 6 , separate what is in the the data records are fed via a line 2087 to the AND gates 1727a to YIlTd and 1726a to the sorting group control 2088.
YIM * d takes place, from where said signals to the 20 The premature reading of the data records means that OR gate 1731 or 1748 arrive. a data record for the purpose of selecting the identifier

Fig. 19 is a schematic block diagram of a field read by the following circuit Sorting arrangement for data processing. The records must be read ahead of time of the invention and is used to illustrate the before the comparison arrangement makes a decision Data flow through the computer part. he hit the dung. A control 2089 of the

The arrangement of Fig. 19 relates to the same arrangement must recognize the signal "NG" (new sorting, as the main program of the arithmetic group), and it must store which machines. The records are in one half of the groups that character has already had in a sorting period 2065a of an input and output serial memory. Control 2089 must then store 2065. This first half of the input 30 the input of the comparison arrangement 2078 for the and output series memory 2065 consists of three following data records of this group via a Lei group memory 2066a, 20666 and 2066c, which block device 2091.

the three groups of records, which sorted the record comes to a 1 to 8 characters are to be allocated. A group switching delaying device 2092, a money selector arrangement 2067 selects the data records from each of 35 2093 and a selector 2094 for data records. Of the one of the memories 2066a, 20666 and 2066c. Selector2094 takes the format from the data record according to the control signal on a line 2068 identifier and then selects the one for the formation the end. The data records become a memory track - the map necessary program. A switch device 2069 supplied. field selection program 2095 is used by the selector

Since the group switch 2067 activates the data 40 2094. A signal generator 2096 receives

satzc signals from the selector 2094 via a line already in channels belonging to groups

has transferred, the memory track switch needs 2097. The activated program 2095 controls the

processing 2069 only the relevant storage track Fcldselektor 2093 via a line 2098. The field

of a pre-store 2071, into which a data record selector 2093 selects not only the fields which

read is to select. The pre-storage 2071 consists of 45 for the formation of the characteristic field, but rather

from four storage tracks 2072 «to 20? 2rf The simultaneously determines by how much a selected field

Data records 1 and 2 from a memory track that has to be delayed in order to move to the intended position.

input and output memory 2065 will arrive in one tion.

Storage track 2072a stores the data sets 3 The character delay arrangement is in two and 4 arrive at a storage track 2072a which divides 50 parts. The first part 2092 is an arrangement, data records 5 and 6 are transferred to a memory track which allows a delay of 1 to 8 2072r for the field and data records 7 and 8 are transferred to a character the length of a normal field allows memory track 2072 rf. Both the group A field delay arrangement 2099 allows pin switching arrangement 2067 and the storage lane to delay the field again by the three field lengths in switching device 2069 are controlled by a storage 55 steps of one field length. _at the field delay 2099 is the se-

The transfer of data records from the pre-selected field in the correct position and is in

store 2071 in a transfer memory 2074 a buffer turret 2101 in the same channel

is stored by a storage track and group selection in which the associated data record is in the

Establishment carried out in 2075. This memory track 60 transmission memory 2074 stored is turned off,

and group selection device 2075 is from The map comes from the buffer memory 2102

a storage track and group selection control into the storage turret 2102. The storage turret

2076 is controlled in the same way as the memory track and contains all the identification fields in the next

Group switching control 2073. The memory track comparison are required

and group selection control unit 2076 receives its 6 ₅ The comparison arrangement 2078 has at least

Via the control signals via lines 2077 a to three control lines 2077 a, 20776 and 2077 c These

2077c from a comparison device 2078. Control lines 2077a to 2077c control the charging

The transfer memory 2074 is composed of two of the preliminary memory 2071 and the transfer memory

713

de 2074, the early reading and transfer of the * data records from the transfer memory 2074 via \ b the sorting group control 2088 and furthermore; e · a collecting turret 2103 in front of the output collecting memory 2065 6. The first two characters »NG«. n- within a group of three characters ü- are suppressed by a corresponding circuit, since e- always three old groups form a new sorted group ig. The data records to be transferred to the output collecting memory 2065 6 • a are compiled in the collecting 3g revolver 2103 until they can be transferred without difficulty. The output serial memory, like the input serial serial memory, consists of three groups of memories i- 2104 α to 2104 c, each of which is a group of

ie records is assigned.

! - The first and second halves 2065 α and 2065 b des

; r input and output series memory 2065 are electronically controllable. The data records can be fed to a computing circuit 2080 from the output of the head switching arrangement 2084 via a line 2070 and from there to the collecting turret 2103 via

reach a line 2090 . The comparison control 2089 and the sorting group control 2088 control the control unit 2105 of the collecting turret 2103 • via lines 2106 and 2107.

F i g. 20 shows an embodiment of a buffer and ■ ι memory turret assembly 2101 2102 of Fig. 19.

The buffer turret 2101 (FIG. 19) works as a pre-store for characteristic maps which are to be transferred to the storage turret, from where they are fed directly to the comparison arrangement 2078 (FIG. 19). The selected fields that make up the code

. · Are to be combined, the in

'- Fig. 20 is supplied to the arrangement shown in the channel 4 via line 2523. The first operation is to put the incoming characters into the channel '. be transferred, in which the associated data

, · Record is stored. This is supported by instructions

Controlled, which are stored in the transmission memory 2074 (FIG. 19). The comparison result j is still available and can be used for this control; it is located as an electrical signal on one of the lines 2077a to ; 2077c (Figure 19).

_; The comparison result signal is still for one

stored in one of the flip-flops 2529er, 2529 6, and 2529c for another purpose. The geset / -th outputs of flip-flops 2529a, 25296, and 2529 c are connected to the AND gates 2531, "25316 and 2531c and the OR gate 2532nd The set outputs of the flip-flops 2529 a, 25296 and 2529 c control ^ij the sub-bit time pulses at the AND gates 2531 a, 2531 b and 2531 c. At the time of sub-bit time

■ ■■ 3-pulse, such a pulse opens the AND element

■ 2533 and brings the flip-flop 2534 into the basic position. I The AND gates 2531 α, 25316 and 2531c and Ϊ 2533, OR gate 2532 and flip-flop 2534; ■ serve for transferring data from sub-bit time. Channel to any other. Purifications for the further ER- I Assume that the incoming I field in the sub-bit time channel is 1. On the other, the two * ren sub-bit time channels are treated in the same way the I bits of the incoming field are given I via the AND gate 2531a to the set input of flip-flop 2535 I a. The set output of the I flip-flop 2535 a is controlled by an AND element 2536 a controlled in the sub-bit time I channel 1. The sub-bit time channel 1 pulses are supplied by the line 2537 a.

The bits which pass through the AND gate 2536 a are supplied through the variable delay line 2538 to the recording head 2541, where the bits in the track buffer 2542 of the turret 2101 (F i g. 19) inscribes. The bits are read by the read head 2543 after 32 character times (4 fields) and are fed to the AND gates 2546 a, 2546 b and 2546 c via the variable delay line 2545. Each of the AND gates 2546 a to 2546 c receives different sub-bit time channel pulses. The AND gate 2546 a receives the pulses of the sub-bit time channel 1. The AND gates 2546a to 2546c are normally open due to their connection to the basic position outputs of the flip-flops 2529a to 2529c. Only when a new field is fed to line 2523 is the relevant flip-flop of group 2529a to 2529c in

% o brought set position and deletes the old contents of the turret in the place, the new field is to be stored in by the corresponding one of AND gates is closed C to 2546 2546a. The flip-flops 25356 and 2525 c are func-

JS function like the flip-flop 2535 a, but they work in the sub-bit time channels 2 and 3. The AND gates 25366 and 2536c receive their sub-bit time channel pulses via the lines 2537 6 and 2537 c . The flip-flops 2547 a to 2547 c transfer the characteristic maps to the storage turret 2102 (FIG. 19) in the order of the sub-bit channels 1 to 3.

The flip-flops 2547 a to 2547 c, the AND gates 2548a to 2548 c, the sub-bit time pulses on lines 2549 a to 2549 c and the comparison result signal on lines 2077a to 2077 c work as a repositioning system for the three sub -Bit time channels. The storage turret works in the same way as the buffer turret. Only the deletion of the old fields takes place differently in the storage turret than in the buffer turret.

C is the comparison result signal in the lines 2077c to 2077 in the inverted L'mkchrgl'.edern 2551a to 2551C, so that an active comparison result signal is for closing the corresponding one of AND gates 2552a to 2552c. The output of the memory is controlled turret c through the AND gates 2553a to 2553rd The AND gates 2553 a to 2553 c are also supplied with sub-bit time channel pulses on the lines 2554 a to 2554 c. The control signal is supplied separately for each sub-bit time channel via the lines 2555 to 2555c during the time of the comparison in the comparison arrangement. The three maps are taken from the storage turret via lines 2556 a to 2556 c and fed to the comparison arrangement.

Two sorting systems are described below. The first system is a two-way mixing system, the second is a three-way mixing system. In the two-way mixed system , the data set groups grow with the powers of 2. In the first run, two data sets from different groups are combined to form the first subgroup. In the second run, 2 subgroups from the first run form a new subgroup of 4 data records. In the third run, 2 subgroups of the second run form a new subgroup of 8 data records. The two-way mixing system only requires one comparison arrangement.

29 30 ■ I.

In the triple mixing system, three rations of the system are inserted each time, as is the case with somewhat un-subgroups of the previous iteration of ordinary operations. The arithmetic func- tions are combined in a new subgroup, which the three functions are not always used in tabulation and ver i; times the number of data records required by an original dividing function. The arithmetic radio :;. Subgroup did. The subgroups grow with 5 tion, however, is usually part of tabulating, since 'each run with the powers of 3. In the three - this one function with a constant addition bin mixing system, three separate comparisons are made. The distribution function can also be carried out, for which three separate comparison arithmetic operations are combined. The voltages can be used. The first group control program controls the comparison arrangement then compares the maps of the io management of these functions in accordance with the comparison processes carried out by data records 1 and 2, the second comparison arrangement, primarily von Zwiver compares the maps of the data records 1 and 3. This means that the maps are divided into four groups. The third comparison arrangement compares the characteristic diagrams. After each part, the field of data records 2 and 3. Intermediate comparison result generates a signal so that it can be fixed. In the triple mixing system, three results 15 can be set in which part of the characteristic field is generated which normally occurs through an AND change. Depending on this link arrangement, additional operations will have to be processed in order to arrive at intermediate results, an end result which is clearly carried out, which are specified by the group control program in accordance with the program, the characteristic field with the program. Such a program with the highest or lowest priority is identified by 20 and a table and distribution function is also used to track or indicate which characteristic diagrams are the same. That described standing.

The end result will be according to the program. Various operations must be performed

Instruction processed. The number of times for a three to be to prepare the map. The first

multiple components required in the operation is the selection of the fields from the

The circuit arrangement is larger than in the case of two data sets that are required for the map.

fold mixing system. This is done by the field selector 2746, which is

It is also possible to use quadruple mixing systems or gram-controlled, the format of the data record.

to build even higher quality mixed systems. One gets played and depending on the group

such a system would operate on the triple mixing system. The selek- '

be very similar and also work like that. The number of 30 fields are assigned to the field turret 2747.

the number of passes required is reduced with the one that saves the selected fields. The ⁱ

Number of comparisons made at the same time. saved fields are not yet in the correct j

FIGS. 21a and 21b, referred to for short as FIG. 21, refer to the position in the meantime. the

show a general representation of the data processing- selected fields are made by the field justifier

management system. In this system the memory 35 has put 2748 in the correct position. The field '

tracks have a length of 4 data records and justifier 2748 consists of a step-by-step switching ^s

4 filled sub-bit time channels. There can be a delay line, which makes it possible,

of course also differently usable mailing, incoming data in each of eight intermediate positions

systems are used. To position the data processing operations in a fixed field. In this ^

system consists of the sorting circuit and the case the field justifier works in such a way that it does the

Arithmetic part. selected fields are positioned so that the last,

The data sorting arrangement, which is in the character in the first character time of a field,

upper left quarter of the drawing is shown The alignment of the fields consists of the _{

and from the top chain of components shift the selected fields to the beginning of the '

is a data sorting and shuffling system, which contains 45 fields, characterized by a field start signal,

works in a similar way to the one described. The aligned fields are in the Paffer-Revol-. '

Systems. That is to say, the data sorting arrangement serves as a preliminary storage for the storage turret 2749

sorts the data in an increasing order or serves, saved. The buffer revolver is called,!

falling order as desired. Only intermediate storage is used to increase the capacity of the _p

starting from sorting, any usable 5 ° storage turret can be enlarged. The storage revolver,

The sorting system already described, instead of the one in the ver, is the main memory for the comparison arrangement.

The system shown in Figures 21a and 21b uses nung2751. _L.

will. The storage turret consists of a storage ~,

The computer part of the data processing system for each map, which is the comparison arrangement

21 performs all arithmetic functions that are supplied to 55 at the same time. The time it takes for the ^s

Distribution functions and tabulation functions that are required with the comparison process correspond to the ■

are connected to a group control program, length of the map and corresponds to the length of _i JJj ¹

the end. The arithmetic functions Ad- four fixed fields will match. After four fixed field _{d (}

dicing, subtracting, multiplying and dividing times is the result of the comparison on line ^

carried out. The tabulation function is given in Ad-60 2752. In a group control program, ^

dicing and subtracting data in verticals that is carried via line 2753 has the _d .

Columns correspond to the structure of the data records. equal arrangement to provide 2751 output signals, g '

Distributing is the transfer of a column of one at the end of each field time. The intermediate _w

given data set in one of several columns comparison results from the comparison arrangement 2751 ~

after specifying a code that is found in the data record, 65 are put on line 2754 . The J

hold is. equal result on line 2752 controls all over-

The arithmetic distribution and tabulation radio transmissions of information units via the control,

functions are included in the normal or ordinary operation for early reading and transmission, the _p

j 31 32

P " i Group control and the control of the arithmetic - two consecutive data records no sub-

! circuit. If there is a difference, the field to be transferred must be in the

£ "I In order to store the fields of the data records in arithmetic, tabulating memory track in channel 1

? "J Edit distribution and tabulation operations to the, after it has acted on the content in channel 1 of the re-

i can, these fields ν; r must be prepared as 5 gisters were added. If the maps have a

^l * ~ I show this loading for the preparation of the maps difference in the first field time, must

¹¹ } was written. the content of channel 1 of the corresponding tabulation

5 ^s I The fields are added to the content of channel 2 in a register via line 2755.

ⁿ "· Field selector 2756 supplied. This field selector The new field is stored in channel 1. At

. 1 works exactly in the same way as the field io of a change during field time 2 of the in-

^v } ~ i selector 2746. The selected fields are changed from field to the content of channel 2 on d des

ⁱⁿ j the field selector 2756 in the field turret 2757 channel 3 of the corresponding tabulating register ad-

¹ ^ j transmitted, which dates similar to the field revolver 2747, channel 1 is transferred to channel 2, and

I i is. The selected fields remain in the field - the new field goes into channel 1. With a

j revolver 2757 until it is changed in the field justifier 15 at field time 3 of the

^en j 2758 can be positioned. At the same time, the field justifier changes the content of channel 3 to that of the

^en · 2758 consists of a stepwise switchable channel 4 added, the data of channels 1 and 2 are

° * I delay line, which is transferred to the higher channel by means of an input sequence proce- dure. if

V * is ¹ · program controlled from the Prograramgerät 2759th on the other hand a difference to field time 4 between two

'.' The input program supplies a signal at the time that 20 characteristic fields are determined, then the content must

I needed the field in the following part of the arrangement of channel 4 to be transferred to another memory

; will. In the arithmetic process, the field will become. The data from the other three channels arrive

^ ^te : which leaves the field justifier 2758, the field in the next higher channel. The whole ope-

^ ^m revolver 2761 supplied, which is used as working memory for ration by the group control program

^ ^1- the arithmetic circuit is used. The arithmetic 25 controls.

^lO ~ ■: circuit 2762 performs the operations addition, sub- A third line 2771 is connected to the second read

^'U ~ traction, multiplication and division by. The device 2772 for early reading is connected

JP ~ arithmetic circuit is carried out by an arithmetic and leads selected data records to the field selector

* Program-controlled that comes from the associated pro 2773. The field selector 2773 corresponds to the selec-

^l y ~ part of gram 2763 originates. The arithmetic proto- 30 tor 2746 and selects the fields to be printed out in

/ ^e gram can be determined by the comparison result on the dependency of a program and a format

y; Line 2764 can be controlled. The arithmetic data on lines 2774 and 2775. The selective

. The program delivers the instructions and the address fields must be brought to the print format

ij ^r 'of the fields undergoing the process, which are independent and not identical to

. ": should. The instructions are: Add, Sub- The field time format is used for the maps

^[ } ' tracing, multiplying, dividing. It is continued and the ones used for arithmetic and other purposes

. ' indicated at what time the operation will find required fields to be used. A compressor

If ¹ "must be carried out. 2776 for data records positions the fields, this one

j ^m For the distribution operations, a field for Compressor 2776 must be used by the print format on the

a time can be stored in a field turret 2765 40 line 2777 controlled. The 2776 compressor is in

rf the. There are four memories for the distribution process, each selected field in any one

Tracks with 32 fields each are provided to bring the four positions. The selected fields are

f ^r "are nested. At least one write in the output memory track 2778 is put together.

, ^s ; head provided. The field which is in one of the This output memory track 2778 has four write

^ia . If the division memory tracks are to be turned off, 45 heads must be distributed around the circumference. The newly assembled

?} ' -i remain in the field turret 2765, with the distorted fields in the output fc memory track 2778

, ι speaking field registers of the distribution memory track can be an on- or off-line printer 2779 to-

f ) are on the write head. Then it can be guided.

j ί Leave field turret 2765 and save the three lines 2781, 2755 and 2771 of the

° l ~ ; the. The register and channel in which the 50th order of FIG. 21 get the records from

j field is to be saved by a signal on the second reader 2772 for premature

j Line 2766 is displayed. The signal on line read from collective storage lanes 2782a and

^ier j 2766 is used by the group control program of the 2782 ft. A first reading device 2783 for previous

y ⁿ &! part of the gram 2767 delivered. timely reading transmits read data records

^len j The third operation is the tabulation process. It 55 has a field selector 2784 and a signal decoder

^3er j gives 32 tabulation registers, nested four times in 2785 to form a program selector 2786 and one

° ⁿ 1 of a storage track of the disk storage 2768 ,. on Format Selector 2787. This is necessary to enable the

to which also the distribution memory tracks are arranged, the appropriate program and the associated format

^ing ': are. The fields concerned are first selected in before a data record is added to the circuits

^m> an input memory track 2769 is stored and 60 of FIG. 21 is subject to the various processes.

^he ~ then transferred to the tabular memory track. Which is thrown. The first reading device 2783 for

^rn> input memory track is selected as intermediate storage for timely reading one data record at a time,

^; ": applies. The channel and the register in the tabulation which correspond to the data record that is generated by the second read

Memory tracks are selected for premature reading by the group control program device 2772,

^ ^r 'grams marked in the following way. 65 leads.

^2r "The map has the length of four fields. The selection of the program and the format;

^J ,? "The comparison arrangement therefore works while four is determined by the second character in the data set.

Field times. If between the maps of is correct, which indicates which type of data:

it is about. The second character of the data record, the controller works as a memory for sub-bit time

the addresses on the sign "start of the information unit". The collective storage track load control follows, indicates the category of the data set. The 2802 controls the output of the disk storage 2796a field-selector 2784, the field of the already mentioned and to 2796 d itself from the controller 2803

Selector 2746 is similar, always selects this s for early reading and transmission controlled,

second character. The selected letter is assigned to which the storage area of the disk storage, which

Signal decoder 2785 which selects the signal memory track and the sub-bit time. the

the letter is decoded and from this the address sub-bit time pulses graze on the responsible

Instruction derives. The address instruction must be on the memory track on disk storage 2767.

be contained in the program memory track 2788, io supplies. The charging unit 2801 consists of the group

in which the program is stored. pin switch arrangement 2067 and the memory track and

The selection of the program is carried out by the per-group selection arrangement 7075 in FIG

program selector 2786 carried out, which the program shown arrangement. The collective memory lane loader

gram with one of the four heads 2789a to 2789 d control 2802 consists of the memory track and

reads and transfers to the program turret 2791. 15 Group switching control 2073 and the storage track

The selected program remains in the pro and group selection control 2076 in the

gram revolver 2791 until needed. Similar to Fig. 19 shown part arrangement,

As with the program selection, the format is The unit that carries the input data

driven from the format storage track 2792 by the for- through a separate arrangement and

mat selector 2787 selected, which does not need format 20 with drive 2804, which drives the shaft ',

with one of the four read heads 2793a to 2793 d reads 2805 drives at a predetermined speed, syn-;

and transfers it to the format turret 2794. To run that chron. The disk storage 2796a bis _]

Format remains in format turret 2794 until it is 2796 d and 2767 are arranged on axis 2805

is needed. net. The synchronous drive can, for. B. from a two- _c

Fig. 21 is a schematic block diagram of 25 poI engines. A drive synchronization unit j

One embodiment of the data direction 2806 shown in FIG. 17 corrects the phase differences between the two

Processing system. 21 shows the central view of the drive 2804 and the external drive j

unit of the main memory system 755 in further by briefly braking one of the drives, to

Details so that FIGS. 17 and 21 together have the phases. The technique of phase

the entire system excluding the serial access correction of two drives by briefly disabling

Represent memory. switching of the drives is known. _s

FIG. 21 shows the central processing unit of the working The data selected by the program 2788 _s .

Storage system 755 and the »output compressor are fed from the loading unit 2801 _vs

759 for the printing unit 764 of FIG. 17. Let us consider the collective storage tracks 2782a and 27826 ^

assumed that the data has already been received from one of the inputs 35 via lines 2807a and 2807 ft and the ρ

transfer means 756 and 757 of FIG. 17 to the dynamic write heads 2808a and 28086. _{f [}

see memory 2795 are transferred. The data- The collective storage tracks work as storage tj

memory 2795 is shown as a disk storage and between the input disk storage and the

consists of four disk storage devices 2796a to 2796a "actual work system. To the data sets loading, _w

for storing data. _{The 40} also contains an access in the order of the data records!

Data storage 2795 the disk storage 2767, regardless of its position in the collective

which are the collective storage tracks, the revolvers, storage tracks. This is done by using

the tabulation registers etc. are located as described. allows multiple heads for one memory track. 5 27

Each of the four disk memories 2796a to 2796d The ones in the collective memory lanes 2782a and J q

stores data on both surfaces. Each of the 45 27826 stored records are stored in the J ΐΊ

Disk storage has a movable arm 2797a in order of their positions by the heads 2809a | _m ,

to 2797 d, which reads the read and write heads for up to 2809 d and 2811a to 281 id and for the | gj,

both surfaces of each disk storage system serve different purposes over the different lines; _nu

carry and which independently movable lines 2812, 2813 and 2814 transmit what through

are. 50 the first and second readers 2783 and 2772, respectively

The arm 2797a carries the read / write heads for early reading and the transfer station _vo

2798a and 275> 9a. The arm 27976 carries the write 2815 is controlled. The reading devices 2772 and _ne ,

Read heads 27986 and 27996. Arm 2797 c carries 2783 for early reading and transmission _e j _n

the read / write heads 2798 c and 2799 c. The arm station 2815 work depending on the control

279Td carries read / write heads 2798 a "and 55 is called 2803 for transfers to other parts of the

2799 d. Central unit. Readers 2772 and pjj

The read / write heads 2798a to 2783 for early reading and transmission _g jj ₍ '

2798a "and 2799a to 2799a" are read station 2815 consist of a combination of *!

fed to the loading unit 2801, which is supplied by the AND gating that is sent by the controller 2803 to- J ^ ₁

Program 2788 can be controlled via a collective memory loader 60, which depends on the project - rj _e

control 2802 is controlled. The loading unit 2801 gram takes place on the input lines 2816. The '^ e

consists of a plurality of AND gates, the program selects the sub-bit time. Furthermore _{Sp (}

the comparison result of the comparison arrangement is accessed by the collective storage load controller 2802; ^ s

be controlled. The collective store loader controller enters 2751 on line 2817 into the controller. [\ consists of a number of counters and flip-65 The sector pulses on line 2818 serve as' jd _e

flops. The counters of the collective store load control start impulses for the control 2085 in the _V0T

tion 2802 control the movement of arms 2797a-F i g. 19 arrangement shown. _sjty

2797a ", the flip-flops of the collective storage loader Each storage track of the collective storage tracks; Au

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2782 σ and 27826 is the length of four data records, each of which has 128 characters.

Furthermore, the data sets are nested 4-fold, so that each storage track carries 16 data sets. For each sector time each record can be read 281 la d through 2811 by one of the four heads 2809a to 2809 d and. The distance between an early reading header and a transfer header is two records. The distance between the reading heads for the first and second early reading is one data record. The distance between the transmission head and the reading head for the second early reading is 3 data records.

The premature read function is to read and manipulate data before it is transmitted will. The first early read reader 2783 reads the records to the program to select. The second reading device 2772 for the data of the comparison arrangement to explore which dataset is needed next. If an available data record is not required his program is saved. The data on disk drives 2796a to 2796 rf are not yet sorted in the sorting process. The program instructs the wards for the premature Reading and transferring via the transfer of data from the next data set.

Each data record is initially read by the first reader 2783 for early reading is selected and fed to the field selector 2784 via the line 2812. The field selector 2784 confirms from a flip-flop and an AND gate, which is controlled by the flip-flop. The AND element is opened by sector pulses not shown in Fig. 21 and by the next following one Drawing time pulse closed. The AND element of the field selector 2784 is therefore for the The time of the first character of each record, which is the code of the record, is opened. That Code character passes the field selector.

The field selector 2784 selects and transmits the code of the data set to the signal decoder 2785. The signal decoder 2785 identifies the code of the data set; d. i.e., the signal decoder 2785 compares the incoming character with all possible characters and determines its identity. Of the The signal decoder works as a comparison arrangement. Its one entrance is with a character generator tied together. Its other input is connected to a plurality of comparison arrangements, each of which is assigned a specific character. Any comparison arrangement in which a match is detected between a generated character and the code character, generates one Pulse. Each comparison arrangement consists of a flip-flop, two AND gates and two inverters.

The output signal of the decoder 2785 controls the program selector 2786 via the line 2819. The program selector 2786 selects the program corresponding to the code character from the program memory track 2788 using the four read heads 2789 a to 2789 rf.

The output signal from the signal decoder 2785 identifies the code Z 'character. If a plural is used by comparison arrangement, each of them has its own output line for Selection of the program. If the code of the data record can be provided multiple times, then a single comparative idea used several times will. The time when the positive comparison result occurs determines the code character.

The output signal of the signal decoder 2785 represents the address of the program to be selected. The selected program is fed to the program turret 2791, where it remains stored, until it is needed. If the next comparison result addresses the same data record group, will this program is required for the selection of the map. The output signal of the signal decoder 2785 controls the selection of the format of the data record via line 2821 with the format selector 2787. The format of the data record is the format storage track 2792 with the heads 2793 a to 27936 Taken and stored in Format Turret 2794 until needed. Each of the two selectors 2786 and 2787 has direct access or partial direct access in a known manner.

The program represents an instruction to perform a process on the next data. A The first part of the program is the general program and is recorded in a memory track. It denotes z. B. which fields are required for the map. A second part of the program consists in the connection of the circuit parts (wired program). A third part of the program is constantly recorded and relates to certain sequences of instructions.

Well-known types of programs identify "from" and "to" addresses and use several Characters for the address. In the present system, only individual addresses are used for "From" and "To" Bits used in certain positions. The program identifies the actual task as Adding, subtracting, dividing, etc. Subprograms can also be addressed that start with arithmetic processes are necessary. Due to the nested recording, one field eight programs can be saved.

The program remains in turret 2791 until the associated data record is fed into the system. If necessary, the program can be transferred to the appropriate circuit, which in a Bit timing occurs because most instructions consist of individual bits in specific positions.

The format is the arrangement of the data in the data set. It shows where the individual fields end. Nothing more is required because the operator knows the content of the fields.

As soon as the previous data record has been processed, the data record for which the Program and format have been selected. It comes with one of the heads 2809 a to 2809 rf and 2811a read to 2811 rf and over the first station 2772 for The premature read, controlled by the control unit 2803, is transmitted on the line 2813. That selected The program leads the data record to one of the field selectors 2746, 2756, and 2773 via the lines 2781, 2755 and 2771. The field selector 2746 selects fields for the map. Everyone who Field Seleclores 2746, 2756, and 2773 compare in time with a signal that was taken from the format, depending on the code, the instruction.

If z. B. the program instruction specifies to select the field 7, what by the binary code l_l_l_0 is specified, field pulses from

37 38

Format fed to the field selector. As soon as 7 field, both turrets then work synchronously

impulses of the format were delivered, opens the must.

corresponding AND element to match the positioned data from the field justifier;. to show. In other words, the selection program 2748 is programmed in the buffer and storage turret 2749, supplies the arrangement, the sequence or 5 stores. The buffer and storage turret 2749 the position of the field, in contrast to the arithme- can from two buffer turrets and two storage tables program, z. B. exist the positioning of the two turrets.

th field in the third position. The format specifies the The buffer turret 2749 stores the from the

Definition or limitation of the field. Justifier 2748 supplied data. The sub-bit time ₍

The fields selected by the field selector 2746 io assignment of the fields in the buffer turret 2749 is ι

are stored in the field turret 2747 in the same way as that of the fields in the storage turret I.

that the first selected field is in channel 1, which is at 2747. If the field leaves the field justifier 2748 , ι

The second selected field is in channel 2, etc. is a control signal for the individual sub-bit times;

The field turret 2747 works as a dynamic one which is not necessary. However, it is necessary to

Short-term storage for data. To know the delay time 15 of the. For this purpose, the field is inserted into the channel (

of the field turret 2747 is a field time to 8 intermediate transferred back, in which it is in the field turret 2747 ]

times, each with 8 four-way interleaved bits. For this purpose, the data is stored at the Aus t

with 256 microseconds. gang de «; Justifiers 2748 transferred to channel 4.

The revolver can be part of a storage track. The field justifier 2748 moves the selected ones

The information can be stored in a portion of a memory field by multiples of 32 microseconds. If '·; 2

track are recorded, a short time later the data leave the field justifier 2748 , are.; i

are read and returned to the write head in sub-bit time 4. The fields are then in; t

will. The information can be read out and transferred to the sub-bit times that it had prior to entry

an output line can be given when it was held in the justifier 2748 . The overpass ΐ.

wishes is. The data can be ro- 25 as described above with a flip:

animals. flop carried out as a bit memory. ]

The field turret can also consist of a delay

arrangement with upstream flip-flop consist of different sub-bit times of the buffer and \

hen. Once the field selector 2746. ^T nstruktions- turret memory 2749. The output of the buffer c

Signal for selecting a field receives, receives and storage revolver delivers the fields to the c

Also catches the between the field selector and the same arrangement 2751, which the fields in a

Field turret arranged flip-flop instruction- from the program on line 2825 specified travel {

Signals to record the data in the order of the sub-order. The group control program on

Store bit characters. The flip-flop thus operates. Line 2753 controls the intermediate results in groups

as a bit memory and transfers the pen control programs from the selector 2746 35 to the lines 2764, 2754 is

selected fields in the order of the sub-bit and 2752nd ;

Times to the delay arrangement. One data bit The program specifies the order in which the 1st

brings the flip-flop into the set position until the fields stored in the storage turret are on the ver 1

agreed sub-bit time impulses should participate in the output of the same. The order of comparison '■' · -. 1

Flip-flops open so that the stored bit can enter the 4 ° in the order of the sub-bit times f.

Exit can happen. The sub-bit time pulse must be carried out. I.

brings the Füpflop in the basic position to it for the The result of the comparison is on the line ξ

to get the next data bit ready. The flip-flop 2752 is given and reaches the s via line 2817

is used to delay the data bit within the controller 2803 in order to prevent the transmissions and the previous 2

Bit time. 45 timely reading of data records to the responsible person

The fields are controlled by a field justifier 2748 via digen stations 2772, 2783 and 2815 . the

the line 2824 from the field turret 2747 in the controller 2803 for the transfer and the pre-F

supplied in the same way in which it is read in said term also from the program via line E.

Field-P svolver are stored. The field justifier 2816 is controlled. The selection impulses are set to 2

2748 is a delay arrangement with controllable 50 line 2818, the sub-bit time pulses on the line

Delay Time. The field justifier 2748 brings lines 2826 a to 2826 d . C.

by delaying the fields in a zero position. If two data sets are to be mixed, then ²

When you exit the field justifier, the characters are displayed , the control 2803 indicates which data record is to be »

With the lowest value for all fields depending on the comparison result via the line. ^v

same drawing time, the zero position of the turret. 55 2814, disk storage loader 2827 on one of the ^w

The field turret 2748 stores 4 fields, one field of disk storage 2796 a to 2796 d are to be transferred,

in each of the four channels. Since each field consists of 8 lines, the comparison device 2751 indicates what ^

the field turret 2747 saves each data record that has to be done. The control η

32 characters in total. Since there are two field times for each field to the tion 2803 , the reading device controls 2772 and the _t a

Selecting a field from the turret 2747 with 60 selected data records, the field selector 2756 I ^s

are required, a total of 8 field times, for arithmetic, distributing and tabulating pro, E

64 character times to supply processes for the transmission of the fields. 'f s

needed from the field turret. The field selector 2756 selects the relevant:; ' s

The 2747 field turret has the advantage that it produces fields in a manner similar to that of the 2746 selector. The Ij ζ

can indicate when a selected field is available. 6 _S group control program on line 2828 of the Se- ii ^

is standing. This can be done in that a line 2746 allows the fields VoO 1 to be divided

chen is placed in front of the field, or by using the Require field selector 2756 , the selected fe e

mat is stored in a parallel turret, fields to the field turret 2757 and from there to the ji>

71 *

en field justifier 2758 to be positioned. The: Justifier 2758 is controlled by the input sequence program from program circuit 2759 , which in turn is controlled by the comparison result of the comparison arrangement 19 2751 via lines 2752 and 2829 .

The comparison result of the comparison arrangement m 2751 reaches the program unit 2763 of the computing circuit via the line 2764. The program st; unit 2763 controls the arithmetic circuit 2762, it it has a program memory track and a arrange- ■ W voltage, for converting program signals in n control signals door, the arithmetic circuit 2762. The \ - program signals are simple signals for the al basic operations or entire signal sequences as sub- 17 programs for major operations such as mulliplication.

The computer program is fed to the field selector; n 2756 via line 2831 and identifies the fields to be processed. The format signal on line 2830 gives the selector the posi-

n tion of the fields within the information unit. tt From the field justifier 2758 , the fields do not get either into the field turret 2761, from there to the arithmetic logic circuit 2762 , or into the field turret 2765.

ι A program indicates on the Fejd selector 2773 ,

J which fields are to be printed out. These fields are stored in the 2832 field turret. From there the fields get into the field compressor r 2776. The fields are then in the revolver 2832

saved.

f The field justifiers 2748 and 2758 work as

controllable delay line. The field compressor ■ 4 _: sor 2776 works similarly to a field justifier. The operation of the field compressor is described in more detail in the c explanation of the circuit.

It works depending on the program and inserts or removes gaps between the data.

l needs them to bring the individual characters into expression-Stelluni ¹ 7U. The data was transferred from the compressor 2776 to the output memory track 2778, where

r they remain until they are needed. The printer

2779 can work clock-bound or clock-independent or it can be an output typewriter.
; From the revolver 2765 the fields get to the

Distribution Track Field Registers 2833.; The fields can also be used to track the input memory

f 2769 and from there to tabulation memory track 2834

reach. The tabulation memory track 2834 is controlled by the group control program from the program work j § 2767 , from where in turn the distribution memory track 2833 is controlled via line 2766; ':': will. The comparison result arrives at the program ,; Γ Werk 2767 via lines 2752 and 2835.

I In the circuit arrangement of FIG. 21, the

i Ij Distribution function to separate transaction

I ns in a column or from the results of a column

; ü on several columns. The tabulation function is that ι 3 Write down various transactions in a column.

I The cross-calculation function is the processing

I different columns of the same transaction, they

* represents the group sums of the tabulation function

3 I z. B. Selection of fields and preparation of sorting

I animal values.

, I The F i g. 22 is a schematic block diagram of an arrangement for early reading and for preparing the sort value of the present invention. It can be used in the data processing system of FIG. 21 can be used, for example, for the circuit 2774 for early reading, for the field selector 2746, the field turret 2747, the field adjuster 2748 and the buffer and storage turret 2749 . These components work together to prepare the sort value for the comparison array 2751 , and the early read controller 2803 selects the unit of information from the in FIG

22 collective memory trace, not shown, as a function of the comparison result and the station 2772 for early reading.

The field selector 2746 is controlled by the program and the format via lines 2822 and 2823 and selects the fields depending on the program and on the format. The field selector 2746 controls the AND gate 2842 and the counter 2843. As soon as a field is to be selected, the field selector 2746 opens the AND gate 2842, and

ao the field is fed via line 2844 to flip-flop 2845 , which transfers the field to the specific channel. The counter 2843 counts the selected fields. The output of said counter is fed to the channel controller 2846. The channel controller 2846 controls the flip-flop 2845 in order to assign the selected fields to the channels in their order. The channel of a field is thus determined by the channel control 2846 , which in turn is controlled by the counter 2843 .

The channel control 2846 consists of 4 AND gates. For each selected field, the counter 2843 is incremented by the field selector 2746 . This means that the first selected field is transferred to sub-bit time 1, the second selected field is transferred to sub-bit time 2, etc. The fields are produced in a four-way interleaved revolver 2847 using A / B technology 8 characters long. The A / B technique is intended to indicate that two revolvers are used alternately with respect to the data records; the first turret takes the first record; the second turret takes the second record; the first turret takes the third record; the second turret takes the fourth data record, etc. As soon as the fields of one data record have been transferred to a field turret, the fields of the next following data record are fed to the other field turret.

As soon as all four fields have been selected, the counter 2843 switches from level 4 to level 1 and produces an enable signal which is fed to the field justifier control 2848 via line 2849 . The field justifier control 2848 causes the field turret to be read to determine how many character times the fields are to be delayed.

The field justifier 2748 works in such a way that the fields are converted into fixed fields so that the data bits can be used for arithmetic operations. The sub-bit time is used here to control the delay time. The field justifier control 2848 takes over the data which is to be delayed differently and establishes the same delay for all parts of a data field.

The dependency on the sub-bit time control and the turret input control 28Sl is transferred from field 1 to sub-bit time 1, field 2 to sub-bit time 2, and so on. The turret input tax

509 610/105

tion 2851 determines in which buffer turrets the data are to be transferred.

The F i g. 23 is a schematic block diagram of an embodiment of a field justifier which may be used in the data processing system of FIG. 21 as field justifier 2748 , for example. The field justifier 2748 consists of a sub-bit time transfer arrangement 2935 and a fixed delay line 2937, the delay time of which can be set in steps. The sub-bit time transfer arrangement 2935 operates as a bit memory and allows data to be transferred from one sub-bit time to another. As long as a field from the field turret 2747 (FIG. 21) is not removed from the field turret, the counter 2938 of the field justifier receives 2748 pulses and changes the delay time with each character time.

At the time of character 1 of a field time, the delay time is 256 microseconds plus 3 microseconds, which equates to a field time delay. The data is transferred from sub-bit time 1 to sub-bit time 4. 4 microseconds correspond to one bit, a character has 8 bits, and 8 characters form a field. After one draw time, the delay is reduced by 32 microseconds to 224 microseconds plus 2 microseconds. A number of AND gates 2939a to 2939 k is driven. These AND gates are switched by the outputs of the counter 2939 in order to select the correct sub-bit time for the purpose of controlling the sub-crossing time transfer arrangement 2935 and 2941.

The field signal is fed to an inverter 2942 which produces an output signal if no signal is fed to it and which in turn has no output signal if no signal is fed to it. That is, if the reversing element 2942 is not activated, it generates an output signal which closes the AND element 2943, which is connected to the input of the counter 2938. As soon as the AND gate 2943 is closed, the operation of the counter 2938 is interrupted and the data is delayed according to the position of the counter at the time it was stopped.

Any of the controllable delay devices 2937 and 2944 of the Justiner 2748 field delayed the supplied data for as long as this is required in order to reach sub-bit time 4. That is, the The output of each of the controllable delay arrangements 2937 and 2944 becomes 4 at sub-bit time controlled. E-- two controllable delay arrangements 2937 and 2944 are required, since each of them can only delay up to a maximum of 4 character times, since each character time delay has a Transmission of the data is connected in a different sub-bit time, but 4 sub-bit times are available and a maximum delay time of 8 character times is necessary.

The first character of a field is given to the field justiner taken with the arrival of the field start signal. The second character of a field becomes taken from the field adjuster one bit time later. Thus, by changing the Field delay can be brought into an exact position.

A field which is to be delayed for 8 character times is first fed to the sub-bit time transfer arrangement 2935 in its own channel and transferred to the next sub-bit time 1. The position in sub-bit time 1 indicates that the total delay of the field in the stepwise controllable delay line 2937 should be 4 character times plus 4 microseconds. After a character time delay, the field tries to pass the AND gate 2945 , which, however, is activated in sub-bit time 4, so that this field remains in the delay line. In the following character time, the field is in sub-bit time 2 and is again delayed by one character time. Then it tries the AND element again

2945 to happen, which is impossible because of the difference in the sub-bit time. In the following

Character time, the field is transferred to sub-bit time 3 and thus delayed by one character time. Only at the fourth character time does the field enter sub-bit time 4 and is delayed by one character time. In channel 4, the field can use the AND element 2945

ao happen.

The AND gate 2946 is closed because the field is delayed again by four character times must to get a total delay time of 8 character times. The field becomes from this

* s is basically fed to the sub-bit time transfer arrangement 2941, which in turn transfers it to the sub-bit time 1 by entering the field into the delay line 2944. The process of delaying is the same as that described for delay line 2937. The field is taken from the delay line 2944 via the AND gate 2947 with a total delay time of 8 character times.

The AND gates 2939 a to 2939 A: control the sub-bit time pulses with which the fields are entered into the controllable delay lines and which determine the delay time for the field. The delay times of 2 to 8 character times are made possible in two steps by the delay line and the AND gates 2939a to 2939 k and the OR gates 2948 and 2949.

For example, a total delay of 5 character times is replaced by a delay of two

Drawing times in delay line 2937 and a delay time of 3 drawing times in delay line 2944 is reached. The first delay time is controlled by the AND gate 2939 c , which controls the supply of the field for

delay line 2937 controls at sub-bit time. The AND gate 2939 / controls the feeding of the field to the delay line 2944 at the sub-bit time 2. The total delay time is specified by the fourth flip-flop of the counter 2938. The field canoe

the delay line 2944 via the AND gate

Bypass 2946, which is opened by the eighth flip-flop of counter 2938 via line 2951 when the total delay time is one character time.

The signal inputs of the sub-bit time transfer arrangement 2935 and 2941 are connected to the SetZ input of their flip-flops, so that each data bit brings the flip-flop into the set position. The AND element is one with the set output

each of the flip-flops of each of the sub-bit timing transfer devices connected and is driven by the sub-bit time pulses leading to that Belong to the sub-bit time in which the data is to be transferred.

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The F i g. Figure 24 is a schematic block diagram of one embodiment of a circuit for positioning fields. The arrangement of FIG. 24 is basically the same as the flip-flop part of the field justifier from FIG. 23 is similar both in structure and in operation. The flip-flops 2958 a to 2958 d form a counter and control a flip-flop 2959 via the AND gates 2961 a to 296Ld, which also receives the sub-bit time pulses. The sector pulses that go to the counter 2958 a to 2958 d are thus passed through the AND gates 2961 a to 2962 d to select the sub-bit time pulses and continue to get through the OR gate 2962 to the To control the position of the flip-flop 2959 and, in turn, to position the fields in the data line.

The F i g. 25 is a schematic block diagram of an arrangement of a universal delay line; which in the data processing system of FIG. 21 can be used. The arrangement of the F i g. 25 is particularly suitable for systems with nested information bits and can used for delaying data over the length of the delay line and multiples thereof will. The arrangement can just as well be used as a turret with many times the length of the delay line can be used or as a parallel turret for several data with the length of the actual Delay Time. This is made possible by having the delay line in a system with nested data is used.

In the delay line arrangement of FIG. 25 it is assumed that a <\ ü a sub-bil time is equal to one microsecond and that the delay unit is a field time.

If the delay line is used as a turret with several parallels and independent sub-bit times, the data on the input line 3044 are first transferred to a sub-bit time transfer arrangement 3045. The set and reset conditions of the flip-flop of this sub-bit time transfer arrangement 3045 are determined by the sub-bit time pulses on line 3046. The sub-bit time pulses 1 to X reach the sub-bit time transfer device as a function of the program control; during the time between the bit-time pulses, the flip-flop of the sub-bit time transfer arrangement works as a bit -Storage. That is, during the time between an incoming data bit and the next bit will cause the sub-bit-time pulses, the sub-bit time-transfer arrangement to work 3045 as a bit Speieher. This results from the activation of the AND element of the sub-bit time transfer arrangement 3045 by the sub-bit time pulses, as has already been described.

The data arrives from the sub-bit time transfer arrangement 3045 via line 3049 and OR gate 3051 onto delay line 3048. Delay line 3048 can be of any useful type, e.g. B. a device which works in such a way that it transmits a pulse by induction on a wire, this transmission carries out mechanically or by applying pressure.

The data traveling through delay line 3048 is one field time minus one Sub-bit time delayed. Because the real field time is 256 microseconds, an actual delay occurs by 255 microseconds. The data then pass a delay line 3052 from the Length of one microsecond so that the total delay is again 256 microseconds and that no change occurs in the sub-bit time allocation of the data. The 1 microsecond delay is through line 3053, line 3054, AND element 3055, delay element 3052, line 3056 and the OR gate 3051 performed. The data is sent back to the OR gate 3051 Input of delay line 3048. The delay line works in this case because of the four nested sub-bit times like four parallel turrets. All data from the sub-bit time transfer arrangement 3045 remain in the sub-bit times given to them by arrangement 3145.

The passage of the data through the one microsecond delay 3052 is signaled by a signal on line 3057, which arrives at AND gate 3055. The added delay of one microsecond in delay element 3052 is provided as the delay line 3048 is one microsecond shorter in its delay time than the total turret for the Delay of data needed without moving the data. The revolver can have so many independent and store various data as it has interleaved sub-bit times. If one or If several data fields are required, the overall arrangement is confirmed by a signal on the line 3058 to provide this. Such data is output via lines 3053, 3059, delay line 3061, AND gates 3062 and output line 3063.

When data is placed on line 3064 from the delay line, that data becomes the delay line at the input is offered in a different sub-bit time. So z. B. Data in sub-bit time 2, after one cycle, transferred to sub-bit time 1. When data is the delay 3065, which has a delay time of 2 microseconds, they will be included in the The next following sub-bit time is transferred as the total delay time now 256 microseconds minus one microsecond plus 2 microseconds, so a total of 257 microseconds. The sub-bit time conversion is made possible by the Program control at AND gates 3065, 3055 and 3067 determined.

Data passing through delay line 3048 is fed to delay line 3061 which resets the data to its original sub-bit time. The AND gates 3066, 3055 and 3067 are then closed. The output data pass the AND-Güed 3082, which is controlled by programmed sub-bit time pulses Y.

The sub-bit pulses Y are also fed to an inverter 3068 , which again is only

713

45 46 -I

The AND gate 3069 controls via the line 3071. Sub-bit time affiliation, which you are given by the
Since the sub-bit time pulses Y are given via the inverter sub-bit time transfer arrangement3045

3068 run, there is: AND element 3069 and thereby became. It is possible to do the arrangement with data ί also the AND gates 3066, 3055 and 3067 are loaded, which are from the output line 3063 in the ΐ j locks. 5 sequence of the sub-bit times were taken. <

As long as the sub-bit time pulses Y are not in front If the data of the delay arrangement in a
are, no signal will be fed to the inverter 3068 sequence, every time
supplied, it generates an output signal and opens when data parts are stored or removed 'j the AND gate 3069, so that all sub-bit time Im-, the remainder of the data via the ι pulse of times 1 to X, which are deselected by the program IO delay 3065 or via the line 3064, to the AND gates 3066, 3055 depending on the direction of the sequence. i and 3067 and this opens. A sub- If no change is desired, all of them happen
Bit time pulse Y on line 3058, to which the data is supplied with the enlargement 3052 and thus remaining> Inverse element 3068, does not leave this in its sub-bit time. _t generate output signal, whereby the AND gate 15 is intended to use the delay arrangement as a turret ar- f

3069 is blocked. This in turn makes the process work, so the data are passed through the delay ^Λ AND element 3055 via the line 3072 closed 3052. The arrangement can hold so much data? and the sub-bit timing pulses on line 3073 include how sub-bit timing is available. λ have no effect. This mode of operation means that the maximum length of data is equal to the length ι, all data that are fed to the turret are available to the delay line 3048 plus a microphone at any time. Second. All data remain in their sub-bit time

The delay line of FIG. 25 can also positions. j

can be used as a shift register. To this if the delay arrangement as a controllable I.

If the data is not working from the output of the delay for data, then the delay line 3048 consists of the delay line 3048, the 15 order, via the line 3053, the
Line 3054, AND gate 3055, delay line AND gate 3067, the two microsecond delay 3052, line 3056 and OR gate 3051 on line 3065 and the OR gate 3051. The
the input of the delay line 3048 back output of the arrangement is through the AND gate

given. Rather, the data is controlled via the line 3062 with signals in the sub-bit time Y. ν

processing 3053, line 3074, AND element 3067, delay 30 The delay time of a data record is given by s

gation 3065, line 3075 and OR gate 3051 determines the sub-bit time in which the data signal i '

returned on delay line 3048. when you enter it. If z. B. a data set e

The program signals close the AND gate 3055 of the sub-bit time transfer arrangement 3045 i _m u

and open the AND gate 3067 via the lines channel Y-3 is fed, so he can η

3057 and 3076. Data to be delayed 35 delay line 3048 for the first time to sub-bit n

Wt ^ ^{en can be taken from lines 3053 and 3077 for} time A - 4. The delay F

AND gate 3066 given. 3065 of two microseconds transfers the data k

The delay arrangement of FIG. 25 can be implemented in the sub-bit time X-2. If the data exceeds the F

also as a step-wise switchable delay delay line 3048 left the second time like this

line can be used. 40 they are in sub-bit time X - 3

If the arrangement is used in this way, delay 3065 then transfers the data to d

is to be, the output AND gate 3062 with sub-bit time XI. The data leave the server

the sub-bit time pulses of the last sub-bit time delay line 3048 for the third time to the sub-bit ^; - ri

controlled. The AND gate 3069, which the AND time X- 2. By the delay 3065 you get 5 U

, i «" ³⁰⁶⁶ ' ^{3055 and 3067 via the lines} 45 in the sub-bit time X. After the fourth pass:' zi

3078, 3072 and 3079 controls, receives the pulses through delay line 3048 are the data w

of all sub-bit times via line 3073. In dirser in the sub-bit time X- 1. The delay 3061 of t

Consideration Y is greater than 1, but less than X. the length of a microsecond converts the data into w

The AND gate 3066 is also from the Pro- the sub-bit time X, and the data can be the Ge R

program control activated via line 3081. 50 complete arrangement via the AND gate 3063 taken d.

Dates that will be forgotten about twice the time. The total delay time is ri

delay line are to be delayed, of which then three times the length of the circulation without sub- is

Sub-bit time transfer arrangement in 3045 in bit time change plus 3 microseconds. The data: pi

Channel AM transferred. After the simple ver at the exit of the overall arrangement are always in hi

delay line is the data in channel XI. 55 sub-bit time X. If desired, the same 'ei

The data passes delay 3065 with the high reference sub-bit time operation to ' di

Time of 2 microseconds and thus reaches the start and the data in a sub-bit time low

Sub-bit time X. After the second pass through ger reference number to end, the data di

the delay line 3048 is the data in the via the AND gate 3066 and the line 3064

Sub-bit time X -1. The total delay is 60 leads, instead of the AND gate 3067 and zi

now 2 lengths of the delay time of the total delay 3065. K

Order minus a microsecond. After the delay arrangement of FIG. 25, a <

Data the delay 3061 of the length of a can also be used to create gaps between

Microsecond happened. they stand in sub-bit see the data parts close. Such an si

Time X and can thus the delay arrangement 65 order then works as a compressor. The length ta

tion of theF ig. 25 taken from the delay line 3048 via the AND element 3062 is one character h n;

^me ". ^w " ^den : time, minus one microsecond. Each character 'w

The delay of data thus depends on the time the delay line becomes 1 in sub-bit time

47. - 48

guided. Whenever a new character is the character encoding that is used

delay line is supplied, the advance _e j _n 8-bit Ccde of type 1248ABPO, where

running characters in the next higher sub- 1 248 is the numerical part and ABPO is the Zo-

Bit time transferred. This is done using the AND part of the character. A bit in position P becomes

Element 3067 and the delay 3065 of 2 micro-5 used as a check bit, so that the Zonenteü also

Seconds. can be used for arithmetic purposes.

As long as no new character arrives, the entry points run. H. The second

stored characters by the AND gate 3055 half of a character zek an uncorrected re-

and the delay 3052 of one microsecond, resulting from the correction values K 1 and K 2 corrected

so that the characters are yawed in their sub-bit time positions 10.

remain. Since all data records are in the memories of the M & · Jie

As soon as the stored data is in nested sub-bit time positions from the

it I use the AND gate 3062 in the delay arrangement, such sub-bit characters can also be used for the

1 another circle is to be transferred, lukewarm arithmetic operations are used. the

r-! j fen this data via the AND _{gate 3067 and the 15} nested sub-bit time positions represent special

, g; Delay 3065, so that all the times of the increased bit positions in the memories between others

: n] delay arrangement represents data taken in their order. If data is stored in a dynamic memory

n. "j. This is achieved by storing records, so the distance between

ψ j the AND gate 3062 in sub-bit time Y drives the bits of these data records constant. The bits of one

> j will. Each of the data records is in the sub-bit time 1

χ. i The computing circuit works binary decimal in (channel 1), the bits of the second data set are available

j input and output. The adding circuit of the sub-bit time 2 (channel 2), the bits of a third

re j arithmetic unit works with binary characters until the data set is in sub-bit time 3 (channel 3),

ti. j value 16. This makes it possible to have the adding circuit and the bits of a fourth data record in the

_m ] to keep its structure simple. All input 15 sub-bit time 4 (channel 4).

e- } data are in sub-bit time 1, all output files. In order to simplify the flow of data, the e _r \ are in sub-bit time 4. Computing circuit _{performs the following operations in ver; c} j ^! During the addition, information 1 is added to information 2 from bit-separated "channels" within the same field. The sign re-time through.
-I ₁ i result must be corrected if it is higher than 9, 30

" _tz by adding a correction number K 1 = 6. The information 1 plus information 2: Channel 1

Itz final result consists of a corrected information 1 minus information 2: channel 2

_m and an uncorrected job result. The information 2 minus information 1: channel 3
_{; r} . uncorrected result is designated as result 1

it- net. The corrected result is labeled 35. The information is always treated as pong result 2. Uncorrected results below 10 and positive values. In the two subtraction corrected results 9 _s are the final operations so doing, as if the result; _r _ ■; Result, result 3, summarized. positive in both cases. One of these two Subtrak _so in the subtraction operation must by subtract tion results, however, must be negative, indicated by _r - are Henten the complement of 15 formed and 40 lack are then added a carry-over momentum in the highest üe to the minuend. At one point of the field is displayed. The positive sub-: r- subtraction with a positive result must be added in the low- traction result, which is characterized by an overriding digit, the value 1. The position impulse in the highest place and excludes the result, which is not corrected, carries the respective other result from the further processing with result 4. The result 4 must be corrected 45. At the end of the field time there is thus a positive result if the digit result including the tive result of the addition process in the "channel" 1 on ^: carry has a value less than 16, ie always and a positive result from the subtraction if the result 4 does not have a carry owns. The process in "Channel" 2 or in "Channel" 3.
ie- result 4 can be corrected by the value K 2 The control unit of the arithmetic circuit decides, m- ; the. K 2 is the complement of K 1 to 16. The cor- 50 of which of the results is the correct and desired one is labeled result 5 and and whether the result is positive or negative.
ib- is the final result if the overall result The information 1 and the information 2 are en positive, as this is supplied by a carry to the computing circuit in "channel" 1 and displayed in the highest position. The result 5 is added during the first half of the character zek. : hey an intermediate result, if the final result 55 Both pieces of information are negative by a sub-bit time to the subtraction, which is indicated by delayed, are then in "channel" 2, the Informa-Iridas absence of a carry in the highest Position 2 is passed via an inverse term, which: <; n of the result. the complement of the information 2 to 15 in every ^ e- Um generated in a subtraction with a negative result digit. The adding circuit then delivers an! Id to arrive at a final result, an uncorrected result of the operation must be: Information correction value jO for every digit of the result 5 tion 1 minus information 2. In addition, the values are added. The corrected result of intermediate information 1 and 2 a further time by a sub-intermediate result 5 is called result 6. The re-bit time is delayed and transferred to "channel" 3, result 6 is the complement of the final result, with information 1 running through a reversing element. _lg e tates 7 to 15, if the result of subtracting 65 performs the arithmetic circuit then the "Channel" which is en-negative third The correction value K 3 is the correction operation information Information 2 minus 1 by, ϊεη Ki value equal except in the lowest at the beginning of the calculation process will supply over-point. Carrying input of the adding circuit in the »channel« 2

49 50

and in "Channel" 3 each one bit is supplied, which is one ad and several delay lines with several dition of the value 1 to the uncorrected result of controllable outputs exists. equals in the smallest position. At the end of the test pulses run through the entire test

The numerical part of each character has an arrangement. The next test pulse through 4

uncorrected result for the relevant point 5 runs not only the entire test arrangement, but _z

ready to in a delay line of the even output to all AND gates is _s, out of the Prüflei- length of a character or in a corresponding processing. Only one of the outputs can transfer a memory. Lead signal. The length of the delay arrangement

In the addition process, the uncorrected voltage between the input and the active output

The result in "Channel" 1 at the input of the addition 10 of the test line corresponds to the length of a memory 4

circuit fed back to cherspur by means of the value K 1 and the speed of the disk drive. j ti

to be corrected. Whenever that doesn't work, the delay lines for the information | ρ

The yawed result or the corrected result are of the same type as the test lead and can |

Carry tripped, the corrected result nen by the output of the test line overall j _e

the right thing. If there is no carry over, 15 must be controlled. This output signal is in a s g

further processing the uncorrected result is saved as a trigger and opens the output f g,

use. of the information delay line, that of the rotating | \ _

In the subtraction operation this does not correspond to the grain number of the rotating accumulator. I _u

yawed result, which is in the memory of The number of outputs of the delay line | _st

the length of half a character is to be used- xo depends on its length, the sub-bit repetition rates? ³ _{S (}

when it is associated with a carry. Step and the possible speed deviation of the rotating ■ _tl

no carry over from memory during the subtraction process. The distance between two loading! j ₍

pulse on, the corrected result is to be used. B. half a micro- > 4

the. At the end of the entire drawing time, there is the second. The length of the fixed delay line ^: _UI

The final result of the operation for a digit to 25 corresponds to the highest possible speed of the rotie- _g;

Available and can be stored in field memory. The additional controllable ver [ _ni

will. At the beginning of the subtraction operation, the sum of the possible positive 4

the value 1 in the lowest place in the »channel« 2 tive and negative deviations from the norm - j

and "Channel" 3 can be added. The transfer pulses correspond to the speed. _s; of uncorrected results must always be in 30

the next higher digit can be added. This becomes Asynchronous Input and Multi-Channel Input gi

enables the carry bit to be in an A

Delay line the length of half a character Since a computer very often uses memories or ^

is saved. One must be connected to the corrected occur- input keyboards that ^

the carry pulse will only be placed outside the memory in the addition process 35, an _in

transferred to the next higher position. Connection arrangement used to connect the trains, 2 '

At the end of the entire operation, the guided information will be entered. It is ex- _sc

The results of the two subtractions are then checked to see if it is seldom that the outer memory or the outer; _te

a carry pulse occurs at its highest point, input devices use the same timing as the '] rp

which indicates the correct result. Have 40 computers that process the data, in particular- J _A ,

Meanwhile, the control unit, the more so where the information about Telefonlei- "^ l

Arithmetic circuit the instruction of the program or similar connections over wide ent- j ^,

converted and the desired result and distances can be transferred. In such a case, _sp

select the associated sign. the bit clock is the one supplied! Information very _un

Normally, a rotating memory rotates slowly, provided that it is synchronized with the clock rate of the Rechchron compares with the frequency of the supply voltage supplier. The information must therefore be

supply. As a result, the speed of the memory can be carried in the fact that it can be converted to characters bit by bit, _you

Range of about plus or minus 1 percent from character by character to fields and field by field to a full _mi

Face value differ. permanent information unit composed. - _m

A delay line has a constant displacement 50 It is possible to have several inputs at the same time j _{like this} :

delay time. The delay time for a service to be served. In this case it is assumed that J j _n

Delay line should always be of a certain length in the time of one revolution of the rotating memory f _c ^.

correspond to a memory track of the memory. If there is only one information bit g _{a per input connection}

a disk storage is fed to its peripheral speed. As the rotating storage unit is divided into several _wc

changes, changes the ratio between different 55 sectors can be divided, each sector can '. : _{e (} j

delay time and track length. The electrical must be connected to one of the inputs. _m

The delay line must then be lengthened or shortened. Assuming that the number of sectors is 8 | _th

according to the speed change of the ro- or 16, 8 or 16 keyboards can be set via J

animal memory. an input stage can be adjusted. In contrast j _ar ^

The delay lines that are adjusted 60 for this purpose is the first synchronous input I _{enl shown}

must consist of a test delay stage practically independent of the bit rate f _spc

device and one or more additional wedges with which the information is supplied. It is \ j _ei

delay lines. The additional delay only necessary that the bit rate with which; j) _a

lines must be controlled for the necessary time the information is supplied, lower than the; _ers

will. One of the disk memories has a storage speed of 65 bit in the machine. \ _Re

track on which test pulses are recorded. The input and output memories from FIG. 21 I g _ra

Test pulses are a test delay line through two static input-output core I _c hi

supplied, which replaces memory 4171 α and 4171b from a fixed delay line. A verse

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Ren ^ gerungsleitung 4172 takes over the task of the delay lines, which are used to record and

; Writing station of the arrangement according to Fig. 21. The groups of data records or fields in different

üf-: Information is saved from the input delay line to those time channels that coincide in time.

ch-, 4172 the delay lines 4173 α to 4173 d are mutually matched in order to memorize the data sets which work the role of the tracks for working together and the program information relating to

lei- \ put from the arrangement according to Fig. 21 take over. to save the time in different time channels,

a ■ <The information can be extracted from the delay lines. The first memory has the first static memory

■ around 1 4173 a to 4173 d via AND gate circuits 4174 a rather 4171a.

• us- j to 4174 d in the input-output core memory The data records will be transferred from the first static * ei- j 4171ft. The AND gate circuits in the memory of the memory system in the processing * take the place of the transfer station from memory of the memory system transferred, and at-Fig-21. closing from the processing memory in which a plurality of AND gate circuits 4175 to 417Sa d second static memory 4171 of the replacement processing that b arrangement of FIG. 21, transmitted back in the system. A control and verBits and information processing device for the first time in advance, in which the processing is also sensed. The information can be contained in this memory, the transmission of the AND gate circuits leads to a field selection circuit 4176 data records from the first static memory to the J and from this field selection circuit to a comparison processing memory and the return to the I circuit 4177. An AND gate data records from the processing ^{memory in the en} z circuit 4178 fulfills the task of the second switching 20 second static memory. If the data ^en tung ^be for the in-VorausabfühJen from the arrangement rates by the control and processing device - 104, passing the program from a program unit so arranged, the control and select-Verarbeiro 4179th An AND gate circuit 4181 converting the first order of the data ⁱⁿ S and an arithmetic unit 4182 convert the same articles into a new order. This is done f ^'e "j gave as the corresponding parts of the arrange- 25 according to predetermined instructions in the program ^he"] voltage according to Fig. 21. The input-output memory are included in formation, and j depending ^3S1 * 417 ? α and 4171 b work as distribution traces, as from the maps.

■ m- i tabulation tracks as well as input and output tracks. Correct stored information is derived from the first static memory. The ' The arrangement according to F i g. 26 operates in the same way as the arrangement according to FIG. 21 on the 30 different circulating delay lines. The 4173a to 4173r / store and process the arrangement according to FIG. 26 is a modification of the information sought, which is taken from the first sta-. ^The arrangement according to FIG. 21, in which the selected table memories 4171a have been read out. Time ^"le dynamic memory of the arrangement of Fig. 21, AND gate circuits clocked 4149a to ^ine in which the memory disks 2796a to 2796 d and 35 4149 Λ carry the information from the first S ^e ~ 2767 (Fig. 21) contained are, as well as the cooperation static memory have been read, the Ver ^he "reduction tracks 2782a and 27826 (Fig. 21), the encryption deceleration lines 4173" to 4173d "throughout loading" ^e graduation tracks 7833 (F i g. 21) , the input track 2769 agreed with temporal positions. The information ^of (Fig. 21), the Tabellierungsspur 2834 (Fig. 21), the delay lines 4173a to 4173 4 ZUJ ³⁰ 'j output track 2778 (Fig. 21), the program track 40 is guided, is also by the Programminfor ^lei "J 2788 (Fig. 21), the output track 2778 (Fig. 21), information from the programming circuit 4179 ge ^nt ~ ^: the program track 2788 (Fig. 21) and the format controls. The data that is in the delay lines track 2792 (Fig. 21) α by the core memory 4171 4173α stored until 4173rf be under and 4171 b g of F i. are replaced 26, controller selectively processed by commands g in all the memory from the F i. 26 are parts of a core memory with a size of 45 program information in the programming unit. The data transfer is stored in 4179. The time-controlled transfer is controlled by an address system which, similar to the transmission and selection circuit, transfers selectively. which are arranged in a certain row must be addressed within an item of information that is to be processed from the delay lines 4173a to 4173a ″ in. The preparation of the data 50 the delay line memory 4172 into it. The in the Fi g. 21 and 26 is the same. The core memory delay line memory 4172 stores the data arranged in rather much more expensive than the individual data arranged in a particular row in components in the arrangement of FIG. 21. Dip. Parallel form, in order to selectively introduce this data through the use of delay devices, address switching of the second static memory, however, the reduction of individual building blocks 55 in certain positions or memory locations of the two to an extent that is considerably smaller than in known static memories,
ten systems. The delay lines 4173 a to 4173 d, of the arrangement according to FIG. 26 therefore have a ver which each contains, for example, a delay of the working memory system which can have several memories of 4096 microseconds. In these memories, a processing 60 is a plurality of groups of bits, characters, or fields, namely ^'1 B * memory included in the plurality of records together with in memory locations or storage positions, the ^medium-IS' the map data are stored, to each of the side in Relationship. The field selector! - * ^er records belong. This storage is in a processing 4176 and the comparison circuit 4177 comparative ■ ^"e first memory of the memory system in a first chen the corresponding bit with all other bits sequence carried out, and besides, production 65 and use the comparison results for several 21 grammiformationen in the Storage system stores operations or processes. Among these opera-τι- stores, which contain predetermined command words. The operation or processes is the control of the selective processing memory contains the dynamic transfer of data records from a memory.

53 54

contain cherplatz to another memory location, to introduce temporal position and also to increase information to rearrange the data stored in the memory from a very specific time position, so that the processing operations for the comparison results are further used to carry out such information selectively and serially under the program control of the 5 can be. The inner time period of the arithmetic radio dialing circuit determined by the timeout arithmetic unit 4182 corresponds to the delay during control functions. The arithmetic functions of the processing time. _ Be applied to a information from the different orbiting Verzogerungsleistatischen memory has been selected, α to the processing memory 4173-4173 d Ver delay line memory 4173a to 4173rf exceeded io delay line or the time selection circuit have carry 4172's and in the delay memory in common, in which the information from the various predetermined sequence of operations is processed. The result of this processing is stored in the second different time channels, so that static memories are transmitted back. The arithmetic- the bits of data sets that are in the various unit is combined with a shift register. 15 delay line memories are stored, while some data records can be transferred to the processing selectively in the shared delay line or in the delay lines 4173 α bis. , _ ".". 4173 rf supplied from the first static memory The bits of the data records are processed by the arithmetic unit, other data records in the same unit 4182 are processed with respect to time in different time delay lines. Although there are more than 0 channels transmitted in each and even in the arithmetic units of the static memory, only one operation ζ can be selectively processed with one another through a unit. Which is carried out, selected 4173 a to '4173 d operation sequences are processed in the delay lines field selection circuit 4176. Fields character or groups which are different from when this operation sequences derived entirely carried records in various Verführt they will deceleration lines in the second static storage 4173 a ₅ α to 4173 are stored d, rather stored. Since the static memories or those of the field selection circuit are always in operation with regard to the core memory time, the delay lines that are supplied in different time channels are enough to delay lines 4173 a to 4173 d selected and the field selection guide. The comparison results are applied to the circuitry in different sub-bit times, which leads to the implementation of the various sequences, can be sent to the comparison circuit 4177 to control functions. will wear. The comparison circuit 4177 ver-An active part of the entire shortening line works or compares the fields with one another, the control system has selected the time selection and time sequence before the various data records. The AND gate circuits 4151 α to 35 den are, and generate a signal via the result of this ver-4151 rf, 4152 and 4181 of the delay line identical, which is used to control other systems are programmed and allow a selection of operating cycles to be controlled. This comparative tive interaction between the circumferential result from the comparison circuit controls first Verzögerungsleiiungsspeichern and Zeitauswahi- via the AND gate circuit 4175a to 4175a "a circuit. The circulating delay lines 40 cycle in which the information can be the first time ab 4173 a to 4173 d Information through which is felt, and then a transfer time delay arrangement run through, in the supply cycle, which runs via the AND gate circuits a control of AND gate circuits as supply 4174 a to 4174 rf.

handle switch for various time delays The program information can relate to the time

acts so that information in the delay lines 45 in one of the sub-bit time positions of the meant introduced or stored from certain time seeds delay line 4172, channels of the entire delay line system and can also be read out to the program unit 4179 can be. The delay lines are carried out so that the data records or data fields The data records are processed in a program-controlled manner by the time selection circuit controls to be able to get information in a very specific 5 °.

For this purpose 26 sheets of drawings

71 *

Claims (10)

Patent claims: 1. Electronic data processing system for mixing, sorting, arithmetic processing of data records consisting of data fields and for rearranging individual data fields with a memory arrangement consisting of a number of dynamic, synchronously circulating memories for storing the data records with a format memory for receiving format information, the specific Select data fields or parts of data fields, and with a program memory which contains instruction information which prescribes the processing method for the data fields or data field parts indicated by the format information, characterized in that from the memory arrangement (Fig. 21, 2782a and 2782 b) the Data records can be read by a first reading device (2783) and read by a second reading device (2872) delayed by the length of a data record that the second reading device (2872) controls with a function of command and format information rten the data processing device for selection (2751), for switching (2833) and for arithmetic processing (2762) is connected that data fields or data field parts of a pre-sensing and transmission control (field selector 2746, 2756), which form classification terms and are read out by the first reading device (2772) , 2772), which can be controlled as a function of command and format information and which controls the data processing device, that the format and program memory (2792, 2787, 2794; 2788, 2786, 2791) an identifier that precedes each data record can be supplied by the first reading device (2783) for addressing command information or format information and that the format and program memories circulate synchronously with the memory arrangement storing the data records (2791, 2784 ) contains. 2. Electronic data processing system according to claim 1, characterized in that in each individual memory of the memory arrangement and the format or program memory several data records or format and command information bit by bit in the manner of a time division multiplex system are stored in several time channels. 3. Electronic data processing system according to claim 2, characterized in that Time channel transfer devices having controllable delay elements there are which data records or data fields or data field parts from one time channel to another convict. 4. Electronic data processing system according to claim 3, characterized in that a first input of a circuit (352) under the control of a first control signal (353) Bit of a data record is supplied and that this bit is fed to the output (356) of the circuit (352) under the control of a second control signal (354) at a predetermined time can be seen in such a way that this removed 3it lies in the desired time channel (FIG. 10). 5. Electronic data processing system according to claim 4, characterized in that the output of a first AND element (364) with the set input of a bistable multivibrator (363) is connected and the input of a second AND element (365) to the output of the Flip circuit is connected that the inputs of the first AND gate the bits of the data set and a first control signal for transmitting the bits of the data record into the bistable multivibrator (363) can be fed that the second input of the second AND element a second control signal can be supplied that the transmission of this bit from the flip-flop to the desired Time channel allowed, and that the output of the second AND element with the reset input the flip-flop is connected (Fig. 11). 6. Electronic data processing system according to claim 3, characterized in that it contains several cyclic storage devices (422, 423, 424), those controlled by the first Control signals (428, 429, 431), several successive bits via AND gates (425,426,427) can be supplied, the successive bits of data records in a plurality of successive ones in time Time channels are arranged, and that one of the output of the selected cyclic memory device, controlled by second control signals (438, 439, 441) via AND gates (442, 443, 444) successive bits are removable, the removed successive bits of data records in several successive time channels are arranged, which corresponds to the delay time of the selected cyclic storage device (Fig / 12). 7. Electronic data processing system according to claim 2, characterized in that the cyclic storage devices (422, 423, 424) all have a delay time that equal to or equal to a multiple of the delay times of the other storage devices is. 8. Electronic data processing system according to claim 3, characterized in that several delay devices (451, 452, 453) are connected in series and each of the have the same delay time of several successive bits of data records and that successive bits of data records in the delay devices via AND gates insertable (458, 459, 461) and removable from the delay devices (466, 467, 468) are. 9. Electronic data processing system according to claim 3, characterized in that it has a Time slot changing device (482) which includes each of a plurality of consecutive bits of data sets in a corresponding first selected time slot of each of the group of Arranges time channels, and that the successive bits of data records of a cyclic Storage device (485) are supplied via the time channel changing device and the bits of the data records are read out from the cyclic storage device via an AND element (487) 1774S45 η 3 7 4 are selected, along with others, when each bit is correspondingly mulated in one the second selected time slot of each of the data fields into the second storage device Groups of time channels is located (Fig. 14a). the memory arrangement result. 10. Electronic data processing system according to claim 9, characterized in that 5 ' to control the number of delay times cycles of the cyclic storage device (485) in the feedback line an AND gate The invention relates to an electronic data (488) is switched on (Fig. 14 a). Processing plant for mixing, sorting, arithmetic