DE1474315B2 - Circuit arrangement for controlling the delay of information as a function of test pulses - Google Patents

Description

3 4

rence between the occurrence of the test pulse on must be the sum of the possible positive and

The end of this delay line and the occurrence of negative deviations from the standard speed.

of the next test pulse. At this address.

In the figure, a test generator 36 a, ie

Fluctuations in the delay times are compensated, 5 in the present case the storage track of a disk

without the need for any further effort. Memory, test pulses with a repetition frequency that

Appropriately, the determination of the peripheral speed of the rotating storage

Time difference by counting the frequency of a chers corresponds. The storage tracks 36 b and 36 c

Counting pulse generator with the help of a counter are information storage tracks. The shown

guided. The counter reading is preferably based on the arrangement contains a test pulse line and a

end of the counting process in an intermediate register long and a short information delay line

transmittable, which in turn short-circuiting the device, which by means of the test pulse line with the

Delay lines of the information delay rotating memory are to be synchronized,

circuit controls. A head 37 α reads a pulse from the memory

One embodiment of the invention is in the trace 36 α and leads it to the delay line 38

Figure shown. to. As soon as the pulse read by the head 37 α

The figure is a block diagram of a circuit - a line 39 is taken from the delay line 38-

arrangement according to the invention. In the normal case, a trigger 41 is set in the SET position.

A circulating store runs synchronously with the freight. This makes an AND gate 42 conductive. the

frequency of the supply voltage network. The 20 pulses generated by a generator 43 can be used

Speed of the memory in the range of about plus pass the AND gate 42 and get over a

or minus 1% from the nominal value. Line 45 to a counter 44 with AND gates

A delay line has a constant displacement 48 and an associated matrix a measuring device

delay time. The delay time of a delay is formed.

line should always have a certain length of a 25 The counter 44 consists of eight triggers 46 a

Corresponding to the memory track of the memory. If one to 46 h. The counter 44 counts out pulses for so long

Disk storage its peripheral speed on generator 43, as the AND gate is conductive. So-

changes, the ratio between the delay soon changes the head 37 α the next test pulse

storage time and track length. The delay reads, the trigger 41 is in RESET via line 47

line must then be brought into position according to the speed changes, so that the AND gate 42 is closed.

the rotating accumulator is extended or forgotten,

be shortened. As soon as the second pulse of the delay line

The delay lines, which are adjusted to 38, are fed through it 16 AND

the must consist of a fixed delay gates 48 α to 48 ρ prepared via a line 49,

line and one or more additional routes 35 to the content of the counter 44 in an intermediate register

delay lines. The additional delay art with triggers 51 α to transmit up 51Λ. As soon

lines are controlled for the necessary time. the new test pulse in delay line 38

One of the disk drives has a storage track, appears at output 52 and is sent to line 53.

on which test pulses are recorded. The test length, the triggers 46 α to 46 ή of the counter

pulses are sent to a test delay line 4 ° 44 in RESET position. The counter 44 is

out, which consists of a fixed delay line and prepares for the next test cycle,

multiple delay lines with multiple The position of the control triggers 51a to 51A

controllable outputs. represents the length of a delay line. If

The test pulses run through the entire test- the speed of a rotating accumulator changes so

arrangement. The next following test pulse through 45 all connected delay lines are closed

not only does the entire test setup run, it can also be shortened or lengthened. The adjustment must

will also be carried out on all output AND gates of the test level. The steps have to be smaller

management led. Only one of the outputs can be used as the smallest bit distance in order to determine an exact position.

carry a signal. To enable the length of the delay arrangement.

voltage between the input and the active output 5 ° This means that every connected delay path exists of the test line corresponds to the length of a feed line from a fixed delay line, which is the track and the speed of the disk drive. highest speed of the rotating accumulator

The delay lines for the information speaks, and an arrangement for extending them

are of the same type as the test line and can delay line up to a value which is the

The output signal of the test line corresponds to the lowest speed of the memory. These

be controlled. This output signal is in an extension arrangement consists of several switching

Trigger is saved and opens the respective output delay lines of different lengths,

the information delay line, which is the rotary The figure shows two controllable delay lines

number of rotating memory corresponds to. tungen, one with a long delay time in the

The number of outputs of the delay line 60 lower part of the drawing, and one with a short one

depends on its length, the sub-bit repetition rate delay time on the right side of the drawing,

and the possible speed deviation of the rotating The long delay arrangement consists of one

the memory. In the case of the delay line 54 shown in the figure and the controllable delay

order is the distance between two neighboring circuits 55 α to 55 d, which in the

half a microsecond. The 65 circuit are equal to each other.

The length of the fixed delay line corresponds to that of the controllable delay circuits 55 a to

The highest possible speed of the rotating storage unit 55 d have different lengths. The circuit 55 a

chers. The additional controllable delays contains a delay line 56 a with the length

of three time units and outputs after one, two and three time units. The circuit 55 b contains a delay line 56 b with a length of 12 time units and outputs after 4, 8 and 12 time units. The circuit 55c contains a delay line 56c with a length of 48 time units and outputs after 24, 36 and 48 time units. The circuit 55 d contains a delay line 56 d with a length of 180 time units and outputs after 60, 120 and 180 time units.

The information is from the delay line

54 supplied via line 57 a to the delay line 56 a. Three output lines 58 a, 59 α and 61 α of the delay line 56 a and one line 62 a lead the information to the AND gates 63 a, 64 a, 65 a and 66 α after the delay times of 1, 2, 3 and 0 time units . These AND gates are controlled by the triggers 51 α and 51 b via a matrix 67 α and lines 68 α to 68 d . One of the AND gates is in each case conductive and carries the information via an OR gate 69 α to the delay circuit 55 b.

The delay circuits 55 b to 55 d operate in the same way as they do for the circuit

55 a. The information is taken from the circuits 55 α to 55 d via a line 71. The maximum delay time of the arrangement is a total of 255 time units. If two time units come to a bit time and a speed fluctuation of ± 1% is to be compensated, the delay arrangement must be the length of

755

2-2

100 = .6300 bit times

to have. In a system with four nested channels and an eight-bit code that results in a length of 196 characters.

The delay line described for a long delay time requires very few switching elements. In the same way, shorter delay lines such as line 72 can also be corrected. The controllable delay line works like the described arrangements 55 α to 55 ά. It contains a delay line 74 with an input line 75 and output lines 76, 77 and 78. The information arrives from the delay line 72 via the line to the AND gates 81α to 81d . The AND gates 81 α to 81 d are controlled by the triggers 51 g and 51 h via the matrix 67 d and the lines 68 m to 68 ρ .

The information passes through the conductive AND gate of the group 81 α to 81 d via an OR gate 83 to an output line 82. The delay line 74 has a length of 3 time units. The length of the delay line 72 can be varied by + 2 time units, that is to say one bit time. In a system with interleaved channels and an eight-bit code, the delay line is three characters in length.

1 sheet of drawings

Claims (5)

1 2 transferred and at the right moment in claims: to save their new storage space again. To determine these points in time correctly, and also to 1. Circuit arrangement for controlling the knowledge of which memory sector is currently passing the delay of information depending on 5 magnetic heads, it is also known to test pulses which are supplied by a cyclically operating test bits to the information source on a track of the disk storage, thereby, which as timing pulses or also to the margin that a test pulse generation serve to generate the angular position of the disk storage, tor (36 a) generates the test pulses which define the start of a cycle and their sequence in, the information, instead of being in intermediate registers, characterize the length of the cycle that is to be transmitted, lead through delay lines to this generator (36 a) with measuring devices. (44; 48 and 67) is connected, which signals This path prepares but in two ways to control delay lines in down difficulties. On the one hand, the speed of disk dependency on the occurrence of successive stores is not constant, since they usually generate test pulses so that synchronous motors are driven at the output, so that their controllable delay lines (56 a, speed have the same fluctuations as the mains 566, 56 c, 56 d) the information is subject to pre-frequency. One must therefore occur times with planes of rotation. Calculate number changes of 1 to 2% of the target value. 2. Circuit arrangement according to claim 1, da- 20 a frequency stabilization of the drive voltage characterized in that the delay line is the power to be expended and thus wasted (56 a, 566, 56 c, 56 d) in stages of bound effort because of unjustifiable. On the other hand, the delay times of the delay range can be set while the bit times are within a specified range. management lines especially when it comes to 3. Circuit arrangement according to one or more acoustic delay lines acts, temperareren of claims 1 and 2, characterized by the characteristics, so that whenever extremely high indicates that the timing test pulse by a requirement on the constancy of the delay delay line (38) is passed through, the times must be set, a temperature stabilizer Establishing the information delay line is necessary. gen equals and has a delay time, 30 The application is based on the task, not which corresponds to the cyclical occurrence of the information only the synchronism between one cyclical, ever, and that the measured temporal deviation is not more rigid, but somewhat fluctuating stood the time difference between the occurrence and speed of the working information source derive the test pulse at the end of this delay to another component of a computer system and the occurrence of the next test point, the one with a fixed frequency or number of revolutions impulse corresponds. works, or vice versa, but beyond 4. Circuit arrangement according to claim 1 also to clearly control the beginning of each cycle, or 3, characterized in that the loading d. H. thus also the phase position of the beginning of a cyst mood determine the time difference by counting the klus. Frequency of a counting pulse generator (43) with 40. According to the invention, this object will help a counter (44) takes place. solved by the fact that a test pulse generator 5. Circuit arrangement according to claim 4, generated pulses which the beginning of a cycle is characterized in that the counter reading and the intervals of which indicate the length of the cycle termination of the counting process in an intermediate that this generator with measuring device register (51 α to 51 A) can be transmitted, which is connected to its 45 lines which control signals for the short-circuiting of the delay lines of delay lines as a function of the gene (56 α to 56 d) of the information delay occurrence of successive test pulses controls. gen, so that the information is given at the output of the controllable delay lines 50 times occur. This circuit arrangement is particularly —— ~ times if the one delay element is a ver Has delay time that of the rotational speed of the hard disk drive at the highest possible speed, and if the rest of them There are data processing systems known, the delay elements such a delay time work with disk storage, and show that in steps of half a bit each rest that the individual information from any one delay between zero and the Transferring disk storage to another disk storage maximum time difference of the circulation times of the plate or from a hard drive 60 at the highest and at the lowest Umtor to another sector. In these systems, the running frequency is controlled by short-circuiting individual information can be set freely in each case. Stored places and through direct access. You can still use the time cycle test pulse accessible. pass through a delay line that To this transfer of information between the information delay lines see the individual places within the plates and have a delay time that corresponds to the memory, it is known that the inter-cyclical occurrence of the information corresponds to information in intermediate registers where the measured time interval between the time differences