DE1774945B2 - Electronic data processing system for mixing, sorting, arithmetic processing of data sets consisting of data fields and for rearranging individual data fields - Google Patents

Description

The invention relates to an electronic data processing system for mixing, sorting, arithmetic processing of existing data fields Data sets and to rearrange individual data fields.

The invention is based on an arrangement in which the data processing system with a memory arrangement, consisting of a number of dynamic, synchronously rotating memories for storing of the data sets, with a format memory for the storage of format information, the specific Select data fields or parts of data fields and with a program memory, the command information contains the editing method for the specified by the format information Prescribes data fields or data field parts is provided.

The invention is based on the object, through the use of dynamic buffers cyclic storage and a two-step processing, namely pre-reading and actual processing of each data record as well as the provision of format and program information which works synchronously with the clock of the buffer memory arrangement, to achieve a continuous flow of data.

According to the invention, this object is achieved in that the data records readable by a first reading device and by a second reading device by the time Length of a data record can be read with a delay that the second reading device with a dependent Data processing device controlled by Bctehls- and format information for selection, for Rearranging and arithmetic processing is linked to the fact that terms of order form and from the first reading device read out data fields or data field parts of a pre-sensing and transmission control are supplied, which can be controlled as a function of command and format information and which controls the data processing device that the format and program memory each Data record prefixed identifier from the first reading device for addressing command information or format information can be supplied and that the format and the program memory dynamic storage arrangements circulating synchronously with the storage arrangement storing the data records contains. A particularly favorable way of working results when in each individual Memory of the storage arrangement and the format or Program memory several data sets or

Format and command information temporarily in the manner of a time division multiplex system in several target channels are stored.

The arrangement can preferably be made such that they have controllable delay elements Time channel transfer devices are present, which data records or data fields or data field parts transfer from one time channel to another.

Further preferred and particularly favorable designs are specified in the subclaims.

The data processing system of the invention has considerable advantages over calculating machines with static memories and especially core memory calculators. It's compared to one Memory core is much cheaper to store data in a memory track. The data processing system The invention can perform a number of functions simultaneously while maintaining a core memory can only fulfill a single function at a time. The commands for a memory core must first be prepared and summarized in a program. Part of a core memory then has to go through an address can be addressed. The commands must then be read and stored in a register be convicted. This register is subject to other commands. A core memory is therefore slow.

A core memory control system is very expensive and 'can do with a memory core at a time only one. The entire memory only performs one task at a time, and its operating speed is in the range of 500 kHz to 1 MHz. The data processing system of the present invention has a higher operating speed than a core memory compared to its size and does not require individual control systems because individual control is required; the data are arranged in the data processing system in a fixed order. The need for memory cores is eliminated by synchronizing the memories directly.

With the calculators known today, the information is stored in different registers, and a program controls the processing of the data. Because the information and the result of the processing are stored in different registers, elaborated programs are necessary in order to Get results. In the data processing system of the invention, the data are in a specific order stored in memory tracks and therefore always available, thus creating the necessary program is reduced. The program practically only has addition or subtraction and a starting point to determine.

In the data processing system of the invention, each field of a data record is in a specific one Position saved. The program is stored one field length in advance so that selected Data can be edited directly and data editing can be done easily.

Programming is very easy, and different programs can be linked together very easily get connected.

The arithmetic operations of the data processing system of the invention are performed in less time and carried out at a higher speed than with arithmetic operation methods known today. This also makes them much cheaper than known methods for arithmetic operations.

In magnetic tape systems in which the data is stored in magnetic tracks, this necessarily results Idles. The data processing system of the invention allows the rollover or Skipping over undesired or unnecessary areas of data. The data processing system the invention thus preserves the advantages of magnetic tape, for example sorting To be mentioned in an order, these advantages are combined with the advantages of the working memory, too which, for example, include direct access to selected information.

The working memory that is in the file processing system of the invention can be changed like reels of magnetic tape as no need is present, to get access to all parts of the memory at the same time. This depends ίο together with the fact that the parts of the total memory are in the specified order and the data processing is only ever part of a part of the total memory takes place.

This reduces the costs of the overall memory, since otherwise all information is direct must be stored in an accessible manner.

In the following description, the principles and exemplary embodiments of the invention are illustrated in FIG Connection with the drawings explained in more detail, ίο In the drawings

F i g. 1 a and 1 b a representation of the sub-bit times,

F i g. 2 shows a representation of the sub-bit clocks, FIG. 3 and 4 show the derivation of the Sub-bit clocks from the bit clocks,

F i g. 5 is a diagram showing the nesting of sub-bit times;

F i g. 6 is an illustration of the format storage track; F i g. 7 shows a rotating memory with four Sectors;

F i g. Fig. 8 shows a character in binary code with four interleaving;

Figure 9 shows the first two bits of 1x5 records;

10 and 11 each schematically show a time channel transfer device for transferring data from one sub-bit time to another sub-bit time;

12, 13, 14a, 14b, 14c, 15a and 15b show block diagrams of further time channel transfer devices;

Fig. 16 shows a block diagram of an arrangement for successive selection of format control and program control data; 17 shows a block diagram of the data processing system ;

Figures 18a, 18b and 18c show a block diagram a circuit that can be used for sorting:

Fig. 19 shows a block diagram of another Sorting circuit;

F i g. Figure 20 is a block diagram of a buffer and storage turret assembly;

Figures 21a and 21b together show a block diagram the data processing system; Fig. 22 shows a block diagram of an arrangement for early reading and preparation one; Sort word;

F i g. 23 is a block diagram of a field justifier F i g. 24 is a block diagram for fault positioning;

Fig. 25 is a block diagram of a delay management;

F i g. Figure 26 shows a block diagram of an arrangement for synchronizing a delay line m a rotating memory.

Data that are processed here are coded.Table I shows the binary code of the characters, table: shows the alphanumeric binary code of the character

1 774 945 U 7th ^Ό 8 Table I. Table II Binary code Alphanumeric binary code

sign 1 Code position
2 4 , 8th 1 1 1 2 _t 1 1 3 1 1 1 4th , 1 5 1 . 6th , 1 7th 1 1 8th . . , 9 1 1 1 10 . 1 1 1 11th 1 1 1 1 12th _I. 1 1 13th 1 . 1 14th 1 1 15th 1 1 1 16 or 0

sign 1 2 4th Code position
8 A 1 BCO B. 1 1 A. _t 1 , 1 * · · C. 1 1 1 . . · D. . 1 1 •> ■ E. 1 1 1 • * · F. 1 1 1 ■ ■ t G 1 1 1 1 ... H . 1 1 ■ * ■ I. 1 . 1 1 • · · J . 1 1 1 ... K 1 1 1 1 L. . 1 1 1 . * M. 1 1 1 1 ... N 1 1 1 1 • ■. O 1 1 1 1 1 . · · P. . . ... Q 1 1 R. 1 1 . S. 1 1 , 1 T 1 1 U 1 . 1 1 . V . 1 1 1 . W. 1 1 1 . 1 X . . . 1 1 Y 1 1 1 Z 1 1 1 .

B a gest dun

Sut bit

Zei Da

SnI bit Ze

In the invention, each character is therefore through a characteristic 8-bit position code is shown in the explanations of the present invention expressions such as the following are used:

Sub-bit time or sbt:

Time of a subordinate bit bit time or bt:

Time instant of a bit with a certain significance character-time or cht:

Time in which a character is displayed Data record:

Sequence of related individual data sub-bit clock:

Control pulse sequence for subordinate bits Bit cycle:

Control pulse sequence for the character clock bits:

Control signal sequence for consecutive

Characters etc.

The bits of a character (letter, number) appear one after the other in a non-parallel system at a certain point in an arrangement. So that this arrangement can properly process these bits, this arrangement must be specified, at which bit position a appearing at a certain point Bit heard. A separate pulse generator generates a pulse around the for each bit position Define bit position. This pulse generator generates 8 pulses within the time required for the 8 bit positions of a character is required to occur at a certain point in the arrangement. These pulses represent the bit cycle ii of their sequence, each individual pulse defines a specific one Bit time.

The time between the first pulse of a group of 8 pulses and the first pulse of the following Group of 8 pulses of the bit clock is di <

Sign time. The first pulse in a sequence of eight-bit clock pulses is the symbol clock pulse.

In the explanations, a »Fixed dates

«5 field« eight characters. This is the first sign Pulse of a sequence of eight character pulses simultaneously a field clock pulse. The time between two Data field clock pulses is the data field time. egg

409 530/15

ίο

r szsr ^{contains 128 characters or} Jn ^^ L; |

Da efn? ETmSTexsystem to gain sub-bit clock for recording. . Sign *

nn? the D ^ SearteSg used is any one piece of information can always be set at a time by ν

S ZeU i? Sub B ^ ZeS UnSiIt. In the present 5 one of these four sub-bit clocks is synchronized

Sen Eri ^ teruneen is the number of bit positions den, i.e. i.e., a first group of information can hch

Z vt SSrfda each bit time is stored in four sub- in sub-bit clocks 1 and 2 led), a

S? Times subtent it _The bit time remains as before during a second group of information with Das S

Bit times is divided. The _{dependent bit} . _the sub-bit clocks 3 and 4 can be connected

pSSen ^M iS ^ ¹ ÄlSS ^ Bit-PÖtioneii »The sub-bit clocks can also be used for storage

FnneSb aniBH times are used by the sub-bit clock of an information item in a storage track

Tfinished the time between two successive ones. So the second data set will always use that

SeJsUbIBMTaMSSSTiSt the sub-bit time. Sub-bit clock 2 recorded. The sub-bit clock will

For the purpose of a more detailed explanation, it is also used to increase delay times

^{i l} ^ ^{SO result in SiCh 15 St} ~

HZein - time division multiplex of the invention will be the

BU time four microseconds, sub-bit time one data records are stored in dynamic memories

MiSoäund half a character time 16 microseconds. As shown in Fig. 5, the B.ts de

A "field" has 1 to 8 character positions. Character of a data record 1 in the sub-bit time 1 Fin word is a field of variable length »o positioned. The bits of the characters of a data record 2

and less than a record. A sector is positioned in sub-bit time 2. The bits of the

«The data record. In a memory track, characters of data record 3 and 4 are accordingly

up to four data records can be saved, so that 3 is positioned in the sub-bit time,

512 characters are then contained within a memory track. The four sub-bit times of a bit time can also In some examples, 5 was used in a group control program

Assume that there will be two records in each memory track. In such a case, there will be a sub-total

can be saved. positioned in sub-bit time 1, the group

Since the characters are nested 4 times, the sum can be positioned in the sub-bit time 2, me

16 data records with a total of 2048 characters are positioned in the sub-bit time 3, and in a memory track get saved. On a surface of the memory 30 the main sum is in the sub-bit time 4 positive

128 storage tracks can be accommodated on the stick.

A storage disk thus has 256 memories. This means that the bits of four different sDuren with 256 ■ 2048 = 524 288 characters are available on your data records in one bit time, two surfaces. A field pulse appears at Fig. 6 shows the format memory track. The format starts with the eighth character. A field impulse always relates to the "fixed" field. A sector impulse record. Each word in a record has an appear at the beginning of each record. Every format signal at the beginning and at the end. Since the ^Te: l of an information, which is transported a word with the Fortraeunesweg a Datenüber- format signal at the beginning, is in a control matsignal for the end of the preceding word sienalübertragungsweg £ ine sequence of time pulses 40 are identical, and! Since the beginning of a data record has the task of controlling the transmission identified by a special code character.Each time pulse train is also used, the format signal is at the end of the synchronization of the information, the word ahead, to the it belongs. The formal signal needs to run. The time impulses or the synchronizing impulses only consist of a single bit. As a result, there are on the control lines, what follows, in a system which has 4 sub-bit signals in the data lines and in which 6 positions are in a gene. 8-bit code for the representation of the characters shown in Fig la shows the bit clock pulses are used in one, 4 x 6 = 24 bit positions are available for signing time, and so that the formats for 24 different F i g. 1 b shows the bit clock pulses and the sub-50 types of data records stored in a character time-bit clock pulses in their temporal assignment. can be cherted. In FIG. 6, the lines drawn in the data processing system of the invention show format signals in the sub-bit time 1, the rotating memories are equipped with a special, while the dashed lines format signals are equipped with a clock memory track in order to show in sub-bit time 2. As shown, the data to be stored can be recorded in each format memory track for the length of a data level in relation to the clock. A set of 24 formats corresponding to the 4-fold special storage track contains the bit clock, a nesting and the 6-bit positions. Another special memory track contains the sub-bit. The format gives the signal at the end of the word T _a k _t and can simultaneously contain the location number of the field

The F i g. 2 shows this bit clock and the sub-bit 60 within the data set. Clock memory tracks. If there is no storage track for The format can be specified in the following ways the sub-bit clock is provided, this will be of the. First, it can be used as a word-end signal directly Bit clock derived with delay circuits. associated with the data. In this case FIG. 3 shows the derivation of the sub-bit clock from consist of no conditions whatsoever with regard to the field length Bit clock. As in Fig. 3, there are 65 entanglements. Second, the "word delay" signal may mean to obtain the sub-bit clock end «as a single pulse in the format memory the bit clock used. track stored in the manner already described F i g. 4 shows the extraction of the bit clock from being; it will then be the same for all data records

order, is that

: r from t werikann erden,; n with can 'Iern' ends tdem t becomes jn to

: n the rt. : s of time 1 itzes2 ts the chend

also always uses ppent that , and posi-

ormat of one zt a ι that For- / ortes iatzes

t-Zeirineni

: save

; just directly

Pre-research

11th

Type used. Since the front memory track is prepared before starting a new task, this must be done Signal "end of word" can be set for a minimum field length, d. i.e., it must be for the maximum word length Provide sufficient space. It is Z. B. possible to have 8000 machine units (4 digits), but only 97 units were counted (2 digits). The "end of word" signal in the format memory track therefore 4 digits (character positions) must be set after the preceding end-of-word signal. Third, instead of the end-of-word signal or an impulse that represents the end-of-word signal, to the format memory track can also store a field sequence signal. Fourth, in the case of one "Fixed" field length for each type of data record is neither an end-of-word signal nor a format identifier needed.

The four types of format representations are shown in Table III. In this Table III there is the Data set from the details A, B, C, D, E, F.

Lo Each character of the information is represented by a χ and each free space represented by an ο.

Table III Formats

First:

E F

Max.

XXX X X XXXX XXXX X XX

Min.

EEE E EEE

WWW W WWW

ABCDEF

χ I χ

EEEEEEE WWWWWWW

Secondly:

Max. Xxx xx xxxx xxxx χ xx

E W

Min. XOO xO xOOO xOOO χ xO

E W Data storage track Format storage track

Data storage track Format storage track

Third: pure format

I A I B j C I D | E | F I

Fourth: Fixed field length. All fields have the same length; z. B. 8 characters.

The field end signal is always in the sub-bit time in which the associated field is also located. Since that Format is a sequence of end-of-word signals, it also indicates the length of the data record.

A sequence of data sets, the characteristics of which are arranged in ascending or descending order, becomes referred to as the data record stream. So that a simultaneous access to each data record on a dynamic Memory is possible, just as many reading devices must be provided as data records can be stored on the memory. The distance between successive readers is equal to the fixed length of the data records and is called a sector. Gel to every sector a sector clock pulse. The time between two consecutive sector clock pulses is Sector time. In a system in which the records are stored nested, verrir the number of necessary reading and striding directions according to the number of in one Time available sub-bit times.

F i g. 7 shows a rotating memory irit Sectors, each storage track within a be carries four interleaved channels. The data; are in their order, each data record is ni orted.

Each of the data records is the same length or shorter than a sector. Data record 1 is 1 in the sub-bit time etc. of sector 1 are stored.

Fi g. 8 shows four characters a in their nested one

Positions.

9 shows the first two bits of 16 data records IV1 to 16 in their interleaved positions.

Table IV shows the nested positions of the records as shown in FIG.

Table IV
Positions of nested records

record sector
number Sub-bit time track 1 1 1 1 2 2 1 1 3 3 1 1 4th 4th 1 1 5 1 2 1 6th 2 2 1 7th 3 2 1 8th 4th 2 1 9 1 3 1 10 2 3 1 11th 3 3 1 12th 4th 3 1 13th 1 4th 1 14th 2 4th 1 15th 3 4th 1 16 4th 4th 1 17th 1 1 2 18th 2 1 2 19th 3 1 2 20th 4th 1 2

The Fiipflop 363 then remains in its tirunasiellung until a new data bit in the line ÄT there? AND-Güed 364 can happen to bring the Füpflop 363 into its set position. FiS 12 is a block diagram of another arrangement which can be used as a time slot transfer device.

The arrangement shown in Fig. 12 exists of three ring registers consisting of a delay line, each of which has a length s. corresponds to the smallest delay time,

■ i ring register 422, 423 and 424 has a \ niied 425, 426 and 427. These AND-SSr ₄₂₅ , 326 and 427 are ^ through

425, 426 and 427 via lines 432, 433 and

The time conversion device when transferring information from a memory location of a dynamic memory into another will now be described.

Fig. 10 shows an arrangement which is used as a time channel transfer device zui Transfer of data from one sub-bit time to another sub-bit time can be used. The time conversion device 352 can at its input for the data can be controlled via the control line 353 and at its output for the data via the control line 3S4. The data is supplied to the time channel transfer device 352 via line 355 and leave the facility on line 356.

The time slot transfer device of FIG. 11 consists of a flip-flop 363. The data bits are fed to the flip-flop 363 via the line 355. The supply of the bits is monitored by the AND element 364; this AND element receives its control signals via line 353. A data bit which passes through AND gate 364 brings flip-flop 363 in his seated position. The output control signal on line 354 is a pulse which is the AND gate 365 opens at a certain, desired instant in time to an output from the Bring flip-flop 363 on line 356 when said flip-flop is in its set position. The control signal for the AND gate 365 is also transmitted via the line 366 and the delay 367 fed to the reset input of the flip-flop 363 in order to return the said flip-flop to its basic position Uie / vusgiujgai ^ iiu ^ i, is to the input line zo directly connected. Such a memory is also called Revolver called.

Information that is fed to one of these delay lines experiences a minimum delay which corresponds to the length of the turret, as the delay time can be extended by whole multiples of this minimum delay time. The outputs of the turrets 422, 423 and 424 are controlled by the AND gates 435, 436 and 437, which in turn receive their control signals via the lines 438, 439 and 411.

Data leaving the arrangement shown in FIG. 12 can be removed from lines 442, 443 and 444.

Fig. 13 shows another arrangement which can be used as a time slot trainer. This arrangement in FIG. 13 consists of a plurality of delay means, only three of which are shown. These three delay units 451, 452 and 453 are connected in series. The output line of the third delay unit 453 is connected to the input of the first delay unit 451 via the line 454. The input lines 455, 4:56 and 457 are controlled by the AND gates 458, 4f> 9 and 461, these AND gates 458, 459 and 461 in turn receive their input control signals via the lines 462 and 463 and 464, respectively. The AND Gates 4i! 8, 459 and 461 control the inputs to the delay unit, which are between the delay units 4SI and 452 and between the delay units 452 and 453 and between the delay units 453 and 451.

The output line 465 is controlled by the AND gate 466, this AND gate in turn receives its control signals over the line 467. Information on the line 457 is corresponding to the Delay time of the delay unit 453 delayed and can of the arrangement over the line

465, but it can also be returned via line 454 to the entire

Arrangement to go through one more time and thereby a further delay in the amount of the sum of the delay times of the three delay units 451, 452 and 453. The information can run through such a revolver as often as required until the arrangement is via the AND gate

466 is taken. This means that information can be provided for additional times, multiples of the total

zögeru 452 ui The one with ni lettunj leitunj 468 ui each member member signal Di (nung <verw «shows« regisi the \ from one is called the Dad des Da <in e has to: Son mat and stai

the one thing about it Vi sp

delay time of the three delay units 451, tion. The arrangement of Fig. I4c consists of 452 and 453 which are delayed. a turret with a selecting input-The arrangement shown in Fig. 13 can also control and with a selecting output control with only one input line and with three outputs. The information reaches the time converter initiators if only the input direction 499 is via line 498. It can enter lines 456 and 457 through the output lines time converter 499 if they are replaced in 468 and 469 . the input control line has the same sub-bit time. Each of the output lines must be controlled by an AND signal in the input control line 500. The information elements 471 and 472 are controlled. This AND-mation is taken from the time conversion device 49S> under elements 471 and 472 its output control io the control of the output control signal on the signals via lines 473 and 474. Line 5Cl and via line 503 . 14a, 14b, 14c show further arrangements supplied to the turret 502 . The sub-bit time in which the information the time conversion device 499 can be used as time channel changing devices. These in the F i g. 14 is left and fed to the turret 502 , the control signal on the line 501 is determined by the arrangements shown consist of controlled ring 15. The] registers are made up of delay units. The length or output line 504 of the turret carries the requirement that the delay time of a delay unit depends on the time conversion device 505 . A selection from the shortest delay time, which is connected to any selection control signal on line 506, selects the one point of a circuit in which it is used. is required. The length of the delay unit 502 and the feedback unit 507 must then be a sub-bit time shorter than it exists.

the shortest necessary delay time is. The selection control signal in line 506 is

This means that the information is correct after each pass. The sub-bit time in which the information is located

of the revolver into a different sub-bit time. The information is sent to the time converter

Since the output of the arrangement is only fed by a signal 25 505 and this is done in a sub-bit time

is controlled in a certain sub-bit time, removed again, which is determined by the output

; the information has to make as many iterations as the control signal on line 508 is determined. So-

until it is in the sub-bit time of the output signal. long the sub-bit time of the information does not match the

This results in the delay time of an information- the control signal on line 506 matches,

mation in the arrangement disclosed in Fig. 14a 30 can pass the AND gate 511th that its

and 14b, from the sub-bit time in which it receives control signals over line 510.

stood, at the time when it fed to the revolver λ'οη this AND element 511 gets the information

became. tion via lines 507 and 509 to the turret

To pre-determine this delay time, 502 is returned. Once the information is in the same

the information on the line 481 in Fig. 14 a 35 sub-bit time is like the control signal in the line

a time conversion device 482 is supplied. An off 506 can send this information over line 512

selectable control signal on line 480 can be determined from the arrangement. The output of the

the sub-bit time in which the information is to be used. in

take is. An output signal on line 483 is controlled by line 508.

converts the information to a desired sub- 40 Figs. 15a and 15b are block diagrams of bit time. The information leaves this time conversion further arrangements, which can be used as a time conversion device 482 via the line 484 and can be used in the direction. The arrangement delay device 485 is supplied. According to the statements in FIGS. 15a and 15b, turrets have a specific delay time of the delay unit with nested storage of the information direction 485 , the information is in 45 and a controlled return time. Each of the arrangements shown in the next lower sub-bit time, with reference to the arrangements shown in FIGS. 15a and 15b, is bit-time in which it is supplied to the entire arrangement from a delay device which is called Rewde. If this sub-bit time does not co-operate with that of the volver and is of the same type as that in the output control signal on line 486, the arrangements shown in Figures 14a and 14b. This the AND gate 487 controls, if the 50 type of intermediate storage can be used in systems with the information through the AND gate 488 and via interleaved information arrangement, the line 491 to the input of the delay. The length or delay time of a device 485 is fed back. The AND gate 488 delay means depends on the shortest behavior for this transfer task a signal about the delay time, which is in the overall arrangement, the line 489. As soon as the information in the 55 in which this device is used, the same sub-bit time is required how the output tax will be. The length of the delay means is one signal on line 486, the information of the sub-bit time can be shorter than the shortest required arrangement of FIG. 14 a via line 492 delay time. This will cause the sub-bit time to be taken. Information with each circulation of the information in The arrangement according to FIG. 14b used at the input 60 of the turret changed by a sub-bit time. Through an AND element instead of the time conversion control of the output of the arrangement in only one direction 482 of FIG. 14a and instead of sub-bit time, the information then runs in the redes AND element 487 from 14a a time revolver for so long. until they have this relevant sub-bit setting device. The arrangement according to Fig. 14b has reached Z.eit. The delay experienced by an information in the same manner as that in Figure 65 mation in such an arrangement is thus shown in Figure 14a. determined by the sub-bit time in which they are

Fig. 14c is a schematic block diagram of order being fed.

Another implementation of the time conversion in order to set the delay time for an item of information in the

to be set in advance, the information in FIGS. 15a and 15b is transmitted via line 513 and a Control unit 514 is fed to a delay device 528. The control unit consists of a time urasetting device, as shown in Figs. 14a and 14b are shown; or from an AND gate, as shown in FIG. 15b. A selective control signal on line 429 determines the sub-bit time in which the information is to be transferred. The delay line 528! Can be made in any manner useful for this purpose, e.g. B. an arrangement which transmit the bits inductively via a wire, or mechanically by transmission a pressure from one end to the other end of the wire.

The information traverses the delay line 528 and throws into it minus one field time delayed by a sub-bit time. Since the field time in the assumed system is 256 microseconds the effective delay time is ao length of 256 Mülcro seconds minus 1 microsecond, so 255 microseconds. After the delay of 255 microseconds, the information by a 1-micro-second delay device 530 out, so that the total delay time is 256 microseconds, i.e. one field time, amounts to; the sub-bit time in which the information is available does not change. The 1 micro second delay device 530 can be referred to as return delay. The information experiences this delay of 1 microsecond if it is fed to the delay device 530 via the line 531 and the AND element 532. from there the information reaches the input of delay line 528 again via line 533. The delay line with its return corresponds to four normal parallel turret paths the fourfold nesting of the information. Any information taken from the control unit 514 retains its sub-bit line in which it was supplied to the arrangement.

The passage of information through the 1 micro-second delay device 530 is controlled by a control signal on line 539, which is fed to AND element 532. The additional One microsecond delay in device 530 is necessary because of the delay line 528 is one microsecond shorter than the time it takes to simply slide the information into the revolver is necessary. _

If, however, the information in FIG the delay line 528 exits and is sent over the line 540, it receives a different one Sub-bit time. Thus, after one cycle, information changes from its original sub-bit time 2 to the sub-bit time 1 over. The delay by a sub-bit time is controlled by the AND gate 542, which in turn receives its control signal via line 541.

In the arrangements of FIGS. 15 a and 15 b, the output line iS31 of the revolver carries the information to the control unit 543. This control unit can consist of an AND element, as shown in FIG. 14a, or also of a time conversion device, which is shown in FIGS 14b and 14c. A select signal on line 544 selects the information from the turret. As long as the inform time sub-bit is not in the same store, in which the control signal appears in the Lemmg 544 laf ° ^mat ™ ^{d "rch} _T ^ ™ ^D T member is passed 532, or in Fig. 15b, the AND Element 542, from this AND element the information arrives back at the input of the revolver 528 Control unit 543 can be removed.

The simultaneous processing of data in a number of ways Processing equipment will now be described. , -LJ- 1_

The arrangement of FIG. 16 enables these sequentially selection of the format control and program control data depending on identifying signals for groups of records. The arrangement according to FIG. 16 also enables the processing of selected heroes, which were determined by the format control. The way of processing is determined by the Program control determined. The signal belonging to the program control appears within the cyclic operation at the time the operation is performed on the field data within the cycle of a data set.

The program data indicate which of the fields identified by the dynamic formai data are to be selected and which operations are to be carried out on the fields.

In FIG. 16, the data sets are stored in the memory 591. In the first cycle of surgery they become a selection unit 592 for the Transfer format control program via AND gate 593. The fields of the record are selected by the selector 594 controlled by the record's identifier field. This selection is made via the AND element 593, which is controlled by the selector 594 via the line 595 will.

A plurality of format information sma in are stored in memory 596 and are selectively via the AND gate in the first cycle of operation 598 is transferred to the format memory 597. The format control program is controlled by the associated Selection unit 592 selected via AND gate 598. This AND element receives its signal from the selection unit 592 via line 599.

A plurality of programs are stored in the program memory 600. The desired will be Transferred to the program memory 601 via the AND gate 602 in the first cycle of the operation. The program is activated by the selector 594 for the identifier field of the data record by means of the AND gate 602, which receives its control signal via line 603, is selected.

The data stored in the data memory 591 is used in the second cycle of the operation via the AND gates 605 and 606 are transmitted to the comparison device 604. The transfer of the records to the comparison device 604 takes place as a function of the format which determines the fields. The transfer takes place via the AND element 605, which is transferred from the format memory 597 via the line 607 is controlled. Furthermore, the transmission is still controlled via the AND element 606, which is controlled by the program memory 601 via the line 608. The comparison device 604 compares the data record that has just been

19 20

leads is, with data records that are in other sub-bit- The following character indicates the format of the

Times are stored and, via line 609, the data record, i. H. the type and order of

are fed. The records, the different fields in the memory.

j 591 are stored, are also stored in the third. The format signals are sent to the format control

¹ '; Operation cycle is fed into the output memory 611 via 5 called 1798 via the line 1799. The For-

^s j the AND gate 612 transferred. This transfer mat control unit 1798 has for every possible type only

■ ^e of records in the output memory 611 is from occurring formats depending on an output 1801a

■ "- under the control of the comparison result of the up to 1801 n. For four of the possible formats are the

Comparison device 604 shown via the output unit outputs. The output lines 1801 α to

I 613 and the AND element 612, on which the comparison io 1801 η are user control 1802 for the field and

j result takes effect via line 614. Word order linked. In this controller 1802

] The F «g. 17 shows a schematic block diagram - it is indicated for each type of data record which

; "j picture of the data processing system. Fig. 17 shows fields to be selected and in different order

'"! the connection between the central unit of one of these fields is compiled into a sort word group

ⁿ J working memory system 755 and the input and 15 should be.

^l "j output stations 756, 757, 758, 759 and 761, about For each type of record can have up to four

^lt ; which new data are selected from the button 762 or special fields and in random order

^1; ; len input means 763 are entered or compiled via sequence.

'■; the data for printing to the printer 764 at the beginning of each field, the output

^e [ can be given. The multiple input 758 ao lines 1803 a to 1803 d signals for various

'" \ is required to transfer data from multiple pushbuttons characters, according to a program in which

^{: r} \ the central processing unit of the working memory system 755 each field is assigned a special character.

^{; r} to feed. The asynchronous input 757 transfers these characters in their order

^1S , incoming data with one of the bit sequence fre- the fields of the data records refer, ie, the characters

sequence of the central unit deviating bit sequences as themselves and their position in a sequence

^r> Frequency in which the central unit of the working a program code to identify the fields

* "Storage system 755. The input serial memory and for the classification of the selected fields in the

^: "■ 756 is the main memory for data that is in the order you want in the sort word group.

The central unit of the memory system 755 processes the signals that are sent by the character generator via the

- 'should be. The output series memory 761 is 30 output lines 1803 a to 1803 d, respectively

ⁱⁿ "; of the same type as the input memory 756. the program and the order of the field selections

^äS Both the input memory 756 and the Ausation are delivered, are in the comparison arrangement

^; The output memory 761 works with the bit sequence frequency 1804 with the identification signal of the following field

^{: n} quency of the central processing unit of the RAM system of the following new data record compared.

ⁿ " 755. For the purpose of printing data, the 35 The comparison is started with the

^'L · the data from the central unit of the working contact of the signal. The signal EF is from the De-

**> Storage system 755 identified by the output compressor encoder 1805 which is on the line

ⁿ "759, which prepares the data for printing, to the 1806 a signal for the generation of field signals

Printer 764 transferred. generated. The field signals are with the signals

ⁱⁿ FIGS. 18a, 18b and 18c forming the lines 1803a compared to to 1803 d together the 4 °. That

^m F i g. 18 and 18 show a block diagram of a field signal is generated in a generator that is used with

- * "Sort the circuit arrangement used. It shows, for each signal» EF «, starting with the letter A,

ⁿ · like a data record from the storage tracks 1723 a and each by one letter in the order of

^u "1723 b is advanced by the controller 1729 for the premature alphabet, that is, every

^{e <} ^ reading depending on the result of the data record running in a 45 identifies its various

^ia ^ comparison arrangement carried out comparison se- fields themselves by a character in alphabetical order

is read. Fig. 18 also shows the assignment sequence. These field characters are then with

° "compilation of the sorting field groups which compared those characters which were used in the four

^r d data record is contained and its transmission via different field positions in the control unit 1802

^m "the field selector and the control (Fig. 18b) for 5 ° for the field selection and the field sequence are generated

^{; n} · the word order in the new order of the words den. The field character generator can be of any

read _for comparison arrangement (Fig. 18c), which in turn can be of a type, such as punch cards or fixed-character

D- the transfer of data sets, the selected generator.

ⁿ 8 were controls. Depending on the desired arrangement

Depending on the set and basic 55 fields within the sorting group, the

In the position of the flip-flop 1793 and 1794, the comparison arrangement 1804 generates a signal when

the data records from the memory tracks 1723 α or 1723 b always between the programmed characters

-h- read out and over the line 1732, the AND and the incoming characters a match

tze members 1727 a to 1727 a * and the OR member 1731 is determined. This signal is sent via one of the

, ig- transferred. A trigger 1795 initially does not leave 60 lines 1807 a to 1807 d of the signal unit 1808

mt. Signals happen because it does not receive any timing pulses. fed. The signal unit 1808 receives via the

OS, the data record is therefore initially transmitted via the Lei lines 1809 a to 1809 d time pulses, the syn-

-leitung 1796 led to a signal decoder 1797, chronologically with the time pulses of the dynamic memory

to determine the format of the data record. The occur. The signal unit 1808 generates signals that

ert, signal decoder 1797 lets the character 1J5 of the programmed position of the next one

the »EI« (end of the data record) following signal, matching character and the run-in time of the signals

check. As already mentioned, the "EI" character depends on the relevant fields. The necessary

ge at the beginning and at the end of each data record. Delay in periods is indicated by the signal in

one of the lines 1809 α to 1809 d determined. It is about the necessary delay of the sorting fields for their compilation in the turret circles in the correct time allocation to the other words of the sorting field group.

Because the sorting field group is divided into four words, a maximum delay of 3 word periods of 8 characters each is necessary. Depending on the required word time delay, the signal unit provides 1808 characterizing sub-bit pulses 1, 2, 3 or 4 via the lines 1811a to 1811 d to the OR gate 1812. The flip flop 1795 is controlled via a line 1813 in which the selectively obtained data for the sorting field group are fed to the necessary word delays. The necessary word delay is determined by the sub-bit position into which the selected data is transferred, in the following order: Sub-bit time 1, 2, 3, 4 results in word delay 0.1, 2, 3.

In the subsequent circuit of the arrangement, the selected data is so many character times increases that character with the lowest value immediately before the beginning of the next one Word time stands. To achieve this, a counter 1814 is always incremented whenever a character comes over line 1732 which cannot be selected. The counter 1814 has a number of outputs which are the inputs of a number of delay lines 1815 a to 1815η via the AND gates 1816a to 1816ft in order to achieve the necessary character time delay to reach. As soon as a field information that is selected for the compilation of the sorting field group is received, the counter 1814 remains in its position and is not incremented. This is done by closing an AND gate 1817 via a flip-flop 1818 by signals on the lines 1807a to 1807d, OR gate 1821 and line 1822. The sort field information passes then one of the delay lines 1815 a to 1815Λ.

The beginning of the selected word leaves the delay system at the time of the first character of the next word time and then enters a word time delay arrangement 1823 a to 1823 d via an OR gate 1824 and a line 1825. As soon as the next "EF" character arrives at the responsible decoder 1805, a signal on a line 1826 is fed to the counter 1814 in order to switch it further.

The selected fields of the data records are then fed together to the delay arrangement 1823 a to 1823 d in different time periods. Since the AND gates 1827 a to 1827 d are controlled by the four sub-bit pulses, only that characteristic map can leave the delay device that is in the corresponding sub-bit time and thus has the correct time position at the same time. The characteristic diagrams are then fed to the trigger 1829 via an OR element 1828, where they are converted into a standard sub-bit time, namely sub-bit time 1. In an adjoining flip-flop 1831, the characteristics map is then transferred to that sub-bit time which is associated with the data record group in which the associated data record is located. All four fields of a code group are transferred to this sub-bit time. The sub-bit time is determined by the set inputs of the flip-flops 1832 a to 1832 c, AND elements 1833 a to 1833 c and in the OR element 1834. The changeover of the maps from one sub-bit time to another takes place after the sorting fields have left ^{the delay device 1823 α to 1823 a 1.}

After a map has been transmitted in the correct sub-bit time and the correct word time, it is fed to a buffer turret 1837 via a line 1835 and an OR gate 1836. Of the

ίο Buffer Revolver 1837 can have three map groups Include 4 fields with 8 characters each, i.e. up to 32 characters.

The return of the map groups from the exit of the revolver in 1837 to the entrance of the revolver

1837 takes place via lines 1838, 1839 and 1841. The feedback is controlled by an AND element 1842, which receives its control signals from outputs 1736 a, 1736 b and 1736d of comparison arrangements 1728 a, 1728 b and 1728 c via a line

ao 1743 received, as this is still to be described. That ' The map group is compared as soon as it is ■ removed from a revolver 1844. The revolver 1844 can assign 3 map groups of four fields each, each of which can have up to 8 characters.

nests in three sub-bit times, save. The return of the map groups from the output the input of the revolver 1844 takes place via a line 1845, an AND element 1846, an OR element 1848 and a line 1849. The repatriation will

controlled via the AND gate 1846.

A new map group is supplied via a line 1851 and the OR gate 1848. The new Map group replaces the relevant preceding map group, which is indicated by the locked AND-

Link is deleted in 1846. An AND gate 1852, which is arranged between the lines 1838 and 1851 is controlled for this purpose by a sienal on a line 1853. This signal controls also the AND element via line 1854,

after it was inverted in the Reverse Song of 1855.

As soon as AND gates 1856a to 1856c are opened by the comparison start signal Cpt on a line 1857, the map groups in their

Sub-bit times are fed to the comparison arrangements 1728a to 1728c via the said AND gates. The map groups are separated from one another by their sub-bit times via lines 1858 β until 1858 c to the AND gates 1856 a to 1856 r

guided. The map group I becomes the comparison circuit III 1728a and the comparison circuit I-III supplied 1728 ft. The map group II is via the AND gate 18566 of the comparison circuit I-II 1728a and the comparison circuit. TI-III 1728c

fed. The characteristic field group gelanst c through the AND gate 1856c to the comparison circuit and IHII 1728 ft to the comparison circuit WITH 1728th There are two characteristic field 'groups α bitwise in Comparative assemblies 1728 to 1728c to each other

compared. Each of the comparison arrangements 1728a to 1728c and 1866a has two outputs 1866ft 1866 c and 1866 a \ 1866 s and 1866 /, according to the operating method of this comparison circuit. The comparison result of the three individual comparison

by comparing the individual results of the Comparative circuits via AND gates 1868a to Logically found 1868 c and given on lines 1867 a to 1H67C. The comparison result is through

a signal combination E II and 55C, as will be described below, enabled.

Depending on the program control on the associated lines, a signal is generated which indicates which of the three key field groups has the highest or lowest priority. The line 1867 α is assigned to the map group I, the line 1867 b is assigned to the map group II, the line 1867 c is assigned to the map group III. The result of the comparison process is stored in flip-flops 1869 α to 1869 c until the data record to be selected has been transferred. As soon as the signal £ 11 of this data record appears on line 1871, the comparison result is deleted. One of the flip-flops 1869 a to 1869 c is then brought into the set position via the AND gates 1868 a to 1868 c by the following comparison result, which is already available in the comparison arrangements 1728 α to 1728 c. After the comparison result has entered the flip-flops 1869a to 1869c, the next operation takes place.

First, the selected data record is transferred from the memory track 1723 a or 1723 b to another memory. The associated map group is then transferred from the storage turret 1844.

The sorting field group is then replaced by the next following characteristic field group of the following data record in the memory track 1723 a or 1723 b .

A new map group is then created for the data record following in the second position on the memory track 1723a or 1723 ft obtained by selection.

The selected maps are then put together to form a map group.

Finally, the reloading of the memory tracks 1723a and 1723 & or 1763a to 1763d is initiated.

These five processes are controlled by the output lines 1736a to 1736 /.

The lines 1736a ″, 1736 e and 1736 / select the sub-bit time for the delay of the characteristic diagrams belonging to the data set in a signal unit 1872 c of the signal unit 1872. These data reach an AND gate 1874 via an OR gate 1875 and a line 1876. As soon as a new comparison residue occurs, a flip-flop 1877 is triggered by pulses on the lines 1736 g, 1736Λ and 1736 and an OR gate 1878, a line 1879 and a pulse shaper 1881 pass, whereby the AND gate 1874 is permeable via a line 1882, brought into the set position.

The flip-flop 1877 is activated by a signal on a line 1883 after a time period of four field lengths brought into the basic position, the AND gate 1874 is blocked again. This allows the Map data in the sub-bit time of the selected data record on line 1884 during the time of four field lengths, which corresponds to the time of a map group in the revolvers 1837 and 1844, reach. The data are inverted in the inverter 1855 and delete the map group of the selected data record in the revolver 1844 by not returning it to the entrance of the revolver will. At the same time, the AND element 1852 is over the line 1853 for the next following map group opened. This next map group is in the same sub-bit time as the deleted one Map group. The new map group goes into the revolver 1844.

This map group, which was transferred to the revolver in 1844, was controlled by the revolver in 1837 of the AND element taken in 1842. The AND element

In 1842 the reverse step becomes 1886 and the line

Controlled in 1843. The transfer of a map group from the revolver 1837 to the revolver 1844 does not depend on a specific start time, since both turrets work synchronously. Just the start the comparison depends on the temporal position of the map groups in the turrets.

Fi g. 18 likewise shows the control arrangement for read heads 1724 a to 1724 d of the storage tracks 1723 a and 17232>. The inFig. The control arrangement shown in FIG. 18 is shown in its entirety for data records of group 3. Line 1736c transmits a signal when a data record is to be selected from this group and transmitted.

In each of the storage tracks 1723 α and 1723 b there are two data records per data record group. Since each of the storage tracks has two read heads, reading of a data record can be started at the beginning of each sector. Each memory track consists of two sectors, and one data record is stored for each group in each sector, since this working method requires the length of two data records in order to be able to sort, namely between the premature reading to form the map group and the reading of the same data record in order to transfer this to other memories depending on the comparison arrangement (FIG. 18c). The control of these read heads is very easy.

Most operations use two separate read heads. The heads are on the same side of the storage tracks, however, are assigned to different storage tracks, as each storage track depends carries two records stored nested in the three sub-bit times. The flip-flops 1793 and 1794 (Fig. 18) control the transfer of data to the signal heads for data of group 3 of the data sets. The 1793 flip-flop gives the pair of Heads to be used. The flip-flop 1794 indicates the memory track. The flip-flop 1793 is switched with every sector pulse. The signal heads are therefore always switched so that they can read the records in their order.

As soon as a signal occurs on a line 1887, there is a switch from one position to the other interrupted once per pulse. The relevant data record is then read and the signal heads then stand in front of the next data record. Having two records from a memory track are read out, the flip-flop 1794 is toggled, and the conditions for the premature Reading and transferring data records related to the storage tracks are reversed. There for everyone the groups of data records have their own control unit, the resetting of the flip-flops 1793 and 1794 to the basic position is only possible during reading out data from the same group of data sets is possible. This is indicated by a signal reached in the line 1736c, which AND gates 1888a to 1888 a * to control the premature Reading and AND gates 1889a to 18890 * supplied to control the transfer process will.

409 530/159

until WWd received

until

and

"Nd 2083" or 20826 and 20836

1894a to 1894a 'and 1895 «to ¹⁸⁹⁵ ^ J" λ "^ rather is the second half 2065 & of the input the merging of the control signal of the three spacner« _ichers ^ _{65 the} transmission

Control units used. This is indicated by arrows one ^ edition _{P 2082b and 2083fl}

1896 «to WM / ^^^ fAlTli and 2083b, which by the head scarf arrangement

until 1897 rf connect the OR £ songs ιβν * β o » _{2ft84 anEes} . The head switching arrangement

1894d with the AND gates 1727 "to 1727" \ 2084 controlled wero P ₅₅ ^ ^ _vQr .

Lines 1898a to 18198d connect before OR- 2084 '™ rd Jon ^ £ ^ _γ

Links 1895a to 189Sd with the W «™ SeSne data sets are used in the head switchgear.

Wekhe taken from the voltage 2084 via a line 2086. the
what nu g,; to transfer _{icher 2065 b -}

in the g ^ P ^ ^ ^. ^^ _{7 def}

_rgrup pen _ontrol 2088 supplied.
^b0 _The ^g _{V0- sided} reading of the data records means that
_e read in data record for the purpose of selecting the identification _field by the subsequent circuit
Data records must be read ahead of time

Lines 1898a to 18198 d ver
Links 1895a to 189Sd with the 1726a to 1726a-. The ^ Jie we 1896a to 1896d are temporal pulse we ^ selected record of denSignakn th of the f b th werdea ™ ^s n, which in ae

selected data record from
Signal heads are offered a. ™ AND gates 1727a to UZTd and 17260- takes place from J ^^ J OR gate 1731 resp.

F i g. 19 is ^s ^ em ematisches
Arrangement for sorting for the processing system of the invention ^ the flow of data through the

The arrangement of FIG. ^ Order when the HauptP ^ro ^ 8 ^m. vending machines. The Datematze ^^

_ao

_one em

_{field is read} by the following circuit
Records must be read in advance who Comparison arrangement has made a decision-making _a5 Control 2089 Ver-.5 ^ 4f _{must anord the} signal "WG" (New

Group) and it must save which
of the groups of this character in a sorting period

already had. The controller 2089 must then

arrangement 2067 selects the uare j _ent

emem the memory 2 66a 2066ö un speaking ^ m Steuusigaal ^ uf ^ ner J

the end. The data set «become a ρ f

switchgear 206 _{according to DateQ} _

Since the. ^G ™ PP, ^e f ^c , fS ^O 'en! Listening channels

iT ^ bSc ^^ d ^ e sSheipurschalteinrichhat brew t de 5> pe «^ p _{s icherspur}

S dS i Dtatz

one

reading is

Datas
input and output,
Storage track 20 / 2a
and 4 get in

Data set and 6
2072c and the D

_P of registration in a _dfe data record 3

serier seriei 2104 Date

Save the

Selector 2094 takes the format identifier from the data record and then selects the program required to create the characteristic field. A map selection program 2095 is activated by the selector 40 2094. A signal generator 2096 receives signals from the selector 2094 via a line 2097. The activated ^»r ogramme 2095 controls the Felctselektor 2093 via a line 2098. The selector einzu- across the fields record 2093 selected not only the fields which

consists of 45 are required to form the map, but

d. At the same time, it determines by how much a selected field

must be delayed to get into the intended position. . _;
uaitluau . _v _ The character delay arrangement is in two
ir 2072 a, which divided 50 parts. The first part 2092 is an arrangement
Memory track which has a delay of 1 to 8 for the field
■ rden in a character, the length of a normal field, allowed

For "r \ ^U M27fertr» SowoW the group A field delay arrangement 2099 allows storage track 2072 d "JfJJf ^ _the storage track- the field again by the three field lengths in pin switching arrangement 2067 ^ s ^ also d, ρ j ^ _ ^ ^ _{pe e} ^ _{delayed at the end} .

switching device 2M9 ^ the yon P ^ _{Fe] dverzö 2099 is the se} -

track and ^G ™ PP ^enst ^ ^e f ™ _e "" AIN from the previous field lected in the correct position and is m

The transmission of ^ " ^sa ^ ^a ^ ^s j _he _ _{2074 a Pu {{erevo} lver 2101 in the same channel

memory 2071? «™ SSSGn ^ Sdektton ^ stored, in which the associated data record is stored in the fine memory track and gJT ^ _ur _ _6o transmission memory 2074 is turned off,

facility 2075? ^ ™haben £ YY _20? / _{% vird} ^F _{von The} map comes from the buffer memory 2102

and group selection _{device ^ in the} storage turret 2102. The storage turret

a memory track and Ο ^ ΡΡ ^ J _contains ^ _{maps? the m to the} next one

2076 as "^" * ^ 3 _D ^P _ie Speicherspur- comparison are needed. "

Group switchover controlZüJJ > u _P H _The comparison arrangement 2078 has at least

and group selection control units to control lines 2077 a. 2077b and 2077c. These

Charging is controlled via the control signals ^ J ± ^l ^ f _MSt control lines 2077a to 2077c

of two of the pre-storage 2071 and the transmission storage

do dai üi

m u

27 '28

ι every 2074, the early reading and the transmission of the sub-bit time channel 1 pulses are carried out by the Lei read Data records from transmission memory 2074 are supplied via device 2537 a.

1083 b the sorting group control 2088 and furthermore the bits that pass the AND element 2536 α,

4 collects a collecting turret 2103 before it is discharged through the variable delay line

Current melspeicher 2065 ft. The first two characters »NG« 5 2538 are fed to the write head 2541, which the

erien- within a group of three characters, bits are stored in memory track 2542 of the buffer revolver

erien- suppressed by an appropriate circuit, since 2101 (FIG. 19) writes. The bits are after

, there would always be three old groups and a new sorted group of 32 character times (4 fields) through the read head 2543

form agung. The read to the output collective memory 2065 b and are via the variable delay

1083 α data records to be transmitted are stored in the collecting line 2545 in the AND gates 2546 α, 2546 b

inung revolver 2103 put together until they were fed with no Schwie- and 2546 c. Each of the AND gates 2546 a

in some circumstances can be transferred. The output to 2546c receives other sub-bit time channel pulses.

before- serial memory exists as well as the input series- the AND gate 2546a receives the impulses of the sub-

• early serial memory from three groups of memories bit-time channel 1. The AND gates 2546 a to

north 2104 a to 2104 c, each of which are a group of 15 2546 c by their connection with the basic

. The records is assigned. position outputs of the flip-flops 2529 α to 2529 c

agen- The first and second halves 2065 α and 2065 b of the normally open. Only if a new one

7 of the input and output series memory 2065 are elek- Field is fed to line 2523, the

electronically controllable. The records can be a permanent flip-flop of group 2529 a to 2529 c in

- that arithmetic circuit 2080 is brought from the output of the head switch 20 set position and deletes the old in-

ζ _εηη . arrangement 2084 fed via a line 2070 stops the revolver in the place in which the new

•, are to be read and stored from there to the collective turret 2103 via the field by the

_who reach a line 2090. The comparison control speaking of the AND gates 2546a to 2546 c

; chei- 2089 ^utl d control the sorting group control 2088 is closed. The flip-flops 2535 b and 2525 c are func-

Encryption ^d i ^e control unit 2105 of the collecting turret 2103 25 tioning as the flip-flop 2535 α, but they work

New via lines 2106 and 2107. in the sub-bit time channels 2 and 3. The AND

elche F i g. 20 shows an embodiment of a buffer and elements 2536 b and 2536 c get their sub-bit

riode storage turret assembly 2101,2102 of FIG. 19. Time channel pulses via lines 2537 b and

Then the buffer turret 2101 (Fig. 19) works as a pre-2537c. The flip-flops 2547a to 2547c transmit the

r the memory for maps, which are stored in the memory 30 maps in the storage turret 2102 (Fig. 19)

Lei. revolver are to be transferred, from where they are directly in the order of the sub-bit channels 1 to 3.

the comparison arrangement 2078 (FIG. 19). The flip-flops 2547a to 2547c, the AND gates

will be. The selected fields for the map 2548 a to 2548 c, the sub-bit time pulses on the

gjjtQj are to be summarized, the in lines 2549a to 2549 c and the comparison result

pet F i g. 20 in the arrangement shown in channel 4 via line 35 act signal on lines 2077a to 2077c

-mat- ^do S 2523 supplied. The first operation is as a repositioning system for the three sub-bit

Jj ₁₁₁ Jj in that the incoming characters in the channel time channels. The storage turret works in the

'enn- are transferred in the same way as the buffer turret. Just that

gktQj record is saved. This is done by instructions deleting the old fields in the memory revolver

is controlled, the ver in the transfer memory 2074 40 different than in the buffer turret,

ituni (F i 8 * ¹ ^) are stored. The comparison result The comparison result signal in the lines

each ,, is still available and can be used for this control 2077 a to 2077 c is used in the reversing elements 2551a field · ^mn 8, it is located as elec- to 2551c inverted, so that an active comparison O ₀ J ₁₈ tric signal on one of the lines 2077 α to result signal the corresponding one of the AND gates "dem ²⁰⁷⁷ c (FIG. 19). 45 2552 α to 2552 c closes. The output of the memory unit The comparison result signal is still used for a revolver controlled by the AND gates 2553 α to ρ _s j. other purpose in one of the flip-flops 2529 a, 25295, 2553 c. The AND gates 2553 a to 2553 c and 2529 c are stored. The set outputs of the also receive sub-bits -Time channel pulses on ^ jJ flip-flops 2529 a, 2529 b and 2529 c are fed to the lines 2554 a to 2554 c. The AND gates 2531a, 2S31fo and 2531c and the 50 control signal is used for each sub-bit time. Channel

rg OR gate 2532 connected. The set separates over the lines 2555 α to 2555 c during

° ubt ^{gears of the} flip-flops 2529 a, 2529 b and 2529 c control the time of the comparison in the comparison arrangement

* _& the sub-bit time pulses are fed to the AND gates. The three maps are assigned to the memory

\ jj 2531a, 25316 and 2531c. At the time of the sub-bit time turret via lines 2556 a to 2556 r,

' 3-pulse, such a pulse opens the AND gate 55 and fed to the comparison arrangement,
ri d Flifl 2534 i Gdll

p p gg g

^ 2533 and brings the flip-flop 2534 into the basic position. Two sorting systems are described below,

.j jj The AND gates 2531a, 25315 and 2531c and The first system is a two-way mixed system, the

. $ 2533, the OR gate 2532 and the second flip-flop 2534 is a triple mix system. In the two

-, _Λ are used to transfer data from the sub-bit time-division mixed system, the data set groups grow in the channel into any other. For the other 60 the powers of 2. In the first run

1102 it is assumed that the incoming two data sets from different groups for

^ eId ^m sub-bit time channel 1 is. The other two - first subgroup combined. In the second

ren sub-bit time channels are run in the same way, each forming 2 subgroups of the first run

treated. The bits of the incoming field become a new subgroup of 4 data records. in the Via the AND gate 2531α on the set input of the third pass, 2 subgroups form the

Flip-flops 2535 a given. The second pass set output a new subgroup of

Flip-flops 2535 a is generated by an im sub-bit time of 8 records. The two-way mixing system is required

Channel 1 controlled AND gate 2536 a controlled. Its just a comparison arrangement.

30th

In the triple mixing system, three subgroups from the previous run are added combined into a new subgroup that contains three times the number of records of an original Has subgroup. The subgroups grow with each pass with the powers of 3. In the three-way mixed system three separate comparisons are made using three separate comparison arrangements can be used. The first comparison arrangement then compares the maps of the Data sets 1 and 2, the second comparison arrangement compares the maps of data sets 1 and 3. The third comparison arrangement compares the maps of data sets 2 and 3.

In the three-way mixing system, three results are generated, which are normally generated by an AND gate arrangement must be processed in order to arrive at an end result which clearly corresponds to the program the map with the highest or lowest valence identifies or shows which maps are the same. That The final result is processed according to the program instruction. The number of for a three-way mixing system The components required in the circuit arrangement are larger than in a two-way mixing system.

It is also possible to build four-way mixing systems or even higher-quality mixing systems. A such a system would be very similar to, and operate, the triple blending system. The number the number of runs required decreases with the number of comparisons carried out at the same time.

FIGS. 21a and 21b, briefly referred to as FIG. 21, show a general representation of the data processing system. In this system, the storage tracks have a length of 4 records and have 4 filled sub-bit time channels. Of course, other usable nesting systems can also be used be used. The data processing system consists of the sorting circuit and the Arithmetic part.

The data sorting arrangement shown in the upper left quarter of the drawing and consists of the top chain of components is a data sorting and merging system, which works in a similar way to the systems described. That is, the data sorting device sorts the data in an increasing or decreasing order as desired. Alone starting from sorting, any usable sorting system already described can be used in place of the one in Figures 21a and 21b are used will.

The computer part of the data processing system of FIG. 21 performs all arithmetic functions, distribution functions and tabulation functions associated with a group control program. The arithmetic functions of adding, subtracting, multiplying and dividing are carried out. The tabulation function consists in adding and subtracting data in vertical columns according to the structure of the data records. Distributing is the transfer of ¹ column of a given data set into one of several columns after specifying a code which is contained in the data set.

The arithmetic distribution and tabulation functions are converted into the normal or ordinary

a function with one constantly

The function tan is also nm
Operations connected ^ * £ * ·

can be, with which Ted des Kennleides

and also "ώΤτ ^ ίη ^ ώ distribution function is below described.

Various operations need to be performed
to prepare the map. The first
Operation is the selection of the person; from the

tierte i-eiaer waus »^ w.

which saves the selected fields. the
Saved fields are not yet in the correct position in relation to the meantime. the
Selected fields are made by the field justifier

2748 brought into the correct position. The field justifier 2748 consists of a step-by-step switchable delay line, which enables
position incoming data in each of eight intermediate positions of a fixed field. In this

The field justifier works in such a way that the
selected fields are positioned so that the last
Character is in the first character time of a field.
Aligning the fields consists of moving the selected fields to the beginning of the

Field, characterized by a field start signal.
The aligned fields are stored in the buffer turret, which is used as a pre-store for the storage turret 2749
serves, saved. The buffer revolver is available as a
Cache used to increase the capacity of the

Enlarge storage turret. The storage turret is the main memory for the comparison arrangement 2751.

The storage turret consists of a storage unit
for each map, which of the comparison arrangement

is fed at the same time. The time for the
Comparison process is required corresponds to
Length of the field and agrees with the length of
four fixed fields match. After four fixed field times, the comparison result will be posted on the line

2752 given. In a group control program,
which is carried via line 2753, the comparison arrangement 2751 has to deliver output signals,
at the end of each field time. The intercomparison results from the comparison assembly 2751

are put on line 2754. The same result on line 2752 controls all transfers of information units through the controller for early reading and broadcasting that

Ve köi the sch

FeI art seli dei is practice. rev 27f 27f zö§ gra Da das wii wel rev die ScI-tral arit Prc gra gra Lei Prc der shall tral down

a · the. spu iac kor part in spr siel FeI der FeI Lei 27f gra I

enter ^ the

ein 'dar Eir wei Sp ₁ gra 1

Ve FeI

31 32

see "Control and the control of the arithmetic - two consecutive data records no sub-

T Änf is eliminated, which must be transmitted m the field

vrm the fields of the data records are stored in arithmetic, tabulating memory track in channel 1

T «• üüiime · = - and table operations to the, after it is on the content in channel 1 of the ke-

f "y- ^er Sn these fields must be prepared as 5 gistsrs was added. If the maps have a

there can, ^ preparation of the maps must show the difference in the first field time

^1S "^ w the content of channel 1 of the corresponding table manufacturer

rut _S chnebec ι ^^ "^ ^ ^ ^ ₅₅ ^^ _{RegistefS from the} ^. ^ _{of channel 2 can be} added.

f _c M Rector 2756 supplied. This field selector The new field is saved in channel 1 - at

ΐ "Wet eenau in the same way as the field 10 a change during the field time 2 of the identification

* T , 11 ^ 746 The selected fields are changed from field, the content of channel 2 to that of des

Visetek% ^Γ - ,; _ktor2 756 in the field turret 2757 channel 3 of the corresponding tabulation register ad-

. ^m i ^ rtien which diert similar to the field turret 2747 , channel 1 is transferred to channel 2, and

read ^ ^er ^ f °; _Selected fields remain in the field - the new field enters channel 1 Be ₁ one

^St - ^Bt · ^The 2757 stored until the field-justifier _l5 change of Keru ^ Eldes to Feldzen 3 of the United

^leS S; S ^S = \ I »^ Fdd-Jü = ^1S at the same time while the content of channel 3 is set to that of the

5ZSI consists of a step-by-step switchable channel 4 added, the data of channels 1 and 2 are

^{ien l} - n ^ Litune which is transferred to the higher channel by means of an input sequence request. if

^r ° ~ ²⁰⁸ Sm ÄS ^ P ^ animgerät 2759 glsteuert ^ rd. on the other hand a difference to field time 4 between two

T CtnSbepTogrzL · supplies a signal at the time that characteristic fields are determined, then the content must

? Field in the mad part of the arrangement needs the channel 4 to be transferred to another memory

_{h (} Sd m arithmetic process will be the field. The data of the three other channels arrive

¹ Sches leaves the field justifier 2758, the field into the next higher channel. The whole ope-

evolver 2761 ^, which is used as working memory for ration by the group control program gee ™ ! L arithmetic circuit is used. The arithmetic 25 controls.

* - ! s ^ 2? 6r: t ⁿ a ^ ^ HriSeS; ¹¹ _p ; ö: ₃₀ «; ™ ^^^^ ™ ^^^

Z S can be determined by the comparison result on the dependency of a program and a form * - The gram μ The arithmetic data on lines 2774 and 2775. The seiek

7 De instructions should read: Add, Sub- 35 the field time ^format ^> ™ lch f ^ K ^ ^d _h Z

ild- should. ^u ^ \. , · · Divide It is further and used for arithmetic and other purposes De

t fÄÄÄÄ required fields are used. A compressor

^h 'Sfhrf must be. 2776 for records Posmome- -c Fd.er d: ee

indicated,

must be performed. The Felüer positioned 2776 for records, this one

; em For the distribution operations, a field for Compressor 2776 must be from the print format on the

the one time is stored in a field turret 2765 40 line 2777 controlled. The 2776 compressor is in

killed the. There are four memories for the distribution process, each selected field in any one

; ht. Tracks with 32 fields each are provided to bring the four positions. The selected fields are

^{r are} simply nested. There is at least one write in the output memory track 2778 compiled,

of the head provided. The field which is in one of the This output memory track 2778 has four write

nal. division memory tracks are to be turned off, 45 heads must be distributed around the circumference. The newly assembled

/ ol- remain in the field turret 2765 , with the deformed fields in the output memory track 2778

749 speaking field registers of the distribution memory track can be connected to an on- or off-line printer 2779

than are on the print head. Then it can be guided.

of the field turret 2765 and stored. The three lines 2781, 2755 and 2771 of the

roll The register and the channel in which the 50th order of the F i g. 21 get the records from

) rd field is to be saved by a signal on the second reader 2772 for premature Line 2766 displayed. The signal on the line read from the collective storage lanes 2782 a and

: her 2766 is used by the group control program of the Pro- 2782 b. A first reading device 2783 for

part of the gram 2767 supplied. timely reading transmits read data records

The third operation is the tabulation process. It 55 has a field selector 2784 and a signal decoder

this gives 32 tabulation registers, nested four times in 2785 to form a program selector 2786 and one

from a disk storage 2768 track, on Format Selector 2787. This is necessary in order to have the

The distribution memory tracks are also arranged according to the appropriate program and the associated format

are. The fields concerned are first selected in before a data record is added to the circuits

nm, an input memory track 2769 and 60 of FIG. 21 the various processes

/ er then transferred to the tabulation memory track. Which will throw. The first reading device 2783 for

The input memory track is selected as a temporary storage. One data record each is selected,

_ie applies. The channel and the register in the tabulation which correspond to the data record that is generated by the second read

751 memory tracks are selected by the group control program 2772 for premature reading,

/ ergramm marked in the following way. 65 leads.

ber- The map has the length of four fields. The choice of the program and the format

sue comparison arrangement therefore works while four is being processed by the second character in the data record

the field times. If between the characteristic diagrams of is correct, which one indicates which type of data record

33 ³⁴

it is about. The second character of the record, the controller work as a spader for sub-bit time.

the Adiessen to the sign "Start of the information unit". The collective memory lane load control

follows, gives the category of the record aa. The 2802 controls the output of the disk stores 2796a

Field selector 2784, the already mentioned field to 2796rf and is itself from the control 2803

Selector 2746 is similar, always selects this S controlled for early reading and transmission,

second character. The selected letter throws the which the storage area desι disk storage, the ■

Signal decoder 2785 which selects the signal memory track and the sub-bit time

the letter is decoded and from this the address sub-bit line pulses are decoded by the responsible

Instruction derives. The address instruction must be contained in this memory track on disk storage 2767 _ge - i in program memory track 2788, io supplies. The Lade-Einhert2801 consists of the group j

in which the program is stored. switch arrangement 2067 and the memory track and!

The selection of the program is carried out by the: n per group selection arrangement 7U75 of the in FIG. 19 i

gram selector 2786 performed whichever the program was shown. The collective storage track loader!

gram with one of the four heads 2789a to 2789rf control 2802 consists of the memory track and i reads and transfers to the program turret 2791. 15 Group switching control 4Ö73 and the storage track L _a

The selected program remains in the pro and group selection control 2076 in the T

gram revolver 2791 until needed. Similar to FIG. 19 arrangement shown. f

As with the program selection, the format The unit carrying the input data is | _ra

driven by the format storage track 2792 through a separate arrangement and selected IU mat selector 2787, which does not need the format 20 with the drive 2804, which drives the shaft L ·

with one of the four read heads 2793 a to 2793d reads 2805 drives at a given speed, syn- fj,

and transfers it to the format turret 2794. To run chronically. The disk storage 2796 a to ^ ₀₁

Format remains in format turret 2794 until it is 2796 rf and 2767 are arranged on axis 2805- | ^ _a

is needed. net. The synchronous drive can, for. Example, of a two-Fj _n. Fig. 21 is a schematic block diagram of a 15 pole motor. A drive _{synchronization unit S rc}

an embodiment of the data direction 2806 shown in FIG. 17 corrects the phase differences between? _Lel

Processing system. Fig. 21 shows the central see the drive 2804 and the external drive φ _Ά

unit of the main memory system 755 in further by briefly braking one of the drives until I j

Details, so that the F i g. 17 and 21 together match the phases. The technique of phase ^i: the whole system excluding the Serienzugriffs- 30 correction of two drives by briefly waste | _us

Represent memory. switching of the drives is known. L j ₍

21 shows the central processing unit of the working The data selected by program 2788 i _ste j

Storage system 755 as well as the output compressor are fed from the loading unit 2801; _we ]

759 for the printing unit 764 of FIG. 17. Let us assume that the collective storage tracks 2782a and 27826 g] j ₍ assume that the data has already been received from one of the inputs 35 via the lines 2807a and 28076 and the pj,

transfer means 756 and 757 of FIG. 17 to the dynamic write heads 2808a and 28086. _fo] g

see memory 2795 are transferred. The data- The collective storage tracks work as storage UN

memory 2795 is shown as disk storage and is located between the input disk storage and the £ _C j-

consists of four disk drives 2796 a to 2796 rf actual work system. Among the records loading _we], to store data. 40 also contains an access in the order of the data columns coc

Data storage 2795 the disk storage 2767, regardless of its position in the collective £

which are the collective storage tracks, the revolvers, storage tracks. This is done by using ^ en

the tabulation registers etc. are located as described. allows multiple heads for one memory track. ] 27g

Each of the four disk storages 2796 a to 2796 rf Die in the collective storage lanes 2782 a and Coc stores data on both surfaces. Each of the 45 27826 stored data sets are stored in the 278

Disk storage has a movable arm 2797a sequence of their positions through the heads 2809a _m ös;

to 2797 rf, which reads the read and write heads for up to 2809 rf and 2811a to 2811 rf and for the sigr

both surfaces of each disk storage various purposes on the various managerial _nu n

wear and which is movable independently obligations transmitted 2812 2813 and 2814 which ^are by ato _r · 50, the first and second reading means 2783 or 2772 MeI

The arm 2797 a carries the read / write heads for early reading and the transfer station of

a and 2799 a. The arm 27976 carries the write 2815 is controlled. Readers 2772 and net Read heads 27986 and 27996. Arm 2797c carries 2783 for early reading and transferring one the read / write heads 2798 c and 2799 c. The arm station 2815 work depending on the control unit

rf carries the read / write heads 2798 rf and 55 is called 2803 for the transmissions to other parts of the imp

rf. Central unit. The reading devices 2772 and flip die through the read / write heads 2798 a to 2783 for the early reading and the transfer; gljei

rf and 2799 α to 2799 rf read data are station 2815 consisting of a combination of D fed to the loading unit 2801, which is controlled by the AND gates that are sent by the controller 2803 to the program 2788 via a collective memory loading 60 what is controlled as a function of the Pro- The controller 2802. The loading unit 2801 gram takes place on the input lines 2816. The time consists of a number of AND gates, the program selects the sub-bit time. Furthermore, the collective memory loading controller 2802 seizes the comparison result of the comparison arrangement until it is controlled. The collective store load control input 2751 on line 2817 into the controller. D consists of a number of counters and flip-flops. 65 The sector pulses on line 2818 serve as identical flops. The counters of the collective store load control start pulses for the control 2085 in the of tion 2802 control the movement of the arms 2797a to F i g. 19 arrangement shown. sits 2797rf, the flip-flops of the collective storage loader each storage lane of the collective storage lanes off

35

c-time 1796a; 2802.: euert, • s, die ■ ^The ustän-> 7 ge group

- and ig. 19 loading

- and rspuri the

becomes ι and wave. syn- i bis; eord-two- one-

Zwiatrive 'e, to asen-

: Ier dem η attaches unelease t.

ir the

; the and

-: from Ί an-Pro- Das jrhin aord-; a.

ν η as the

uren

2782 & has the length of four data ends each has 128 characters, the data records are nested ^{4 times:} each storage track carries 16 data records. to

^ each record can be replaced by one of the,. Kftofeze ^ a to 2809 d and 2817.C to 28Hd ι η be. The distance between ehiem head £ λ ** premature reading and a transmission head * "-rt two records. The distance between the

Wofen for the first and second early reading ¹ -at a data set, the distance between the ^ iLuntfskopf and the reading head for the second

The reading is 3 data records. In; _The function of the premature reading is then to work on reading the Uten rad before they are over- ™. The first pre-read reader 2783 reads the records to select the pro. The second reader ϊιη for the data of the comparison arrangement to to "announce which record as required närhster _ao If a record does not standing by bewird his program remains stored. The twen on the disk storages 2796 α to 2796d • λ ι not yet sorted in the sorting process. The gram instructs the stations for the premature a ₅ IfSIn and transmitting via the transmission of similar naten from the next record, ί Teder record is first of all from the '' Sn reading means 2783 for premature reading ^{i'll eat} Lkhlt and the Leitung2812 the field M ^ f ^ gi fed. The field selector 2734 beaus a flip-flop and an AND-Güed, -s is controlled by the flip-flop. The AND-i element is opened by sector pulses, which are not shown in Sfie 21, and by the next- ^! fade character time pulse closed. The SgSied of the field selector 2784 is thus opened for the id of the first character of each data record, which is the code of the data record. That ^! Sde character passes the field selector

i The field selector 2784 selects and transfers' the code of the data set to the signal decoder 2785, the signal decoder 2785 identifies the code of the data set; that is, the signal decoder 2785 compares the incoming character with aUen! Sure sign and determines its identity. The ¹ s3l.Decod.erer works as a comparison arrangement. One of its inputs is connected to a character generator. Its other input is connected to a plurality of comparison arrangements, each of which is assigned to a specific character. Each comparison arrangement in which an agreement between a generated character and ^: the code character is established generates one

Each comparison arrangement consists of two AND gates and two inverse

SS output signal of the decoding., 2785 the program selector 2786 via the line 2819. The program selector 2786 selects the program corresponding to the code character from the program memory ^{track 2788} by means of the four read heads 2789 a blS The ⁸⁹ output signal from the signal decoder 2785 identifies ^g the code sign. If a plurality of comparison arrangements are used, each of them has its own output line for selecting the program. If the code of the data record can be provided several times, a single comparison arrangement can be used several times. The time when the positive comparison result occurs determines the code character.

The output signal of the signal decoder 2785 represents the address of the program to be selected. The selected program is fed to the program turret 2791, where it is stored until it is required. If the next comparison result addresses the same data set group, this program is required for the selection of the characteristic diagram. The output signal of the signal decoder 2785 controls the selection of the format of the data set via the line 2821 with the format selector 27S7. The format of the data record is taken from the format storage track 2792 with the heads 2793 α to 2793 b and stored in the format turret 2794 until required. Each of the two selectors 2786 and 2787 has direct access or partial direct access in a known manner.

The program represents an instruction to perform a process on the next data. A The first part of the program is the general program and is recorded in a memory track. It denotes z. B. which fields are required for the map. A second part of the program consists in the connection of the circuit parts (wired program). A third part of the program is constantly recorded and relates to certain sequences of instructions.

Well-known types of programs identify "From" and "To" addresses and use several Characters for the address. In the present system, only individual addresses are used for "From" and "To" Bits used in certain positions. The program identifies the actual task as Adding, subtracting, dividing, etc. Subprograms can also be addressed that start with arithmetic processes are necessary. Due to the nested recording, one field eight programs can be saved.

The program remains in turret 2791 until the associated data record is fed into the system. If necessary, the program can be transferred to the appropriate circuit, which in a Bit timing occurs because most instructions consist of individual bits in specific positions.

The format is the arrangement of the data in the data set. It shows where the individual fields end. Nothing more is required because the operator knows the content of the fields.

As soon as the previous data record has been processed, the data record for which the program and format have just been selected is read. It is read with one of the heads 2809 a to 2809 d and 2811 a to 2811 d and transmitted to the line 2813 via the first station 2772 for early reading, controlled by the control unit 2803. The selected program leads the data record to one of the field selectors 2746, 2756, and 2773 via the lines 2781, 2755 and 2771. The field selector 2746 selects fields for the map. Each of the field selectors 2746, 2756 and 2773 compares the instruction in time with a signal taken from the format, depending on the code.

If z. B. the program instruction specifies to select the field 7, what by the binary code 1–1–1–0 is specified, field pulses from

37 * " ³⁸

Format fed to the field selector. As soon as 7 field, both turrets then work synchronously ^

JSdS ^ ÄtÄÄ S "" ST positioned data from the fields - P-S In other words, the selection pro 2748 is stored in the buffer and storage turret 2749.

The second selected field is in channel 2, etc. is a control signal for the individual Sub-B

^ Field Turret 2747 does not work as dynamic. It is necessary, however _; Kind ^ es FeI- ^

Short-term storage for data. Knowing the delay time x _{5 of} the. Herfur becomes the field in the> canal

The field revolver 2747 is a field time to 8 intermediate transfers, in which it is in the field revolver £ 2747 *

given with 8 quadruple interleaved bits each, so. For this purpose, the data is

scnenzeuen, mii depending ο Vi ^ _{Justifiers 274g m channel 4 via} f _u hrt. ~ '

¹¹¹ ^ ÄfSSA 8 hib di lktitn ««

^ _Jut

De ^ ÄfSSTeil a storage track. Ar Feld-Justiner 2748 moves the selected

Amelioration in "n part can _Justifier a storage fields * o by multiples of 32 microseconds. If the information Kaan in a ι _{ßaten the field. 2748 according ver} i, are

ÄÄ $ zSckeflrt it in the sub-bit time 4 EKc fields are then in and converted to a sub-bit time, which they entered before

^^ SaSTweriS ^ n ¹ "« ge In the Justifier 2748. The overpass

The Wi can ro- «becomes in ^^^^ e mU an Fhp- ^

The field turret can also consist of a delay

ming arrangement with upstream flip-flop consist of different sub-bit times of the buffer and _the

Sen as soon as de? Field selector 2746 an instruction storage revolver 2749 The output of the buffer _there

Signal for selecting a field receives, receives and storage revolver delivers the fields to the Ver _27?

Fdd-Reiolver arranged rip-flop instruction- Re- ^e ^ ₍

Signals? to accommodate the data in the order of the sub-order. The group control _{program ajrf steU (}

Save bi-characters. The flip-flop thus operates. Line 2753 controls the intermediate results in Gmp- _gor

as a bit memory and transfers the pen control programs from the selector 2746 35 to the lines 2764, 2754 _D

selected fields in the order of the sub-bit "^ ™. ,,." ■ ». ,, λ- ErUi

Zriten to the delay arrangement. A data bit The program specifies the order in which de _{& %}

brings the flip-flop into the set position until the fields stored in the storage turret are on the Vay _Zwi

SmSten sub-bit time pulses should take part in the output of the same. The order of comparison

So opener > \ o that the stored bit can also be passive _{in the order of the Sl} ib bit times ^ AuLang. The sub-bit time pulse must be carried out

Brinet the flip-flop in the basic position in order for it to be The result of the comparison is shown on the line _sje

to get the next data bit ready. The flip-flop 2752 is given and reaches the _{2 ??}

is used for the delay of the data bits within the controller 2803 to the transmissions and the upstream _th

B "t Zet ^{45 ze} '^ 8 ^e Le ^{sen records} to the competent for ^

¹ DSe fields are controlled by a field justifier 2748 via digen stations 27721, 2783 and 2815. The _{pe] (}

the line 2824 from the field turret 2747 in the controller 2803 for the transfer and the pre- _The

Bleaching manner in which it is stored in the said term reading is also _{stored by the program via line 2W} field turret. The field justifier 2816 controls the selection pulses

2748 is a delay arrangement with controllable 5 »line 2818, the sub-Brt time pulses on the line ^ _n

Delay time. The field justifier 2748 brings lines 2826 a to 2826 d . _{27 (}

by delaying the fields in a zero position. _{If two sets of} data are to be mixed, then Ιχα

When exiting the field justifier, the characters are displayed, the control 2803 indicates which data record is _missing.

with the lowest value for all fields depending on the comparison result via the line _we

oleichen 'time of the zero position of the revolver. 55 2814, disk storage loader 2827 on one of the _]

The field turret 2748 stores 4 fields, one field of disk storage 2796 α to 2796 d are to be transferred. _Vg

in each of the four channels. Since each field consists of 8 lines, the comparison arrangement 2751 specifies what _{n &}

the field turret 2747 saves each data record that has to be done. The control _{au |}

32 characters in total Since there are two field times for each field to the tion 2803, the reading device controls 2772 and the _{N (} ,

Selecting a field from the revolver 2747 with selected data records, the field selector 2756 _β .;

are required, a total of 8 field times for arithmetic, distributing and tabulating _Prosd

64 character times to supply processes for the transmission of the fields. _ste

needed from the field turret. The field selector 2756 selects the relevant _χ

The field turret 2747 has the advantage that it can 2746. The ^ anzeieen fields in a manner similar to the selector if a selected field to Verfü- 6 ₅ group control program on line 2828 of Sc

eunc is available This can be done by a line marker 2746 allowing the fields to be split up. From _ek

is placed in front of the field, or by using the request field selector 2756, the selected _{V (} mat is saved in a parallel turret, fields are sent to the field turret 2757 and from there to the

39 40

2758 field justifiers work to be positioned. Of the discovery. It can be in the data processing system

For example, Justifier2758 is used by the input sequence program of FIG. 21 for circuit 2774 for

-Justifiei ^from P ^r ° g ^ramm circle 2759 controlled, which again- the premature reading, for the field selector 2746, the

2749 ee · ^{um from the} comparison result of the comparison arrangement field turret 2747, the field adjuster 2748 and the

274) 2751 controlled via lines 2752 and 2829 5 buffer and storage turrets 2749 can be used

. . will. the. These components work in preparation

^L The comparison result of the comparison arrangement of the sort value for the comparison arrangement 2751

the ^^ 1 comes to the program together via line 2764, and the control 2803 for the premature

3it-Zeit · ^einneit 2763 of the computing circuit. The program reading selects the information unit from the in

749 iä ^ ¹¹ ^ ¹ ^ 763 controls the arithmetic circuit 2762;

"evolva ^bes i ^TZT a program storage track and an arrange- dependence on the comparison result and the sta-

"Lets you convert program signals into 2772 for early reading.

t-Zeita control signals for the arithmetic logic circuit 2762. The field selector 2746 is activated by the program

. Fei · P ^r ° g ^ram sig ^na l ^s are simple signals for the format and via the lines 2822 and 2823

Channel basic operations or entire signal sequences controlled as sub-15 and selects the fields as a function

₂ -ij programs for larger operations such as multiples of the program and the format. The field

^he Off · ^functions · selector 2746 controls the AND gate 2842 and the

■ _hTt The computer program is sent to the field selector counter 2843. As soon as a field is to be selected, open

~ T '2756 supplied via line 2831 and the field selector 2746 knows the AND gate 2842, and

W m ^show the fields to be processed. The format 20 the field is sent via line 2844 to the flip-flop

'j Tz signal on line 2830 gives the selector the position 2845, which the field in the specific

\ tion of the fields within the information unit. Channel transferred. The counter 2843 counts the selected

^From ^ ^em field justifier 2758 the fields with no entry are sent. The output of the said counter

_{we (} j _{er m} ^ _6n field turret 2761, in order from there to is fed to the channel control 2846. The channel-

unruiif ReCj _16n SCj ₁₃ ItU ₁ Ig 2762, or in the field control 2846, the flip-flop 2845 controls the

^a P Revolver 2765. Selected fields in their order of the channels

. u A program indicates on field selector 2773 that it is to be assigned. The channel of a field thus becomes

^{n [} which fields should be printed out. This FeI- determined by the channel controller 2846 which

ο flutes ^{are stored in the} 2832 field turret. From, in turn, is controlled by the counter 2843.

Ji * there the fields get into the field compressor 30 The channel control 2846 consists of 4 AND-

2776. The fields are then 2832 links in the revolver. The counter is for each selected field

: f. saved. 2843 by the field selector 2746 by one level

^α , The field justifiers 2748 and 2758 work as further switched. That is, the first one selected

Controllable delay line. The field compress field is transferred to sub-bit time 1, the second

^G ™ L sor 2776 works in a similar way to a field justifier. 35 selected field is transferred to sub-bit time 2

The work of the field compressor is with the etc. The fields are interlaced in a fourfold.

Explanation of the circuit will be described in more detail. The length of the revolver 2847 in A / B technology

It works depending on the program and adds 8 characters saved. The A / B technique is supposed to be here

Γ Gaps between the dates indicate that two turrets alternate with respect to

7 ° ^{enables you to use the individual} characters in the expression position 4 ° of the data records; the first revolt

- ^ lung τι. » bring. The first data record arrives from the compressor 2776; the second revolver

gen the data in the output memory track 2778, where takes the second record; the first revolver

Mtufli _s j _e remain until they are needed. The printer takes the third record; the second revolver

i7 number 2779 can work cycle-linked or cycle-independent takes the fourth data record, etc. As soon as the fields

s ^v ? ' or be an output typewriter. 45 of a data record are transferred to a field turret,

^{: St} nT ^The fields of the revolver 2765 come to become the fields of the next following data record

^{u 1} T field register of distribution memory tracks 2833. supplied to the other field turret.

Dizei · j-jj _e p _e j _der can also go to the input memory track. As soon as all four fields are selected, the switches

2769 and from there into the tabulation memory track 2834 counter 2843 from level 4 to level 1 and

reach. The tabulation memory track 2834 is produced by the 50 an enable signal, which the field

⁰ Group control program from the Justifier control 2848 program via line 2849

2767, from where the distribution is also managed. The 2848 field justifier control

^s0 lungs memory track 2833 controlled via line 2766 initiates the reading of the field turret in order to determine

b " . The comparison result is sent to the program to determine how much character time the fields should be delayed.

werk 2767 via lines 2752 and 2835. 55 are welcome.

\? '-; In the circuit arrangement of FIG. 21, the field justifier 2748 operates in such a way that the

are ·, distribution function for the separation of transaction fields are transferred into fixed fields so that the

^WHAT ; In a column or in the results of a column, data bits are used for arithmetic operations

^e "f; on multiple columns. The tabulation function is that can be. The sub-bit time is used here for the

' % Record various transactions in one column. 60 Delay time control used. The field

Π5ο j) j _e cross billing function is comparable processing Justifier controller 2848 transfers the data,

^ ¹⁰ * different columns of the same transaction, which one should be delayed differently and

■ represents the group totals the tabulation function represents the same delay for all parts of a

iden χ _eg selection of the fields and preparation of the Sor data field.

^ i animal values. 65 The dependence on the sub-bit time control

S ^e 'The F i g. 22 is a schematic block diagram and the turret input control 2851 is the

an arrangement for early reading and for field 1 in sub-bit time 1, field 2 in sub-

Preparing the sorting value of the present Er-bit time 2, etc. transferred. The turret input tax

41 ⁴²

tion 2851 determines in which buffer turrets are fed and lead to the next sub-bit time 1

the data are to be transmitted. convicted. The position in sub-bit time 1 indicates 6ntsprec

The F i g. 23 is a schematic block diagram showing the total delay of the field in the stu,

an embodiment of a field justifier, which in fen-wise controllable delay line 2937 position

the data processing system of FIG. 21 should be 5 4 drawing times plus 4 microseconds. Flip flop

For example, it can be used as a field justifier 2748. After a character delay, the field tries first

can. The field justifier 2748 consists of a sub to pass the AND gate 2945, which, however, is in tet to s

Bit-time transfer arrangement 2935 and a sub-bit time 4 is controlled, so that this field The 1

fixed delay line 2937, the delay of which remains in the delay line. In the following an A

time can be set in steps. The sub-bit time io the character time is in the field in sub-bit time 2 and ren vo

Transfer arrangement 2935 works as a bit memory is again delayed by one character time. Grundsi

rather and allows the transfer of data, it tries again the AND element from the dei

one sub-bit time to another. As long as a field 2945 to happen, which is not possible because of work

from the field turret 2747 (FIG. 21) not the field difference in the sub-bit time. In the following form

revolver is removed, the counter 2938 receives 15 character time, the field is transferred to sub-bit time 3 via di

of the field justifier 2748 impulses and changes the temptation and thus delayed by one character time, also (3

delay time with each character time. Only at the fourth drawing time does the field enter the sector

At the time of character 1 of a field time, the sub-bit time is 4 and is delayed by one character time «

Delay time 256 microseconds plus 3 microseconds. In channel 4, the field can use the AND gate 294S to 29i

Seconds what will happen with a field time delay. selektii

comes. The data is transferred. The AND element 2946 is closed because the element field

from sub-bit time 1 to sub-bit time 4. 4 micro- controls are delayed again by four character times

cßininHpn correspond to one bit, a character must in order to achieve a total delay time of 3 characters

«SET«?

Inverse member 2942 taken from intermittent times.

i generated when the AND gates 2939 a to 2939 k control d »

rSd again no 35 sub-bit time pulses with which the fields «J no signal fed to him the controllable delay lines entered verac

^ St ^^^ uA ^ 294! will not be and what the delay time for the Fe | Jaflj wira. L »db , im,. Output signal, which determine. The delay times from 2 to 8 ti *

SSdS Un £ ^ Aί seißi Liehest dem chenzzeiten are connected in Lei steps through the In c & es aas V ¹ "^ r | 't", _g , ₈ j _st As soon as the 40 delay line and the AND gates 2939 a to isi ar . S ^ lM IM ^ SÄ ^ d the work 29 ^ * s' as well as the OR gates 2948 and 2949 er Mikr, the counter 2938 is interrupted, and the data is mogheht. _w

the intrinsic value of the position of the counter, to which So, for example, a total delay of vv <

St Ss he was stopped, delayed. 5 drawing times due to a delay of two more

Each of the controllable delay devices 45 character times in the delay line 2937 and a
2937 and 2944 of the field justifier 2748 delays the delay time of 3 character times in the S-guided data for as long as this is required to reach delay line 2944. The first Ve ^ udm ÄrSub-Bit-Zeit 4 to arrive. That is, the delay time is controlled by the AND gate 2939c overall ™ £ * __ "a ieden the controllable delay controls which delay line feeding the field for encryption _(output emei ■ juien α sub-bit time 4 50 2937 controls at sub-bit time.

SÄ Ef leTden ^ rs ^ erable delay AND cled 29 & f controls the supply of the field "" J "™ S5SSSnuni" T2937 and 2944 required, since each to the delay line 2944 at sub-bit time 2. ™ X hZ only Hs to a maximum 4 character times delayed The total delay time is given by the fourth flip- ^ lSnn since each character time delay with a flop of the counter 2938. The field kaon ZeU ™ ήσ Hm data in a different sub-bit time 55 the delay line 2944 via the AND gate riiR X ⁸ ^? 4 ^ sub-bit times available 2946 bypassing which of the eighth Flippy

e delay time of 8 digits of counter 2938 via line 2951 geoftg J ^ _{; <! t} , if the total delay time is a L & ,

STStTS? Each field is equal to the field time. ⁸ g £

TuSfier mU the Kntreffen the start of field signal 60, the signal inputs of the sub-bit time-Überfuh- ^ Justifier with the baked _it ^^ _approximate arrangement 2935 and 2941, are ™ ⁿ with the type-setting

2 "SSAr ^ B"? Z ^ £ removed later. Input of its flip-flops connected so that each DA? Brings the tenbit ™ t ^ it tons d e data by changing the flip-flop set in position. The pol

S ^ ™ «^ JL» brought into an exact position AND element is with the set output of a / -field delay in an exactly * ^ ^ _flip-flops ^^. ^ _Def sub-bit time- ^

which for 8 character times delayed transfer order connected and is d «« *
l first of all the sub-bit-time-over- the sub-bit-time-pulses which are driven to that
^ 35 belong in its own channel sub-bit time in which the data is to be transferred.

43 ** / 44

Time 1 lead are. There is always a signal from the device which functions in such a way that it creates an im-

igt to 'transmits the corresponding controllable delay line to pulse by induction on a wire,

it is performed when the corresponding flip-flop carries out this transmission mechanically or also when it is set

2937 position is. At the same time, the appropriate pressure is applied.

; n should, flip-flop brought into basic position in order for the 5 The data that run through the delay line is field next bit of the supplied data is 3048 in-tet by one field time minus one hole. Sub-bit time delayed. Since the real field time is 256 Mi-5S field The F i g. 24 is a schematic block diagram of microseconds, there is an actual delay following execution of a circuit for positioning by 255 microseconds. Then t 2 and Ten of fields pass. The arrangement of the F i g. 24 io is the data a delay line 3052 from the rt. Basically the flip-flop part of the field justifier length of one microsecond, so that the total link from FIG. 23 is again 256 microseconds both in structure and in delay and that * s the mode of operation is similar. The flip-flops 2958 α to 2958 d no change in the sub-bit time affiliation Igend form a counter and control a flip-flop 2959 of the data occurs. The 1-microsecond delay exceeds 3 via the AND gates 2961a to 2961 d in, which there are 15 is passed through line 3053, line 3054, the AND rzögert the sub-bit time pulses are performed. The element 3055, delay element 3052, line 3056 1 in the sector pulses, which are carried out to the counter 2958 a to 2958 d and the OR element 3051. The data t delay, are thus passed via the AND gates 2961 α from the OR element 3051 back to the ed 2945 ¹ Ws 2962 α *, in order to transfer the sub-bit time pulses to the input of the delay line 3048. The Delay selected and continue to get through the OR line works in this case because of the four field "element 2962 to control the position of the flip-flop 2959 at nested sub-bit times like four parallel Rewerden and in turn thereby the fields in the volver. All Data coming from the sub-bit time L 8 line data line to be fed into the transfer arrangement 3045. Fig. 25 is a schematic block diagram remaining in the sub-bit times given to you by ordering an arrangement of a universal delay 25 the arrangement 3145 were given.
Sub-bit line, which in the data processing system of The passage of the data through the delay / ore · F i g. 21 can be used. The arrangement of the 3052 by a microsecond is indicated by a signal output of FIG. 25 is particularly suitable for systems with controlled on the line 3057, which arrives at the delayed nested information bits and can AND element 3055. The additional Vcrzöge-'eld "is used for delaying data on the length of the 30 tion of one microsecond in the delay-ID gate" delay line and multiples thereof membered 3052 is provided because the Verzögerungslei- a are 8 characters " The arrangement can just as well be used as the revolver 3048 in its delay time by one microsecond shorter than the total turret for the people who ^do it, or as a parallel turret delay of data without shifting the Dawider in ^ ^{r mem} "ere data with the length of the actual 35 th required. The turret can give so many independent delay times. This is made possible by storing various and diverse data as determined by the field that the delay line possesses in a system with nested sub-bit times. If one or more interleaved data is used, multiple data fields are required, the entire arrangement is accepted by a signal on line 939a to ' ^st that a sub-bit time equal to a 40 causes 3058 to provide this. The off 2949 is microsecond and that the delay unit would give such data via lines 3053, a field time is 3059, delay line 3061, AND- Limits 3062 MTing of When the delay line is used as a turret with and output line 3063.

If data from the delay line is used on the 2937 and ^ ^en , the data is given on the 45 line 3064, this data is first a sub-bit in the input line 3044 -Time- the delay line at the input in another transfer arrangement 3045 passed. The set sub-bit time is offered. So z. B. Data ¹ 939 c ge ^ ⁿ d reset conditions of the flip-flop of this sub- in the sub-bit time 2 after a cycle in the "bit time transfer arrangement 3045 are given by sub-bit time 1 If data is delayed pjs - the sub-bit time pulses on line 3046 pass through 3065, which is a delay time of 1 s. The sub-bit time pulses 1 to X reach 2 microseconds has, as they are in the. ~ _e j _t 2 ^ u of the sub-bit time-transfer means next following in the absence sub-bit time transferred, as the overall ¹ rte flip .Bangigkeit by the program control, During the total delay time there can now be 256 microseconds ^: ^ et between the bit-time impulses, minus one microsecond and plus 2 Mi-TsTO element Tlipflop of the sub-bit time transfer arrangement, it works as 55 microseconds, i.e. a total of 257 microseconds -Flioflop ^ bit memory. That is, during the time between carries. The sub-bit time conversion we d through the J —open fine incoming data bit and the next program control at the AND gates 3065, a line ^bit causes the sub-bit time pulses which sub-3055 and 3067 are determined.

^ei 'bit-time transfer arrangement 3045 as bit storage data, which the delay line 3048 pass-

fih rfüli- ^ kcr ™ work. This results from the activation, the delay line 3061 is activated

"" c _e tz- " ¹¹¹ S of the AND element of the sub-bit time transfer, which returns the data to its original state

• Reset d "Da- -Tur.gs arrangement 3045 by the Sub-Bit-Zeit-Im-Sub-Bit-Zeit. The AND gates 3066,

Each ^one - pulse, as has already been described. 3055 and 3067 are then closed. The edition-

f The "P ^u l ^se >" as already described. 3055 and 3067 are then closed.

^nng J ₁₁₀ i The data come from the sub-bit time over-data pass through the AND element 3082, which is controlled ^{by ai} timing arrangement 3045 via the lines 3049 and 65 programmed sub-bit time pulses Y _{J 11} TcIi the OR gate 3051 is on the delay line.

. _ner 3048. The delay line 3048 can be from a. The sub-bit pulses Y are also from a

^m over- '-! be of any useful type, e.g. B. fed a Einrich- reversing member 3068, which in turn

45 - "46

The AND gate 3069 controls via the line 3071. Sub-Bh-tot-ZugJo ^ tAj ^ e ^ durrähe ehe _ft

Since the sub-bit time impulses Y via the inverse sub-Bi ^ - ^ ητηη »J« ⁰ ^ ^ J f _{ög (}

3068 run, the AND element becomes 3069 and thereby became. It's moguch, ^ * ™ ^^ 3063 in the! run also the AND gates 3366, 3055 and 3067 were ^^^^ SiiS-tnonLen were bit-

^SP Soln _g e the sub-bit time pulses Y not in front If the data of the V - * ^ - ™ <£

the are; there is no signal to the reversing element 3068 sequence moves leads ™ * £ ™> ™ J _tnomm ? _n S, supplied, it generates an output signal and opens when D ^ S *

the AND gate 3069, so that all sub-bit time-Im-, the rubbing remainder ^ ^

Pulse of the times 1 to X, which are selected by the program xo delay 3065 or via the £ W> £ _{so c} , to the AND gates 3066, 3055 depending on the respect of the series tog na

and 3067 and this opens. A sub- If no change gP ^ »" ^ g ^ sornit S «

Bit time pulse Y on line 3058, which increases the size of the data 3052 and remains ^

Reversing element 3068 is supplied, this does not allow any in their sub-bit dead revolver

Generate output signal, whereby the AND gate i ₅ Soll the delay _arrangement U fen

3069 is blocked. This in turn causes the frying, so the data uw ω S Jg AND element 3055 are closed 3052 via line 3072. The. ^^^ "S trains and the sub-bit time pulses on line 3073 such as ^^^ Sto longitudinal ^ were have no effect. By this mode of operation, the maximum length of data is. giei bp are all data that are fed to the turret ₂ o the delay line 3048 ^z ^ £ em ^ micro-

den, available at any time. Second. All data remain in their sub-bit time _ß

The delay line of FIG. 25 can also have positions. controllable ,. One

can be used as a shift register. To this if the Verogßrungwadn ^ g ^^ Hbw ^ The purpose of the data is not to work from the output of the delay for data, so it is best to do so

Delay line 3048 over line 3053, * ₅ order from the ^Ve ™ 2 ^emn f ^ Senver ₇ £? in ü

Line 3054, AND element 3055, delay line AND element 3067 «^ ZWemiIaosekmdengMZOge. m ^ tion 3052, line 3056 and OR gate 3051 on rungs line 3065 and the ODbK-Oüe a ^ l.lki

the input of the delay line 3048 back output of the arrangement is given by du ^ - member ^ . Rather, the data will be sampled over line 3062 with signals in sub-bi-time r

tion 3053, 'line 3074, AND gate 3067, delay 30 The delay time of a date η ⁵ ^ ^{5 w} ' ^rd ^ _sulta

gation 3065, line 3075 and OR gate 3051 the sub-bit time determines which of the data ate. ^ returned on delay line 3048. when you enter it. If z. B a uatensate

The program signals close the AND gate 3055 of the sub-bit Zot transfer arrangement 3045 in ^

and open the AND gate 3067 is fed via the lines channel Y-3 , so it can α «ver ^^ 3057 and 3076. Data to be delayed 35 delay line 3048 for the first time to the sud-ηπ-

are taken from the lines 3053 and 3077 on the ZeitZ-4 The delay ^

AND gate 3066 given. 3065 of two microseconds transfers the data £

The delay arrangement of FIG. 25 can be implemented in the sub-bit time * -2. If the data exceeds the ^

likewise as a step-wise switchable delay delay line 3048 leave the second Ma ^ so ^ line can be used. 40 you are in sub-bit time Λ J υ ie ν er

If the arrangement is used in this way delay 3065 transfers the data so dan m the Jen *

is to be, the output AND element 3062 with sub-bit time X - 1. The. Dates compose the λ er, then

the sub-bit time pulses of the last sub-bit time delay line 3048 for the third time1 to the sub-bit ^ m

controlled. The AND gate 3069, which the AND time X-2. Due to the delay 3065 monetary jigs «

Elements 3066, 3055 and 3067 via lines 45 in the sub-bit time X. After the fourth_ ^ pass * nre

3078, 3072 and 3079 controls, receives the pulses through delay line 3048; are the data ^

of all sub-bit times via line 3073. In this in the Sub-Bit-Z.it X-I. The Delay3Ml of ™

Consideration Y is greater than 1, but less than X. the length of a microsecond transfers the data to υ Der

The AND gate 3066 is also from the pro the sub-bit time X, and the data can if

program control controlled by the line 3081, so overall arrangement via the AND ülied ä »t> o ^{e" in} ° V \ _"the

Dates that will be forgotten about twice the time. The total delay ^ t is ^

delay line are to be delayed, of which then three times the length of the circulation without sub-g

Sub-bit time transfer arrangement in 3045 in the bit time change plus 3 microseconds. The data «d

Channel ΧΛ transferred. After the simple transfer at the output of the overall arrangement, the data are always in channel XI. 55 Sub-bit time X. If desired, the * same

The data passes delay 3065 with the high reference S, .b-bit time operation to cm ^

Time of 2 microseconds and thus arrives at the start and the data in a sub-bit register ^ sub-bit time X. After the second pass through ger reference numeral to end the data the delay line 3048 is the data in the via the AND gate 30 (, 6 and the line, 3064

Sub-bit time AT-1. The total delay is 60 leads, instead of the AND gate 3067 and ^ ui

now 2 lengths of the delay time of the total delay 3065. _Corr

Order minus a microsecond. After the the delay arrangement of tig · ^ can ^^

Data the delay 3061 of the length of a can also be used to create gaps between ^

Microsecond has happened, they stand in sub-bit see the dater share close. Such an ^^ time AT and can thus the delay _{arrangement 6 5} order then work as a compressor. The length of the fig. 25 via the AND gate 3062 taken from the delay line 3048 amounts to a character

Men become time, minus a microsecond. Any ^

The delay of data therefore depends on the delay line in sub-bit time 1 to- ^^

I. 47 (y ° 48

ι the *;

just * led- Whenever a new character is added to the The character encoding that is used is

η is fed to 1 delay line, which are preceded by an 8-bit code of type 124SABPO, where

! the - current characters in the next higher sub- 124 8 is the numerical part and ABPO is the zo-

rden .; Bit time transferred This is done via the AND part of the character. A bit in position P becomes

an I ^{element 3067 and} ^ ^delay 8 ^erun g 3065 of 2 micro-5 used as a check bit, so that the zone part also

smaLi seconds. can be used for arithmetic purposes,

amen As long as no new character arrives, the entry points run. H. The second

r die: stored characters by the AND element 3055 half of a character time an uncorrected re-

Removing afld ^ώε delay 3052 of one microsecond, sultat by the correction values K1 and Kl cor-

Eührt, ^{since s0} ^ ^{d 'e} ^ hen Z i ^Q their sub-bit time positions are io yaws.

ι all remain. Because all the records are in the memory of the machine

Thus, as soon as the stored data from the system is in nested sub-bit time positions

delay arrangement via the AND gate 3062 in the, such sub-bit characters can also be used for the

; r ar- ^ n ^another circle are to be transferred, lukewarm arithmetic operations are used. the

arung f ^{fin d 'ese} data via the AND gate 3067 and the 15 interleaved sub-bit time positions represent spe-

Data delay 3065, so that all the times of the increased bit places in the memories between others

Ehen delay arrangement in their order taken data represent. If data is stored in a dynamic memory

-än »e can be .. This is achieved by the fact that records are stored, so is the distance between

fikro- the AND element. 3062 in sub-bit time Y the bits of these data records are driven constant. The bits of one

-Time "frd · ^ao first record are in the sub-bit time 1

The computing circuit works in binary decimal in (channel 1), the bits of the second data record are available

: rable input and output. The adding circuit of the sub-bit time 2 (channel 2), the bits of a third

> The processing unit works with binary characters until the data record is in sub-bit time 3 (channel 3),

'dem ^ ert * ^' ^{This enables the adding} circuit and the bits of a fourth data set to be in the

-zöge- i ^fl easy to hold their construction. All input 25 sub-bit time 4 (channel 4).

_He Tj data are in sub-bit time 1, all output data in order to simplify Datennuß, leading the

• elements are in sub-bit time 4. arithmetic circuit the following operations in different

_rt During the addition, the information is sent to 1 bit different "channels" within the same field

by ^we ' ^{se au} * ^d ' ^e I ⁿ f ° ^rmat i ° ^{n 2} added. The sign re-time through.

. The result must be corrected if it is greater than 9, 30

set ^{by adding a correction number} K1 = 6. The information 1 plus information 2: channel 1

5 j _m final result consists of a corrected information minus 1 Information 2: Channel 2

_Ver _ and an uncorrected job result. The information 2 minus information 1: Channel J

b_Bj * uncorrected result is designated as result 1

• eruno ^net · ^ ^{as the} corrected result is the designation 35 The information is basically

Data result 2. Uncorrected results below 10 and shive values treated. In the two subtraction

. y _er corrected results above 9 become final operations will proceed as if the result were

zn as a result, result 3 summarized. positive in both cases. One of these two subtracts

^w Y _e , _ In the subtraction operation, the result of the subtraction must be negative, however, what by

in the henten the complement to 15 are formed and 40 the absence of a carry pulse in the highest

^{Then the} minute ends can be added. At one point of the field is displayed. The positive sub-

ib-bit subtraction with a positive result must be in the low- traction result characterized by an over-

-en the rigsten place the value 1 is added. The position impulse in the highest place and closes that

Any result that is not corrected carries the other result from further processing

Data drawing result 4. The result must be corrected 4 ^45a us. At the end of the field time, there is thus a positive

»1 of become, if the digit result including the tive result of the addition process in the» channel «1

iten in carry-over has a value less than 16, d. H. always and a positive result from the subtraction s-

: r Ge ^{if the result 4 has} no carry. The process in "Channel" 2 or in "Channel" 3.

itnom result 4 can be corrected by the value Kl The control unit of the computing circuit decides

Let ^the · ^ ^ 'is ^the complement of Kl to 16. The cor- 50 which of the results is the correct and desired one

* Subordinated result is labeled Result 5 and and whether the result is positive or negative.

Data 'is ^the final result when the overall result becomes Information 1 and Information 2

Tier in is positive, as this is supplied by a carry to the computing circuit in "channel" 1 and

■ the highest point is displayed. The result 5 is added during the first half of the drawing time,

tier to ^e ' ⁿ intermediate result if the final result is 55 Both pieces of information are taken at a sub-bit time

niedri- ^subtracting what is displayed is negative, delayed by, then stand in the "Channel" 2, the information

^The lack of data ^em there unearned in the highest place tion 2 is guided via a reversal member which

64 ee of ^the result. the complement of information 2 to 15 in each

»7 and Um digit generated for a subtraction with a negative result. The adding circuit then delivers oir

To arrive at a final result, an uncorrected result of the operation must be: Informa

k _arm Correction value K 3 for each digit of the result 5 tion I minus information 2. In addition, di <

, j_ are added. The corrected result of the intermediate information 1 and 2 one more time by a sub

The result 5 is called result 6. The re-bit time is delayed and transferred to "channel" 3

Lan result 6 is the complement of the final result, with information 1 running via an inverse link

■ ights ^{7 to 15} > ^{if the} result of the subtraction is 65 The arithmetic circuit then leads in the »channel« 3 di

calibration is negative. The correction value K 3 is the correction operation information 2 minus information 1 through

1 additional ^value ^ - ■ "■ £ ' ^e i ^cn with the exception of the lowest At the beginning of the arithmetic process, the over

Job. transmission input of the adding circuit in the "channel"

and one bit each is fed into "Channel" 3, which is an Ad-Lon of the value, 1 equals the uncorrected result in the smallest control. At the end of In the gymnastics part of each mark, there is an uncorrected result for that point ready and turns into a one character length delay line or equivalent Transfer memory. . .

In the addition process, the uncorrected result in "channel" 1 is fed back to the input of the adding circuit in order to be corrected by means of the value K1. Whenever the non-corrected result or the corrected result triggers a transfer, then the corrected result is the correct one. If no carryover occurs, the uncorrected result is applicable for further processing

use. , _,.

In the subtraction operation is the uncorrected result, which is in the memory of half a character is to be used when it is associated with a carry. Tnft If no carry pulse occurs during the subtraction process, the corrected result is to be used. At the end of the entire drawing time, that's what it stands for Final result of the operation is available for one and can be stored in field memory will. At the beginning of the subtraction operation must the value 1 in the lowest digit in "Channel" 2 and "Channel" 3 can be added. The carry pulses of uncorrected results, the next higher digit must always be added. this will thereby enables the carry bit in a Half-character delay line

is saved. One occurring with the corrected The carry pulse is only transferred to the next higher level in the addition process.

At the end of the entire operation, the results will be of the two subtractions then checked whether a transmission pulse occurs at its highest point, which indicates the correct result.

In the meantime the control unit of the computing circuit has the instruction of the program « converted and can select the desired result and the associated sign.

Normally a rotating memory rotates synchronously with the frequency of the supply voltage supply. As a result, the speed of the memory can be in the range of about plus or minus 1 percent of the Face value differ.

A delay line has a constant

delay time. The delay time of a

delay line should always be of a certain length

correspond to a memory track of the memory. if

a disk storage its peripheral speed

changes, the relationship between

delay time and memory track length. The Ver-

The delay line must then be lengthened or shortened

according to the speed change of the ro-

animal memory. . . ^ _n

The delay lines that are being adjusted

must consist of a fixed delay line

management and one or more additional defense

reluctance lines. The additional delay

Lines must be controlled for the necessary time J * ^e

γ _erZ Qoerungsleiter nut mehrereaji _e

n outputs, L

"* J" f _through i _au fen the entire Prutf ,, f JSX next following Prufimpuls transit | ₂ ^^ f „^ entire test arrangement, but ^ not only runs m | ^ _UN - _{D. T} ore of PiufU "£

will aucr ^ an ^ _{dgr outputs can e} _,

tunggefuhrt.Le ^ g ^ _y ogeruagsanord-jp

5 ^ At the entrance and the active exit between _{the right} length of a storage room

»Gang de PnJiHt ^^ _des p _laUenS p _ei . _chers . - ^ ₁ rather P ^u _y ^ ?, _sleiran gen for the informaUonsϊ _g . The ν ^e «° p \ _{like the} test line and koa ~ _w are ^ / ^^ Lgssignal of the test line _{. This} output signal is in ememg, ^^^ λ and opens the output ^ ^ ^r _fo f !; _ationS delay line, which corresponds to the turning ,, πι ^ ς rotating memory. _fld

number of rouc * of _the delay line ^

IJe ^ " _{Lä the} sub-bit _{repetition frequency ^ al}

»Depends on _{Dr £; h} numerical deviation of the rotating- ^

uiad the ^ mogi _{tand between z%} v _ei ^

^ n Speiser ^ aD. ^ _{ß half} ^ ₇₉

rebuild A g | ^ _{fe $ ten delay} , _{ei tion ad} , scUnde u « _{high ( highest} possible speed aes roü ^ _e ^ tspncru: additional controllable constriction

Jgs _n ^ uS the sum of the _P möghcher osi-i ₇₁ pulled srungen _abwe m: n _{Chunge abe} from the norm

t; ven_ ^{UDfl n§} _chen . _from e,

speed cor

Asynchronous input and multi-channel input free

And because it has to be very often associated with storing _οάβ Λο1 Fingabe keyboards _{d> a} "are arranged uüßerhalb of memory, one _dc verb ndungsanordnung used de conces-, ₆₁ - enter ^ information is outside _Szi: - rare that external memory or foreign, ■ "obligations the same timing as the p j _£ ner naoen that processes the data insbeson. ^ if the information on Iclefonk-gg

- ', connections over wide ent- _ie ]

₂ en uoenntgcii be. In such FaB _major Bitzeittakt the supplied information see _nd "ianesam you provided it with the timing of accounting _A nerf ^ like. The information must therefore be "protrude so überaß that they bitwe.se to Zeichew Shenweise to fields and field-wise to a VOH * constant information unit composed _ine

, 0 It is possible to have multiple inputs for the same Zen ₃ n to serve In this case, it is assumed that, _d, in the time of revolution of the rotating SpeI ^ r Chers per input terminal only a Informaüonsbil is supplied _au ° d5 of the rotating storage m can be divided into several «sectors, each Sektotfe ⁵⁵ elektrsih can be allied with one of the inputs., be, _e ! Assuming that the number of sectors or ^ is 16, 8 or 16 can practice keyboards, _E an input stage to be adjusted. In contrast to this, the first synchronous input stage shown is practically independent of the speed with which the information is supplied. It is _en nur'notwendig that the bit rate at de _"a t - as dici is fed information, lower 6 ₅ RITOP ^ hwindiskeit in the machine.

Ehrereaj gerungsleitung 4172 takes on the task of! . nschreibstation the arrangement of Figure 21. The e test j [onnation is throughput from the input delay line | 72 4173 a guided sondernj to 4173 rf the delay lines, the _zen the role of the tracks to co-Priiflei-j _from the arrangement according to F i g. 21 take over. ann ay _s information can from the delay lines; sanord- | 73 _a to 4173 rf via AND gate circuits 4174 a 2n Aus, i 4174 rf in the input-output core memory ier storage, 71 j, transferred. The AND gate circuits aers. j, _th replaces the transmission station from lationerijj g. 21.

nd can-; A plurality of AND gate circuits 4175 α to 4175 indicate the arrangement from FIG. 21 in which η anj _{B and} information are sensed for the first time in advance from the output. The information can be fed from these rotary j siD element circuits to a field selection circuit 4176 and from this field selection circuit to a comparison line circuit 4177 . An AND gate sequence, attitude 4178 performs the task of the second formwork ■ otieren-, _a g fo _r the in-Vorausabfühlen from the arrangement: wei be-j 4 _to the program from a program unit iMikro-j: select 79th An AND gate circuit 4181 ', sleitungld an arithmetic unit 4182 rotate the same up-2s as the corresponding parts from the arrangement Ver _in g _{according to} FIG. 21. The input-output memories en posi-j η \ _{α and} d 4171 fc work as distribution tracks, as standardization tracks and as input and output tracks of the arrangement according to FIG. 21.
ί The arrangement according to F i g. 26 works in the same way as the arrangement according to FIG. 21. The arrangement according to FIG. 26 is a modification of the rijLoj expansion according to FIG. 21, in which the selected uß, dieil _nam ; _scnen memory of the arrangement of Figure 21; contained ird einejjj which the storage discs 2796α to 2796rf and IE conces- _"7 67, and the composition - ^" - "tzungsspuren 2782a and 2782b (Fig. (F i g. 21). . 21) € Veraußer _{g! un} g _SS p _Uren 2833 (Fig. 21), the input trace in 2769 as derpig. 21), the tabulation track 2834 (Fig. 21), the isbeson- ^ jsgangssurse 2778 (Fig. 21), the program track lefoniei-, ₇₈₈ (Fig. 21), the output track 2778 (Fig. 21), Mte EtIt- JiI ₀ program track 2788 (Fig. 21) and the formats Faller 2792 (Fig. 21) through the core memory 4171 a very ^ d 4171 b from Fig. 26 are replaced.
- ^s ^. ^ec h "All operates the memory of Fig. 26 are parts of a so exceeded ^ _ü ß _en core memory. The data transfer is controlled ^ ^eic ^ ^s> lurch an address system similar to ner vOii- _{üit Cinem} random access, so DALI each position must be önerhalb an information processed hen ZeUj ₀ H ₁ addressed. the preparation of data itzt that _n of. Fi g 21 and 26 is the same. the core spitting spectral _ner are considerably more expensive than the individual ationsbi ^. _hanks iie _m the arrangement according to Fig. 21. The _{increased use} of delay devices allows the sector _e but the reductions of individual building blocks to an extent which is considerably smaller than in known S _6n systems.

Ten überei rjj _e arrangement according to FIG. 26 therefore shows a

^ egensat ^ r processing storage system based on multiple memories

.input ^ u holds. In these memories there is a processing

hwindig-5p _e j _c h _er , in which several data records together with

d. It is stored ISFL _s map data of at any

include deo with _a t _ens etch. This storage is in one

as diets store the memory system in a first

Order carried out, and also Pro-Fig. 21 Grammar information stored in the memory system, which contains predetermined instruction words. The processing memory contains the dynamic delay lines which are used to store data sets and groups of data sets or fields in different time channels, which are timed to process the data sets and to store the program information relating to the time in different time channels. The first memory has the first static memory 4171a .

The data records are transferred from the first static memory of the memory system in din processing memory of the memory system, and then from the processing memory in the second static memory 4171 b transmitted back to the processing system. A control and processing device, which also contains the processing memory, transfers the data records from the first static memory to the processing memory and transfers the data records back from the processing memory to the second static memory. When the data records pass through the control and processing device, the control and processing device rearranges the first order of the data records into a new order. This happens according to given commands that are contained in the program information, as well as depending on the maps.

Certain stored information is derived from the first static memory. The various circulating delay lines 4173 α to 4173 rf store and process the selected information that has been read out from the first static memory 4171 α. Clock-controlled AND gate circuits 4149 a to 4149 Λ lead the information that has been read from the first static memory, the delay lines 4173 α to 4173 rf in very specific time positions. The information supplied to the delay lines 4173 α to 4173 rf is also controlled by the program information from the programming circuit 4179. The data stored in the delay lines 4173 a to 4J 73 rf are selectively processed under the control of instructions stored in the program information of the programming unit 4179. The timed transmission and Auswählschaltur ^ selectively transmits data, arranged in a particular row, from the delay lines 4173 α to 41 "^ d into the delay line memory 4172nd The delay line memory 4172 stores the arranged in a particular row data in parallel form, in order to introduce this data selectively through the address circuit of the second static memory into specific positions or memory locations of the second static memory.

The delay lines 4173 a to 4173 rf, before each of which, for example, a delay before 4096 microseconds, stores multiple groups of bits, characters or fields, and two in memory locations or memory positions that are related to each other. The field selection scarf device 4176 and the comparison circuit 4177 compare the corresponding bits with all other bits; and use the comparison results for several operations or processes. Under these operations or processes is the control of the selective transfer of data records from a memory

to the data stored in the memory .ιηα, ^^^ ^ ^ ^ _processing operations f

i * SS = V Wahlschatag «. in other words, the delay is true,

Si

Record! the processing * - selectively in the common

is weSn processed in the delay lines field selection circuit 4176 selected S 4173? Opera'lon series carried out. Groups of characters or fields that come from, ve ^ den j "A ^ crirmcfniopn volktändie durchge- records that are in different

wendei the implementation ^ of the various sequences leads, can be sent to the comparison circuit 4177 id *

wenaei, uic JL7U1 & _{en will} "_ _The comparison circuit 4177 ve

Tin ^U aX Tdl ^S _g of esamten Verzögerungslei- operates or compares the fields with each other

tungssysteSTis the time selection and time sequence in advance of the various data records from aiJ wo

direction The AND gate circuits 4151a to 35 den are, and generated via the result of this V

4151 d 4152 and 4181 of the delay line equals a signal that is used to go away

4131 a, mm uuu allow a selek operation to control onszj'k.len. This comparison

systems are ^^^^^^ J ^^ _he ^P _{sebnis au} J _the comparison circuit controls «

vZS ^ Zts save u ⁿ nd the time selection via the AND ^ gate circuit 4175a bi, 4175Λ «·

scSrS circulating delay lines ₄ o cycle in which the information is the first man

4173 a to 4173 d let information be felt through the, and then an overtt

Zeltverzöiruninordnung go through in the supply cycle, which is via the AND gate circuit.

S ^ Ans ^ ueT of ^ So-member circuits as a-4174 a to 4174 a-runs. .. _{vh Aerli}

circuit for different time delays The program improvement can be related to the »

SirkL so that information in the delay line 45 in one of the sub-bit time positions of the gen »·

tangen introduced or also from certain time seeds delay line 4172 stored SJ

tanllen the entire delay line system and can also the program unit 417 »train

The delivery lines can be read so that the data records or data field

The data sets are processed by the time selection circuit and processed under program control

controls to get information in a very specific 50 köntien.

For this purpose 26 sheets of drawings

Claims (16)

Patent claims: L Electronic data processing system for mixing, sorting, arithmetic processing of data records consisting of data fields and for rearranging individual data fields with a memory arrangement consisting of a number of dynamic, synchronously circulating Save to save the data sets with a format memory to hold format information, which select certain data fields or parts of data fields, and with a program memory, the command information contains the editing method for the specified by the format information Prescribes data fields or data field parts, characterized in that from the Storage arrangement (Fi g. 21, 2782 a and 2782 b) the data sets by a first reading device (2783) readable and by a second reading device (2872) by the length of a data record delayed readable that the second reading device (2872) with a depending on Command and format information controlled as data processing device for selection (2751), for switching (2833) and for arithmetic processing (2762) is connected that Data fields which form organizational terms and are read out by the first reading device (2772) or data field parts of a pre-sensing and transmission control (field selector 2746, 2756, 2772), which can be controlled depending on command and format information and which controls the data concatenation device that the format and program memory (2792, 2787, 2794; 2788, 2786, 2791) an identifier from the first preceding each data record Reading device (2783) for addressing command information or format information can be supplied and that the format memory and the program memory are synchronous with that of the data records storing memory arrangement circulating dynamic memory arrangements (2791, 2784) contains. 2. Electronic data processing system according to claim 1, characterized in that in each individual memory of the memory arrangement and the format or program memory several data records or format and command information bit by bit in the manner of a time division multiplex system are stored in several time channels. 3. Electronic data processing system according to claim 2, characterized in that time channel transfer devices with controllable delay elements are available, which data records or data fields or data field parts from one time channel to another convict. 4. Electronic data processing system according to claim 3, characterized in that a first input of a circuit (352) under the control of a first control signal (353) Bit of a data record is supplied and that this bit is fed to the output (356) of the circuit (352) under the control of a second control signal (354) at a predetermined time can be inferred in such a way that this removed bit is in the desired time channel (FIG. 10). 5. Electronic data processing system according to claim 4, characterized in that the output of a first AND element (364) with the set input of a bistable multivibrator (363) is connected and the input of a second AND element (365) to the output of the Flip-flop is connected, that the inputs of the first AND element the bits of the data set and a first control signal for transmitting the bits of the data record into the bistable multivibrator (363) can be fed that the second input of the second AND element a second control signal can be supplied that the transmission of this bit from the flip-flop to the desired Time channel allowed, and that the output of the second AND element with the reset input the flip-flop is connected (F i g. Π). 6. Electronic data processing system according to claim 3, characterized in that it contains several cyclic storage devices (422, 413, 424), those controlled by the first Control signals (428, 429, 431), several successive bits via AND gates (425,426,427) are feedable, the successive; Bits of data records in several consecutive times Time channels are arranged, and that one of the output of the selected cyclic memory device, controlled by second control signals (438, 439, 441) via AND gates (442, 443, 444) successive bits are removable, the removed successive bits of data records in several successive time channels are arranged, which corresponds to the delay time of the selected cyclic storage device (Fig. 12). 7. Electronic data processing system according to claim 2, characterized in that the cyclic storage devices (422, 423, 424) all have a delay time that equal to or equal to a multiple of the delay times of the other storage devices is. 8. Electronic data processing system according to claim 3, characterized in that several delay devices (451, 452, 453) are connected in series and each of the have the same delay time of several successive bits of data records and that successive bits of data records in the delay devices via AND gates insertable (458, 459, 461) and removable from the delay devices (466, 467, 468) are. 9. Electronic data processing system according to claim 3, characterized in that it has a Time slot changing device (482) which includes each of a plurality of consecutive bits of data sets in a corresponding first selected time slot of each of the group of Arranges time channels, and that the successive bits of data records of a cyclic Storage device (485) are supplied via the time channel changing device and the bits of the data records are read out from the cyclic storage device via an AND element (487) if each bit is in a corresponding second selected time slot of each of the Groups of time channels is located (Fig. 14a). 10. Electronic data processing system according to claim 9, characterized in that an AND element (488) is switched on in the feedback line to control the number of delay cycles of the cyclic memory device (485) (Fig. 14a). 11. Electronic data processing system according to claim 9, characterized in that a first delay device (528) with a delay time which corresponds to the multiple, reduced by 1, of the entire group of time channels, and a second delay device (530) with a delay time which corresponds to the time of one Time channel, are provided, which together form the cyclic memory device, the successive bits at the output of the first delay device being removable and the output of the first delay circuit being connected to the input of the second delay device via an AND element (532). 12. Electronic data processing system according to claim 10, characterized in that an AND element (542) is located between the output and the input of the first delay devices (528, 530) (Fig. 15b). 13. Electronic data processing system according to claim 1, characterized in that the pre-sensing and transmission control device (2746, 2756) contains static storage devices (1802, 1808) which are suitable for storing a plurality of program information items which are selectively to be used to control the processing of data information fields and which can be actuated in relation to time for the transmission of data fields into the processing device (FIG. 18 b). 14. Electronic data processing system according to claim 13, characterized in that the static storage devices (1802, 1808) have a matrix structure (Fig. 18b). 15. Electronic data processing system according to claim 13, characterized in that a program data selection control device with a comparison device (1804) for comparing the maps of program data information and data sets is provided, and a comparison result storage device (1808) which controls the program data transmission device as a function of the stored comparison result ( Fig. 18b). 16. Electronic data processing system according to claim 15, characterized in that the program data selection control device comprises a comparison device for comparing two Data sets for the purpose of group control and a partial comparison result storage device contains which the program data transmission device depending on the stored Comparison result controls, and that identical maps the addition of selected data information fields in registers that are assigned to these fields of consecutive records are, and unequal maps the transfer of totals accumulated in the registers are, along with other selected data fields, into the second storage device the memory arrangement result.