CN111669648B - Video frequency doubling method - Google Patents
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- CN111669648B CN111669648B CN202010565581.9A CN202010565581A CN111669648B CN 111669648 B CN111669648 B CN 111669648B CN 202010565581 A CN202010565581 A CN 202010565581A CN 111669648 B CN111669648 B CN 111669648B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/44—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream, rendering scenes according to MPEG-4 scene graphs
- H04N21/4402—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream, rendering scenes according to MPEG-4 scene graphs involving reformatting operations of video signals for household redistribution, storage or real-time display
- H04N21/440263—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream, rendering scenes according to MPEG-4 scene graphs involving reformatting operations of video signals for household redistribution, storage or real-time display by altering the spatial resolution, e.g. for displaying on a connected PDA
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
- H04N7/0117—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level involving conversion of the spatial resolution of the incoming video signal
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Abstract
The invention discloses a video frequency doubling method, wherein a video input interface chip receives HDMI video signals output by a computer host and converts the HDMI video signals into standard VESA time sequence signals, an FPGA receives video pixel signals through a video acquisition module, the video pixel signals are buffered through an FIFO and then sent to a video frequency doubling module, the video frequency doubling module receives video signals with any frame rate and then outputs video frame signals at a fixed frequency of 60HZ, and the video output module receives the video signals output by the video frequency doubling module and converts the video signals into the standard VESA time sequence signals to be output to a video output interface chip for output and display. The video frequency doubling module is simple to use and can be used for a video processing system based on an FPGA.
Description
Technical Field
The invention belongs to the field of video processing, and relates to a video frequency doubling method.
Background
With the rapid development of the process technology and the manufacturing technology of the video display terminal, the resolution and the frame rate of video display are greatly improved, which means that the video display effect is improved. However, some video sources have a low frame rate, the display effect is greatly reduced, and even some display terminal devices do not support the frame rate of the original video source, so to solve the problem, the frame rate of the original video source needs to be increased by frequency doubling.
Disclosure of Invention
The invention aims to solve the problems of poor real-time performance, high cost and low flexibility of the conventional video frequency multiplication.
The invention provides a video frequency doubling method, which comprises the following specific steps:
firstly, an FPGA (Field-Programmable Gate Array) collects original video signals Output by a video receiving chip according to a VESA standard interface time sequence, buffers the original video signals through an FIFO (First in First out) module, namely a First in First out queue, performs clock domain conversion, and outputs data to a video frequency doubling module by a 200MHZ clock;
step two, the video frequency doubling module receives video signals with any frame rate and then outputs the video signals at a frame rate of 60 HZ;
and step three, the video output module receives the signal output by the video frequency doubling module, and then converts the signal into a standard VESA signal for output and display.
The video acquisition module receives external video data.
The video frequency doubling module can receive video sources with any frame rate.
The video frequency doubling module outputs video signals at a fixed 60HZ frame rate.
The maximum resolution of the video multiplier input is 1920x 1080.
The video frequency doubling module is used for an FPGA platform, and the specific design method comprises the following steps:
1) opening two memory areas with fixed size of 1920x1080x3 in the memory, wherein the first memory area is marked as A, and the second memory area is recorded as B;
2) the frequency doubling module counts rows and columns of the input video data and controls the video data to be stored in a specific block memory area according to the frame number;
3) the frequency doubling module controls a first frame of image to be stored in the memory area 0, an effective signal is output after the first frame of image is stored, meanwhile, the next frame of image is stored in the memory area 1, the frequency doubling module continuously detects the effective signal, video signals are continuously output from the memory area 0 at a frame rate of 60HZ after the effective signal is detected, when the memory area 1 is filled with second frame of image data, an effective signal of the memory area 1 is output, at the moment, the frequency doubling module outputs the video signals from the memory area 1 at a frame rate of 60HZ, and simultaneously, a third frame of video signals is stored in the memory area 0, so that the function of doubling the video frequency at any frame rate to 60HZ can be realized repeatedly.
The video frequency doubling module can be directly used on an FPGA development platform.
The video frequency doubling module can receive video signals with any frame rate, the input frame rate can be larger than the output frame rate or smaller than the output frame rate, internal data flow is processed in a full pipeline mode, the use of logic resources is reduced, the module only has delay of one frame of image, the resolution ratio of the input image is adjustable, and the video frequency doubling module can be used for design needing a video frequency doubling function.
Drawings
FIG. 1 is a system diagram of a method for video frequency doubling;
FIG. 2 is a schematic block diagram of a video frequency doubling module;
FIG. 3 is a timing diagram of an original video receive signal;
FIG. 4 is a first flowchart of a processing method of the video frequency doubling module;
fig. 5 is a flowchart of a processing method of the video frequency doubling module.
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.
The first implementation mode comprises the following steps:
the embodiment discloses a video frequency doubling method, which comprises the following steps:
firstly, a video acquisition module acquires an original video signal and performs clock domain conversion, and a 200MHZ clock outputs converted video data to a video frequency doubling module;
step two, the video frequency doubling module outputs video signals to the received video data at a frame rate of 60 HZ;
and step three, the video output module receives the signal output by the video frequency doubling module and converts the signal into a standard VESA signal for output and display.
In the above steps, the specific process of the first step is as follows: the FPGA acquires an original video signal output by the video receiving chip according to the VESA standard interface time sequence, the original video signal is cached through an FIFO module and subjected to clock domain conversion, and data are output to a video frequency doubling module through a 200MHZ clock. The video acquisition module receives external video data. The video frequency doubling module can receive video sources with any frame rate. The video frequency doubling module outputs video signals at a fixed 60HZ frame rate.
In the above steps, as shown in fig. 4 and 5, the processing method of the video frequency doubling module is as follows:
1) two memory areas are opened up in the memory module, the first memory area is marked as A, and the second memory area records B;
2) the video frequency doubling module counts rows and columns of input video data, and the control module controls the video data to be stored in a memory area of which block according to the frame number;
3) storing a first frame of image into a first internal memory area A under the control of a video frequency doubling module, outputting an effective signal to a control module after the first frame of image is stored, simultaneously storing a next frame of image into a second internal memory area B by the control module, simultaneously outputting the effective signal to the video frequency doubling module by the control module, and starting to continuously output a video signal from the first internal memory area A to a video output module at a 60HZ frame rate after the video frequency doubling module detects the effective signal;
when the second block internal memory area B is filled with the second frame image data, the control module stores the next frame image into the first block internal memory area A, meanwhile, the control module outputs an effective signal to the video frequency doubling module, and the video frequency doubling module starts to continuously output the video signal to the video output module from the second block internal memory area B at a 60HZ frame rate after detecting the effective signal;
when the second frame of image data is filled in the second block memory area B, the third frame of video signal is stored in the first block memory area A, and the function of doubling the frequency of the video at any frame rate to 60HZ can be realized repeatedly.
In the above steps, the maximum resolution of the video frequency doubling module input is 1920 × 1080. The video frequency doubling module can be directly used on an FPGA development platform.
The video frequency doubling module can receive video signals with any frame rate, the input frame rate can be larger than the output frame rate or smaller than the output frame rate, internal data flow is processed in a full pipeline mode, use of logic resources is reduced, the module only has delay of one frame of image, resolution of the input image is adjustable, and the video frequency doubling module can be used for design of needing a video frequency doubling function.
The second embodiment:
referring to fig. 1, the present embodiment discloses a method for video frequency doubling, including: a video acquisition module, a video frequency doubling module and a video output module, wherein,
the parameter configuration module completes configuration of the HDMI receiving chip, the video acquisition module, the video frequency doubling module, the video display module and the HDMI transmitting chip according to the resolution requirement.
The HDMI receiving chip completes HDMI video receiving, and converts the HDMI video receiving into RGB24 bit video signals for FPGA acquisition.
The video acquisition module finishes the acquisition of RGB24 bit data according to the detected video frame line-field synchronizing signal.
The video frequency doubling module receives the image data of the video acquisition module, stores the image data into the memory area according to frames, and then outputs video signals at a fixed 60HZ frame rate.
The video display module receives the video data output by the video frequency doubling module, converts the video data into RGB24 bit time sequence signals and sends the signals to the HDMI transmitting chip.
The HDMI transmitting chip outputs HDMI signals which can be received by the standard display under the control of the video display module.
A method for video frequency multiplication specifically comprises the following steps:
1) the HDMI video receiving chip collects 1920x1080 resolution video data output by a computer host, and outputs the video data at 148.5MHZ clock speed through an RGB24 data bus;
2) the parameter configuration module writes initialization parameters into an internal register of the HDMI receiving chip through an I2C interface, initializes the initialization parameters into 1920x1080 resolution, and initializes the output time sequence into RGB24 which is single-edge output; setting the resolution of a video frequency doubling module to 1920x 1080; the HDMI transmitting chip is initialized to 1920x1080 resolution, and its input reception is initialized to RGB24 as a single edge input interface.
3) The video acquisition module needs to realize an RGB24 acquisition interface and an FIFO output interface, the RGB24 bit video interface comprises CLK, HS, VS, DE and DATA [24] signal lines, the CLK clock is 148.5MHZ, HS is a line synchronous signal, VS is a field synchronous signal, DE is an effective output signal, DATA [24] is a DATA signal, the video acquisition module detects the start of each frame of video signal according to the HS and VS signals, then acquires effective video DATA according to the effective DE signal, and particularly refers to a timing sequence diagram 2, and finally outputs the video DATA to a next-level DATA buffer module through the FIFO interface.
4) The video frequency doubling module is characterized in that two memory areas with fixed sizes of 1920x1080x3 are opened in DDR3, the memory area of a first block is marked as 0, and the memory area of a second block is recorded as 1; the frequency doubling module counts rows and columns of the input video data and controls the video data to be stored in a specific block memory area according to the frame number; the method comprises the steps that a first frame of image is stored in a memory area 0 under the control of a frequency doubling module, an effective signal is output after the first frame of image is stored, meanwhile, the next frame of image is stored in a memory area 1, the frequency doubling module continuously detects the effective signal, video signals are continuously output from the memory area 0 at a 60HZ frame rate after the effective signal is detected, when the memory area 1 is filled with second frame of image data, the effective signal of the memory area 1 is output, at the moment, the frequency doubling module outputs the video signals from the memory area 1 at the 60HZ frame rate, and simultaneously, a third frame of video signals is stored in the memory area 0, and the function of video frequency doubling to the 60HZ frame rate at any frame rate can be achieved repeatedly.
The third embodiment is as follows:
on the basis of the first and second embodiments, the present embodiment further includes a video overlay module between the video frequency doubling module and the video display module. Specifically, after the multiple paths of video frequency doubling modules are respectively zoomed through a video stepless zooming module, the superposition is uniformly completed in the video superposition module according to superposition parameters, and the video superposition module sends the superposed video to the video display module.
When the M paths of image data are superposed, the video superposition module respectively intercepts two frames of image data of different paths and then superposes the two frames of image data according to the configuration parameters and the superposition coordinate points of the parameter configuration module.
The video superposition module firstly acquires a superposition coordinate point before two frames of images are superposed, then acquires first new coordinate point pixel information of an abscissa-1 in one frame of image and second new coordinate point pixel information of an abscissa-1 in the other frame of image, and then adjusts the pixel information of the superposition coordinate point according to the first new coordinate point pixel information and the second new coordinate point pixel information; and finally, intercepting two frames of image data of different paths and then superposing the two frames of image data at present.
Before the video overlapping module calls M paths of zooming data, each path of zooming data is converted into a plurality of frames of image data, and the plurality of frames of image data of the M paths are overlapped in the video overlapping module. One video cache module corresponds to one video stepless scaling module; a video frequency doubling module is arranged between the video cache module and the video stepless zooming module; the video frequency doubling module calls the video data in the video cache module and outputs the video data to the video stepless scaling module at a frame rate of 60 HZ.
The video overlapping module receives four paths of video data through the AXI-STREAM interface, completes overlapping processing on a frame of video data according to the input and output resolution set by the parameter configuration module, and then outputs the overlapped video data through the AXI-STREAM interface. The video display module receives the video data output by the video scaling module, converts the video data into RGB24 bit timing signals and sends the signals to the HDMI transmitting chip. The HDMI transmitting chip outputs HDMI signals which can be received by the standard display under the control of the video display module.
The video superposition module is developed by adopting C language, the algorithm adopts bilinear interpolation algorithm, the C code is optimized through an optimization instruction, and the specific optimization steps comprise: A) firstly, compiling C language codes of a video zooming module; B) optimizing input and output variables of a video scaling module into an AXI-STREAM interface, wherein the data bit width is 24 bits; C) an outer-layer circulation structure in the algorithm is subjected to pipeline optimization, so that the internal pipeline processing of the module is ensured, and the algorithm efficiency is improved; D) performing expansion optimization on the innermost layer cycle to ensure that the output of one pixel is finished in each clock period; E) and (5) carrying out constraint processing on the module clock, and positioning the clock period to be 6.73 ns. F) After the video zooming module code is finished, C language simulation is firstly carried out, and the algorithm is guaranteed to have no problem; G) and C, integrating the codes after the simulation is passed, converting the codes into FPGA logic codes, and then simulating the integrated codes. H) After simulation is successful, the video scaling module IP is derived, and then the IP can be used for design in FPGA development.
The foregoing is a more detailed description of the present application in connection with specific embodiments thereof, and it is not intended that the present application be limited to the specific embodiments thereof. For a person skilled in the art to which the present application pertains, several simple alternatives can be made without departing from the inventive concept of the present application.
Claims (7)
1. A method for video frequency doubling, comprising the steps of:
firstly, a video acquisition module acquires an original video signal and performs clock domain conversion, and a 200MHZ clock outputs converted video data to a video frequency doubling module;
step two, the video frequency doubling module outputs the received video data to a video signal at a fixed 60HZ frame rate;
thirdly, the video output module receives the signal output by the video frequency doubling module and converts the signal into a standard VESA signal for output and display;
the processing method of the video frequency doubling module comprises the following steps:
1) two memory areas are opened up in the memory module, the first memory area is marked as A, and the second memory area records B;
2) the video frequency doubling module counts rows and columns of input video data, and the control module controls the video data to be stored in a memory area of which block according to the frame number;
3) storing a first frame of image into a first internal memory area A under the control of a video frequency doubling module, outputting an effective signal to a control module after the first frame of image is stored, simultaneously storing a next frame of image into a second internal memory area B by the control module, simultaneously outputting the effective signal to the video frequency doubling module by the control module, and starting to continuously output a video signal from the first internal memory area A to a video output module at a 60HZ frame rate after the video frequency doubling module detects the effective signal;
when the second block internal memory area B is filled with the second frame image data, the control module stores the next frame image into the first block internal memory area A, meanwhile, the control module outputs an effective signal to the video frequency doubling module, and the video frequency doubling module starts to continuously output the video signal to the video output module from the second block internal memory area B at a 60HZ frame rate after detecting the effective signal;
when the second frame of image data is filled in the second block memory area B, the third frame of video signal is stored in the first block memory area A, and the function of doubling the frequency of the video at any frame rate to 60HZ can be realized repeatedly.
2. The method according to claim 1, wherein the specific process of the step one is as follows: the FPGA acquires an original video signal output by the video receiving chip according to the VESA standard interface time sequence, the original video signal is cached through an FIFO module and subjected to clock domain conversion, and data are output to a video frequency doubling module through a 200MHZ clock.
3. The method according to claim 1, wherein the video capture module receives external video data.
4. The method according to claim 1, wherein the video frequency doubling module can receive video sources with any frame rate.
5. The method according to claim 1, wherein the video frequency doubling module outputs the video signal at a fixed 60HZ frame rate.
6. The method of claim 1, wherein the maximum resolution of the video frequency doubling module input is 1920x 1080.
7. The method according to claim 1, wherein the video frequency doubling module can be directly used on an FPGA development platform.
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| TWI761064B (en) * | 2021-02-04 | 2022-04-11 | 瑞昱半導體股份有限公司 | Control circuit and control method applied to display panel |
| CN115209024A (en) * | 2022-07-18 | 2022-10-18 | 湖南华南光电(集团)有限责任公司 | FPGA (field programmable Gate array) electronic zoom preposed DDR (double data Rate) based camera system |
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