CN106780288B - Hardware acceleration circuit that polygon was filled - Google Patents
Hardware acceleration circuit that polygon was filled Download PDFInfo
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- CN106780288B CN106780288B CN201611125211.3A CN201611125211A CN106780288B CN 106780288 B CN106780288 B CN 106780288B CN 201611125211 A CN201611125211 A CN 201611125211A CN 106780288 B CN106780288 B CN 106780288B
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T1/00—General purpose image data processing
- G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T2200/00—Indexing scheme for image data processing or generation, in general
- G06T2200/28—Indexing scheme for image data processing or generation, in general involving image processing hardware
Abstract
The invention belongs to the technical field of graphic generation, and relates to a hardware acceleration circuit for polygon filling. The polygon filling hardware acceleration circuit comprises a DSP digital signal processor, an FPGA programmable logic device, a first frame memory and a second frame memory. The FPGA programmable logic device comprises a frame controller, a marking data register, a color data register, a state machine and a time sequence module. The frame controller is connected with the DSP digital signal processor, the first frame memory, the second frame memory, the time sequence module, the state machine, the marking data register and the color data register; the time sequence module, the marking data register and the color data register are simultaneously connected with the state machine. The polygon filling hardware accelerating circuit can obviously improve the polygon filling efficiency and reduce the software algorithm load, thereby improving the whole picture generating efficiency.
Description
Technical Field
The invention belongs to the technical field of graphic generation, and relates to a hardware acceleration implementation method and circuit for polygon filling.
Background
Polygon fill is an important piece of research in computer graphics, and its function is to modify all pixel elements within a given polygon footprint on the display screen to specified color data. The existing polygon filling algorithm is generally implemented by adopting a software algorithm method, such as a seed filling algorithm, a scanning line filling algorithm, an edge mark filling algorithm and the like. The method is characterized in that software calculates color data of all pixels in a polygon area needing to be filled and writes the color data into a frame memory.
With the development of the technology, the resolution of the liquid crystal display is higher and higher, the requirement for polygon filling is higher and higher, and the content of the picture to be displayed is more and more complex, which puts higher requirements on the polygon filling circuit. The existing software algorithm realization polygon filling method has the following defects: the algorithm is complex, the polygon filling efficiency is low, and the requirements of high resolution and real-time application are difficult to meet.
Disclosure of Invention
The purpose of the invention is as follows: the polygon filling circuit is easy to implement, strong in expandability, high in efficiency and realized by hardware.
In order to adapt to the trend of the airborne cabin liquid crystal display developing towards high resolution and high picture complexity, a high-performance and easy-to-realize polygon filling implementation scheme is provided, a DSP (digital signal processor) 1 and an FPGA (field programmable gate array) programmable logic device 2 are used as main processing devices and perform ping-pong operation on a first frame memory 8 and a second frame memory 9, the DSP 1 writes marking information and color information of a polygon boundary to be filled into the first frame memory 8 or the second frame memory 9, the FPGA programmable logic device 2 reads pixel marks and color information in the first frame memory 8 or the second frame memory 9 point by point and line by line according to a scanning sequence, a state machine 5 performs state conversion processing on the marking information and processes color data at the same time, and the processed color data is written into the first frame memory 8 or the second frame memory 9 by a frame controller 3, thereby realizing the hardware filling of the polygon.
The technical scheme of the invention is as follows: a polygon filled hardware acceleration circuit, the circuit comprising: the device comprises a DSP (digital signal processor) 1, an FPGA (field programmable gate array) programmable logic device 2, a first frame memory 8 and a second frame memory 9;
the FPGA programmable logic device 2 comprises a frame controller 3, a time sequence module 4, a state machine 5, a marking data register 6 and a color data register 7;
the frame controller 3 is respectively connected with the DSP 1, the first frame memory 8, the second frame memory 9, the time sequence module 4, the state machine 5, the marking data register 6 and the color data register 7;
the time sequence module 4, the marking data register 6 and the color data register 7 are also respectively connected with the state machine 5;
the DSP 1 writes pixel data into a first frame memory 8 or a second frame memory 9 through a frame controller 3, wherein the written data is comprehensive data containing pixel color information and marking information;
the DSP digital signal processor 1 and the FPGA programmable logic device 2 adopt a ping-pong operation mode for a first frame memory 8 and a second frame memory 9 through a frame controller 3, and alternately switch by taking a field synchronization signal sent by a time sequence module 4 as a period;
during the operation of the FPGA programmable logic device 2 on the first frame memory 8 or the second frame memory 9, pixel data are processed point by point and line by line according to a screen scanning sequence, and the processing of the pixel data in each address comprises two operations of reading and writing, and is completed within and outside one pixel clock period;
the FPGA programmable logic device 2 operates each address unit of the first frame memory 8 or the second frame memory 9 in two steps, wherein the first step is reading operation, and pixel color data in the frame memory is read out and displayed; writing the processed color data information into the same frame memory address;
when reading the pixel data in the first frame memory 8 or the second frame memory 9, the FPGA programmable logic device 2 registers the color information contained in the read pixel data by the color data register 7, and registers the read mark information by the mark data register 6;
the marking data register 6 sends the pixel marking information to the state machine 5, the color data register 7 sends the pixel color information to the state machine 5, the state machine 5 carries out state transition processing according to the previous marking state, the current marking state information and the previous state, and meanwhile, the processed pixel color information is sent to the frame controller 3 and written into the first frame memory 8 or the second frame memory 9 by the frame controller.
The invention has the beneficial effects that: the polygon filling hardware accelerating circuit takes a DSP (digital signal processor) 1 and an FPGA (field programmable gate array) comprehensive programmable device 2 as main processing chips, adopts a marking data register 6 and a color data register 7 in the FPGA programmable logic device 1 to register a polygon boundary pixel marking signal and a color signal which are pre-placed in a first frame memory 8 or a second frame memory 9 of the DSP digital signal processor 2, uses a state machine 5 to carry out marking state transfer and color data processing on marking and color information, and fills processed colors in corresponding polygon internal areas. The scheme adopts hardware to realize polygonal area filling, is simple and feasible, has high hardware realization efficiency, reduces the complexity of a software algorithm, and improves the polygonal filling efficiency and the graphic generation and display efficiency. The polygon filling hardware accelerating circuit can meet the pixel filling requirements of various irregular polygons and can complete the filling of a plurality of polygons in one picture.
Drawings
FIG. 1 is a functional block diagram of the polygon fill hardware acceleration circuit of the present invention;
the system comprises a 1-DSP digital signal processor, a 2-FPGA programmable logic device, a 3-frame controller, a 4-time sequence module, a 5-state machine, a 6-marking data register, a 7-color data register, an 8-first frame memory and a 9-second frame memory.
Detailed Description
The present invention will be described in detail with reference to the accompanying drawings.
A polygon filled hardware acceleration circuit, the circuit comprising: the device comprises a DSP (digital signal processor) 1, an FPGA (field programmable gate array) programmable logic device 2, a first frame memory 8 and a second frame memory 9;
the FPGA programmable logic device 2 comprises a frame controller 3, a time sequence module 4, a state machine 5, a marking data register 6 and a color data register 7;
the frame controller 3 is respectively connected with the DSP 1, the first frame memory 8, the second frame memory 9, the time sequence module 4, the state machine 5, the marking data register 6 and the color data register 7;
the time sequence module 4, the marking data register 6 and the color data register 7 are also respectively connected with the state machine 5.
The DSP 1 is used for carrying out drawing algorithm operation to obtain pixel data and address data of a polygon boundary, wherein the pixel data is comprehensive data containing mark information and color information, the mark information is two-bit binary data, and the three states are a filling mark, an ending mark and a null mark respectively; the color information is RGB three-color component data. And along the picture scanning direction, setting the polygon boundary pixels at the filling starting position with filling marks, setting the polygon boundary pixels at the filling ending position with ending marks, and setting the remaining pixels at positions which do not need to be filled with filling marks with empty marks.
The frame controller 3 is configured to receive an access request of the DSP digital signal processor 1 and the FPGA programmable logic device 2 for a frame memory device, perform access to the first frame memory 8 and the second frame memory 9 in a ping-pong operation manner, and perform alternate switching with a field synchronization signal generated by the timing module 4 as a period, where when the DSP digital signal processor 1 accesses one of the frame memories in a certain field period, the FPGA programmable logic device 2 accesses the other frame memory, the DSP digital signal processor 1 accesses a frame memory operated by a previous field FPGA in a next field period, and the FPGA programmable logic device 2 accesses a frame memory operated by the previous DSP digital signal processor 1. The DSP digital signal processor 1 writes the pixel address signal and the pixel data signal obtained by operation into a certain frame memory through a frame controller 3, and the FPGA programmable logic device 2 carries out filling acceleration processing on the mark data and the color data written into the DSP digital signal processor 1 in the frame memory in the next field.
The FPGA programmable logic device 2 performs read-write operation on the first frame memory 8 or the second frame memory 9 point by point and line by line according to a scanning sequence. The clock frequency of the FPGA programmable logic device 2 accessing the frame memory is generated by the time sequence module 4 by frequency multiplication of the pixel clock, and is twice of the pixel clock frequency. The FPGA programmable logic device 2 operates the pixel data of each address unit in the first frame memory 8 or the second frame memory 9 into two steps, the first step is reading operation, corresponding to the first frame memory operation clock period of the address unit, the pixel data written into the frame memory by the DSP digital signal processor 1 is read and displayed, meanwhile, the marking information and the color information in the pixel data are respectively registered, the marking information is registered by the marking data register 6, and the color data is registered by the color data register 7; the second step is a write operation, corresponding to the second frame memory operation clock cycle of the address unit, and writing the corresponding color data back to the currently operated frame memory address unit according to the processing result of the state machine 5 on the marking data and the color data.
The state machine 5 includes three states, which are a current pixel output state, a filling state, and an end filling state, and outputs the processed pixel data in each state. The initial state of the state machine 5 is the current pixel output state, and the state transition processing is performed with the pixel clock as a cycle according to the marking information sent by the marking data register 6. When the state machine 5 is in the current pixel output state, if the received pixel mark is an empty mark, the state machine is kept in the current pixel output state, the FPGA programmable logic device 2 reads out the pixel color information of the current address, and writes back all-zero data in the frame memory address unit to empty the pixel color information; if the received pixel mark is a filling mark, the state machine 5 is converted into a filling state, and the FPGA programmable logic device 2 registers the color data while reading out the pixel color information of the current address, and writes the color data back to the current address unit. When the state machine 5 is in a filling state, if the received pixel mark is a null mark, the state machine is kept in the filling state, the FPGA programmable logic device 2 outputs color data registered by the color data register 7, and writes the color data back to the current frame memory address unit; if the received pixel mark is the end mark, the state machine 5 is switched to the end filling state, the FPGA programmable logic device 2 outputs the color data registered by the color data register 7, and writes back all zero data in the frame memory address unit to empty the frame memory address unit. When the state machine 5 is in the end filling state, if the received pixel is marked as the empty mark, the state machine 5 is switched to the current pixel output state, the FPGA programmable logic device 2 reads out the pixel color information of the current address, and writes back all-zero data in the frame memory address unit to empty the pixel.
In summary, the present invention provides a polygon filling hardware accelerating circuit with easy implementation, strong expandability and high efficiency, which adopts a DSP digital signal processor 1 and an FPGA programmable logic device 2 as main processing devices, the DSP digital signal processor 2 performs ping-pong operation on a first frame memory 8 and a second frame memory 9, the DSP digital signal processor 2 writes mark information and color information of a polygon boundary to be filled into the first frame memory 8 or the second frame memory 9, the FPGA programmable logic device 2 reads pixel marks and color information in the frame memory point by point and line by line according to a scanning sequence, a state machine 5 performs state conversion processing according to the mark information, and meanwhile, the color data is processed and the processed color data is written into the first frame memory 8 or the second frame memory 9 by the frame controller 3, so that the hardware filling of the polygon is realized.
The DSP 1 may be implemented by DSP devices of AD company or TI company. When the FPGA programmable logic device 2 is implemented, any series of FPGAs from Altera corporation or Xilinx corporation can be used. After the programmable logic device is selected, the frame controller 3, the mark data register 6, the color data register 7, the timing module 4 and the state machine 5 are realized by programming of a VHDL or Verilog hardware description language, and can also be realized by adopting a graphic input mode. The first frame memory 8 and the second frame memory 9 can be selected from conventional random static or dynamic memories.
Claims (1)
1. A polygon padding hardware acceleration circuit, the circuit comprising: the device comprises a DSP (digital signal processor) (1), an FPGA (field programmable gate array) programmable logic device (2), a first frame memory (8) and a second frame memory (9);
the FPGA programmable logic device (2) comprises a frame controller (3), a time sequence module (4), a state machine (5), a marking data register (6) and a color data register (7);
the frame controller (3) is respectively connected with the DSP digital signal processor (1), the first frame memory (8), the second frame memory (9), the time sequence module (4), the state machine (5), the marking data register (6) and the color data register (7);
the time sequence module (4), the marking data register (6) and the color data register (7) are also respectively connected with the state machine (5);
the DSP digital signal processor (1) writes pixel data into a first frame memory (8) or a second frame memory (9) through a frame controller (3), wherein the written data is comprehensive data containing pixel color information and marking information;
the DSP digital signal processor (1) and the FPGA programmable logic device (2) adopt a ping-pong operation mode for the first frame memory (8) and the second frame memory (9) through the frame controller (3), and alternately switch by taking a field synchronization signal sent by the timing module (4) as a period;
during the operation of the FPGA programmable logic device (2) on the first frame memory (8) or the second frame memory (9), pixel data are processed point by point and line by line according to a screen scanning sequence, and the processing of the pixel data in each address comprises two operations of reading and writing and is completed in one pixel clock period;
the FPGA programmable logic device (2) performs operation on each address unit of a first frame memory (8) or a second frame memory (9) in two steps, wherein the first step is reading operation, and pixel color data in the frame memory is read out and displayed; writing the processed color data information into the same frame memory address;
when reading pixel data in a first frame memory (8) or a second frame memory (9), the FPGA programmable logic device (2) registers color information contained in the read pixel data by a color data register (7) and registers read mark information by a mark data register (6);
the state machine (5) comprises three states, namely a current pixel output state, a filling state and an end filling state, and correspondingly outputs the processed pixel data in each state; the initial state of the state machine (5) is the current pixel output state, and the state transfer processing is carried out by taking a pixel clock as a period according to the marking information sent by the marking data register (6); when the state machine (5) is in the current pixel output state, if the received pixel mark is an empty mark, the state machine is kept in the current pixel output state, the FPGA programmable logic device (2) reads out the pixel color information of the current address, and writes back all-zero data in the frame memory address unit to empty the pixel color information; if the received pixel mark is a filling mark, the state machine (5) is converted into a filling state, and the FPGA programmable logic device (2) registers the color data while reading out the pixel color information of the current address and writes the color data back to the current memory address unit; when the state machine (5) is in a filling state, if the received pixel mark is an empty mark, the state machine is kept in the filling state, the FPGA programmable logic device (2) outputs color data registered by a color data register (7) and writes the color data back to a current memory address unit; if the received pixel mark is an end mark, the state machine (5) is switched to an end filling state, the FPGA programmable logic device (2) outputs color data registered by the color data register (7), and writes back all-zero data in the frame memory address unit to empty the color data; when the state machine (5) is in a filling ending state, if the received pixel is marked as an empty mark, the state machine (5) is converted into a current pixel output state, the FPGA programmable logic device (2) reads out pixel color information of a current address, and writes all-zero data back in the frame memory address unit to empty the pixel color information;
the marking data register (6) sends the pixel marking information to the state machine (5), the color data register (7) sends the pixel color information to the state machine (5), the state machine (5) carries out state transition processing according to the previous marking state, the current marking state information and the previous state, and meanwhile, the processed pixel color information is sent to the frame controller (3) and written into the first frame memory (8) or the second frame memory (9).
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