CN103475842A - Method for converting LVDS video signals into MIPI video signals - Google Patents
Method for converting LVDS video signals into MIPI video signals Download PDFInfo
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Abstract
The invention discloses a method for converting LVDS video signals into MIPI video signals. The method comprises the following steps of 1 respectively and simultaneously receiving and demodulating each link of the LVDS video signals to produce parallel demodulation data and LVDS pixel clocks of all of links; 2 performing video decoding to the parallel demodulation data of all of links to generate LVDS video source signals of all of links, wherein the LVDS video source signals include LVDS video source data and LVDS video source synchronizing signals, and the LVDS pixel clocks are converted into LVDS video source pixel clocks; 3 converting the LVDS video source signals of all of links into RGB video signals; 4 converting the RGB video signals into the MIPI video signals. The method has the advantages of being simple in operation, high in detecting efficiency and low in cost.
Description
Technical field
The present invention relates to demonstration field and the field tests of liquid crystal module, refer to that particularly a kind of LVDS vision signal is converted to MIPI vision signal method.
Background technology
Liquid crystal display module (Liquid Crystal Display Module, hereinafter to be referred as liquid crystal module) is the critical component that liquid crystal display can normally show, it is by liquid crystal display screen, original paper backlight, Graphics Processing chip and the electric circuit constitute.Liquid crystal display module structure is accurate, processing procedure is complicated, manufacturing technique requirent is high, in order to guarantee yields when producing, need to produce various test video signals by special liquid crystal module testing apparatus and be input in liquid crystal module and show, strictly, comprehensively detect its display effect.Its display interface of common liquid crystals module of using on TV, display product at present and inner Graphics Processing circuit are used LVDS(Low-Voltage Differential Signaling, Low Voltage Differential Signal) signal carrys out work.And existing liquid crystal module testing device also corresponding output be that the LVDS vision signal is to realize the test of module.Because common liquid crystals module production time is of a specified duration, output is large, so its module testing apparatus also uses in a large number.
Constantly pursue high definition more, display effect more true to nature on mobile device, portable equipment along with people, therefore the common liquid crystals module can't meet the need gradually.So occurred on market that a kind of novel liquid crystal module with ultrahigh resolution and very-high solution density meets people's demand.The interface of this liquid crystal module and inner Graphics Processing circuit adopt MIPI(Mobile Industry Processor Interface to move the industry processor interface) signaling interface.This interface is formulated by the MIPI alliance that comprises the companies such as ARM, Samsung, Intel, purpose is that handle movement, inner each assembly of portable equipment are as nuclear interface standardizings and open each other such as camera, display screen, processors, thereby improved performance, reduced cost and power consumption.The MIPI interface can not only be supported ultrahigh resolution and refresh rate, and has farther transmission range, better Electro Magnetic Compatibility, and therefore the liquid crystal module with the MIPI interface has become development trend.
Yet the testing apparatus of MIPI liquid crystal module need to be exported same MIPI test signal, but existing common liquid crystals module testing apparatus does not have this function, and the common liquid crystals module also continues to produce, its testing apparatus does not enter the replacement cycle yet will be continued to use.Although the module manufacturer also produces the MIPI liquid crystal module, in order to protect investment, to reduce production costs, can not eliminate existing equipment, again make a big purchase expensive MIPI module Special testing device in large quantities.In order to produce cheaply the MIPI liquid crystal module in enormous quantities within short-term and to guarantee its yields, just still reuse on a large scale existing common module testing apparatus.
Therefore, need a kind of technical scheme the LVDS signal can be converted to the method for MIPI vision signal, common liquid crystals module testing apparatus can be tested the MIPI module by this conversion equipment.
Summary of the invention
The object of the present invention is to provide a kind of LVDS vision signal to be converted to MIPI vision signal method, it has characteristics simple to operate, that detection efficiency is high, cost is low.
For achieving the above object, the method for 8MIPI vision signal that the LVDS vision signal is converted to that the present invention is designed, its special character is, comprises the following steps:
Preferably, described LVDS vision signal comprises the LVDS vision signal of single LINK, two LINK, four LINK, the LVDS vision signal of described single LINK is that LINK1 transmits all video pixels, the LVDS vision signal of described couple of LINK, comprise LINK1, bis-links of LINK2, transmit respectively the odd even video pixel; The LVDS vision signal of described four LINK, comprise four links, according to the video pixel order, at LINK1, LINK2, LINK3, LINK4, transmits successively; Described MIPI vision signal shows module for the MIPI of the single whole screen type of 4LANE, 8LANE left and right split screen type and 8LANE odd even split screen type, when the MIPI vision signal that will change is exported to the MIPI demonstration module of the single whole screen type of 4LANE, the LVDS vision signal is transmitted with single, double, four LINK modes; When the MIPI vision signal that will change is exported to the MIPI liquid crystal display module of 8LANE left and right split screen type, 8LANE odd even split screen type, the LVDS vision signal is transmitted in four LINK modes; The LVDS vision signal of described each link comprises LVDS receive clock and LVDS data, and described LVDS data are by the transmission of LVDS data/address bus, and described LVDS data/address bus comprises some root holding wires, and every holding wire transmits the serial code signal.
Preferably, before in described step 1, the vision signal of each link being carried out to receiving demodulation, according to the characteristic of the LVDS vision signal that will receive, LVDS vision signal decoding parametric, LVDS video conversion parameter are set; Receive the MIPI video conversion configurations parameter in the LVDS vision signal, the configuration operation and the MIPI that carry out the MIPI conversion process show the module initialization operation; Produce LVDS coding standard control signal, LVDS video color range bit wide control signal, LVDS odd even pixel reverse control signal, LVDS video signal cable sequence control signal according to described LVDS vision signal decoding parametric; Produce LINK translative mode control signal, MIPI demonstration module type signal, LVDS synchronous mode control signal according to described LVDS video conversion parameter; According to described MIPI video conversion configurations parameter generating MIPI conversion initialization command and MIPI module initialization command.
Preferably, the process of in described step 1, the vision signal of each link being carried out to receiving demodulation comprises: to the serial code signal in described each link received be terminated respectively, demodulation, dynamic calibration, produce parallel demodulation data and LVDS pixel clock.
Preferably, the process of in described step 2, the parallel demodulation data of described each link being carried out to video decode comprises: with described LVDS pixel clock, the first buffer memory of the parallel demodulation data of described each link is synchronously read again, then respectively to the parallel demodulation decoding data of described each link, obtain LVDS video source data and the LVDS video source synchronizing signal of each link, described LVDS pixel clock is converted into LVDS video source pixel clock.
Preferably, in described decode procedure in described LVDS video decode control signal, while receiving described odd even pixel reverse control signal, the data of LINK1 and LINK2 in described two links are exchanged, while receiving described LVDS video signal cable sequence control signal to described four links according to LINK1, LINK2, LINK3, LINK4 ordering.
Preferably, the transfer process that in described step 3, the LVDS video source signal of each link is converted to rgb video signal comprises: described LVDS video source signal is at first by the rgb video signal adaptive control, produce the rgb video clock and carry out rgb video clock adaptive configuration and rgb video clock output adjustment according to described LVDS video source pixel clock, described LVDS video source signal carries out rgb signal output after the rgb video signal conversion process is converted to rgb video signal to be processed.
Whether preferably, after forming described rgb video signal in step 3, receive described LVDS synchronous mode control signal, detecting described rgb video signal is Low level effective, if described rgb video signal is Low level effective, by described rgb video signal output; If described rgb video signal is that high level is effective, export after transferring described rgb video signal to Low level effective, send MIPI video conversion starting signal during output.
Preferably, the configuration operation of described execution MIPI conversion process and MIPI show that the module initialization operation comprises and receive after MIPI conversion initialization command the configuration operation of carrying out the MIPI conversion process, confirm to carry out again described MIPI module initialization command after configuration operation completes, and MIPI module initialization command is transferred to described MIPI with the form of MIPI order shows module, complete the module initialization operation, send afterwards MIPI video conversion starting command when receiving described MIPI video conversion starting signal.
Preferably, the process that respectively described rgb video signal is converted to the MIPI vision signal in step 4 comprises: after carrying out the configuration operation and MIPI demonstration module initialization operation of MIPI conversion process, the described rgb video signal that starts to receive when receiving described MIPI video conversion starting command is converted to the MIPI video signal transmission and shows module to described MIPI.
Beneficial effect of the present invention is:
(1) the present invention can be converted to the LVDS vision signal MIPI vision signal.The present invention is by arranging, and the different qualities such as the multiple color range of LVDS vision signal, transmission means, coded system all can well be mated; All can change out the desired MIPI vision signal of display mode with it to dissimilar MIPI liquid crystal module.
(2) the LVDS vision signal of convertible 6,8,10 color ranges of the present invention, the convertible LVDS signal based on VESA and JEIDA transfer encoding, can be changed the LVDS transmission mode of single LINK, two LINK, four LINK, the MIPI signal of changing has single whole screen display to show mode, left and right split screen display mode, odd even split screen display mode, shows that applicable to the single whole screen type MIPI of 4LANE module, 8LANE left and right split screen type MIPI show that module and 8LANE odd even split screen type MIPI show module respectively.
(3) the present invention is before use only by manually changing the toggle switch state applicable to different LVDS vision signals; Before the different MIPI liquid crystal module of application, need to receive this module running parameter by jtag interface.
(4) single FPGA(field programmable logic array for the present invention) chip just can be realized described repertoire; FPGA is a kind of programmable semicustom chip, can realize the synchronous processing of multilink video data, parallel conversion, can reach higher performance, not only working stability, realization are easily, and low price, avoided the problems such as design complexity because using various special chips to cause, poor stability, design cost height.
(5) video resolution that the present invention supports is higher, not only integrated level is high, reliable operation, antijamming capability are strong, and simple to operate, economical and practical, can not only promote the detection efficiency of MIPI liquid crystal module, reduce its equipment cost and production cost, also will further improve the universal of MIPI display device.
The accompanying drawing explanation
Fig. 1 is flow chart of the present invention;
Fig. 2 is block diagram of the present invention;
The circuit block diagram that Fig. 3 a is LVDS video reception unit and LVDS video signal decoding unit in Fig. 2;
The circuit block diagram that Fig. 3 b is rgb video signal converting unit in Fig. 2, MIPI vision signal converting unit and video conversion configurations unit;
The circuit diagram that Fig. 4 is single-link pattern rgb video modular converter in Fig. 3 b;
The circuit diagram that Fig. 5 is Fig. 3 b double center chain road pattern rgb video modular converter;
The circuit diagram that Fig. 6 is four link mode rgb video modular converters in Fig. 3 b;
Fig. 7 is the left circuit diagram that parts screen pattern rgb video modular converter on the right side of Fig. 3 b;
The circuit diagram that Fig. 8 is odd even span mode rgb video modular converter in Fig. 3 b;
In figure: 1.LVDS video reception unit, 1-1.LVDS video signal interface, 1-2.LVDS video reception termination module, the LVDS clock signal demodulation module of 1-3. tetra-LINK, 1-4. the LVDS demodulated data signal module of four LINK, 1-5.LVDS demodulation dynamic calibration module;
2.LVDS video signal decoding unit, 2-1.LVDS audio video synchronization buffer module, the LVDS video signal cable order control module of 2-2. tetra-LINK, 2-3.LVDS video synchronization signal decoder module, the LVDS video data decoding module of 2-4. tetra-LINK;
3.RGB vision signal converting unit, 3-1.RGB video signal self-adaptive control module, 3-2.RGB video clock adaptive configuration module, 3-3.RGB video clock generation module, 3-4.RGB video clock output adjusting module, 3-5. single-link pattern rgb video modular converter, 3-5-1.LVDS signal sampling, 3-5-2.DC-FIFO buffer memory, 3-5-3.RGB signal sampling, 3-6. dual link pattern rgb video modular converter, 3-6-1.LVDS signal sampling, 3-6-2.DC-FIFO buffer memory, 3-6-3.RGB signal sampling, 3-7. four link mode rgb video modular converters, 3-7-1.LVDS signal sampling, 3-7-2.DC-FIFO buffer memory, 3-7-3.RGB signal sampling, 3-8. left and right span mode rgb video modular converter, 3-8-1.LVDS synchronizing signal sampling, 3-8-2.LVDS video pixel sampling, 3-8-3. synchronizing signal FIFO buffer memory, 3-8-4. the strange pixel FIFO buffer memory of video, 3-8-5. video dual pixel FIFO buffer memory, 3-8-6.RBG signal sampling, 3-9. odd even span mode rgb video modular converter, 3-9-1.LVDS video pixel sampling, 3-9-2. synchronizing signal FIFO buffer memory, 3-9-3. the strange pixel FIFO buffer memory of video, 3-9-4. video dual pixel FIFO buffer memory, 3-9-5.RBG signal sampling, 3-10.RGB vision signal output module,
4.MIPI the vision signal converting unit, 4-1.MIPI register module, the left road of 4-2. MIPI vision signal modular converter, 4-3. right wing MIPI vision signal modular converter, 4-4.MIPI liquid crystal display module connector;
5. video conversion configurations unit, the manual toggle switch of 5-1., 5-2.JTAG interface, 5-3.MIPI video conversion configurations module;
6.MIPI demonstration module.
Embodiment
Below in conjunction with the drawings and specific embodiments, the present invention is described in further detail.
As shown in Figures 1 to 8, a kind of LVDS vision signal of the present invention is converted to MIPI vision signal method, comprises the following steps:
The LVDS vision signal comprises the LVDS vision signal of single LINK, two LINK, four LINK, the LVDS vision signal of single LINK is that LINK1 transmits all video pixels, the LVDS vision signal of two LINK, comprise LINK1, bis-links of LINK2, transmits respectively the odd even video pixel; The LVDS vision signal of four LINK, comprise four links, according to transmitting successively at LINK1, LINK2, LINK3, LINK4 of video pixel order; The MIPI vision signal comprises that the MIPI of the single whole screen type of 4LANE, 8LANE left and right split screen type and 8LANE odd even split screen type shows module, when the MIPI vision signal that will change is exported to the MIPI demonstration module of the single whole screen type of 4LANE, the LVDS vision signal is transmitted with single, double, four LINK modes; When the MIPI vision signal that will change is exported to the MIPI liquid crystal display module of 8LANE left and right split screen type, 8LANE odd even split screen type, the LVDS vision signal is only transmitted in four LINK modes.The LVDS vision signal of each link comprises LVDS receive clock and LVDS data, and the LVDS data are by the transmission of LVDS data/address bus, and the LVDS data/address bus comprises some root holding wires, and every holding wire transmits the serial code signal.
The LVDS vision signal refers to take the general name of the signal that the LVDS electrical characteristic be to characterize, and has the combination of the signal of string of different video pixel color range, signal transfer encoding standard, signal transmission link mode.The LVDS video signal characteristic received comprises: the color range of the LVDS video source pixel that receive (consisting of tri-kinds of color components of RGB) can have 6 or 8 or 10, each pixel is all according to VESA or the JEIDA coding standard of LVDS transmission of video, by stringization and be encoded into one group of homochromy component level number corresponding 3 or 4 or 5 s' data signal line forms one group of data/address bus, with the electrical form of LVDS, transmit.
According to the characteristic of the LVDS vision signal that will receive, LVDS vision signal decoding parametric, LVDS video conversion parameter are set; Receive the MIPI video conversion configurations parameter in the LVDS vision signal, the configuration operation and the MIPI that carry out the MIPI conversion process show the module initialization operation; Produce LVDS coding standard control signal, LVDS video color range bit wide control signal, LVDS odd even pixel reverse control signal, LVDS video signal cable sequence control signal according to LVDS vision signal decoding parametric; Produce LINK translative mode control signal, MIPI demonstration module type signal, LVDS synchronous mode control signal according to LVDS video conversion parameter; According to MIPI video conversion configurations parameter generating MIPI conversion initialization command and MIPI module initialization command.
LVDS vision signal decoding parametric comprises: LVDS video signal transmission coding standard has VESA and JEIDA; The pixel color component level of LVDS video source is wide 6,8,10; Synchronous mode is controlled parameter and is comprised high level effectively and Low level effective; MIPI video conversion configurations parameter comprises: the signal sequence of MIPI modular converter, transmission frequency, group pack mode, the display timing generator of MIPI liquid crystal display module, time delay Synchronization Control, initialization directive.By the manual toggle switch 5-1 in video conversion configurations unit 5, LVDS vision signal decoding parametric and LVDS video conversion parameter are set, by jtag interface 5-2, according to MIPI, show that the type of module 6 receives MIPI video conversion configurations parameter.
The configuration operation and the MIPI that carry out the MIPI conversion process show that the module initialization operation comprises: the configuration operation of carrying out the MIPI conversion process after the MIPI video conversion configurations module 5-3 reception MIPI conversion initialization command in video conversion configurations unit 5, confirm to carry out again MIPI module initialization command after configuration operation completes, and MIPI module initialization command is transferred to liquid crystal module 6 with the form of MIPI order, complete the module initialization operation, when receiving the MIPI video conversion starting signal transmitted from rgb video signal converting unit 3, MIPI video conversion configurations module 5-3 sends MIPI video conversion starting command to MIPI vision signal converting unit 4 afterwards.
MIPI video conversion configurations module 5-3 first will receive MIPI conversion initialization command and write one by one in MIPI register module 4-1, read the state value of MIPI register module 4-1 after often writing an order, to guarantee that command execution completes, when confirm MIPI vision signal modular converter 4-2 complete configure and start normal operation after write again the order of MIPI demonstration module initialization register, the form transmission MIPI that MIPI vision signal modular converter 4-2 converts thereof into the MIPI order shows module 6, completes the module initialization operation.
Complete the configuration of decoding parametric, conversion parameter and produce corresponding control signal before receiving the LVDS vision signal.
The process of in step 1, the vision signal of each link being carried out to receiving demodulation comprises: the serial code signal to LVDS data in each link received is terminated respectively, demodulation, dynamic calibration, produces LVDS parallel demodulation data; The process of termination comprises: LVDS terminating resistor coupling, LVDS signal level coupling, LVDS signal equalization and postemphasis, the signal buffering with rebuild; The process of demodulation comprises: the LVDS receive clock is carried out to demodulation, produce demodulation clock and demodulation enable signal, serial code signal to the LVDS data of each link is demodulated to separately parallel data respectively, and the LVDS receive clock is demodulated into the LVDS pixel clock simultaneously simultaneously.
The LVDS vision signal receives by the LVDS video signal interface 1-1 in LVDS video reception unit 1, then by LVDS video reception termination module 1-2, is terminated.Purpose to LVDS vision signal termination is: guarantee that the LVDS video signal quality received is high, noiseless.The process of termination comprises: before receiving the LVDS vision signal, carry out ESD(Electro Static Discharge static discharge) protective treatment disturbs with the strong discharge impact of eliminating moment, then carries out common-mode noise filtering processing to suppress line noise, to improve anti-electromagnetic interference capability.The distortion caused with the erasure signal transmission is processed in the impedance matching that is terminated when receiving signal, and also the additional interference of further erasure signal is carried out equilibrium and the processing of postemphasising to signal simultaneously, to eliminate the signal attenuation because loss was caused.Reconstruct high-quality LVDS vision signal afterwards again to the signal Hyblid Buffer Amplifier, and through the judgement of reference level.
The LVDS clock signal demodulation module 1-3 of four LINK carries out demodulation to the LVDS receive clock process of the LVDS vision signal by termination, and the LVDS data are carried out demodulation through the LVDS demodulated data signal module 1-4 of four LINK.LVDS receive clock demodulating process to each link comprises: the LVDS receive clock is carried out after speed buffering to frequency multiplication operation and high-frequency clock conversion process, produce with the LVDS demodulation clock of LVDS data same frequency and with the LVDS receive clock with LVDS pixel clock, LVDS demodulation gating signal frequently, and output in the high-frequency clock network, make them there is very low delay and jitter, very strong driving force, guarantee reliable and stable the LVDS data to be carried out to demodulation.Also carry out the moving calibration of clock jitter removing when the LVDS receive clock is carried out to the frequency multiplication operation, think that the subsequent operation generation is not affected by input jiffer, stable frequency-doubled signal.
The LVDS data demodulation process is comprised: to each data independently demodulation respectively in the LVDS serial data bus of each link, by each LVDS data-signal its phase delay half-bit bit period after the speed buffering input, make this data value that samples that the LVDS demodulation clock can be correct at the center of each LVDS data bit, and according to the demodulation gating signal, it is periodically blocked to the bunchiness data, doing string with the LVDS pixel clock again turns and processes the parallel demodulation data that obtain this LVDS signal, each LVDS demodulating data is merged into to the LVDS demodulating data.The demodulation that each LVDS holding wire is all run simultaneously, make each holding wire no matter how data all can the phase mutual interference not cause the demodulation mistake.Also carry out the data dithering removal calibration the LVDS data being carried out to demodulation simultaneously, to produce, not affected by input jiffer, reliable and stable demodulating data.Phase delay process in the data input is subject to LVDS data flow phase alignment signal controlling all the time, when the phase place between demodulation clock and LVDS data has deviation, the phase alignment signal is made its delay adjustment contrary with phase deviation on data delay half period basis, make data center align along maintenance with the sampling of demodulation clock all the time, guarantee correctly to sample data.When the demodulation gating signal is blocked serial data, the bit that is subject to byte-aligned moves calibrating signal and controls, and the start bit that makes it the parallel data that will cut apart moves on next serial data position.
For guaranteeing that bits per inch is according to correctness and the reliability of separating timing, LVDS receive clock and each LVDS data of each link are carried out to dynamic calibration by LVDS demodulation dynamic calibration module 1-5 respectively in demodulation.
The process of in step 2, the parallel demodulation data of each link being carried out to video decode comprises: with the LVDS pixel clock to the parallel demodulation data of each link first in the LVDS audio video synchronization buffer module 2-1 in LVDS video signal decoding unit 2 buffer memory synchronously read again, then LVDS video synchronization signal decoder module 2-3 and LVDS video data decoding module are decoded with the operation of sequential logic to the parallel demodulation data of four links respectively, obtain LVDS video source data and the LVDS video source synchronizing signal of each link.Convert the LVDS pixel clock of LINK1 to LVDS video source pixel clock by the global clock path, with this, produce LVDS video source data and synchronizing signal.
Delay, the asynchronous situation that cause subsequent treatment mistake are arranged between for the LVDS signal of avoiding occurring each link in the LVDS vision signal in transmission, need to LVDS pixel clock separately, it be sampled and buffer memory respectively to the parallel demodulation data of each link, the buffer memory degree of depth is large as far as possible, so that all links have abundant data to be buffered to offset maximum delay between them, carry out synchronized sampling with LVDS video source pixel clock in the mode of fifo queue again, make it to become synchrodata.
When LVDS vision signal order module 2-2 receives the odd even pixel reverse control signal in LVDS video decode control signal in decode procedure, the data of LINK1 and LINK2 in two links are exchanged, while receiving LVDS video signal cable sequence control signal, to four links according to LINK1, LINK2, LINK3, LINK4 ordering.
Because LVDS video signal transmission coding standard (VESA or JEDIA standard) is all supported 6 bits, 8 bits, the coding of 10 bit pixel color ranges, its LVDS video synchronization signal also together is encoded with video pixel data, and its coding rule separately is unique, therefore can obtain unique LVDS decoded video data according to LVDS video standard control signal and LVDS video bit wide control signal, by LVDS video source pixel clock, respectively the demodulating data of each is decoded with the operation of sequential logic thus, recover LVDS video source synchronizing signal and the LVDS video source data signal of each link.
LVDS video source synchronizing signal comprises video level line synchronizing signal (Hsync), video perpendicualr field synchronizing signal (Vsync), video data useful signal (DE).Due in VESA and JEIDA coding standard, the mode of the coding of the synchronizing signal of each link with sequential identical, therefore only need will sequence after the LINK1 synchronizing signal of decode as LVDS video source synchronizing signal, also export.
The transfer process that in step 3, the LVDS video source signal of each link is converted to rgb video signal comprises: the LVDS video source signal is at first by the rgb video signal adaptive control, produce the rgb video clock and carry out rgb video clock adaptive configuration and rgb video clock output adjustment according to LVDS video source pixel clock, the LVDS video source signal carries out rgb signal output after the rgb video signal conversion process is converted to rgb video signal to be processed.
When the MIPI liquid crystal module type in control signal is the whole screen type of 4LANE single/bis-/tetra-LINK translative mode under, rgb video signal (data and synchronizing signal) by corresponding by single/bis-/tetra-LINK patterns conversions produce, the rgb video clock also accordingly by single/bis-/tetra-LINK mode producing; When the MIPI liquid crystal module type in control signal is 8LANE left and right split screen type or odd even split screen type, be the translative mode of four LINK, rgb video signal is produced by left and right split screen or the conversion of odd even span mode respectively, and the rgb video clock is by the dual link mode producing.
Rgb video signal adaptive control process is: rgb video signal self-adaptive control module 3-1 first shows that according to the LINK translative mode control signal in LVDS video changeover control signal and MIPI the module type signal produces that the rgb video clock configuration signal be complementary is given rgb video clock adaptive configuration module 3-2 together with LVDS video source pixel clock so that rgb video clock generating module 3-3 produces the rgb video clock adapted; Also producing in addition the RGB modulus of conversion block selection signal be complementary is operated rgb video signal output module 3-10 together with the LVDS audio video synchronization pattern in LVDS video changeover control signal.Simultaneously, for avoid the transcription error caused because video data is asynchronous with sequential in transfer process, ignore the input of LVDS video source data when starting, and wait for that first complete video line arrives, when the LDVS video source synchronizing signal Hsync of input occurs that initial saltus step means that first complete video line starts, now by detecting video synchronization signal DE, calculate the horizontal resolution of LVDS vision signal, but still ignore the data input, when the complete line when subsequently starts to input by the LVDS video source data of each link, synchronizing signal, resolution value is given the rgb video modular converter and is started it and processes (now the RGB clock produced and stablizes through the time of a line) together with the rgb video clock.
Rgb video clock adaptive configuration and production process are: rgb video clock adaptive configuration module 3-2 according to produced list/bis-/the rgb video clock configuration signal of tetra-LINK patterns, by the local clock signal produce corresponding single/bis-/configuration parameter and the configuration sequential of tetra-LINK patterns carry out the dynamic recognition operation to the clock generating module, make rgb video clock generating module 3-3 automatically produce needed rgb video clock signal, single when being configured to/bis-/during tetra-LINK patterns, LVDS video source pixel clock is converted into the rgb video pixel clock (hereinafter to be referred as the RGB clock) of its same frequency/bis-frequencys multiplication/quadruple, in four LINK patterns, when rgb video signal is changed by left and right split screen or odd even span mode, LVDS video source pixel clock is converted into the rgb video pixel clock of its two frequency multiplication.
The rgb video signal translation process comprises: with the RGB clock, LVDS video source synchronizing signal is become to rgb video synchronizing signal and data with data transaction; When MIPI liquid crystal display module is the whole screen type of 4LANE, carry out separately the video conversion of the mono-LINK of LVDS, two LINK, four LINK patterns according to LINK translative mode control signal; When showing that module is 8LANE split screen type, MIPI carries out separately the video conversion of left and right span mode and odd even span mode according to changeover control signal.
Carry out the LVDS video transfer process of single LINK, two LINK, four LINK patterns respectively:
Under single LINK pattern, with single-link pattern rgb video modular converter 3-5, the LVDS data of LVDS synchronizing signal and LINK1 are formed to parallel data, LVDS signal sampling 3-5-1 is with LVDS video source pixel clock sampling and write the fifo queue in DC-FIFO(Double Clock-Frist In Frist Out doubleclocking territory simultaneously) buffer memory in buffer memory 3-5-2, rgb signal sampling 3-5-3 by frequency the rgb video clock identical with LVDS video source pixel clock read, and isolate data and synchronizing signal, be the rgb video signal that RGB data and RGB synchronizing signal form, thereby complete conversion process.
Under two LINK patterns, with dual link pattern rgb video modular converter 3-6 by LVDS synchronizing signal and synchronous LINK1, the LVDS data of LINK2 are according to " LINK1-data, synchronizing signal, the LINK2-data, synchronizing signal " form be combined into a channel parallel data, LVDS signal sampling 3-6-1 is with the LVDS clock sampling and write buffer memory in DC-FIFO buffer memory 3-6-2, rgb signal sampling 3-6-3 frequency is that the rgb video clock of two times of LVDS video source pixel clocks is read LINK1 successively, the signal of LINK2, and isolate data and synchronizing signal, thereby the rgb video signal that is RGB data and RGB synchronizing signal composition completes conversion process, for data, due to LINK1,2 transmission odd and even datas (being determined by the odd even reverse control signal), therefore the RGB data are actual is alternately to export LINK1,2(very-occasionally) data, thereby complete the conversion of all data, for synchronizing signal, because the rgb video clock has read twice to it at each LVDS in the clock cycle, so the video sequential of RGB and LVDS is consistent, for transfer process, because DC-FIFO writes the data volume of twice a unit interval with the clock of a times, and by the data volume of one times of the Clockreading of twice, the throughput that is read-write operation equates, therefore not there will be and write completely or read empty situation, i.e. the carrying out of conversion operations energy continous-stable.
Under four LINK patterns, with four link mode rgb video modular converter 3-7 by the LVDS data of LVDS synchronizing signal and synchronous four links according to " LINK1-data, synchronizing signal, the LINK2-data, synchronizing signal, the LINK3-data, synchronizing signal, the LINK4-data, synchronizing signal " form form parallel data, LVDS signal sampling 3-7-1 with LVDS video source pixel clock to its sampling and write in DC-FIFO buffer memory 3-7-2, rgb signal sampling 3-7-3 by quadruple in the RGB of LVDS clock Clockreading and separate the rgb video data and the RGB synchronizing signal, form rgb video signal, for data, because being exports LINK1,2,3,4 data successively, need put in order to coordinate conversion operations by " control of LVDS video line order " signal selection LVDS video pixel, for synchronizing signal, because the rgb video clock has read four time to it at each LVDS in the clock cycle, so the video sequential of RGB and LVDS is consistent, for transfer process, because the throughput of read-write operation equates, therefore can not write full or read sky, the carrying out of conversion operations energy continous-stable.
Above-mentioned each pattern is with the DC-FIFO buffer memory time, need the certain data volume of buffer memory to occur that with the LVDS signal transfer rate of the delay of canceling DC-FIFO id reaction and each LINK the caused read-write speed of fluctuation has fine difference (this fluctuation only causes that the data transmission rate that current video is capable changes, at line blanking period without affecting).
The video transfer process of carrying out the left and right span mode is: LVDS synchronizing signal sampling 3-8-1, LVDS video pixel sampling 3-8-2 in odd even split screen rgb video modular converter 3-8 are synchronously sampled to the LVDS video source data of LVDS video source synchronizing signal and four links with LVDS video source pixel clock respectively, and are written in corresponding FIFO buffer memory.To LVDS video source synchronizing signal, be copied into the parallel synchronizing signal of two-way according to the form of " Vs, Hs, DE, Vs, Hs, DE ", with LVDS video source pixel clock, be written in synchronizing signal FIFO buffer memory 3-8-3; The LVDS video source data forms parallel data according to " LINK1, LINK2, LINK3, LINK4 " form simultaneously, according to the capable resolution of inputted LVDS, with LVDS video source pixel clock, every row LVDS video source signal is divided into to the sampling of front hemistich parallel data, rear hemistich parallel data according to LVDS video line resolution value and alternately writes successively buffer memory in front hemistich pixel FIFO buffer memory 3-8-4, rear hemistich pixel FIFO buffer memory 3-8-5.After first complete line has been inputted, its front hemistich parallel data, rear hemistich parallel data and synchronizing signal be buffer memory all.Rgb signal sampling 3-8-6 reads front hemistich parallel data, rear hemistich parallel data and synchronizing signal with the rgb video clock simultaneously, is converted into respectively left half screen rgb video data, right half screen rgb video data and rgb video synchronizing signal; Described rgb video synchronizing signal is copied as to two-way, form left half screen rgb video signal and right half screen rgb video signal with left half screen rgb video data, right half screen rgb video data, rgb video clock respectively; When next video line starts, LVDS synchronizing signal and the data of this row continue to be written in corresponding buffer memory on the one hand, produce on the other hand RGB sampling commencing signal, make the rgb video clock read left half screen RGB data, right half screen RGB data and synchronizing signal from corresponding FIFO buffer memory simultaneously; Because read rgb video clock is the twice of write LVDS video source pixel clock, and the bit wide of the data that write and synchronizing signal is read twice, thus the throughput of reading and writing operation equate, the carrying out of conversion operations energy continous-stable.
The video transfer process of carrying out the odd even span mode is: the LVDS video pixel sampling 3-9-1 in odd even split screen rgb video modular converter 3-9 is synchronously sampled to the LVDS video source data of LVDS video source synchronizing signal and four links with LVDS video source pixel clock respectively, by LINK1 in the LVDS video source data of four links, LINK3 is divided into strange pixel parallel data, by LINK2 in the LVDS video source data of four links, LINK3 is divided into the dual pixel parallel data, strange pixel parallel data is write to the strange pixel FIFO buffer memory of video 3-9-3, the dual pixel parallel data is write to video dual pixel FIFO buffer memory 3-9-4, by LVDS video source synchronizing signal, according to " Vs, Hs, DE, Vs, Hs, DE " form be copied into the parallel synchronizing signal of two-way, with LVDS video source pixel clock, be written in synchronizing signal FIFO buffer memory 3-9-2, rgb video clock while read output signal from three FIFO buffer memorys for rgb signal sampling 3-9-5, be converted into respectively the strange pixel data of RGB, RGB dual pixel data and rgb video synchronizing signal, described rgb video synchronizing signal is copied as to two-way, form the strange split screen vision signal of RGB and the even split screen vision signal of RGB with the strange pixel data of RGB, RGB dual pixel data, rgb video clock respectively.For data, due to strange pixel parallel data and dual pixel parallel data simultaneously by the rgb video Clockreading, therefore the RGB data are actual is alternately to export strange pixel parallel data, dual pixel parallel data, thereby complete the conversion of all data, for synchronizing signal, because the RGB clock has read twice to it at each LVDS in the clock cycle, so the video sequential of RGB and LVDS is consistent; For transfer process, because DC-FIFO writes the data volume of twice a unit interval with the clock of a times, and by the data volume of one times of the Clockreading of twice, the throughput that is read-write operation equates, therefore not there will be and write completely or read empty situation, i.e. the carrying out of conversion operations energy continous-stable.
Rgb signal output processing procedure is: rgb video signal output module 3-10 selects corresponding rgb video data output according to the modulus of conversion block selection signal, and with the RGB clock to its dozen of beats, guarantee the output timing reliability; When producing synchronous mode and control to the video synchronization signal reverse operating; Phase place between effective edge of contrast RGB output clock and the sampling center of RGB data, and respectively output clock and data are done to fine delay by the signal lag assembly and process to eliminate phase difference between the two, guarantee that output clock is effectively along the sampling center in data all the time.After forming rgb video signal in step 3, receiving LVDS synchronous mode control signal, whether be Low level effective, if rgb video signal is Low level effective, rgb video signal is exported if detecting rgb video signal; If rgb video signal is that high level is effective, export after transferring rgb video signal to Low level effective, send MIPI video conversion starting signal during output.
When the modulus of conversion block selection signal is single, double, four LINK pattern, its RGB data and synchronizing signal (whole screen signal) is copied into to two-way and exports to MIPI vision signal converting unit 4; When selecting left and right split screen translative mode, left and right half screen data and synchronizing signal are exported respectively left half screen rgb video signal, right half screen rgb video signal Gei Zuo road MIPI vision signal modular converter 4-2 and right wing MIPI vision signal modular converter 4-3; When selecting odd even split screen translative mode, strange pixel parallel data, dual pixel parallel data and synchronizing signal are exported respectively the strange split screen vision signal of RGB and the even split screen vision signal of RGB to MIPI vision signal converting unit 4.
When starting to export RGB data and synchronizing signal, postpone to produce MIPI video changeover control signal after some RGB clocks, start follow-up MIPI signal conversion module work, doing like this is to receive at the very start normal video data for the MIPI modular converter, improves the reliability of MIPI conversion.
After MIPI video conversion configurations module 5-3 carries out the configuration operation and MIPI demonstration module initialization operation of MIPI conversion process, MIPI video conversion configurations module 5-3 sends MIPI video conversion starting command after receiving MIPI video conversion starting signal.When starting to carry out the MIPI conversion configurations, left road MIPI vision signal modular converter 4-2 and right wing MIPI video conversion module 4-3 are configured operation according to the MIPI register command write, and these MIPI register command comprise: the order of MIPI conversion configurations, MIPI show module initialization command, the order of MIPI conversion and control; After configuration completes, show the module initialization command according to the MIPI of write register, left road MIPI vision signal modular converter 4-2 converts these orders to respectively the MIPI command signal with right wing MIPI video conversion module 4-3 and is transferred to the MIPI demonstration module 6 that MIPI liquid crystal display module connector 4-4 is connected, and makes MIPI show that module 6 carries out initialization operation.Afterwards when the order of MIPI video conversion and control writes MIPI register module 4-1, left road MIPI vision signal modular converter 4-2 and right wing MIPI video conversion module 4-3 are converted to the rgb video signal of input the MIPI vision signal simultaneously and send the MIPI be connected with MIPI liquid crystal display module connector 4-4 to and show that module 6 shows, be converted to respectively left passage MIPI vision signal and right passage MIPI video signal transmission to.
The present invention is not limited to above-mentioned execution mode; for those skilled in the art, also be considered as the protection range of patent of the present invention according to know-why of the present invention and scheme or some improvement of making, change, retouching, distortion, replacement under enlightenment of the present invention within.
The content be not described in detail in this specification, write a Chinese character in simplified form, term belongs to the known prior art of professional and technical personnel in the field.
Claims (10)
1. a LVDS vision signal is converted to MIPI vision signal method, it is characterized in that: comprise the following steps:
Step 1, the vision signal of each link of LVDS vision signal is carried out respectively to receiving demodulation simultaneously, produce parallel demodulation data and the LVDS pixel clock of each link;
Step 2, the parallel demodulation data of described each link are carried out to video decode, generate the LVDS video source signal of each link, described LVDS video source signal comprises LVDS video source data and LVDS video source synchronizing signal, and described LVDS pixel clock is converted into LVDS video source pixel clock;
Step 3, the LVDS video source signal of described each link is converted to rgb video signal;
Step 4, described rgb video signal is converted to the MIPI vision signal.
2. LVDS vision signal according to claim 1 is converted to MIPI vision signal method, it is characterized in that: described LVDS vision signal comprises the LVDS vision signal of single LINK, two LINK, four LINK, the LVDS vision signal of described single LINK is that LINK1 transmits all video pixels, the LVDS vision signal of described couple of LINK, comprise LINK1, bis-links of LINK2, transmit respectively the odd even video pixel; The LVDS vision signal of described four LINK, comprise four links, according to the video pixel order, at LINK1, LINK2, LINK3, LINK4, transmits successively; Described MIPI vision signal shows module for the MIPI of the single whole screen type of 4LANE, 8LANE left and right split screen type and 8LANE odd even split screen type, when the MIPI vision signal that will change is exported to the MIPI demonstration module of the single whole screen type of 4LANE, the LVDS vision signal is transmitted with single, double, four LINK modes; When the MIPI vision signal that will change is exported to the MIPI liquid crystal display module of 8LANE left and right split screen type, 8LANE odd even split screen type, the LVDS vision signal is transmitted in four LINK modes; The LVDS vision signal of described each link comprises LVDS receive clock and LVDS data, and described LVDS data are by the transmission of LVDS data/address bus, and described LVDS data/address bus comprises some root holding wires, and every holding wire transmits the serial code signal.
3. LVDS vision signal according to claim 1 is converted to MIPI vision signal method, it is characterized in that: before in described step 1, the vision signal of each link being carried out to receiving demodulation, according to the characteristic of the LVDS vision signal that will receive, LVDS vision signal decoding parametric, LVDS video conversion parameter are set; Receive the MIPI video conversion configurations parameter in the LVDS vision signal, the configuration operation and the MIPI that carry out the MIPI conversion process show the module initialization operation; Produce LVDS coding standard control signal, LVDS video color range bit wide control signal, LVDS odd even pixel reverse control signal, LVDS video signal cable sequence control signal according to described LVDS vision signal decoding parametric; Produce LINK translative mode control signal, MIPI demonstration module type signal, LVDS synchronous mode control signal according to described LVDS video conversion parameter; According to described MIPI video conversion configurations parameter generating MIPI conversion initialization command and MIPI module initialization command.
4. LVDS vision signal according to claim 1 is converted to MIPI vision signal method, it is characterized in that: the process of in described step 1, the vision signal of each link being carried out to receiving demodulation comprises: to the serial code signal in described each link received be terminated respectively, demodulation, dynamic calibration, produce parallel demodulation data and LVDS pixel clock.
5. LVDS vision signal according to claim 2 is converted to MIPI vision signal method, it is characterized in that: the process of in described step 2, the parallel demodulation data of described each link being carried out to video decode comprises: with described LVDS pixel clock, the first buffer memory of the parallel demodulation data of described each link is synchronously read again, then respectively to the parallel demodulation decoding data of described each link, obtain LVDS video source data and the LVDS video source synchronizing signal of each link, described LVDS pixel clock is converted into LVDS video source pixel clock.
6. LVDS vision signal according to claim 3 is converted to MIPI vision signal method, it is characterized in that: in described decode procedure in described LVDS video decode control signal, while receiving described odd even pixel reverse control signal, the data of LINK1 and LINK2 in described two links are exchanged, while receiving described LVDS video signal cable sequence control signal to described four links according to LINK1, LINK2, LINK3, LINK4 ordering.
7. LVDS vision signal according to claim 3 is converted to MIPI vision signal method, it is characterized in that: the transfer process that in described step 3, the LVDS video source signal of each link is converted to rgb video signal comprises: described LVDS video source signal is at first by the rgb video signal adaptive control, produce the rgb video clock and carry out rgb video clock adaptive configuration and rgb video clock output adjustment according to described LVDS video source pixel clock, described LVDS video source signal carries out rgb signal output after the rgb video signal conversion process is converted to rgb video signal to be processed.
8. LVDS vision signal according to claim 3 is converted to MIPI vision signal method, it is characterized in that: after forming described rgb video signal in step 3, receive described LVDS synchronous mode control signal, whether detect described rgb video signal is Low level effective, if described rgb video signal is Low level effective, by described rgb video signal output; If described rgb video signal is that high level is effective, export after transferring described rgb video signal to Low level effective, send MIPI video conversion starting signal during output.
9. LVDS vision signal according to claim 3 is converted to MIPI vision signal method, it is characterized in that: the configuration operation of described execution MIPI conversion process and MIPI show that the module initialization operation comprises and receive after MIPI conversion initialization command the configuration operation of carrying out the MIPI conversion process, confirm to carry out again described MIPI module initialization command after configuration operation completes, and MIPI module initialization command is transferred to described MIPI with the form of MIPI order shows module (6), complete the module initialization operation, send afterwards MIPI video conversion starting command when receiving described MIPI video conversion starting signal.
10. LVDS vision signal according to claim 9 is converted to MIPI vision signal method, it is characterized in that: the process that respectively described rgb video signal is converted to the MIPI vision signal in step 4 comprises: after carrying out the configuration operation and MIPI demonstration module initialization operation of MIPI conversion process, the described rgb video signal that starts to receive when receiving described MIPI video conversion starting command is converted to the MIPI video signal transmission and shows module (6) to described MIPI.
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| CN106571113B (en) * | 2016-10-20 | 2019-11-19 | 昆山龙腾光电有限公司 | A kind of test equipment and test method of display module |
| CN109348157A (en) * | 2018-11-21 | 2019-02-15 | 深圳创维数字技术有限公司 | Based on circuit, the method and device for controlling information iteration in video realization |
| CN112135176A (en) * | 2019-06-25 | 2020-12-25 | 西安诺瓦星云科技股份有限公司 | Video processing method, device and system and computer readable storage medium |
| CN110636219A (en) * | 2019-09-03 | 2019-12-31 | 北京三快在线科技有限公司 | Video data stream transmission method and device |
| CN111669648A (en) * | 2020-06-19 | 2020-09-15 | 艾索信息股份有限公司 | Video frequency doubling method |
| CN111669648B (en) * | 2020-06-19 | 2022-03-25 | 艾索信息股份有限公司 | Video frequency doubling method |
| CN114245029A (en) * | 2021-12-20 | 2022-03-25 | 北京镁伽科技有限公司 | FPGA-based data stream processing method and device and PG equipment |
| CN114245029B (en) * | 2021-12-20 | 2023-08-01 | 北京镁伽科技有限公司 | FPGA-based data stream processing method and device and PG equipment |
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