CN109068023B - Synchronous control system and control method for reading circuit of super-large area array image sensor - Google Patents
Synchronous control system and control method for reading circuit of super-large area array image sensor Download PDFInfo
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- CN109068023B CN109068023B CN201810837539.0A CN201810837539A CN109068023B CN 109068023 B CN109068023 B CN 109068023B CN 201810837539 A CN201810837539 A CN 201810837539A CN 109068023 B CN109068023 B CN 109068023B
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- H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
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Abstract
The invention discloses a synchronous control system of a reading circuit of an ultra-large area array image sensor, which comprises a photosensitive array formed by a plurality of photosensitive array lines, wherein the photosensitive array is divided into a plurality of photosensitive areas according to the number of columns, the output end of each column of photosensitive array line in each photosensitive area is connected with an A/D conversion unit, the input ends of all A/D conversion units in each photosensitive area are commonly connected with a D/A conversion unit, the input ends of the A/D conversion unit and the D/A conversion unit are both connected with a local synchronization unit, and the input end of the local synchronization unit in each photosensitive area is commonly connected with a controller and the output end of a phase-locked loop, so that the synchronism of a time sequence signal and an analog signal in each area is ensured.
Description
Technical Field
The invention belongs to the technical field of super large area array image sensors, in particular to a synchronous control system of a reading circuit of a super large area array image sensor, and further relates to a method for synchronously controlling the reading circuit of the super large area array image sensor by adopting the synchronous control system.
Background
The CMOS image sensor is a photoelectric sensing device implemented by using a CMOS process, and can integrate higher performance in a single-chip image processing system, while maximally reducing the area and power consumption of the image processing system, compared to a CCD. This makes the CMOS visible light image sensor become more advantageous than the CCD image sensor, and with the further development of the CMOS standard process, the CMOS image sensor has a greater integration level, lower power consumption and lower cost, so the CMOS image sensor is more and more widely researched and used by people.
With the rapid development of high-definition imaging technology and spatial imaging technology, the array scale of CMOS image sensors is increasing continuously, and the image sensors in large arrays also bring about further increase of the scale of readout circuits, and currently, most CMOS image sensors in large arrays still use column-level processing systems, and each column or every few columns of pixel units in image sensor arrays share one readout circuit by utilizing the advantage that chips can transmit data in parallel. Since the pixel array is read row by row, signals of the pixels of the whole row are read out into the signal processing circuit at the same time, and then the signals in the pixels of the row are transmitted to the output end one by one in series. The column level processing system structure has many advantages of parallel processing, and has low requirement on the speed of a CMOS visible light image sensor processing system, so that the chip power consumption is reduced. Compared with the pixel level processing system structure, the readout circuit is transferred to the outside of the pixel unit array from the inside of the pixel unit, so that the filling factor is improved, and the light sensitivity of the image sensor is also improved. Although column-level processing systems still have some limitations on chip area, their high degree of freedom in the vertical direction also makes column-level processing systems relatively flexible to implement.
However, as the array size increases, the read-out circuit cannot realize global uniform control, and the split-up control is necessary for regional control, but the technique can introduce inconsistency between regions, and the quality of the whole image is seriously affected.
Disclosure of Invention
The invention aims to provide a synchronous control system of a reading circuit of an ultra-large area array image sensor, which ensures the synchronism of a time sequence signal and an analog signal in each area.
The invention also aims to provide a synchronous control method of the readout circuit of the super-large area array image sensor.
The technical scheme includes that the synchronous control system of the reading circuit of the super-large area array image sensor comprises a photosensitive array formed by a plurality of photosensitive array lines, the photosensitive array is divided into a plurality of photosensitive areas according to the number of columns, the output end of each column of photosensitive array line in each photosensitive area is connected with an A/D conversion unit, the input ends of all A/D conversion units in each photosensitive area are connected to a D/A conversion unit, the input ends of all A/D conversion units and one D/A conversion unit in each photosensitive area are connected to a local synchronization unit, and the input end of the local synchronization unit in each photosensitive area is connected with a controller and the output end of a phase-locked loop.
The invention adopts another technical scheme that a synchronous control method of a reading circuit of a super large area array image sensor adopts a synchronous control system of the reading circuit of the super large area array image sensor, and is implemented according to the following steps:
step 1, a controller and a phase-locked loop respectively send out a time sequence control signal and an internal high-frequency clock signal, and a local synchronization unit in each photosensitive area carries out synchronization processing on the received time sequence control signal and the internal high-frequency clock signal;
The invention has the beneficial effects that:
the self-adaptive synchronous driving system of the super large area array image sensor synchronizes and shapes received global signals in an area through a local synchronization unit, and then transmits the global signals to each row of reading circuits in the area, so that the phase of a counting signal converted and received by each row of A/D conversion units in each area is consistent with that of a ramp signal;
the self-adaptive synchronous driving method of the super-large area array image sensor aims at the problem of time sequence asynchronism in the super-large array subarea reading technology, ensures the consistency of large-scale reading circuit time sequence control by combining global control and local synchronization and dynamically adjusting areas, can be applied to repetitive design based on splicing process technology, and effectively solves the problem of contradiction between the design difficulty of a reading circuit and the increase of array scale.
Drawings
Fig. 1 is a driving scheme of a conventional CMOS image sensor;
FIG. 2 is a schematic structural diagram of an adaptive synchronous driving system of a super large area array image sensor according to the present invention;
FIG. 3 is a flow chart of the adaptive synchronous driving method of the ultra-large area array image sensor according to the present invention.
In the figure, 1, a photosensitive array, 2, an A/D & D/A conversion unit, 2-1, an A/D conversion unit, 2-2, a D/A conversion unit, 3, a local synchronization unit, 4, a controller and 5, a phase-locked loop.
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.
Fig. 1 is a conventional readout circuit mechanism of a super large area array image sensor, in which a photosensitive array is quantized by an a/D & D/a unit, a global controller and a phase-locked loop are directly output to a column-level readout circuit, and when the array size increases, a global control signal output by the controller and a ramp signal required by an a/D conversion unit cannot reach each column readout circuit at the same time, so that the structure encounters a huge challenge in the application of the super large array CMOS image sensor.
In order to overcome the above defects, the present invention provides a synchronous control system for a readout circuit of an image sensor with an ultra-large area array, as shown in fig. 2, a global module outputs a uniform quantization start signal, i.e., a timing control signal and a high frequency clock signal, and then a local synchronization unit 4 and a D/a conversion unit 3 output a synchronous timing control signal and a ramp signal in each area respectively, so as to ensure the synchronism of the timing control signal and an analog signal in each area; meanwhile, local synchronous logic can be configured respectively so as to achieve mutual consistency among the regions.
The invention relates to a synchronous control system of a reading circuit of an oversized area array image sensor, which particularly comprises a photosensitive array 1 formed by a plurality of photosensitive array lines, wherein the photosensitive array lines in the photosensitive array 1 receive external optical input signals and output weak electric signals through photoelectric conversion, and the electric signals need to be sampled, amplified, quantized and transmitted through a subsequent reading circuit. The core unit of the reading circuit is an A/D & D/A conversion unit 2, namely an integrated A/D conversion unit 2-1 and a D/A conversion unit 2-2, the photosensitive array 1 is divided into a plurality of photosensitive areas according to the number of columns, wherein the output end of each column of photosensitive array line in each photosensitive area is connected with an A/D conversion unit 2-1, the input ends of all the A/D conversion units 2-1 in each photosensitive area are connected to one D/A conversion unit 2-2, the input ends of all the A/D conversion units 2-1 and one D/A conversion unit 2-2 in each photosensitive area are connected to one local synchronization unit 3, and the input end of the local synchronization unit 3 in each photosensitive area is connected to the output ends of a controller 4 and a phase-locked loop 5.
The photosensitive array 1 completes the conversion of photoelectric signals; the readout circuit, namely the A/D & D/A conversion unit 2, finishes the sampling, reading and quantization processing of the photoelectric signals of the photosensitive array; the input of the A/D conversion unit 2-1 is composed of three parts, wherein an analog signal to be converted is a photoelectric output signal from the photosensitive array 1, the other input is a reference signal provided by the D/A conversion unit 2-2, a digital signal is output through quantization, and the digital signal is output to the outside of a chip through interfaces such as LVDS (low voltage differential signaling); control signals between the readout circuit and the photosensitive array 1 are provided by a controller 4, including digital control signals required by the various modules in the exposure and readout processes. Since the off-chip clock signal of higher frequency cannot be provided and the diversified internal required clock signal is also output, the phase-locked loop 5 is integrated inside, the input of the phase-locked loop 5 is the external master clock, and the output main signal is the internal high-frequency clock signal which is the quantized positioning signal required by the a/D conversion unit 2-1. In order to keep the corresponding phase relation between the analog signals and the internal high-frequency clock signals among the columns in the area, the local synchronization unit 3 is added, the received global signals are synchronized and shaped in the area, and then the global signals are transmitted to each column reading circuit in the area. In addition, in order to further adjust the phase consistency among the modules and improve the reliability of data received outside the chip, the delay information of the local synchronization unit can be dynamically adjusted, so that the data among the areas keep a good corresponding relation.
In the synchronous control system of the readout circuit of the super large area array image sensor, the input of an A/D conversion unit 2-1 consists of three parts, wherein the analog signal to be converted is the photoelectric output signal from the photosensitive array 1, the other two inputs are the timing control signal outputted by the controller 4, i.e. the counting clock signal (time domain) and the ramp signal outputted by the D/a conversion unit 2-2 (voltage domain), the ramp signal outputted by the D/a conversion unit 2-2 corresponds to the counting clock signal one by one, namely, a definite relation is established between the counting signal of the time domain and the ramp signal of the voltage domain, so that a digital signal corresponding to the analog signal can be obtained by comparing the analog signal to be converted with the ramp signal output by the D/A conversion unit 2-2, and the conversion from analog to digital is completed; the controller 4 and the phase locked loop 5 belong to a common module, located on the left side of the readout circuit. The controller 4 completes the exposure and readout timing control of the photosensitive array 1 and the readout circuit; the phase locked loop 5 outputs an internal high frequency clock signal required for a/D conversion and D/a conversion.
The invention divides a photosensitive array 1 into a plurality of photosensitive areas according to the number of columns for reading and outputting, each photosensitive area is correspondingly provided with a set of reading circuits and is in one-to-one correspondence with the photosensitive array above the photosensitive array, each photosensitive area receives a quantization start signal, namely a time sequence control signal from a controller 4 and an internal high-frequency clock signal from a phase-locked loop 5, a local synchronization unit 3 synchronizes the quantization start signal and the internal high-frequency clock signal, and the phase of a counting signal received by each column of A/D conversion units 2-1 in each area is ensured to be consistent with that of a ramp signal.
As shown in fig. 1, the photosensitive array 1 is divided into four regions for reading and outputting, and the specific region division can be adjusted according to the array scale and the performance requirement of the readout circuit.
As shown in fig. 3, the synchronous control method of the readout circuit of the ultra-large area array image sensor of the present invention is implemented by using the readout circuit synchronous control system of the ultra-large area array image sensor, specifically according to the following steps:
step 1, a controller 4 and a phase-locked loop 5 respectively send out a time sequence control signal and an internal high-frequency clock signal, and a local synchronization unit 3 in each photosensitive area carries out synchronization processing on the received time sequence control signal and the internal high-frequency clock signal;
Taking fig. 3 as a specific embodiment, taking a column-level single-slope a/D conversion structure as an example for explanation, fig. 3 illustrates a global unit, a first area and a second area, where the specific number of partitions is determined by an array scale, the number of columns contained in the second area needs to be determined by specific module driving capability and power consumption, and here, taking 2048 columns as an example for explanation, the number of the second area can be expanded as needed, and generally, the second area should be completely repeated.
The embodiment comprises a controller 4 and a phase-locked loop 5 of a global unit, a local synchronization unit 3 and a D/A conversion unit 2-2 in an area are a set, and a timing control signal and a ramp signal received by a 2048-column A/D conversion unit 2-1 are provided by the local synchronization unit 3 and the D/A conversion unit 2-2 in a matching way; the timing control signals of the a/D conversion units 2-1 in the 1 st to 2048 th columns are respectively output to each column from the same source local synchronization unit 3 in a clock tree manner, and the ramp signals of the a/D conversion units 2-1 in the 1 st to 2048 th columns are respectively output to each column from the same source D/a conversion units 2-2 in a clock tree-like manner.
The analog signals of each column are converted by the corresponding a/D conversion unit 2-1 to output respective digital signals.
When the global controller 4 sends out a quantization start signal, i.e. a timing control signal, the local synchronization unit 3 synchronizes the received timing control signal with an internal high-frequency clock signal output by the phase-locked loop 5, and if the D/a conversion unit 2-2 has a certain delay, the local synchronization unit 3 also needs to consider together, so that the phase of a counting clock signal output by the local synchronization unit 3 is consistent with that of a ramp signal output by the D/a conversion unit 2-2; due to the adoption of the layout mode of the clock tree, the clock signals between each column are basically consistent, the ramp signals between each column are basically consistent, and at the moment, the clock signals of each column and the ramp signals only need to be adjusted and synchronized through the local synchronization unit 3. Therefore, when the quantization starts, the counting clock signal of each column and the ramp signal start to change simultaneously, and when the ramp voltage is equal to the sampling analog signal of a certain column, namely the array column line voltage, the number of the counters of the current column is the digital conversion result of the analog signal of the current column; when the ramp voltage is scanned from the lowest voltage to the highest voltage, all columns complete one conversion, namely, the reading of one row of photosensitive units is completed; and so on, completing the reading of the whole image.
Claims (2)
1.A synchronous control system for a reading circuit of an image sensor with an ultra-large area array is characterized by comprising a photosensitive array (1) formed by a plurality of photosensitive array lines, the photosensitive array (1) is divided into a plurality of photosensitive areas according to the number of columns, the output end of each column of photosensitive array line in each photosensitive area is connected with an A/D conversion unit (2-1), the input ends of all A/D conversion units (2-1) in each photosensitive area are connected to one D/A conversion unit (2-2) together, the input ends of all A/D conversion units (2-1) and one D/A conversion unit (2-2) in each photosensitive area are connected to one local synchronization unit (3) together, and the input end of the local synchronization unit (3) in each photosensitive area is connected with the output ends of a controller (4) and a phase-locked loop (5) together.
2. The synchronous control method for the reading circuit of the image sensor with the oversized area array is characterized in that the synchronous control method adopts the synchronous control system for the reading circuit of the image sensor with the oversized area array as claimed in claim 1, and is implemented by the following steps:
step 1, a controller (4) and a phase-locked loop (5) respectively send out a time sequence control signal and an internal high-frequency clock signal, and a local synchronization unit (3) in each photosensitive region carries out synchronization processing on the received time sequence control signal and the internal high-frequency clock signal;
step 2, the local synchronization unit (3) directly outputs the timing control signals after synchronization processing to each A/D conversion unit (2-1), the local synchronization unit (3) outputs the internal high-frequency clock signals after synchronization processing to the D/A conversion unit (2-2) first, slope signals are obtained through conversion, and the D/A conversion unit (2-2) outputs the slope signals to each A/D conversion unit (2-1);
step 3, each A/D conversion unit (2-1) compares the analog signal acquired by the current photosensitive array line with the voltage of a ramp signal, and when the voltage of the ramp signal is equal to the voltage of the analog signal, the number of counters of the current photosensitive array line is the digital conversion result of the analog signal of the current photosensitive array line; when the voltage of the ramp signal is scanned from the lowest voltage to the highest voltage, all columns complete one conversion, namely, the reading of one row of photosensitive units is completed; and so on, completing the reading of the whole image.
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| CN111669526B (en) * | 2020-06-18 | 2023-02-10 | 中国电子科技集团公司第四十四研究所 | CMOS image sensor for improving frame frequency high-speed all-digital data reading |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1523878A (en) * | 2003-02-18 | 2004-08-25 | CMOS image sensor having reduced numbers of column readout circuits | |
| JP2005130382A (en) * | 2003-10-27 | 2005-05-19 | Matsushita Electric Ind Co Ltd | Solid state imaging device |
| CN104796635A (en) * | 2015-04-20 | 2015-07-22 | 中国航天科技集团公司第九研究院第七七一研究所 | Global reset release control method used for oversized-area-array CMOS (complementary metal-oxide-semiconductor transistor) image sensor |
| CN104836573A (en) * | 2015-04-30 | 2015-08-12 | 北京空间机电研究所 | Synchronized clock system for ultra-large area array CMOS camera multipath high-speed signals |
| CN108200364A (en) * | 2018-01-05 | 2018-06-22 | 浙江大学 | A kind of row reading circuit applied to cmos image sensor |
| CN108270980A (en) * | 2016-12-30 | 2018-07-10 | 三星电子株式会社 | Imaging sensor |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI559771B (en) * | 2014-07-31 | 2016-11-21 | 義隆電子股份有限公司 | Active pixel sensor device and operating method of the same |
| KR102275711B1 (en) * | 2014-11-17 | 2021-07-09 | 삼성전자주식회사 | Image sensor and method of outputting data in the image sensor |
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Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1523878A (en) * | 2003-02-18 | 2004-08-25 | CMOS image sensor having reduced numbers of column readout circuits | |
| JP2005130382A (en) * | 2003-10-27 | 2005-05-19 | Matsushita Electric Ind Co Ltd | Solid state imaging device |
| CN104796635A (en) * | 2015-04-20 | 2015-07-22 | 中国航天科技集团公司第九研究院第七七一研究所 | Global reset release control method used for oversized-area-array CMOS (complementary metal-oxide-semiconductor transistor) image sensor |
| CN104836573A (en) * | 2015-04-30 | 2015-08-12 | 北京空间机电研究所 | Synchronized clock system for ultra-large area array CMOS camera multipath high-speed signals |
| CN108270980A (en) * | 2016-12-30 | 2018-07-10 | 三星电子株式会社 | Imaging sensor |
| CN108200364A (en) * | 2018-01-05 | 2018-06-22 | 浙江大学 | A kind of row reading circuit applied to cmos image sensor |
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