CN114071038B - Image processing system and method - Google Patents
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Abstract
The invention provides an image processing system and method, relating to the technical field of image processing, wherein the system comprises: the system comprises an image acquisition module, an image cache module, an image display module and a main control module; the image acquisition module is electrically connected with the image acquisition device and the main control module and is used for acquiring image data acquired by the image acquisition device; the image caching module is electrically connected with the main control module and is used for caching the image data, and the image caching module and the image acquisition module are used for processing the image data in parallel; the image display module is electrically connected with the main control module and is used for displaying the image data. The invention can complete the functions of image acquisition, image data compression, image storage and the like at high speed, improves the image acquisition rate and provides convenience for subsequent image processing and intellectualization.
Description
Technical Field
The present invention relates to the field of image processing technologies, and in particular, to an image processing system and method.
Background
In the field of image processing, the technology of image acquisition, caching and display which is behind the background cannot meet the current demands, and the current image processing is not just a complete image or simple imaging, but high-speed image acquisition, transmission and display, and large data processing, intelligent recognition and biological recognition of the image.
The development of current image processing has not been met by the ever-increasing number of integrated transistors, very large scale integrated circuits (Very Large Scale Integrated Circuit, VLSLC), small and medium scale integrated circuits, and therefore, there is a need for improvements to existing image processing systems.
Disclosure of Invention
The invention provides an image processing system and method, which are used for solving the defect of insufficient bandwidth in a high-speed image acquisition control system in the prior art, realizing the functions of high-speed image acquisition, image data compression, image storage and the like, improving the image acquisition rate and providing convenience for subsequent image processing and intellectualization.
The present invention provides an image processing system including:
the system comprises an image acquisition module, an image cache module, an image display module and a main control module;
the image acquisition module is electrically connected with the image acquisition device and the main control module and is used for acquiring image data acquired by the image acquisition device;
the image caching module is electrically connected with the main control module and is used for caching the image data, and the image caching module and the image acquisition module are used for processing the image data in parallel;
the image display module is electrically connected with the main control module and is used for displaying the image data.
According to the image processing system provided by the invention, the image acquisition module comprises:
the image acquisition unit is used for acquiring the image data acquired by the image acquisition device;
the analog-to-digital conversion unit is used for converting the image data acquired by the image acquisition unit into a digital image signal;
the first transmission unit is used for transmitting the digital image signals to the main control module;
according to the image processing system provided by the invention, the image acquisition module further comprises:
and the adjusting unit is used for adjusting parameters of the image acquisition device.
According to the image processing system provided by the invention, the image acquisition module adopts an image sensor OV7670.
According to the image processing system provided by the invention, the image buffer module comprises:
a synchronous dynamic random access memory chip and a synchronous dynamic random access memory controller electrically connected with the synchronous dynamic random access memory chip;
the synchronous dynamic random access memory controller is electrically connected with the main control module and is used for acquiring the digital image signals transmitted by the main control module;
the synchronous dynamic random access memory is used for caching the digital image signals transmitted by the synchronous dynamic random access memory controller, and the synchronous dynamic random access memory controller is used for controlling the synchronous dynamic random access memory chip to perform read/write operation on the digital image signals.
According to the image processing system provided by the invention, the image display module comprises:
the second transmission unit is used for acquiring the digital image signals transmitted by the main control module;
the digital-to-analog conversion unit is used for converting the digital image signals acquired by the second transmission unit into image data;
and the display unit is used for acquiring and displaying the image data.
According to the image processing system provided by the invention, the image display module adopts a video graphic array module.
According to the image processing system provided by the invention, the main control module adopts a field programmable gate array chip.
According to the image processing system provided by the invention, the main control module adopts a CycloniV series chip.
The invention also provides an image processing method, which comprises the following steps:
acquiring the image data;
converting the image data into the digital image signals and caching the digital image signals in parallel;
the digital image signal is converted into the image data and the image data is displayed.
The invention also provides an electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the steps of the image processing method as described in any of the above when executing the program.
The present invention also provides a non-transitory computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the image processing method as described in any of the above.
The invention also provides a computer program product comprising a computer program which, when executed by a processor, implements the steps of the image processing method as described in any of the above.
The image processing system and the method provided by the invention have the advantages that the system designs a high-speed image processing system based on the SOPC technology through the arrangement of the image acquisition module, the image cache module, the image display module and the main control module, solves the problem of insufficient bandwidth in a high-speed image acquisition control system, can complete the functions of image acquisition, image data compression, image storage and the like at high speed, improves the image acquisition rate, and provides convenience for subsequent image processing and intellectualization; in addition, the image acquisition module and the image cache module are subjected to parallelization processing, so that the working efficiency of the image processing system is improved;
the method designs a high-speed image processing system based on the SOPC technology, improves the efficiency of image processing work by parallelizing image acquisition and image cache, can lighten the data transmission pressure of a main control module, further solves the problem of insufficient bandwidth in a high-speed image acquisition control system, can rapidly complete the functions of image acquisition, image data compression, image storage and the like, improves the image acquisition rate, and provides convenience for subsequent image processing and intellectualization.
Drawings
In order to more clearly illustrate the invention or the technical solutions of the prior art, the following description will briefly explain the drawings used in the embodiments or the description of the prior art, and it is obvious that the drawings in the following description are some embodiments of the invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of an image processing system provided by the present invention;
FIG. 2 is a schematic diagram of a specific structure of an image acquisition module in the image processing system according to the present invention;
FIG. 3 is a schematic circuit diagram of an image acquisition module in the image processing system according to the present invention;
FIG. 4 is a schematic circuit diagram of an image buffer module in the image processing system according to the present invention;
FIG. 5 is a schematic diagram of a specific structure of an image display module in the image processing system according to the present invention;
FIG. 6 is a schematic circuit diagram of an image display module in the image processing system according to the present invention;
FIG. 7 is a flow chart of an image processing method provided by the invention;
fig. 8 is a schematic structural diagram of an electronic device provided by the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
An image processing system of the present invention is described below in conjunction with fig. 1, the system comprising:
the device comprises an image acquisition module 100, an image cache module 200, an image display module 300 and a main control module 400. The image acquisition module 100 is electrically connected with an external image acquisition device and the main control module 400, and the image acquisition module 100 is used for acquiring image data acquired by the image acquisition device; the image buffer module 200 is electrically connected with the main control module 400, the image buffer module 200 is used for buffering image data, and the image buffer module 200 and the image acquisition module 100 process the image data in parallel; the image display module 300 is electrically connected to the main control module 400, and the image display module 300 is used for displaying image data.
In this embodiment, the image acquisition module may employ an OV-series complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS) image sensor OV7670 as the core. The image acquisition device can correspondingly adopt OV series cameras.
The image sensor OV7670 serves as a core of the image acquisition module 100 in the system, and is responsible for initializing an external image acquisition device, acquiring image data transmitted by the image acquisition device, converting the acquired image data into a digital image signal, and inputting the digital image signal to the main control module 400.
In this embodiment, the image buffer module 200 uses a Synchronous Dynamic Random Access Memory (SDRAM) chip as a core.
In this embodiment, the image display module 300 may employ a video graphics array (Video Graphics Array, VGA) module, such as a VGA display.
In this embodiment, the master control module employs a field programmable gate array (Field Programmable Gate Array, FPGA) chip. Preferably, the master control module 400 may use a cycloniv chip as a core.
The CycloniV series chip is used as the core of the main control module 400 of the system and is responsible for controlling output of the VGA display, setting of the CMOS image sensor module, image acquisition, controlling and outputting of the SDRAM memory and the like.
The image processing system designs a high-speed image processing system based on the SOPC technology through the arrangement of the image acquisition module 100, the image cache module 200, the image display module 300 and the main control module 400, solves the problem of insufficient bandwidth in a high-speed image acquisition control system, can fulfill the functions of image acquisition, image data compression, image storage and the like at high speed, improves the image acquisition rate, and provides convenience for subsequent image processing and intellectualization; in addition, the image acquisition module and the image caching module are subjected to parallelization processing, so that the working efficiency of the image processing system is improved.
The programmable System on Chip (System On Programmable Chip, SOPC), which is a highly developed product of the large-scale integrated circuit technology, fuses a System on Chip (SoC) and FPGA technology, so that the development of a hardware System becomes more flexible, efficient and low in cost. The SOPC embeds the digital signal processing system, the digital communication system, the embedded processor chip and the storage circuit in a single FPGA, adopts software and hardware cooperation and embeds an Internet protocol (Internet Protocol, IP) core, realizes thousands of rows of VHDL languages originally required by the SOPC through the IP core by only needing tens of rows of C language codes, and greatly shortens the design period of hardware.
SOPC technology has fused SoC and FPGA technology for the development of hardware system becomes more nimble, high-efficient, with low costs. The method specifically comprises the following steps: the production scale is larger and larger, and the method is more suitable for industrial production; the scale of the logic gate is larger and larger, and millions, tens of millions and even hundreds of millions of logic gates can be accommodated by a single chip, so that millions of transistors are excellent in complex time sequence and complex logic circuits; the SOPC production and development cost is low, the chips are subjected to strict test after production is finished, the SOPC is flexible in design, errors can be immediately changed after discovery, and unnecessary human loss of the chips is reduced; because of the characteristic of the SOPC of being capable of being programmed repeatedly, the actual use function of the chip can be changed only by changing the program input of the core, and the SOPC is greatly helpful for learning the programmable logic device; electronic design automation (Electronic design automation, EDA) development tools are more and more perfect, and functions are more and more powerful, so that the development of the FPGA is promoted; the novel FPGA is matched with the kernel CPU to develop more actual functions, and has great promotion effect on the development of soft and hard systems.
The image processing system of the present invention is described below with reference to fig. 2 and 3, and the image acquisition module 100 includes:
the image acquisition unit 110 is configured to acquire image data acquired by the image acquisition device.
The analog-to-digital conversion unit 120 is configured to convert the image data acquired by the image acquisition unit 110 into a digital image signal.
The first transmission unit 130 is configured to transmit the digital image signal to the main control module 400.
The adjusting unit 140 is configured to adjust parameters of the image capturing device, such as an initialization setting for the image capturing device.
In the image acquisition module 100, a serial camera control bus protocol (Serial Camera Control Bus, SCCB) is required to initialize registers within the image sensor before the image sensor OV7670 acquires the corresponding image data. SCCB is a serial camera control bus protocol. It is a three-wire protocol but is typically controlled by data lines and clock lines. SIO_D is the data line of the SCCB, and SIO_C is the clock line of the SCCB control protocol. The SCCB supports two address control modes in total: the first is an internal register unit Address (8 bit) that is used to determine which register in the system to operate on; the second is to distinguish between a write address and a read address from the first phase DATA, i.e., an address (ID address,8 bits) of the device, in which DATA7 to DATA1 are used to select the chip, DATA0 bits are write/read control bits (W/R), and if DATA0 bits are 1, a write operation is performed and if DATA0 bits are 0, a read operation is performed. The SCCB control bus realizes the initialization of the OV series cameras through the high-low level conversion of the data lines and signals.
The image processing system of the present invention is described below with reference to fig. 4, and the image buffer module 200 includes:
SDRAM chip and SDRAM controller connected with SDRAM chip electricity. The SDRAM controller is electrically connected with the main control module 400, and the SDRAM controller is used for acquiring the converted digital image signals transmitted by the main control module 400; the SDRAM chip is used for buffering the digital image signals transmitted by the SDRAM controller, and the SDRAM controller is used for controlling the SDRAM chip to perform read/write operation on the digital image signals.
The SDRAM controller is designed based on VHDL, and the custom SDRAM controller can directly store corresponding image information into two cache areas of an SDRAM chip, so that the link that data are cached by using a first-in first-out queue (First Input First Output, FIFO) in a traditional data acquisition system is omitted, and the data transmission task of the main control module 400 is lightened. In addition, the image acquisition module 100 and the image cache module 200 in the system are parallelized based on the SDRAM controller and the SDRAM chip, so that the working efficiency of the system is improved.
The image processing system of the present invention is described below with reference to fig. 5 and 6, and the image display module 300 includes:
the second transmission unit 310 is configured to acquire the digital image signal transmitted by the main control module 400. In this system, a digital image signal is transmitted to the second transmission unit 310 based on the SDRAM controller.
The digital-to-analog conversion unit 320 is configured to convert the digital image signal acquired by the second transmission unit 310 into image data.
And a display unit 330 for acquiring and displaying the image data.
The VGA interface has fifteen pins, of which useful pins are five pins VGA_ R, VGA _ G, VGA _ B, VGA _HS and VGA_VS. As R, G, B is any combination of three primary colors, different colors can be generated. The colors output by the VGA interface adopt 8bit3:3:2RGB, can display up to 256 colors, then different pixel points are generated on a VGA display screen through an electron gun, and finally, the combination of different colors forms an image. VGA_HS is a line synchronizing signal of the VGA display screen, and because the VGA display screen is displayed one by one pixel point by one from left to right by the electron gun, when the electron gun scans the VGA display screen from left to right, VGA_HS is generated, namely, the line is displayed completely. Then the electron gun returns to the left of the VGA display, and continues scanning the next line until the last line is scanned, and a VGA_VS field synchronizing signal is generated, namely the frame image of the surface is displayed. Currently, the highest image information that human eyes can accept is 30 frames per second, so that a common VGA display can completely meet the requirements of human eyes after 60 frames, VGA_VS of a standard VGA display screen in the system is set to be 60hz, and VGA_HS is set to be 31.5Khz.
The image processing method of the present invention is described below with reference to fig. 7, and is implemented based on the image processing system of the present invention, and includes the steps of:
s100, acquiring image data acquired by an external image acquisition device through an image acquisition module 100.
S200, converting the image data into a digital image signal by the image acquisition module 100, and then buffering the digital image signal in parallel by the image buffering module 200.
The image processing method designs a high-speed image processing system based on the SOPC technology, improves the efficiency of image processing work by parallelizing image acquisition and image caching, can lighten the data transmission pressure of the main control module 400, further solves the problem of insufficient bandwidth in a high-speed image acquisition control system, can rapidly complete the functions of image acquisition, image data compression, image storage and the like, improves the image acquisition rate, and provides convenience for subsequent image processing and intellectualization.
S300, the main control module 400 converts the digital image signal into image data based on the image buffer module 200, and displays the image data through the image display module 300.
Fig. 8 illustrates a physical structure diagram of an electronic device, as shown in fig. 8, which may include: processor 810, communication interface (Communications Interface) 820, memory 830, and communication bus 840, wherein processor 810, communication interface 820, memory 830 accomplish communication with each other through communication bus 840. The processor 810 may call logic instructions in the memory 830 to perform an image processing method comprising the steps of:
acquiring the image data;
converting the image data into the digital image signals and caching the digital image signals in parallel;
the digital image signal is converted into the image data and the image data is displayed.
Further, the logic instructions in the memory 830 described above may be implemented in the form of software functional units and may be stored in a computer-readable storage medium when sold or used as a stand-alone product. Based on this understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server, a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
In another aspect, the present invention also provides a computer program product comprising a computer program storable on a non-transitory computer readable storage medium, the computer program, when executed by a processor, being capable of performing the image processing method provided by the methods described above, the method comprising the steps of:
acquiring the image data;
converting the image data into the digital image signals and caching the digital image signals in parallel;
the digital image signal is converted into the image data and the image data is displayed.
In yet another aspect, the present invention also provides a non-transitory computer readable storage medium having stored thereon a computer program which, when executed by a processor, is implemented to perform the image processing method provided by the above methods, the method comprising the steps of:
acquiring the image data;
converting the image data into the digital image signals and caching the digital image signals in parallel;
the digital image signal is converted into the image data and the image data is displayed.
The apparatus embodiments described above are merely illustrative, wherein the elements illustrated as separate elements may or may not be physically separate, and the elements shown as elements may or may not be physical elements, may be located in one place, or may be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art will understand and implement the present invention without undue burden.
From the above description of the embodiments, it will be apparent to those skilled in the art that the embodiments may be implemented by means of software plus necessary general hardware platforms, or of course may be implemented by means of hardware. Based on this understanding, the foregoing technical solution may be embodied essentially or in a part contributing to the prior art in the form of a software product, which may be stored in a computer readable storage medium, such as ROM/RAM, a magnetic disk, an optical disk, etc., including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the method described in the respective embodiments or some parts of the embodiments.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims (8)
1. An image processing system, comprising:
the system comprises an image acquisition module, an image cache module, an image display module and a main control module;
the image acquisition module is electrically connected with the image acquisition device and the main control module and is used for acquiring image data acquired by the image acquisition device;
the image caching module is electrically connected with the main control module and is used for caching the image data, and the image caching module and the image acquisition module are used for processing the image data in parallel;
the image display module is electrically connected with the main control module and is used for displaying the image data;
the image acquisition module comprises:
the image acquisition unit is used for acquiring the image data acquired by the image acquisition device;
the analog-to-digital conversion unit is used for converting the image data acquired by the image acquisition unit into a digital image signal;
the first transmission unit is used for transmitting the digital image signals to the main control module;
the image buffer module comprises:
a synchronous dynamic random access memory chip and a synchronous dynamic random access memory controller electrically connected with the synchronous dynamic random access memory chip;
the synchronous dynamic random access memory controller is electrically connected with the main control module and is used for acquiring the digital image signals transmitted by the main control module;
the synchronous dynamic random access memory is used for caching the digital image signals transmitted by the synchronous dynamic random access memory controller, and the synchronous dynamic random access memory controller is used for controlling the synchronous dynamic random access memory chip to perform read/write operation on the digital image signals.
2. The image processing system of claim 1, wherein the image acquisition module further comprises:
and the adjusting unit is used for adjusting parameters of the image acquisition device.
3. The image processing system of claim 1, wherein the image acquisition module employs an image sensor OV7670.
4. The image processing system of claim 1, wherein the image display module comprises:
the second transmission unit is used for acquiring the digital image signals transmitted by the main control module;
the digital-to-analog conversion unit is used for converting the digital image signals acquired by the second transmission unit into image data;
and the display unit is used for acquiring and displaying the image data.
5. The image processing system of claim 1, wherein the image display module employs a video graphics array module.
6. The image processing system of claim 1, wherein the master control module employs a field programmable gate array chip.
7. The image processing system of claim 6, wherein the master control module employs a cycloniv series chip.
8. An image processing method implemented on the basis of an image processing system as claimed in any one of claims 1-7, characterized by comprising the steps of:
acquiring the image data;
converting the image data into digital image signals and caching the digital image signals in parallel;
the digital image signal is converted into the image data and the image data is displayed.
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| JP2010097438A (en) * | 2008-10-16 | 2010-04-30 | Keyence Corp | Outline information extraction method using image processing, creation method for pattern model in image processing, positioning method for pattern model in image processing, image processor, image processing program and computer-readable recording medium |
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