CN110096452A - Non-volatile random access memory and its providing method - Google Patents
Non-volatile random access memory and its providing method Download PDFInfo
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Abstract
This application involves nonvolatile memory (NVRAM, Non-VolatileRandom Access Memory), specifically, it is related to non-volatile random access memory and its providing method, it include: control unit, random access storage device RAM and NVM chip, wherein, the control unit includes NVRAM management module, the part of the random access storage device RAM and the part of NVM chip provide NVRAM service, the NVRAM management module provides NVRAM random access storage device RAM and the NVM chip of service according to NVRAM address space access, the ability of efficient random access is provided by random access storage device RAM for corresponding NVRAM address space, and NVM chip is corresponding NVR The update of AM address space provides non-volatile ability.
Description
Technical field
This application involves nonvolatile memory (NVRAM, Non-VolatileRandom Access Memory), specifically,
It is related to non-volatile random access memory and its providing method.
Background technique
Fig. 1 illustrates the block diagram of solid storage device.Solid storage device 102 is coupled with host, for mentioning for host
For storage capacity.Host can be coupled in several ways between solid storage device 102, and coupled modes include but is not limited to
For example, by SATA (Serial Advanced Technology Attachment, Serial Advanced Technology Attachment), SCSI
(Small Computer System Interface, small computer system interface), SAS (Serial Attached
SCSI, Serial Attached SCSI (SAS)), IDE (Integrated Drive Electronics, integrated drive electronics), USB
(Universal Serial Bus, universal serial bus), PCIE (Peripheral Component Interconnect
Express, PCIe, high speed peripheral component interconnection), NVMe (NVM Express, high speed non-volatile memory), Ethernet, optical fiber it is logical
Road, cordless communication network etc. connect host and solid storage device 102.Host, which can be, to be set through the above way with storage
The standby information processing equipment communicated, for example, personal computer, tablet computer, server, portable computer, network exchange
Machine, router, cellular phone, personal digital assistant etc..Storing equipment 102 includes interface 103, control unit 104, one or more
A NVM chip 105 and DRAM (Dynamic Random Access Memory, dynamic RAM) 110.
Nand flash memory, phase transition storage, FeRAM (Ferroelectric RAM, ferroelectric memory), MRAM
(Magnetic Random Access Memory, magnetoresistive memory), RRAM (Resistive Random
Access Memory, resistance-variable storing device), XPoint memory etc. be common NVM.
Interface 103 can be adapted to for example, by the side such as SATA, IDE, USB, PCIE, NVMe, SAS, Ethernet, optical-fibre channel
Formula and host exchanging data.
Control unit 104 is used to control the data transmission between interface 103, NVM chip 105 and DRAM 110, also
For storage management, host logical address to flash memory physical address map, erasure balance, bad block management etc..Control unit 104 can
It is realized by the various ways of software, hardware, firmware or combinations thereof, for example, control unit 104 can be FPGA (Field-
Programmable gate array, field programmable gate array), ASIC (Application Specific
Integrated Circuit, application specific integrated circuit) or a combination thereof form.Control unit 104 also may include place
Device or controller are managed, software is executed in processor or controller and carrys out the hardware of manipulation and control component 104 to handle IO
(Input/Output) it orders.Control unit 104 is also coupled to DRAM 110, and may have access to the data of DRAM 110.?
DRAM can store the data of the I/O command of FTL table and/or caching.
Control unit 104 includes flash interface controller (or being Media Interface Connector controller, flash memory channel controller), is dodged
It deposits interface controller and is coupled to NVM chip 105, and sent out in a manner of the interface protocol to follow NVM chip 105 to NVM chip 105
It orders out, to operate NVM chip 105, and receives the command execution results exported from NVM chip 105.Known NVM chip connects
Mouth agreement includes " Toggle ", " ONFI " etc..
Memory target (Target) is shared CE (, Chip Enable, chip enabled) signal in nand flash memory encapsulation
One or more logic units (LUN, Logic UNit).It may include one or more tube cores (Die) in nand flash memory encapsulation.
Typically, logic unit corresponds to single tube core.Logic unit may include multiple planes (Plane).It is more in logic unit
A plane can be with parallel access, and multiple logic units in nand flash memory chip can execute order and report independently of one another
State.
Data are usually stored and read on storage medium by page.And data are erased in blocks.Block (also referred to as physical block) packet
Containing multiple pages.Block includes multiple pages.Page (referred to as Physical Page) on storage medium has fixed size, such as 17664 bytes.
Physical Page also can have other sizes.
In solid storage device, safeguarded using FTL (Flash Translation Layer, flash translation layer (FTL)) from
Map information of the logical address to physical address.Logical address constitutes the solid-state that the upper layer software (applications)s such as operating system are perceived and deposits
Store up the memory space of equipment.Physical address is the address for accessing the physical memory cell of solid storage device.In related skill
Also implement address of cache using intermediate address form in art.Such as logical address is mapped as intermediate address, and then will be intermediate
Address is further mapped as physical address.
The table structure for storing the map information from logical address to physical address is referred to as FTL table.FTL table is that solid-state is deposited
Store up the important metadata in equipment.The data item of usual FTL table has recorded the ground in solid storage device as unit of data page
Location mapping relations.
Each storage unit of NVM storage medium can store 1 bit or more bit informations.For example, 1 bit letter can be stored
The storage unit of breath is known as SLC (single stage unit, Single Level Cell), and the storage unit that can store 2 bit informations is known as
MLC (multi-level unit, MultipleLevelCell), can store 3 bit informations storage unit be known as TLC (three-level unit,
TripleLevelCell), the storage unit that can store 4 bit informations is known as QLC (level Four unit, quadruple Level
Cell)。
NVRAM is the memory that can be accessed randomly, and even if power cut-off, the data stored in NVRAM will not
It loses.After next time powers on, the data stored in NVRAM can be accessed again.
Summary of the invention
The application is intended to provide NVRAM by solid storage device, and provided NVRAM can be set by same solid-state storage
The host access of standby coupling, and/or accessed by the controller of solid storage device.
According to a first aspect of the present application, the first non-volatile random access storage according to the application first aspect is provided
Device, comprising: control unit, random access storage device RAM and NVM chip, wherein the control unit includes NVRAM management mould
Block, the part of the random access storage device RAM and the part of NVM chip provide NVRAM service, the NVRAM management module
NVRAM random access storage device RAM and the NVM chip of service is provided according to NVRAM address space access.
The first non-volatile random access memory according to a first aspect of the present application, wherein the offer NVRAM service
The memory space of NVM chip be organized as multiple bulks, the storage for providing the random access storage device RAM of NVRAM service is empty
Between be organized as multiple Memory slices, the NVRAM address space is organized as multiple fritters, the NVRAM management module according to
The bulk of the fritter instruction or the address of Memory slice access the bulk or Memory slice.
First or second non-volatile random access memory according to a first aspect of the present application, wherein random access is deposited
Reservoir RAM is dynamic random access memory DRAM.
Third non-volatile random access memory according to a first aspect of the present application, wherein the dynamic randon access
Some or all of DRAM memory is substituted by static random access memory SRAM.
First or second non-volatile random access memory according to a first aspect of the present application, wherein the address NVRAM is empty
Between be continuous address space.
First or second non-volatile random access memory according to a first aspect of the present application, wherein NVRAM manages mould
Block safeguards NVRAM address space.
The 6th non-volatile random access memory according to a first aspect of the present application, wherein each fritter occupies
The size in the region of NVRAM address space is identical.
The the 6th or the 7th non-volatile random access memory according to a first aspect of the present application, wherein the NVRAM pipe
Module is managed according to the address of NVRAM address space, calculates the corresponding fritter in the address.
The 8th non-volatile random access memory according to a first aspect of the present application, wherein the NVRAM management module
According to the address of NVRAM address space divided by the size of the corresponding NVRAM address space of fritter, the index of fritter is obtained.
The second non-volatile random access memory according to a first aspect of the present application, wherein the size of the Memory slice
It is identical with the size of fritter.
The second non-volatile random access memory according to a first aspect of the present application, wherein the bulk includes: basis
Bulk and log bulk, for storing data, the log bulk is for recording to NVRAM address space for the basis bulk
Modification.
The 11st non-volatile random access memory according to a first aspect of the present application, wherein the storage of the bulk
Space is organized as frame.
The 12nd non-volatile random access memory according to a first aspect of the present application, wherein the NVRAM manages mould
Log bulk frame tissue is chained list by block.
The 12nd or 13 non-volatile random access memories according to a first aspect of the present application, wherein the NVRAM
Each log bulk frame tissue in log bulk is chained list by management module.
The 12nd non-volatile random access memory according to a first aspect of the present application, wherein the size of the frame is same
The size of fritter is identical.
The 12nd non-volatile random access memory according to a first aspect of the present application, wherein in response to NVRAM
The address NADDR in location space is written data D, and the NVRAM management module generation has recorded<NADDR, D>journal entries, institute
It states NVRAM management module and log bulk frame is written into journal entries.
The 11st or 12 non-volatile random access memories according to a first aspect of the present application, wherein in response to
The address NADDR of NVRAM address space is written data D, and data D is recorded in and NADDR pairs of address by the NVRAM management module
In the Memory slice answered.
The 12nd non-volatile random access memory according to a first aspect of the present application, wherein the random access is deposited
Reservoir RAM is stored with fritter conversion table, and the fritter conversion table includes multiple entries, and each entry corresponds to one of fritter, item
Purpose value have recorded for fritter provide data basic bulk frame address or Memory slice address.
The 18th non-volatile random access memory according to a first aspect of the present application, wherein will be greater than threshold value
NVRAM address space address of cache is the address of basic bulk frame, will be not more than the NVRAM address space address of threshold value, mapping
For the address of Memory slice.
The 18th non-volatile random access memory according to a first aspect of the present application, wherein record has mark in entry
Will position, the value that flag bit is used to indicate entry indicate the address of basic bulk frame or the address of Memory slice.
The 12nd non-volatile random access memory according to a first aspect of the present application, wherein the NVRAM manages mould
Block safeguards NVRAM metadata.
The 21st non-volatile random access memory according to a first aspect of the present application, wherein NVRAM metadata note
Record log bulk frame head and Memory slice descriptor head；The log bulk frame head is the address of log bulk frame, and indicates
The head node of log bulk frame chained list；The Memory slice descriptor head is Memory slice descriptor address, and indicates Memory slice
The head node of descriptor chained list.
The 22nd non-volatile random access memory according to a first aspect of the present application, wherein the Memory slice is retouched
Symbol is stated for describing Memory slice.
The 22nd or 23 non-volatile random access memories according to a first aspect of the present application, wherein memory
Piece descriptor has recorded basic bulk frame address corresponding to Memory slice.
The 22nd or 23 non-volatile random access memories according to a first aspect of the present application, wherein memory
Piece descriptor has recorded the state of Memory slice.
The 22nd or 23 non-volatile random access memories according to a first aspect of the present application, wherein described
Memory slice and the Memory slice descriptor correspond.
The 22nd to 26 non-volatile random access memories according to a first aspect of the present application, wherein described
Memory slice descriptor is organized as chained list.
According to a second aspect of the present application, it provides and provides non-volatile random access according to the first of the application second aspect
The method of memory includes the following steps: the NVRAM address space of identification access；Identify the ground of the NVRAM address space of access
Location is mapped to the address or Memory slice address of basic bulk frame；It is obtained from basic bulk frame or Memory slice according to recognition result
Take data to be visited.
First according to a second aspect of the present application provides the method for non-volatile random access memory, wherein basis is big
Block frame is the storage unit of the memory block positioned at NVM chip, and Memory slice is the storage unit positioned at volatile memory.
The first or second according to a second aspect of the present application provides the method for non-volatile random access memory, wherein
According to the address for the NVRAM address space to be accessed, fritter index (ID) is generated；(ID) access fritter conversion is indexed according to fritter
Table；Fritter translation table entry is obtained according to the address for the NVRAM address space to be accessed, is wanted according to the identification of fritter translation table entry
The address of the NVRAM address space of access is mapped to the address or Memory slice address of basic bulk frame.
Third according to a second aspect of the present application provides the method for non-volatile random access memory, wherein by fritter
NVRAM address space is provided, multiple fritters together provide complete NVRAM address space.
First to fourth according to a second aspect of the present application provides the method for non-volatile random access memory, also wraps
It includes: deviant is generated from the address of NVRAM address space to be visited, for the data read from basic bulk frame, with offset
Value addressing obtains data to be visited.
First to fourth according to a second aspect of the present application provides the method for non-volatile random access memory, also wraps
It includes: generating deviant from the address of NVRAM address space to be visited, data to be visited are obtained from Memory slice.
Third or the 4th according to a second aspect of the present application provides the method for non-volatile random access memory, wherein
If fritter translation table entry record is Memory slice address, data to be visited are obtained from Memory slice；If fritter translation table entry
Record be basic bulk frame address, be the basic bulk frame storage allocation piece of data to be obtained, will be from data to be obtained
Basic bulk frame reads the Memory slice of data write-in distribution to be visited, and data to be visited are obtained from the Memory slice of distribution.
The 7th according to a second aspect of the present application provides the method for non-volatile random access memory, wherein further include:
Fritter translation table entry is updated with the Memory slice address of distribution.
According to the third aspect of the application, provides and provide non-volatile random access according to the first of the application third aspect
The method of memory includes the following steps: that identification will be written into the NVRAM address space of data；Identification will be written into data
The address of NVRAM address space is mapped to the address or Memory slice address of basic bulk frame；To be written into the NVRAM of data
The address of address space is Memory slice address, then data is written to Memory slice；To be written into the NVRAM address space of data
Address is the address of basic bulk frame, then generates and have recorded the NVRAM address space address NADDR of data to be written into and write
Log bulk frame is written in journal entries by the journal entries of the data D entered.
The method of non-volatile random access memory is provided according to the first of the third aspect of the application, wherein basis is big
Block frame is the storage unit of the memory block positioned at NVM chip, log bulk framing bit in the storage unit of the memory block of NVM chip,
Memory slice is the storage unit positioned at volatile memory.
The method of non-volatile random access memory is provided according to the first or second of the third aspect of the application, wherein
According to the address of the NVRAM address space of data to be written into, fritter index (ID) is generated；It is small that (ID) access is indexed according to fritter
Block conversion table；Fritter translation table entry is obtained according to the address of the NVRAM address space of data to be written into, is converted according to fritter
The address for the NVRAM address space that table clause identification will be written into data is mapped to address or the Memory slice of basic bulk frame
Address.
The method of non-volatile random access memory is provided according to the third of the third aspect of the application, wherein by fritter
NVRAM address space is provided, multiple fritters together provide complete NVRAM address space.
The method of non-volatile random access memory is provided according to the first to fourth of the third aspect of the application, is also wrapped
It includes: if fritter translation table entry record is Memory slice address, after data are written to Memory slice, generating journal entries；By log
Log bulk frame is written in entry.
The method of non-volatile random access memory is provided according to the 5th of the third aspect of the application the, wherein log item
Program recording will be written into the NVRAM address space address NVRAM and the data D being written into of data.
The method of non-volatile random access memory is provided according to the first to the 6th of the third aspect of the application, wherein
After data D generation journal entries being written to NVRAM address space address NADDR, the write-in to NVRAM address space is indicated
Data processing is completed.
The method of non-volatile random access memory is provided according to the first to the 7th of the third aspect of the application, wherein
Journal entries are generated, and log bulk frame is written into journal entries, the write-in data processing of instruction NADDR address space is completed.
According to the fourth aspect of the application, provides and provide non-volatile random access according to the first of the application fourth aspect
The method of memory includes the following steps: that identification will be written into the NVRAM address space of data；According to data to be written into
The address of NVRAM address space generates and has recorded the NVRAM address space address NVRAM of data to be written into and to be written into
Data D journal entries；Log bulk frame is written into journal entries.
The method of non-volatile random access memory is provided according to the first of the fourth aspect of the application, wherein log is big
Block framing bit is in the storage unit of the memory block of NVM chip.
The method of non-volatile random access memory is provided according to the first or second of the fourth aspect of the application, is also wrapped
Include: the address for the NVRAM address space that data will be written in identification is mapped to the address or Memory slice address of basic bulk frame；If
The address for being written into the NVRAM address space of data is Memory slice address, and data are written to Memory slice.
The method of non-volatile random access memory is provided according to the third of the fourth aspect of the application, wherein Memory slice
It is the storage unit positioned at volatile memory.
The method of non-volatile random access memory is provided according to the third of the fourth aspect of the application or the 4th, wherein
According to the address of the NVRAM address space of data to be written into, fritter index (ID) is generated；It is small that (ID) access is indexed according to fritter
Block conversion table；Fritter translation table entry is obtained according to the address of the NVRAM address space of data to be written into, is converted according to fritter
The address for the NVRAM address space that table clause identification will be written into data is mapped to address or the Memory slice of basic bulk frame
Address.
The method of non-volatile random access memory is provided according to the 5th of the fourth aspect of the application the, wherein by fritter
NVRAM address space is provided, multiple fritters together provide complete NVRAM address space.
The method of non-volatile random access memory is provided according to the 5th or the 6th of the fourth aspect of the application the, wherein
It is executed concurrently to generate journal entries and generate fritter and indexes (ID).
The method of non-volatile random access memory is provided according to the third of the fourth aspect of the application to the 7th, wherein
It is completed to any one of Memory slice write-in data and generation journal entries, the write-in data processing of instruction NVRAM address space is completed.
According to the 5th of the application the aspect, provides and provide non-volatile random access according to the first of the 5th aspect of the application
The method of memory includes the following steps: to scan Memory slice descriptor chained list in response to powering on；Obtain each Memory slice description
The address of the corresponding basic bulk frame of the same Memory slice recorded in symbol；Data are read from basic bulk frame and will read data write-in
Memory slice.
The method of non-volatile random access memory is provided according to the first of the 5th of the application the aspect, wherein basis is big
Block frame is the storage unit of the memory block positioned at NVM chip, and Memory slice is the storage unit positioned at volatile memory.
The method of non-volatile random access memory is provided according to the second of the 5th of the application the aspect, further includes: scanning
Log bulk frame chained list；Journal entries are read from the log bulk frame in log bulk frame chained list；Memory is updated with journal entries
Piece.
The method of non-volatile random access memory is provided according to the third of the 5th of the application the aspect, wherein log is big
Block frame is the storage unit of the memory block positioned at NVM chip.
The method of non-volatile random access memory is provided according to the 4th of the 5th of the application the aspect the, further includes: power down
When, NVM chip is written into Memory slice descriptor.
Non-volatile random access memory and its providing method provided by the present application pass through Memory slice for corresponding NVRAM
Location space provides the ability of efficient random access, and the log bulk frame recording of log bulk journal entries<NADDR, D>,
Non-volatile ability is provided for the update of corresponding NVRAM address space.
Detailed description of the invention
In order to illustrate the technical solutions in the embodiments of the present application or in the prior art more clearly, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The some embodiments recorded in application can also be obtained according to these attached drawings other for those of ordinary skill in the art
Attached drawing.
Fig. 1 is the block diagram of solid storage device in the related technology；
Fig. 2 illustrates the block diagram of NVRAM provided by the embodiments of the present application；
Fig. 3 illustrates the schematic diagram of NVRAM address space provided by the embodiments of the present application；
Fig. 4 illustrates fritter conversion table provided by the embodiments of the present application；
Fig. 5 illustrates provided by the embodiments of the present application for providing the block diagram of the data organization of NVRAM service；
Fig. 6 A illustrates the flow chart of processing NVRAM read request provided by the embodiments of the present application；
Fig. 6 B illustrates the flow chart for the processing NVRAM read request that the another embodiment of the application provides；
Fig. 6 C illustrates the flow chart for the processing NVRAM write request that another embodiment of the application provides；
Fig. 6 D illustrates the flow chart of the processing NVRAM write request of the application another embodiment offer；
Fig. 7 illustrates the flow chart provided by the embodiments of the present application for powering on and restoring NVRAM.
Specific embodiment
Below with reference to the attached drawing in the embodiment of the present application, technical solutions in the embodiments of the present application carries out clear, complete
Ground description, it is clear that described embodiment is some embodiments of the present application, instead of all the embodiments.Based on the application
In embodiment, those skilled in the art's every other embodiment obtained without making creative work, all
Belong to the range of the application protection.
Fig. 2 is the block diagram of NVRAM provided by the embodiments of the present application.
According to an embodiment of the present application, NVRAM is provided by solid storage device 102.As an example, it can be used according to fig. 2
Solid storage device structure.The control unit 204 of solid storage device 102, further includes NVRAM management module, by making
With the part and the part of NVM chip 105 of DRAM 110,200 are serviced to provide NVRAM.Optionally, using SRAM come part or
Replacing whole DRAM.SRAM can be integrated in inside control unit 204.Embodiment according to fig. 2 is to use the part of DRAM 110
It is introduced to provide for NVRAM is serviced, it is possible to use SRAM partly or entirely to substitute DRAM.NVRAM management module is by for example
Operate in software, firmware and/or the hardware realization of the part as ASIC in the CPU of control unit 204.
Host is coupled to solid storage device 102 by interface 103.Host accesses solid storage device by interface 103
The 102 NVRAM services 200 provided.For example, solid storage device 102 is coupled to host by PCIe interface, NVRAM is mapped
To the storage space (MemorySpace) of PCIe device.Host is visited in the way of the storage space of access PCIe device
The NVRAM service that solid storage device 102 provides is asked, so that host, which need not be changed i.e., can be used NVRAM service.As another
NVRAM is supplied to host as independent PCIe device and used by example.
NVRAM management module also serves the other component of control unit 204.For example, being transported in the CPU of control unit 204
NVRAM service can be used in other capable programs.These programs use in the way of accessing local storage (SRAM or DRAM)
NVRAM service.Optionally, NVRAM service is organized as file or object, other journeys run in the CPU of control unit 204
Sequence is serviced in the way of access file or object using NVRAM.
Fig. 3 is the schematic diagram of NVRAM address space provided by the embodiments of the present application.As an example, NVRAM address space is
Continuous address space.NVRAM management module safeguards NVRAM address space.Direction in Fig. 3 from the top down is the address NVRAM
The incremental direction in space.NVRAM address space includes multiple regions with same size, and each region is referred to as fritter.Fig. 3
In show multiple fritters, including fritter 0, fritter 1 ... fritter 5.For example, the corresponding NVRAM address space of each fritter
Size can be such as 512 bytes, 1KB or 4KB.According to the address of NVRAM address space, it is corresponding small that the address can be calculated
Block.For example, resulting quotient is fritter with the address of NVRAM address space divided by the size of the corresponding NVRAM address space of fritter
Index or small block number (ID).
In one embodiment, using other journeys run in the host of NVRAM service or the CPU of control unit 204
Sequence (being referred to as applying) uses NVRAM by NVRAM address space.For example, NVRAM address space is mapped directly to PCIe device
Storage space the address NVRAM sky is obtained directly or through specified offset by the storage space address of PCIe device
Between address.
In another embodiment, used address space is (for example, PCIe device when servicing using NVRAM
Memory space or file deviant), need to obtain the address of NVRAM address space by address conversion.NVRAM pipe
Reason module also provides address translation table, for that used Address space mappinD will be applied to NVRAM address space.
Fig. 4 illustrates fritter conversion table provided by the embodiments of the present application.NVRAM management module safeguards fritter conversion table.It is small
Block conversion table includes multiple entries, and each entry corresponds to one of fritter, and by fritter ID index, it is small that the value of entry, which has recorded,
Block provides the address of the basic bulk frame of data or the address of Memory slice.It will be described in detail later basic bulk frame and Memory slice.
Optionally, according to the value of entry, identify that the value indicates the address of basic bulk frame or the address of Memory slice.
For example, will be greater than the entry values of threshold value, map for the address of basic bulk frame, and the entry of threshold value will be not more than
Value, is mapped as the address of Memory slice.As another example, flag bit is also recorded in the entry, and the value for being used to indicate entry refers to
Show the address of basic bulk frame or the address of Memory slice.
Fritter conversion table is stored in such as DRAM 110 (referring also to Fig. 2) or SRAM.NVRAM management module is according to visit
The NVRAM address space address asked calculates corresponding fritter ID, and inquires fritter conversion table with fritter ID, is small to obtain
Block provides the address of the basic bulk frame of data or the address of Memory slice.
Fig. 5 illustrates provided by the embodiments of the present application for providing the block diagram of the data organization of NVRAM service.As act
Example, NVRAM management module (are denoted as DRAM using the part (being denoted as NVM chip 510) of NVM chip 105 and the part of DRAM 110
520)。
The memory space of NVM chip 510 is organized as bulk.Bulk is the single one physical block of such as NVM chip, NVM core
Multiple physical blocks with same physical block number of each plane (Plane) in the LUN of piece, or the object from multiple LUN
Manage block.Optionally, bulk further includes verification data, and the data for storing for bulk provide protection.Still optionally, in bulk
Multiple copies of middle storing data, the data for storing for bulk provide protection.Optionally, the SLC of NVM chip 105 is deposited
Storage unit is used as NVM chip 510.
The memory space of bulk is organized as frame (referring to bulk 512).Bulk 512 includes multiple frames.The size of frame is the same as small
The size of block is identical, so that the data that the corresponding NVRAM address space of a fritter is stored may be recorded in a frame.
Bulk includes at least two classes, basic bulk and log bulk.The frame of basic bulk, referred to as basic bulk frame.It returns
It returns referring to Fig. 4, the address of the basic bulk frame of the value record of the entry of fritter conversion table indicates basic bulk frame.According to base
The address of plinth bulk frame may have access to basic bulk frame.
With continued reference to Fig. 5, the memory space of DRAM 520 is organized as Memory slice.Memory slice is the one of such as DRAM 520
Section memory space.The size of Memory slice is identical with the size of fritter, so that the corresponding NVRAM address space of a fritter is stored
Data may be recorded in a Memory slice.Referring back to Fig. 4, the ground of the Memory slice of the value record of the entry of fritter conversion table
Location indicates Memory slice.It may have access to Memory slice according to the address of Memory slice.
With continued reference to Fig. 5, the value of the entry (fritter 0) of fritter conversion table indicates and is located at the basic big of basic bulk 514
The address of block frame.The value of the entry (fritter 1) of fritter conversion table, indicates the address of Memory slice 526.And Memory slice 526 is base
The copy (in Fig. 5, being indicated by dotted line) in DRAM 520 of the basic bulk frame of some of plinth bulk 516.NVRAM management module
By the value of the entry (fritter 1) of fritter conversion table, Memory slice 526 is accessed, as to the basic bulk for accessing basic bulk 516
The substitution of frame, efficiently to press the corresponding NVRAM address space of byte-accessed fritter 1.
Log bulk is used to record the modification to NVRAM address space.For example, to the address NADDR of NVRAM address space
Data D is written, then generates journal entries, record<NADDR, D>.NVRAM management module will have recorded<NADDR, D>log item
Log bulk frame is written in mesh.Log bulk frame tissue is such as chained list by NVRAM management module, big in favor of accessing multiple logs
Block frame.For example, one log bulk frame (L1) of log bulk 532 has recorded a log of log bulk 534 referring to Fig. 5
The address of bulk frame (L2), the log that a log bulk frame (L3) of log bulk 534 has recorded log bulk 536 are big
The address of block frame (L4), a log bulk frame (L5) of log bulk 536 have recorded a log bulk of log bulk 538
The address of frame (L6).Optionally or further, it is big to be recorded in log for the address of the log bulk frame (L1) of log bulk 532
In the log bulk frame (L2) of block 534, the address of the log bulk frame (L3) of log bulk 534 is recorded in log bulk 536
Log bulk frame in (L4), the address of the log bulk frame (L5) of log bulk 536 is recorded in the log of log bulk 538
In bulk frame (L6).
Each log bulk frame in log bulk is also organized as such as chained list.For example, one of log bulk 532
The address of another log frame of log bulk 532 is had recorded in log frame.
Still as an example, using modification with fritter conversion table the corresponding NVRAM address space of entry (fritter 1), to
Data D is written in the address NADDR of the NVRAM address space, by<the NADDR that has recorded of generation, D>journal entries log is written
The log bulk frame of bulk 538.Since log bulk 538 is the memory space of NVM chip, the day that Xiang Zhi bulk 538 is written
Will has non-volatile characteristic, even if storage device looses power can still be read in log bulk 538 when next time stores device power
Have recorded<NADDR, D>journal entries.
Data D is written to the address NADDR of the NVRAM address space in response to application, NVRAM management module is also samely
Data D is recorded in the corresponding Memory slice 526 of location NADDR.Since Memory slice is the memory space that DRAM 520 is provided, can be pressed
Byte addressing or random access, to efficiently complete the operation for recording data D in Memory slice 526.
According to an embodiment of the present application, Memory slice 526 for the NVRAM address space corresponding to fritter 1 provide efficiently with
The ability of machine access, and the log bulk frame recording of log bulk 538 journal entries<NADDR, D>, for corresponding to fritter 1
The update of NVRAM address space provides non-volatile ability.It is provided simultaneously with the address NVRAM of random access Yu non-volatile ability
Space, Xiang Yingyong provide NVRAN service.
Optionally, according to an embodiment of the present application, NVRAM management module also safeguards NVRAM metadata.NVRAM metadata
Have recorded such as log bulk frame head and Memory slice descriptor head.Log bulk frame head is the address of log bulk frame, and refers to
The head node of log bulk frame chained list is shown.By the head node of log bulk frame chained list, log bulk frame chained list can be traversed
All nodes.Memory slice descriptor head is Memory slice descriptor address, and indicates the head node of Memory slice descriptor chained list.
Still optionally, Memory slice descriptor is for describing Memory slice.The Memory slice used describes one by one with Memory slice
It is corresponding.Descriptor memory symbol is organized as such as chained list.Still as an example, Memory slice descriptor has recorded corresponding to Memory slice
The state of Memory slice is also recorded in basic bulk frame address, Memory slice descriptor, for example, Memory slice is being written into from basis
The data of bulk frame, the data of Memory slice are being written into basic bulk frame, the data of Memory slice corresponding basis bulk with its
Frame is identical or different.
Fig. 6 A illustrates the flow chart of processing NVRAM read request provided by the embodiments of the present application.
Data are read using from NVRAM.In one example, data are read from NVRAM using in the way of accessing memory；?
In another example, data are read from NVRAM using in the way of access file or object.
NVRAM management module identification application will read data from NVRAM.For example, NVRAM management module, is identified using visit
Ask that NVRAM address space or application access are used to provide the NVRAM file or object of service.NVRAM management module is according to answering
With the address for the NVRAM address space to be read, fritter index (fritter ID) (A610) is generated.According to fritter search index fritter
Conversion table (referring also to Fig. 3-Fig. 5) (A620).According to the value of fritter translation table entry, identify that the value recorded is basic bulk
The address of frame or the address (A630) of Memory slice.If what fritter translation table entry recorded is the address of basic bulk frame, from base
Plinth bulk frame reads data to be visited (A640)；If fritter translation table entry record is Memory slice address, from Memory slice
Read data to be visited (A650).
Optionally, NVRAM management module also generates deviant (for example, will from the address for the NVRAM address space to be read
The designated bit of the address is as deviant).For the data read from basic bulk frame, addressing to obtain with deviant will be read
Data.For Memory slice, the data in DRAM 520 are read (referring also to figure plus the result of deviant with Memory slice address
5)。
Fig. 6 B illustrates the flow chart of the processing NVRAM read request of the another embodiment of the application.It is read using from NVRAM
According to.The NVRAM address space to be read is applied in the identification of NVRAM management module.NVRAM management module to be read according to application
The address of NVRAM address space generates fritter index (fritter ID) (B610).According to fritter search index fritter conversion table (
- Fig. 5 referring to Fig. 3) (B620).According to the value of fritter translation table entry, identify that the value recorded is the address of basic bulk frame
Or the address (B630) of Memory slice.If fritter translation table entry record is Memory slice address, read from Memory slice wait visit
The data (B650) asked.It is basic bulk frame to be read if what fritter translation table entry recorded is the address of basic bulk frame
Storage allocation piece will read the Memory slice (B640) of data write-in distribution to be visited from basic bulk frame, out of distribution
It deposits and reads data to be visited in piece.And the entry (B660) of fritter conversion table is also updated with the address of the Memory slice of distribution,
To record the Memory slice address of distribution in the corresponding fritter translation table entry in address with the NVRAM address space to be read.
Optionally, with the Memory slice address of distribution, in addition the offset generated from the address for the NVRAM address space to be read
Value accesses the Memory slice of the distribution in DRAM 520.
Fig. 6 C illustrates the flow chart for the processing NVRAM write request that another embodiment of the application provides.
Data are write using to NVRAM.The identification application of NVRAM management module will write the NVRAM address space of data.NVRAM
Management module generates fritter index (fritter ID) (C610) according to the address of the application NVRAM address space to be written.According to small
Block search index fritter conversion table (referring also to Fig. 3-Fig. 5) (C620).According to the value of fritter translation table entry, identify that the value is remembered
What is recorded is the address or the address (C630) of Memory slice of basic bulk frame.If fritter translation table entry record is Memory slice
Then data (C650) is written to Memory slice in location.If what fritter translation table entry recorded is the address of basic bulk frame, note is generated
The journal entries (C640) of NVRAM address space address NADDR to be visited with the data D being written into are recorded, and by log
Log bulk frame (C660) is written in entry.
For fritter translation table entry record be Memory slice address situation, to Memory slice be written data after, also give birth to
At log.The journal entries of log recording NVRAM address space address NADDR to be visited and the data D being written into, and
Log bulk frame is written into journal entries.
Optionally, it after generating journal entries for write request, has been handled to the write request of application instruction NVRAM address space
At.Solid storage device provides backup power source, even if log generated also can be by guarantee that power down occurs for solid storage device
Log bulk frame is written, or is recorded in NVM chip 520.
Fig. 6 D illustrates the flow chart of the processing NVRAM write request of the application another embodiment offer.It is write using to NVRAM
Data.The identification application of NVRAM management module will write the NVRAM address space (D610) of data.NVRAM management module is according to application
The address for the NVRAM address space to be written generates and has recorded NVRAM address space address NADDR to be visited and be written into
Data D journal entries (D620), and by journal entries be written log bulk frame (D630).Optionally, for write request
After generating journal entries, handles and complete to the write request of application instruction NVRAM address space.
NVRAM management module generates fritter index (fritter ID) according to the address of the application NVRAM address space to be written
(D640).According to fritter search index fritter conversion table (referring also to Fig. 3-Fig. 5) (D650).According to fritter translation table entry
Value identifies that the value recorded is the address or the address (D660) of Memory slice of basic bulk frame.If fritter translation table entry
Record is Memory slice address, then data (D670) also is written to Memory slice.
Optionally, NVRAM management module is executed concurrently the operation for generating log and generating fritter index (fritter ID), with
And to Memory slice write-in data, any one is completed with log is generated, i.e., at the write request of application instruction NVRAM address space
Reason is completed.Postpone to reduce the processing of the write request of NVRAM address space.
Fig. 7 illustrates the flow chart provided by the embodiments of the present application for powering on and restoring NVRAM.
According to an embodiment of the present application, the solid storage device of NVRAM service is provided when powering on, and NVRAM management module is logical
Process shown in Fig. 7 is crossed to prepare to provide NVRAM service.In response to powering on, NVRAM management module scans Memory slice descriptor chained list
(710), for each Memory slice descriptor, the corresponding basic bulk frame of the same Memory slice recorded in Memory slice descriptor is obtained
Address, and read data from basic bulk frame and data write-in Memory slice (720) will be read.
NVRAM management module also scans log bulk frame chained list.It is read from the log bulk frame in log bulk frame chained list
Journal entries record, is recorded with journal entries and updates Memory slice (730).For example, journal entries record indicates the address NVRAM sky
Between the address NADDR and data D that is written into, according to NVRAM address space address NADDR access fritter conversion table obtain it is corresponding
Memory slice, and the Memory slice is written into data D.
As an example, NVRAM management module obtains the head node of Memory slice descriptor chained list from NVRAM metadata, with
And the head node of log bulk frame chained list.
Optionally, the tail of the tail node of NVRAM metadata record Memory slice descriptor chained list and log bulk frame chained list
Node.And when solid storage device powers on recovery NVRAM, NVRAM management module obtains Memory slice from NVRAM metadata
The tail node of descriptor chained list and the tail node of log bulk frame chained list.
In solid storage device power down, NVRAM management module is by NVRAM metadata, fritter conversion table and/or Memory slice
NVM chip 520 is written in descriptor, restores NVRAM when powering on for next time and uses.
Additionally provide a kind of solid storage device according to an embodiment of the present application, the solid storage device include controller with
Nonvolatile memory chip, wherein controller executes any one processing method provided by the embodiments of the present application.
A kind of program being stored on readable medium is additionally provided according to an embodiment of the present application, when by solid storage device
Controller operation when so that solid storage device execute according to any one processing method provided by the embodiments of the present application.
Although the preferred embodiment of the application has been described, it is created once a person skilled in the art knows basic
Property concept, then additional changes and modifications may be made to these embodiments.So it includes excellent that the following claims are intended to be interpreted as
It selects embodiment and falls into all change and modification of the application range.Obviously, those skilled in the art can be to the application
Various modification and variations are carried out without departing from spirit and scope.If in this way, these modifications and variations of the application
Belong within the scope of the claim of this application and its equivalent technologies, then the application is also intended to encompass these modification and variations and exists
It is interior.
Claims (10)
1. a kind of non-volatile random access memory, comprising: control unit, random access storage device RAM and NVM chip, wherein
The control unit includes NVRAM management module, and the part of the random access storage device RAM and the part of NVM chip provide
NVRAM service, the NVRAM management module provide the NVRAM random access storage device serviced according to NVRAM address space access
RAM and NVM chip.
2. non-volatile random access memory according to claim 1, wherein described to provide the NVRAM NVM chip of service
Memory space be organized as multiple bulks, the memory space of random access storage device RAM for providing NVRAM service is organized as
Multiple Memory slices, the NVRAM address space are organized as multiple fritters, and the NVRAM management module refers to according to the fritter
The address of the bulk or Memory slice shown accesses the bulk or Memory slice.
3. the non-volatile random access memory stated according to claim 2, wherein the bulk includes: basic bulk and log
Bulk, for storing data, the log bulk is used to record the modification to NVRAM address space the basis bulk.
4. a kind of provide the method for non-volatile random access memory, include the following steps:
Identify the NVRAM address space of access；
Identify that the address of the NVRAM address space of access is mapped to the address or Memory slice address of basic bulk frame；
Data to be visited are obtained from basic bulk frame or Memory slice according to recognition result.
5. according to claim 4 provide the method for non-volatile random access memory, wherein further include:
According to the address for the NVRAM address space to be accessed, fritter index (ID) is generated；
(ID), which is indexed, according to fritter accesses fritter conversion table；
Fritter translation table entry is obtained according to the address for the NVRAM address space to be accessed, is identified according to fritter translation table entry
The address for the NVRAM address space to be accessed is mapped to the address or Memory slice address of basic bulk frame.
6. according to claim 5 provide the method for non-volatile random access memory, wherein provide NVRAM by fritter
Address space, multiple fritters together provide complete NVRAM address space.
7. according to claim 6 provide the method for non-volatile random access memory, wherein if fritter translation table entry
Record is Memory slice address, and data to be visited are obtained from Memory slice；If fritter translation table entry record is basic bulk
The address of frame, be data to be obtained basic bulk frame storage allocation piece, by from the basic bulk frame of data to be obtained read to
The Memory slice of the data write-in distribution of access, obtains data to be visited from the Memory slice of distribution.
8. a kind of provide the method for non-volatile random access memory, include the following steps:
Identification will be written into the NVRAM address space of data；
Identify the address for the NVRAM address space that be written into data with being mapped to address or the Memory slice of basic bulk frame
Location；
The address of NVRAM address space to be written into data is Memory slice address, then data is written to Memory slice；
The address of NVRAM address space to be written into data is the address of basic bulk frame, then generates and have recorded and to be write
The journal entries for entering the NVRAM address space address NADDR and the data D being written into of data are big by journal entries write-in log
Block frame.
9. according to claim 8 provide the method for non-volatile random access memory, wherein further include:
According to the address of the NVRAM address space of data to be written into, fritter index (ID) is generated；
(ID), which is indexed, according to fritter accesses fritter conversion table；
Fritter translation table entry is obtained according to the address of the NVRAM address space of data to be written into, according to fritter conversion table item
The address for the NVRAM address space that mesh identification will be written into data is with being mapped to address or the Memory slice of basic bulk frame
Location.
10. a kind of provide the method for non-volatile random access memory, include the following steps:
Identification will be written into the NVRAM address space of data；
According to the address of the NVRAM address space of data to be written into, the address the NVRAM sky for having recorded data to be written into is generated
Between address NADDR and data to be written D journal entries；
Log bulk frame is written into journal entries.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111177029A (en) * | 2018-11-12 | 2020-05-19 | 创义达科技股份有限公司 | System and method for managing software-defined persistent memory |
| WO2023046129A1 (en) * | 2021-09-26 | 2023-03-30 | 超聚变数字技术有限公司 | Computer device, method for processing data, and computer system |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090193184A1 (en) * | 2003-12-02 | 2009-07-30 | Super Talent Electronics Inc. | Hybrid 2-Level Mapping Tables for Hybrid Block- and Page-Mode Flash-Memory System |
| CN103377009A (en) * | 2012-04-20 | 2013-10-30 | 内存技术有限责任公司 | Managing operational state data in memory module |
| CN103810112A (en) * | 2014-01-28 | 2014-05-21 | 华中科技大学 | Nonvolatile memory system and management method thereof |
| CN103810113A (en) * | 2014-01-28 | 2014-05-21 | 华中科技大学 | Fusion memory system of nonvolatile memory and dynamic random access memory |
| CN105027090A (en) * | 2012-10-05 | 2015-11-04 | 西部数据技术公司 | Methods, devices and systems for physical-to-logical mapping in solid state drives |
| US9489296B1 (en) * | 2012-10-17 | 2016-11-08 | Western Digital Technologies, Inc. | Methods, devices and systems for hardware-based garbage collection in solid state drives |
| US20180024754A1 (en) * | 2016-07-19 | 2018-01-25 | Sap Se | Adapting in-memory database in hybrid memory systems and operating system interface |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120297147A1 (en) * | 2011-05-20 | 2012-11-22 | Nokia Corporation | Caching Operations for a Non-Volatile Memory Array |
| US9898410B2 (en) * | 2013-09-10 | 2018-02-20 | Intel Corporation | Hybrid main memory using a fine-grain level of remapping |
| CN105786400B (en) * | 2014-12-25 | 2020-01-31 | 研祥智能科技股份有限公司 | heterogeneous hybrid memory component, system and storage method |
| US9928168B2 (en) * | 2016-01-11 | 2018-03-27 | Qualcomm Incorporated | Non-volatile random access system memory with DRAM program caching |
| CN107544912B (en) * | 2016-06-29 | 2021-09-03 | 北京忆恒创源科技股份有限公司 | Log recording method, loading method and device |
-
2018
- 2018-01-31 CN CN201810094060.2A patent/CN110096452B/en active Active
- 2018-06-27 WO PCT/CN2018/093075 patent/WO2019148757A1/en active Application Filing
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090193184A1 (en) * | 2003-12-02 | 2009-07-30 | Super Talent Electronics Inc. | Hybrid 2-Level Mapping Tables for Hybrid Block- and Page-Mode Flash-Memory System |
| CN103377009A (en) * | 2012-04-20 | 2013-10-30 | 内存技术有限责任公司 | Managing operational state data in memory module |
| CN105027090A (en) * | 2012-10-05 | 2015-11-04 | 西部数据技术公司 | Methods, devices and systems for physical-to-logical mapping in solid state drives |
| US9489296B1 (en) * | 2012-10-17 | 2016-11-08 | Western Digital Technologies, Inc. | Methods, devices and systems for hardware-based garbage collection in solid state drives |
| CN103810112A (en) * | 2014-01-28 | 2014-05-21 | 华中科技大学 | Nonvolatile memory system and management method thereof |
| CN103810113A (en) * | 2014-01-28 | 2014-05-21 | 华中科技大学 | Fusion memory system of nonvolatile memory and dynamic random access memory |
| US20180024754A1 (en) * | 2016-07-19 | 2018-01-25 | Sap Se | Adapting in-memory database in hybrid memory systems and operating system interface |
Non-Patent Citations (1)
| Title |
|---|
| 何耀;蔡涛;彭长生;: "面向NVM的混合粒度文件系统", 软件导刊, no. 07, pages 17 - 21 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111177029A (en) * | 2018-11-12 | 2020-05-19 | 创义达科技股份有限公司 | System and method for managing software-defined persistent memory |
| WO2023046129A1 (en) * | 2021-09-26 | 2023-03-30 | 超聚变数字技术有限公司 | Computer device, method for processing data, and computer system |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110096452B (en) | 2024-05-28 |
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