CN111290975A

CN111290975A - Method for processing read command and pre-read command by using unified cache and storage device thereof

Info

Publication number: CN111290975A
Application number: CN201811496068.8A
Authority: CN
Inventors: 路向峰; 刘玉进; 孙清涛
Original assignee: Beijing Memblaze Technology Co Ltd
Current assignee: Beijing Memblaze Technology Co Ltd
Priority date: 2018-12-07
Filing date: 2018-12-07
Publication date: 2020-06-16

Abstract

The application provides a method for processing a read command and a pre-read command by using a unified cache and a storage device thereof, wherein the method for the storage device comprises the following steps: responding to the received read command, inquiring an FTL table through a logic address indicated by the read command, and if the FTL table is inquired, obtaining a first FTL entry recording the index of the first cache container; allocating an idle second cache unit and associating the second cache unit with the first cache container; copying data of a first cache unit associated with the first cache container to a second cache unit; the data of the second buffer unit is read out in response to the read command.

Description

Method for processing read command and pre-read command by using unified cache and storage device thereof

Technical Field

The present application relates to a storage technology, and in particular, to a method for processing a read command and a read-ahead command using a unified cache of a storage device and a storage device thereof.

Background

FIG. 1 illustrates a block diagram of a storage device. The storage device 102 is coupled to a host for providing storage capabilities to the host. The host and the storage device 102 may be coupled by various methods, including but not limited to, connecting the host and the storage device 102 by, for example, SATA (Serial Advanced Technology Attachment), SCSI (Small computer system Interface), SAS (Serial Attached SCSI), IDE (Integrated Drive Electronics), USB (Universal Serial Bus), PCIE (Peripheral Component Interconnect Express, PCIE, high speed Peripheral Component Interconnect), NVMe (NVM Express, high speed nonvolatile storage), ethernet, fibre channel, wireless communication network, etc. The host may be an information processing device, such as a personal computer, tablet, server, portable computer, network switch, router, cellular telephone, personal digital assistant, etc., capable of communicating with the storage device in the manner described above. The Memory device 102 includes an interface 103, a control section 104, one or more NVM chips 105, and a DRAM (dynamic random Access Memory) 110.

NAND flash Memory, phase change Memory, FeRAM (Ferroelectric RAM), MRAM (magnetoresistive Memory), RRAM (Resistive Random Access Memory), XPoint Memory, and the like are common NVM.

The interface 103 may be adapted to exchange data with a host by means such as SATA, IDE, USB, PCIE, NVMe, SAS, ethernet, fibre channel, etc.

The control unit 104 is used to control data transfer between the interface 103, the NVM chip 105, and the DRAM110, and also used for memory management, host logical address to flash physical address mapping, erase leveling, bad block management, and the like. The control component 104 can be implemented in various manners of software, hardware, firmware, or a combination thereof, for example, the control component 104 can be in the form of an FPGA (Field-programmable gate array), an ASIC (Application-specific integrated Circuit), or a combination thereof. The control component 104 may also include a processor or controller in which software is executed to manipulate the hardware of the control component 104 to process IO (Input/Output) commands. The control component 104 may also be coupled to the DRAM110 and may access data of the DRAM 110. FTL tables and/or cached IO command data may be stored in the DRAM.

Control section 104 includes a flash interface controller (or referred to as a media interface controller, a flash channel controller) that is coupled to NVM chip 105 and issues commands to NVM chip 105 in a manner that conforms to an interface protocol of NVM chip 105 to operate NVM chip 105 and receive command execution results output from NVM chip 105. Known NVM chip interface protocols include "Toggle", "ONFI", etc.

The memory Target (Target) is one or more Logic Units (LUNs) that share CE (Chip Enable) signals within the NAND flash package. One or more dies (Die) may be included within the NAND flash memory package. Typically, a logic cell corresponds to a single die. The logical unit may include a plurality of planes (planes). Multiple planes within a logical unit may be accessed in parallel, while multiple logical units within a NAND flash memory chip may execute commands and report status independently of each other.

Data is typically stored and read on a storage medium on a page-by-page basis. And data is erased in blocks. A block (also referred to as a physical block) contains a plurality of pages. Pages on the storage medium (referred to as physical pages) have a fixed size, e.g., 17664 bytes. Physical pages may also have other sizes.

In the storage device, mapping information from logical addresses to physical addresses is maintained by using a Flash Translation Layer (FTL). The logical addresses constitute the storage space of the solid-state storage device as perceived by upper-level software, such as an operating system. The physical address is an address for accessing a physical memory location of the solid-state memory device. Address mapping may also be implemented using an intermediate address modality in the related art. E.g. mapping the logical address to an intermediate address, which in turn is further mapped to a physical address.

A table structure storing mapping information from logical addresses to physical addresses is called an FTL table. FTL tables are important metadata in solid state storage devices. Usually, the data entry of the FTL table records the address mapping relationship in the unit of data page in the solid-state storage device.

The FTL of some memory devices is provided by a host to which the memory device is coupled, the FTL table is stored by a memory of the host, and the FTL is provided by a CPU of the host executing software. Still other storage management devices disposed between hosts and storage devices provide FTLs.

And a cache is provided for the storage device to improve the performance of the storage device. Distributed caching for solid state storage is provided, for example, in chinese patent applications 201710219077.1, 201710219096.4 and 201710219112. X. Unified caching for storage devices is provided in chinese patent applications 2018112036939, 2018111542948, 2018112036905 and 2018111541907. The cache may also be provided by the host or by the storage management device.

Disclosure of Invention

The address mapping and caching method and device aim at improving the FTL, and address mapping and caching of the storage device are managed by the FTL in a unified mode, so that the performance of the storage device is improved.

According to a first aspect of the present application, there is provided a method for a storage device according to the first aspect of the present application, comprising: responding to the received read command, inquiring an FTL table through a logic address indicated by the read command, and if the FTL table is inquired, obtaining a first FTL entry recording the index of the first cache container; allocating an idle second cache unit and associating the second cache unit with the first cache container; copying data of a first cache unit associated with the first cache container to a second cache unit; the data of the second buffer unit is read out in response to the read command.

The first method for a storage device according to the first aspect of the present application, wherein in response to associating the second cache unit with the first cache container, a reference count indicating a number of cache units associated with the first cache container is incremented.

The first or second method for a storage device according to the first aspect of the present application, wherein the association of the second cache unit with the first cache container is revoked in response to reading out data of the second cache unit.

The third method for a storage device according to the first aspect of the present application, wherein in response to revoking the association of the second cache unit with the first cache container, the reference count indicating the number of associated cache units of the first cache container is decremented.

One of the first to fourth methods for a storage device according to the first aspect of the present application, wherein in response to revoking the association relationship of the second cache unit with the first cache container, the data of the first cache unit associated with the first cache container is data read from the NVM data frame address by a read-ahead command.

The fifth method for a storage device according to the first aspect of the present application, further includes querying an FTL table by a logical address indicated by the read-ahead command, and obtaining a second FTL entry recording a second NVM data frame address; allocating an idle third cache unit, and storing the data read from the second NVM data frame address in the third cache unit; allocating an idle second cache container and associating the third cache unit with the second cache container; and updating a second FTL entry recording the NVM data frame address in the FTL table by using the third cache container index.

The sixth method for a storage device according to the first aspect of the present application, wherein the generated read-ahead data message indicating that the third cache unit is associated with the second cache container is added to the read-ahead queue in response to updating the second FTL entry.

A seventh method for a storage device according to the first aspect of the present application, further comprising: responding to a second FTL entry recording a second cache container index obtained by querying the FTL table according to the received read command, allocating an idle fourth cache unit, and associating the fourth cache unit with the second cache container; copying data of a third cache unit associated with the second cache container to a fourth cache unit; and reading out the data of the fourth cache unit in response to the read command.

The eighth method for a storage device according to the first aspect of the present application, wherein the third cache unit that holds the data indicated by the read-ahead command is released under a specified condition.

A ninth method for a storage device according to the first aspect of the present application, wherein in response to releasing the third storage unit, the reference count indicating the number of cache units associated with the second cache container is decremented.

The tenth method for a storage device according to the first aspect of the present application, wherein the second cache container is released in response to a reference count of the second cache container being 0.

The eleventh method for a storage device according to the first aspect of the present application, wherein in response to releasing the second cache container, updating the second FTL entry recording the second cache container index with the NVM data frame address of the second cache container record.

One of the sixth to twelfth methods for a storage device according to the first aspect of the present application, wherein the read-ahead command is a read command internally generated by the control section.

One of the first to thirteenth methods for a storage device according to the first aspect of the present application, wherein in response to receiving a read command, the FTL table is queried by a logical address indicated by the read command, and if the FTL table is queried, a third FTL entry recording an NVM data frame address is obtained; allocating a free fifth cache unit and storing the data read out according to the NVM data frame address recorded by the third FTL entry in the fifth cache unit; and reading out the data of the fifth cache unit in response to the read command.

A fourteenth method for a storage device according to the first aspect of the present application, wherein a third cache container is allocated and a fifth cache unit is associated with the third cache container; and updating a third FTL entry recording the NVM data frame address in the FTL table by using the index of the third cache container.

The fifteenth method for a memory device according to the first aspect of the present application, wherein the NVM data frame addresses are recorded in a third cache container, and in response to the fifth cache unit and the third cache container being released, a third FTL entry in the FTL table that records an index of the third cache container is updated with the NVM data frame addresses recorded in the third cache container.

One of the methods for a storage device according to the first to sixteenth aspects of the present application, wherein in response to reading out all data of the second buffer unit or the fifth buffer unit, a message indicating that the read command is complete is sent to the host.

The seventeenth method for a memory device according to the first aspect of the present application, wherein the second cache unit or the fifth cache unit is released in response to completion of the read command processing.

One of the methods for a storage device according to the first to eighteenth aspects of the present application, further includes: in response to the data indicated by the write command being written into a sixth cache unit of the cache, adding an eviction message to the tail of the eviction queue indicating that the sixth cache unit is associated with a sixth cache container of the cache; and writing the data of the seventh cache unit into a seventh data frame of the NVM chip according to the eviction message of the head of the eviction queue, and updating a seventh entry recording an index of a seventh cache container in the FTL table by using the address of the seventh data frame, wherein the eviction message of the head of the eviction queue indicates that the seventh cache unit is associated with the seventh cache container.

The nineteenth method for a storage device according to the first aspect of the present application further includes checking whether an association relationship between the seventh cache unit and the seventh cache container recorded in the eviction message that evicts the head of the queue is valid, if so, writing data of the seventh cache unit into a seventh data frame of the NVM chip, and updating a seventh entry in the FTL table that records an index of the seventh cache container with an address of the seventh data frame.

The nineteenth or twentieth method for a storage device according to the first aspect of the present application, wherein it is checked whether an association relationship between the seventh cache unit and the seventh cache container recorded in the eviction message of the eviction queue head is valid, and if not, the eviction message of the eviction queue head is discarded without writing the data of the seventh cache unit to the NVM chip, and the FTL table is not updated with the address of the seventh data frame.

According to one of the nineteenth to twenty-first methods for a storage device according to the first aspect of the present application, if a first write command and a second write command that are combined together are received, in response to writing of data indicated by the first write command into the eighth cache unit and writing of data indicated by the second write command into the ninth cache unit, a combined eviction message is added to the eviction queue; the combined eviction message indicates that the eighth cache unit is associated with an eighth cache container and indicates that the ninth cache unit is associated with a ninth cache container.

A twentieth method for a storage device according to the first aspect of the present application, further comprising: writing data of a tenth cache unit to a fourth data frame of the NVM chip and writing data of an eleventh cache unit to a fifth data frame of the NVM chip according to a combined eviction message obtained from the eviction queue, wherein the combined eviction message indicates that the tenth cache unit is associated with the tenth cache container and indicates that the eleventh cache unit is associated with the eleventh cache container, and wherein the fourth data frame and the fifth data frame have consecutive physical addresses.

A twenty-third method for a storage device according to the first aspect of the present application, further comprising: and updating an eighth entry in the FTL table, in which an index of the tenth cache container is recorded, with the address of the fourth data frame, and updating a ninth entry in the FTL table, in which an index of the eleventh cache container is recorded, with the address of the fifth data frame.

A twenty-fourth method for a storage device according to the first aspect of the present application, further comprising checking whether an association relationship between a tenth cache unit and a tenth cache container and an association relationship between an eleventh cache unit and an eleventh cache container recorded in a combined eviction message acquired from an eviction queue are valid; and if the association relation between the tenth cache unit and the tenth cache container and the association relation between the eleventh cache unit and the eleventh cache container recorded by the combined elimination message acquired from the elimination queue are both valid, writing the data of the tenth cache unit into the tenth data frame of the NVM chip, and writing the data of the eleventh cache unit into the eleventh data frame of the NVM chip.

According to a twenty-fifth method for a storage device in the first aspect of the present application, if one of the association relationship between the tenth cache unit and the tenth cache container and the association relationship between the eleventh cache unit and the eleventh cache container recorded in the combined eviction message obtained from the eviction queue is invalid, data in the cache unit with the valid association relationship is written into the NVM chip.

According to a twenty-fifth method for a storage device of the first aspect of the present application, if an association relationship between a tenth cache unit and a tenth cache container and an association relationship between an eleventh cache unit and an eleventh cache container recorded in a combined eviction message obtained from an eviction queue are both invalid, the eviction message is discarded without writing data of the tenth cache unit into an NVM chip or writing data of the eleventh cache unit into the NVM chip.

According to a second aspect of the present application, there is provided a first information processing apparatus according to the second aspect of the present application, comprising a memory, a processor, and a program stored on the memory and executable on the processor, the processor implementing one of the above-described methods for a storage apparatus when executing the program.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present invention, and other drawings can be obtained by those skilled in the art according to the drawings.

FIG. 1 illustrates a block diagram of a solid-state storage device;

FIG. 2 is a schematic diagram of FTL managed memory according to an embodiment of the present application;

FIG. 3 is a schematic diagram of a logical address (LBA) space of an embodiment of the present application;

FIG. 4 illustrates an FTL table in accordance with an embodiment of the present application;

FIG. 5 is a diagram illustrating an embodiment of an FTL providing cache;

FIG. 6A illustrates a flow chart for writing data to a storage device according to an embodiment of the present application;

FIG. 6B illustrates a flow diagram for writing data to a storage device according to yet another embodiment of the present application;

FIG. 6C illustrates a flow chart for reading data from a memory device according to another embodiment of the present application;

FIG. 7 is a diagram illustrating a cache eviction technique according to an embodiment of the application;

FIGS. 8A-8D illustrate a schematic diagram of processing a write command according to an embodiment of the present application;

FIGS. 9A-9E illustrate a schematic diagram of processing a write command according to yet another embodiment of the present application;

FIG. 10 is a diagram illustrating a cache eviction technique according to another embodiment of the application;

11A-11C illustrate schematic diagrams of read commands according to yet another embodiment of the present application;

FIGS. 12A-12D illustrate a read-ahead command and a subsequent read command in accordance with yet another embodiment of the present application;

FIGS. 13A-13E illustrate a schematic diagram of processing a write command according to yet another embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application are clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some, but not all, embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

Fig. 2 is a schematic diagram of FTL managed memory space according to an embodiment of the present application.

According to an embodiment of the present application, the control component 204 of the storage device 102 provides an FTL. The storage device provides the host with logical address (referred to as LBA) space. The host accesses the storage device using the logical address. The FTL maps logical addresses provided by the host to physical addresses.

According to an embodiment of the present application, the FTL maps the physical address, partly the physical address accessing the NVM chip 105 and partly the physical address accessing the DRAM 110. Thus, referring to FIG. 2, portions of the NVM chips 105 and the DRAM110 provide memory space 200 managed by the FTL.

Alternatively, other types of memory, such as SRAM, are used in addition to DRAM110 to provide storage space managed by the FTL.

It is to be appreciated that the FTL according to yet another embodiment of the present application is provided by a host coupled to a storage device or a storage management apparatus disposed between the host and the storage device.

The FTL is implemented by software, firmware, for example, running in the CPU of the control component 204 and/or hardware as part of an ASIC.

Fig. 3 is a schematic diagram of a logical address (LBA) space according to an embodiment of the present application. By way of example, the logical address space is a continuous address space. The FTL maintains a logical address space.

The direction from top to bottom in fig. 3 is the direction in which the logical address space is incremented. The logical address space includes a plurality of areas having the same size, each area being called a tile. Each entry of the FTL table, called FTL entry, records mapping of small blocks of logical address space to physical addresses. A plurality of entries of the FTL table are shown in fig. 3, including FTL entry 0, FTL entry 1 … … FTL entry 5. For example, the size of the logical address space corresponding to each FTL entry may be, for example, 512 bytes, 1KB, or 4 KB. FTL entries are indexed according to the address of the logical address space. For example, the quotient obtained by dividing the address of the logical address space by the size of the logical address space corresponding to the FTL entry is the index of the FTL entry.

Fig. 4 shows FTL tables of embodiments of the present application.

The FTL table includes a plurality of FTL entries, each FTL entry corresponding to one of the small blocks, and the value of FTL entry records NVM data frame address or cache container index providing storage space for the small block. Optionally, from the value of the FTL entry, it is identified whether the value indicates the NVM data frame address or the cache container index. For example, FTL entry values greater than a threshold are mapped to NVM data frame addresses, while FTL entry values not greater than a threshold are mapped to cache container indices. As yet another example, a flag bit is recorded in the FTL entry to indicate whether the value of the FTL entry indicates the NVM data frame address or the cache container index.

The FTL table is stored in, for example, DRAM110 (see also fig. 2) or SRAM. And the FTL calculates the index of the corresponding FTL entry according to the accessed logical address, and obtains the NVM data frame or the cache container which provides the storage space for the small block from the FTL entry.

The NVM data frame address is, for example, a physical address for accessing a physical page of the NVM chip, a physical address for accessing multiple combined physical pages of the NVM chip (a combined physical page is, for example, a physical page with the same physical page number on multiple planes (planes) of the same Logical Unit (LUN)), a physical address for accessing a portion of data units within a physical page of the NVM chip. The cache container index is, for example, an address of a cache location in the DRAM or an address of a descriptor of the cache location. A cache unit is a segment of storage space in, for example, DRAM or SRAM. The buffer unit descriptor is used for describing the buffer unit. The buffer container is used for recording buffer unit descriptors.

Fig. 5 is a schematic diagram illustrating an FTL providing cache according to an embodiment of the present application. By way of example, the FTL maps the logical address space to portions of the one or more NVM chips 105 (denoted as NVM chips 510) and DRAM110 (denoted as unified cache 520).

The memory space of NVM chip 510 includes multiple physical blocks. The memory space of NVM chip 510 is organized into NVM data frames (see block 512). The large block 512 includes a plurality of NVM data frames. The size of the NVM data frame is the same as the size of the small block, so that data stored in the logical address space corresponding to one small block can be recorded in one NVM data frame.

With continued reference to FIG. 5, the storage space of the unified cache 520 is organized as cache units. The cache unit is, for example, a segment of the storage space of the unified cache 520. The size of the cache unit is the same as that of the small blocks, so that data stored in a logical address space corresponding to one small block can be recorded in one cache unit.

Referring back to fig. 4, the index of the cache container of the value record of the FTL entry indicates the cache container. The cache unit associated with the cache container may be accessed according to the cache container.

The cache container describes one or more cache elements associated therewith. The cache molecule may be assigned to the cache container or have a specified association with the cache container. For example, the cache container records cache unit descriptors associated with one or more cache units of the cache container, and the cache unit descriptors record addresses of the cache units and working states of the cache units.

With continued reference to fig. 5, the values of FTL entry 0, FTL entry 2, FTL entry 3 and FTL entry 4 indicate NVM data frame addresses located in NVM chip 510, and the values of FTL entry 1 and FTL entry 5 indicate indexes of cache containers located in unified cache 520. The FTL thus obtains FTL entries from the logical addresses and provides physical addresses providing storage space for small blocks of logical address space according to the values of the FTL entries.

FIG. 6A shows a flow chart of writing data to a storage device according to an embodiment of the application.

The storage device obtains a write command provided by the host, the write command indicating a logical address (610). And the control part of the storage device inquires the FTL table (612) according to the logical address and acquires the physical address corresponding to the logical address.

Optionally, the write command indicates a plurality of small blocks of the logical address space, and accordingly, the FTL table is queried according to the logical address of each small block to obtain the corresponding physical address. For clarity, embodiments according to the present application are described in one or more of the following examples, taking a write command to access a single tile as an example.

It is identified whether the resulting physical address corresponding to the logical address indicates a cache container index (614). If the physical address of the logical address accessed by the write command provided by the FTL is the cache container index, the cache unit of the corresponding cache container is accessed by using the cache container index to carry the data to be written by the write command (616). Optionally, after the data to be written by the write command is written into the cache unit, the host that issued the write command indicates that the write command processing is completed.

If the physical address provided by the FTL corresponding to the logical address accessed by the write command is not a buffer container index (614) (e.g., is an NVM data frame address, or other content), a new buffer container is allocated for the logical address (618), and the data to be written by the write command is written into the buffer unit of the newly allocated buffer container (620). The index of the newly allocated cache container is also recorded in the FTL entry corresponding to the logical address (622).

According to the embodiment of the present application, optionally, data stored in the cache unit of the cache container indicated by one or more FTL entries is written to the NVM chip when needed or periodically. And in response to the data stored in the cache unit being written into the NVM chip, replacing the cache container index in the FTL entry with the NVM data frame address of the NVM chip. Thus, the FTL table entries are always recorded with the cache container index until the cache container index recorded in the FTL table entries is modified to indicate the physical address of the data unit of the NVM chip, which means that during this time, if a read command or a write command is received to access these FTL table entries, a hit will be made to the unified cache and the cache unit recorded with the cache container index will respond to the read command or the write command.

FIG. 6B illustrates a flow diagram for writing data to a storage device according to yet another embodiment of the present application.

The storage device retrieves a write command provided by the host, the write command indicating a logical address (630). And the control component of the storage device inquires an FTL (flash translation layer) table (632) according to the logical address and acquires the physical address corresponding to the logical address.

It is identified whether the resulting physical address corresponding to the logical address indicates a cache container index (634). If the physical address of the logical address accessed by the write command provided by the FTL is the cache container index, it is further identified whether the cache unit of the cache container corresponding to the cache container index is being used (636). The buffer unit is being used, for example, data is being written to the buffer unit, data is being read from the buffer unit, or the control section is writing data of the buffer unit to the NVM chip according to other write commands. If the cache unit is not currently in use, the cache unit is used to carry data to be written by the write command (638). If the cache unit is currently being used, a new cache unit is allocated for the cache container (640), and the new cache unit is used to carry data to be written by the write command (642).

If the physical address of the logical address accessed by the write command provided by the FTL is not the buffer container index (634) (e.g., is an NVM data frame address, or other content), a new buffer container is allocated for the logical address (644), and the data to be written by the write command is written into the buffer location of the newly allocated buffer container (646). An index to the newly allocated cache container is also recorded in the FTL entry corresponding to the logical address (648).

FIG. 6C illustrates a flow diagram for reading data from a memory device according to another embodiment of the present application.

The storage device retrieves a read command provided by the host, the read command indicating a logical address (650). And the control component of the storage device inquires the FTL table (652) according to the logical address and acquires the physical address corresponding to the logical address.

It is identified whether the resulting physical address corresponding to the logical address indicates a cache container index, an NVM data frame address, or another type of physical address (654). If the physical address of the logical address accessed by the read command provided by the FTL is the cache container index, the cache unit of the cache container is accessed, and data is obtained from the cache unit as a response to the read command (656). If the physical address provided by the FTL is an NVM data frame address, then a read command is sent to the NVM chip to read out the data (658). Alternatively, other types of addresses are recorded in the FTL entry, for example, indicating that the read logical address has not been written with data, indicating to the host that the read command is in error, or responding to the read command with a specified value (e.g., all 0 s).

Fig. 7 is a schematic diagram illustrating a cache eviction scheme according to an embodiment of the present application.

The control part of the storage apparatus (see also fig. 1) includes a host interface 760, a command processing unit 765, and a media interface 770. The host interface 760, the command processing unit 765, and the media interface 770 may each be implemented by a CPU, dedicated hardware, or a combination thereof.

The host interface 760 receives commands to access the storage device. Command processing unit 765 retrieves pending commands from host interface 760 and instructs media interface 770 to generate one or more commands to operate NVM chip 740 according to the addresses to be accessed by the commands. By way of example, command processing unit 765 accesses FTL table 750 with the logical address indicated by the retrieved command to obtain the physical address corresponding to the logical address, and accesses NVM chip 740 with the physical address.

Those skilled in the art will appreciate that commands received by the host interface 760 may access a logical address space corresponding to one or more FTL entries. And the command processing unit 765 may morph the command received from the host interface 760 (e.g., split the command according to the logical address space size corresponding to the FTL entry) and process the morphed command. For purposes of clarity, embodiments according to the present application are described with the example of an IO command received by host interface 760 accessing a single FTL entry.

Entries of FTL table 750 record NVM data frame addresses or cache container indices. In fig. 7, FTL entry 1 and FTL entry 5 record the cache container index, and the other FTL entries record the NVM data frame address.

The unified cache 710 includes a plurality of cache containers. The cache container index of the FTL entry record of FTL table 750 indicates the cache container of unified cache 710. Referring to fig. 7, the cache container index of FTL entry 1 record indicates the cache container 712 of the unified cache 710, and the cache container index of FTL entry 5 indicates the cache container 716. Cache container 714 is not indexed by any FTL entries and is an unused free cache container.

The unified cache 710 also includes a plurality of cache units. The cache container is associated with one or more cache units. For example, cache container 712 is associated with cache unit 722, cache container 716 is associated with cache unit 726 and cache unit 727, and cache unit 724 is not associated with any cache container and is an unused free cache unit.

According to an embodiment of the present application, an eviction queue 780 is also included. Retire queue 780 holds retired messages for unified cache 710. By way of example, in response to cache unit 727 carrying data to be written to the storage device as indicated by the write command, a retirement message 787 is added to the tail of retirement queue 780. Eviction message 787 indicates that data carried by buffer cell 727 is to be written to NVM chip 740. Optionally, the eviction message 787 also indicates that a cache unit 727 is associated with the cache container 716.

Eviction is the process of writing data in the cache units of the unified cache 710 to the NVM chips. In the elimination process, an NVM data frame address for the NVM chip is also allocated to the data in the buffer unit, and the data in the buffer unit is written into the NVM chip according to the NVM data frame address. The assigned NVM data frame address is also recorded in an entry of the FTL table. So that after the eviction process is complete, the FTL entry is changed from the record cache container address to the record NVM data frame address.

And adding elimination messages to the tail of elimination queue 780, taking out the elimination messages from the head of elimination queue 780, and writing the data recorded by the cache unit into the NVM chip according to the elimination messages.

It takes a period of time for an eviction message to change from the tail to the head in the eviction queue 780, during which time the data of the cache unit indicated by the eviction message may become invalid (for example, because the cache container corresponding to the cache unit is updated by writing new data to the logical address), and for an eviction message fetched from the head of the eviction queue 780, the fetched eviction message is checked by the checking unit 790. The checking unit 790 checks whether the cache unit indicated in the eviction message is currently associated with one of the cache containers, or whether the cache unit currently recorded in the cache container indicated in the eviction message is the same as the cache unit indicated in the eviction message. If the cache element indicated by the eviction message is not currently recorded or associated with any cache container, checking unit 790 discards the eviction message and instructs unified cache 710 to release the cache element indicated by the eviction message. If the cache unit indicated by the eviction message is currently recorded or associated with a cache container, check unit 790 instructs media interface 770 to write the data of the cache unit indicated by the eviction message to the NVM chip (e.g., to write to NVM data frame 742). And also updates the FTL entry (e.g., FTL entry 2) indexing the cache container corresponding to the cache unit with the NVM data frame address of NVM data frame 742. And the cache container is also released.

According to an embodiment of the present application, the operations of unified cache 710 adding evicted messages to eviction queue 780 are processed in parallel or concurrently with the operations of checking unit 790 fetching evicted messages from the eviction queue. And the ratio of the number of add-out messages to retire queue 780 to the number of retired messages removed from retire queue 780 may be set. For example, the ratio of the number of added obsolete messages to the number of taken obsolete messages is set equal to 1, so that the number of obsolete messages contained in the obsolete queues is substantially stable. Optionally, the ratio is further adjusted according to the number of obsolete messages contained in the obsolete queue, and is decreased if the obsolete messages in the obsolete queue are too large or are accelerated too fast, and is increased otherwise. Still alternatively, only add obsolete messages to the obsolete queue and not remove obsolete messages for a period of time to accommodate a certain number of obsolete messages in the obsolete queue and to keep the obsolete messages in the obsolete queue at a certain number, e.g., each time a obsolete message is added to the obsolete queue, a obsolete message is correspondingly removed from the obsolete queue.

By the cache elimination scheme of the embodiment of the application, the elimination operation of the unified cache 710 is continuously performed, but not performed according to the use condition of the cache container or the cache unit of the unified cache 710, so that the elimination queue 780 always has space to accommodate the elimination message, and the unified cache 710 can always provide the available cache container and cache unit to respond to the write command under the load of the specified IO command. When the command processing unit 765 processes the write commands, all the write commands (regardless of whether the FTL entries corresponding to the accessed logical addresses record the cache container index) are processed by the unified cache 710, so that the processing delay of the write commands is reduced, and the processing delays of all or most of the write commands are substantially consistent, thereby avoiding the jitter of the processing delays of multiple write commands.

Further, according to embodiments of the present application, the number of cache containers is limited to meet hardware resource limitations of the control unit of the storage device, and the cache units are provided by, for example, a memory external to the control unit, and the number of cache units is greater than the number of cache containers, thereby further enabling the unified cache to respond to more write commands than the number of cache capacities at the same time.

Still further, the write command processing capability of the media interface 770 is known, and the write command bandwidth of the unified cache 710 depends on the processing capability of the media interface 770, so that the command processing unit 765 receives the write command according to the processing capability, an immediate response of the unified cache 710 can be always obtained, the processing delay of all write commands by the storage device is basically consistent, the fluctuation of the processing delay is reduced, and the service quality is improved.

FIGS. 8A-8D illustrate a schematic diagram of processing a write command according to an embodiment of the present application.

Referring to fig. 8A, the command processing unit 865 receives a write command from the host interface 860. The command processing unit 865 accesses the FTL table 850 according to the logical address indicated by the write command. By way of example, the logical address of the write command indexes FTL entry 2. FTL entry 2 records the NVM data frame address, meaning that the write command misses any cache container of the unified cache 810. Cache container 812 and cache container 814 of unified cache 810 are being used, which are associated with cache unit 822 and cache unit 824, respectively.

Referring to FIG. 8B, in response to a write command miss on any cache container of the unified cache 810, a free cache container 816 is allocated and a free cache unit 826 is allocated. The cache container 816 is associated with the cache unit 826, for example, an index of the cache unit 826 is recorded in the cache container 816. Data to be written to the storage device by the write command is moved to the cache unit 826 through the host interface 860, and the NVM data frame address recorded by FTL entry 2 is updated to the cache container index indicating the cache container 816. And optionally, cache container 816 also records its reference count as 1 to indicate the number of its associated cache units. To this end, the completion of the write command processing is indicated to the host.

And, an eviction message 887 is also added to the eviction queue 880, the added eviction message 887 indicating that cache element 826 is associated with its associated cache container 816.

With continued reference to fig. 8C, after a period of time, a retire message 887 becomes the head of the retire queue. The checking unit 890 takes out the elimination message 887 from the head of the elimination queue 880, and checks whether the association relationship of the cache container 816 and the cache unit 826 recorded by the elimination message 887 is still valid. By way of example, the checking unit 890 accesses the cache container 816 and identifies that the cache unit currently recorded by the cache container 816 is still the cache unit 826, thereby identifying that the association relationship between the cache container 816 and the cache unit 826 recorded by the eviction message 887 is still valid. Accordingly, check unit 890 instructs medium interface 870 to write the data recorded in cache unit 826 to NVM chip 840. By way of example, data frames 842 of NVM chip 840 are allocated for data of buffer unit 826.

With continued reference to fig. 8D, in response to the data of the buffer unit 826 being written to the NVM data frame 842, FTL entry 2 is updated, and the NVM data frame address of the NVM data frame 842 is recorded in FTL entry 2. And freeing the cache unit 826 so that the cache unit 826 may be allocated to other write commands or other cache containers. And in response to the cache unit 826 being released, the reference count of the cache container 816 originally associated with the cache unit 826 is decremented, resulting in a new reference count of 0. Since FTL entry 2 no longer indexes cache container 816, the reference count of cache container 816 is 0, and cache container 816 is released. The freed cache container 816 may be allocated to other write commands or other cache containers.

FIGS. 9A-9E illustrate a schematic diagram of processing a write command according to yet another embodiment of the present application.

Referring to fig. 9A, the command processing unit 965 receives a write command from the host interface 960. The command processing unit 965 accesses the FTL table 950 according to the logical address indicated by the write command. By way of example, the logical address of the write command indexes FTL entry 1. FTL entry 1 records the cache container index, meaning that the write command hits cache container 912 of unified cache 910. The cache container 912 of the unified cache 910 is associated with a cache unit 922. Eviction message 982 for cache element 922 is already in eviction queue 980. The eviction message 982 indicates that cache unit 922 is associated with cache container 912. And the reference count of the cache container 912 is 1, and the cache unit 922 references the cache container 912.

Referring to fig. 9B, in response to a write command hitting the cache container 912 of the unified cache 910, a free cache unit 926 is allocated for the cache container 912. The cache container 912 is associated with the cache unit 926, for example, an index of the cache unit 926 is recorded in the cache container 912. Data to be written to the storage device by the write command is moved to the cache unit 926 through the host interface 960. And incrementing the reference of cache container 912 to 2 to indicate that there are two cache locations (922 and 926). To this end, the completion of the write command processing is indicated to the host.

And, an eviction message 984 is also added to eviction queue 980, the added eviction message 984 indicating that cache element 926 is associated with its associated cache container 912. Since FTL entry 1 still records the index of the cache container 912, FTL entry 1 does not need to be updated.

According to an embodiment of the present application, in response to a write command hitting a cache container, a free cache unit (e.g., cache unit 926, see fig. 9B) is allocated to carry data to be written by the write command, while data of other cache units (e.g., cache unit 922) of the hit cache container is not updated, so that access to the other cache units is not affected and data transmission of a read command or a write command being processed by the cache unit is not interrupted.

With continued reference to fig. 9C, after a period of time, a retire message 982 becomes the head of the retire queue. The checking unit 990 takes out the elimination message 982 from the head of the elimination queue 980, and checks whether the association relationship of the cache container 912 and the cache unit 922 recorded by the elimination message 982 is still valid. In the example of fig. 9C, checking unit 990 accesses cache container 912, and identifies that the cache unit currently recorded by cache container 912 is cache unit 926 instead of cache unit 922 indicated by eviction message 982, thereby identifying that the association relationship between cache container 912 and cache unit 922 recorded by eviction message 982 has failed. Accordingly, checking unit 990 discards eviction message 982 without writing the data accommodated by cache unit 922 indicated by eviction message 982 to the NVM chip. And the checking unit 990 also releases the cache unit 922 so that the cache unit 922 can be allocated to other cache containers. Further, in response to cache location 922 being released, the cache location referencing cache container 912 is decremented, decrementing the reference count of cache container 912 to 1.

With continued reference to fig. 9D, after a period of time, the retirement message 984 becomes the head of the retirement queue 980. The checking unit 990 takes out the elimination message 984 from the head of the elimination queue 980, and checks whether the association relationship of the cache container 912 and the cache unit 926 recorded by the elimination message 984 is still valid. In the example of fig. 9D, checking unit 990 accesses cache container 912, and identifies that the cache unit currently recorded by cache container 912 is cache unit 926, thereby identifying that the association relationship between cache container 912 and cache unit 926 recorded by eviction message 982 is valid. Accordingly, the check unit 990 instructs the medium interface 970 to write the data recorded in the buffer unit 926 to the NVM chip 940. By way of example, data frame 942 of NVM chip 940 is allocated for data of buffer unit 926.

With continued reference to fig. 9E, in response to the data of the cache unit 926 being written to the NVM data frame 942, FTL entry 1 is updated, and the NVM data frame address of the NVM data frame 942 is recorded in FTL entry 1. And freeing cache molecule 926 such that cache molecule 926 may be allocated to other write commands or other cache containers. And in response to cache element 926 being released, the reference count of cache container 912 originally associated with cache element 926 is decremented, resulting in a new reference count of 0. Since FTL entry 1 no longer indexes cache container 912 and no other FTL entries refer to cache container 912, the reference count of cache container 912 is 0, thereby releasing cache container 912. The freed cache container 912 may be allocated to other write commands or other cache containers.

Fig. 10 is a diagram illustrating a cache eviction scheme according to another embodiment of the present application.

The control part of the storage apparatus (see also fig. 7) includes a host interface 760, a command processing unit 765, and a media interface 770.

The unified cache 1010 includes a plurality of cache containers (1012, 1014, and 1016). Referring to fig. 10, the cache container index recorded in FTL entry 1 indicates the cache container 1012 of the unified cache 1010, and the cache container index of FTL entry 5 indicates the cache container 1016. Cache container 1014 is not indexed by any FTL entries and is an unused free cache container.

The unified cache 1010 includes a plurality of cache units. For example, cache container 1012 is associated with cache unit 1022, cache container 1016 is associated with cache unit 1026 and cache unit 1027, and cache unit 1024 is not associated with any cache container and is an unused free cache unit.

The embodiment of FIG. 10 includes an eviction queue 1080, a read-ahead queue 1082, and a hot data queue 1084. Retire queue 1080 holds retire messages for unified cache 1010. Some cache units hold data that is hot data. Hot data is data that is likely to be re-accessed in the near future, and it is therefore desirable to retain the hot data in the unified cache 1010. In response to writing hot data to a cache unit (e.g., cache unit 1024), a retirement message for cache unit 1024 is not added to retirement queue 1080, but rather is added to hot data queue 1084, except for associating cache unit 1024 with one of the cache containers. Thus carried in hot data queue 1084 is an eviction message for hot data. Inspection unit 1090 obtains eviction messages from eviction queue 1080 and hot data queue 1084 with different policies. For example, inspection unit 1090 obtains retired messages from retire queue 1080 and hot data queue 1084, respectively, at a ratio of N:1, where N is a natural number much greater than 1. Thereby allowing hot data to be retained in the buffer unit for a longer period of time. For retired messages taken from hot data queue 1084, inspection unit 1090 processes retired messages obtained from retired queues in the same manner. Alternatively still, it is often the case that the inspection unit only obtains retired messages from retired queue 1080 and not from hot data queue 1084, and only obtains retired messages from hot data queue 1084 under specified conditions (e.g., an indication of a host being received, the storage device being powered down, or the number of retired messages within the hot data queue being greater than a threshold).

With continued reference to FIG. 10, some cache molecules hold data that is not a write command from the host, but rather a command from the control unit to read data from the NVM chip, e.g., a command from the control unit to read data generated in a prefetch operation or a garbage collection operation. The data held in these buffer units is referred to as read-ahead data. The pre-read data need not be written to the NVM chip. And thus there is no need to perform a culling process on the pre-read data. In response to writing the read-ahead data to the cache unit, a read-ahead data message is generated and added to read-ahead queue 1082. By way of example, the read-ahead data message has the same structure or content as the eviction message. Check unit 1090 does not retrieve read-ahead data messages from read-ahead queue 1082. In some cases, the cache location storing the read-ahead data is released. For example, the read-ahead data message is acquired from the read-ahead queue 1082, and the cache unit storing the read-ahead data is acquired based on the read-ahead data message and released. For example, the cache locations storing the read-ahead data are released in response to an evaluation that the read-ahead data is no longer being used, the storage device is powered down, or the like.

It will be appreciated that read-ahead queue 1082 may be implemented in other data structures, such as arrays, linked lists, stacks, etc., since messages in read-ahead queue 1082 need not be fetched in order. It will be appreciated that other data structures may be employed to store the eviction message.

Still alternatively, other numbers or kinds of queues are provided to accommodate eviction messages corresponding to cache molecules that are filled with data. The inspection unit 1090 provides different processing strategies for different queues. For example, data to be filled into a buffer unit is accompanied by a stream identifier, and a queue is selected based on the stream identifier, so that eviction messages corresponding to buffer units carrying data from different streams are added to different queues. Still optionally, one or more flows are bound to one of the queues while the other one or more flows are bound to the other queue.

FIGS. 11A-11C illustrate a read command according to yet another embodiment of the present application.

Referring to fig. 11A, the command processing unit 1165 receives a read command from the host interface 1160. The command processing unit 1165 accesses the FTL table 1150 according to the logical address indicated by the read command. By way of example, the logical address of the read command indexes FTL entry 1. FTL entry 1 records the cache container index, meaning that the read command hits cache container 1112 of unified cache 1110. The cache container 1112 of the unified cache 1110 is associated with a cache unit 1122. When the reference count value of the current cache container 1112 is 1, the cache unit 1122 references the cache container 1112.

Referring to fig. 11B, in response to a read command hitting a cache container 1112 of the unified cache 1110, although the cache unit 1122 associated with the cache container 1112 stores therein data capable of responding to the read command, according to an embodiment of the present application, the cache unit 1122 is not used to directly respond to the read command, but a free cache unit 1126 is allocated to the read command. The data of the buffer unit 1122 is copied to the buffer unit 1126. During data replication, the reference count of the cache container 1112 is 2 to indicate that both the cache unit 1122 and the cache unit 1126 reference the cache container 1112.

With continued reference to FIG. 11C, after copying the data of the cache unit 1122 to the cache unit 1126 is complete, the data of the cache unit 1126 is transmitted to the host via the host interface 1160 as a response to the read command. And the cache container 1112 is no longer associated with cache unit 1126 but is still associated with cache unit 1122, the reference count of the cache container 1112 becomes 1. In response to the data of cache unit 1126 being transmitted to the host, the completion of read command processing is indicated to the host, and cache unit 1126 is also released.

The buffer unit 1126 is used to transmit data to the host so that the response process to the read command does not affect the other processing of the buffer unit 1122. In response to a read command with cache molecule 1126, cache molecule 1122 may be eliminated or updated. And if multiple read commands hit the cache container 1112 continuously, allocating a new cache unit for each read command, and copying the data of the cache unit 1122 to the new cache unit, this process also makes the reference count of the cache container not become zero, so that the cache unit 1122 is not used, and can continuously respond to the read commands.

According to an embodiment of the present application, if the command processing unit obtains the FTL entry recorded with the NVM data frame address according to the logical address of the received read command, it means that the read command misses any cache container. And the command processing unit instructs the medium interface to read data from the NVM chip according to the NVM data frame address recorded by the FTL entry. Optionally, an available buffer location is also allocated for the read command to accommodate data read from the NVM chip. However, the allocated cache units are not associated to any cache container. The cache molecules are released in response to providing the data in the cache molecules to the host through the host interface.

According to one embodiment of the present application, if the read command misses any cache container, the media interface is instructed to read data from the NVM chip according to the NVM data frame address recorded by the FTL entry. And allocating a cache unit and an associated cache container, wherein the cache unit is used for carrying data read out from the NVM chip and providing the data in the cache unit to the host, and updating the FTL table by using the allocated cache container index. The address of the NVM data frame is recorded in the buffer container. And in response to the buffer container and the buffer unit being released, updating the FTL table again with the NVM data frame address recorded in the buffer container.

FIGS. 12A-12D illustrate a read-ahead command and a subsequent read command according to yet another embodiment of the present application.

Referring to fig. 12A, the command processing unit 1265 processes a pre-read command. The read-ahead command is not initiated by the host, but rather by the control component of the storage device itself. By way of example, command processing unit 1265 reads the logical address indicated by the command to access FTL table 1250. The logical address of the read-ahead command indexes FTL entry 2. FTL entry 2 records the NVM data frame address indicating NVM number frame 1242. Data is read from NVM chip 1240 according to the NVM data frame address recorded by FTL entry 2. Free buffer locations 1224 are allocated in the unified buffer 1210 to carry data read from the NVM data frames 1242.

Referring to fig. 12B, a free buffer container 1214 is allocated, and a buffer unit 1224 is associated with the buffer container 1214. And record the cache container index of the cache container 1214 in FTL entry 2. Optionally, a read-ahead data message is also generated and added to read-ahead queue 1282. The read ahead data message indicates that the cache unit 1224 is associated with the cache container 1214.

The read-ahead queue 1282 records the cache locations used to hold read-ahead data and the cache containers associated therewith. Cache locations that hold read-ahead data need not be evicted.

Optionally, the NVM data frame address accessed by the read-ahead command is also recorded in the buffer container 1214 used in processing the read-ahead command. In response to the cache container 1214 being released, the NVM data frame address recorded by the cache container 1214 is recorded in the FTL entry recording the index of the cache container 1214.

With continued reference to FIG. 12C, the command processing unit 1265 receives a read command from the host interface 1260. FTL table 1250 is accessed according to the logical address of the read command, resulting in FTL entry 2. Currently, FTL entry 2 records the cache container index of the cache container 1214, meaning the cache container 1214 that the read command hits. And the cache unit 1224 associated with the cache container 1214 records the data read by the read-ahead command. In response to a read command hitting the cache container 1214, a free cache location 1226 is allocated for the read command. The data of the buffer unit 1224 is copied to the buffer unit 1226. In response to the start of the data copy, the reference count of the cache container 1214 is incremented.

With continued reference to fig. 12D, after the copying of the data of the buffer unit 1224 to the buffer unit 1226 is completed, the data of the buffer unit 1226 is transmitted to the host through the host interface 1260 as a response to the read command. And decrementing the reference count for the cache container 1214.

Optionally, after a period of time, the cache unit 1224 holding the read-ahead data is released. And in response, increment the reference count of the cache container 1214. When the reference count of the cache container 1214 is 0, the cache container 1214 is released. And also updates FTL entry 2 with the NVM data frame address recorded by the cache container 1214.

Referring to fig. 13A, the command processing unit 1365 receives two write commands combined together from the host interface 1360. The command processing unit 1365 accesses the FTL table 1350 according to the logical address indicated by each of the two write commands. By way of example, the logical addresses of the two write commands index FTL entry 1 and FTL entry 2, respectively. FTL entry 1 records the cache container index of cache container 1312, meaning that the write command hits cache container 1312 of unified cache 1310. Cache container 1312 is associated with cache unit 1322. FTL entry 2 records the NVM data frame address, meaning that the further write command misses the cache container index.

Referring to FIG. 13B, in response to a write command hitting cache container 1312, cache container 1312 is allocated a free cache location 1223. Cache container 1312 is associated with cache unit 1223. Data to be written to the storage device by the write command is moved to the cache unit 1323 through the host interface 1360.

For this other write command to access FTL entry 2, the free cache unit 1326 and the free cache container index 1316 are allocated, the cache container 1316 is associated with the cache unit 1326, and data to be written to the storage device by this other write command is moved to the cache unit 1326 through the host interface 1360. The cache container index of cache container 1316 is also recorded in FTL entry 2.

And, an eviction message 1387 is also added to eviction queue 1380, the added eviction message 1387 indicating that cache element 1323 is with its associated cache container 1312, and also indicating that cache element 1326 is with its associated cache element 1316.

Referring to fig. 13B, further within eviction message queue 1380 is an eviction message 1382 indicating that cache unit 1322 is associated with its associated cache container 1312.

With continued reference to fig. 13C, after a period of time, the retirement message 1382 becomes the head of the retirement queue. The checking unit 1390 fetches the elimination message 1382 from the head of the elimination queue 1380, and checks whether the association relationship between the cache container 1312 and the cache unit 1322 recorded in the elimination message 1382 is still valid. In the example of fig. 13C, the checking unit identifies that the association between cache container 1312 and cache unit 1322 recorded by eviction message 1382 has failed. Accordingly, check unit 1390 discards eviction message 1382 without writing the data held by cache unit 1322 indicated by eviction message 1382 to the NVM chip. And the checking unit 1390 also releases the cache unit 1322.

With continued reference to fig. 13D, after a period of time, retire message 1387 becomes the head of retire queue 1380. The checking unit 1390 fetches the elimination message 1387 from the head of the elimination queue 1380, and checks whether the association relationship of the cache container 1316 and the cache unit 1326 recorded by the elimination message 1387 is still valid, and whether the association relationship of the cache container 1312 and the cache unit 1323 is still valid. In the example of fig. 13D, the checking unit 1390 identifies that the association relationship between the cache container 1316 and the cache unit 1326 and the association relationship between the cache container 1312 and the cache unit 1323 are both currently valid. Accordingly, the check unit 1390 instructs the media interface 1370 to write the data recorded in the buffer unit 1323 in the buffer unit 1326 into the NVM chip 1340. By way of example, the data of the buffer unit 1326 is allocated with the data frame 1342 of the NVM chip 1340, and the data of the buffer unit 1323 is allocated with the data frame 1344 of the NVM chip 1340, wherein the NVM data frame 1342 and the NVM data frame 1344 have consecutive addresses, and the data of the NVM data frame 1342 and the NVM data frame 1344 can be read out by using a single read command.

With continued reference to fig. 13E, in response to the data of the buffer unit 1326 being written into the NVM data frame 1342, FTL entry 1 is updated, and the NVM data frame address of the NVM data frame 1342 is recorded in FTL entry 1. And a release buffer unit 1326. And in response to the cache unit 1326 being released, the cache container 1316 originally associated with the cache unit 1326 is also released. In response to the data of the buffer unit 1323 being written into the NVM data frame 1344, FTL entry 2 is updated, and the NVM data frame address of the NVM data frame 1344 is recorded in FTL entry 2. And the release buffer unit 1323 and buffer container 1312 are also released.

The embodiment according to the application also provides a storage device which executes any one of the processing methods provided by the embodiment of the application.

Embodiments according to the present application also provide a program stored on a readable medium, which when executed by a controller of a storage device, causes the storage device to perform any one of the processing methods provided according to the embodiments of the present application.

While the preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all alterations and modifications as fall within the scope of the application. It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.

Claims

1. A method for a storage device, comprising:

responding to the received read command, inquiring an FTL table through a logic address indicated by the read command, and if the FTL table is inquired, obtaining a first FTL entry recording the index of the first cache container;

allocating an idle second cache unit and associating the second cache unit with the first cache container;

copying data of a first cache unit associated with the first cache container to a second cache unit;

the data of the second buffer unit is read out in response to the read command.

2. The method for a memory device of claim 1, further comprising, in response to receiving a read-ahead command, querying the FTL table with the logical address indicated by the read-ahead command to obtain a second FTL entry recording the second NVM data frame address;

allocating an idle third cache unit, and storing the data read from the second NVM data frame address in the third cache unit;

allocating an idle second cache container and associating the third cache unit with the second cache container;

and updating a second FTL entry recording the NVM data frame address in the FTL table by using the third cache container index.

3. The method for the storage device according to claim 1 or 2, wherein in response to receiving the read command, querying the FTL table by the logical address indicated by the read command, if querying the FTL table, obtaining a third FTL entry recording the NVM data frame address;

allocating a free fifth cache unit and storing the data read out according to the NVM data frame address recorded by the third FTL entry in the fifth cache unit;

and reading out the data of the fifth cache unit in response to the read command.

4. The method for the storage device of claim 3, wherein a third cache container is allocated and a fifth cache unit is associated with the third cache container;

and updating a third FTL entry recording the NVM data frame address in the FTL table by using the index of the third cache container.

5. The method for the storage device of claim 4, wherein the NVM data frame address is recorded in a third cache container, and in response to the fifth cache unit and the third cache container being released, a third FTL entry in the FTL table that records an index of the third cache container is updated with the NVM data frame address recorded in the third cache container.

6. The method for a storage device of claim 1 or 2, further comprising:

in response to the data indicated by the write command being written into a sixth cache unit of the cache, adding an eviction message to the tail of the eviction queue indicating that the sixth cache unit is associated with a sixth cache container of the cache;

and writing the data of the seventh cache unit into a seventh data frame of the NVM chip according to the eviction message of the head of the eviction queue, and updating a seventh entry recording an index of a seventh cache container in the FTL table by using the address of the seventh data frame, wherein the eviction message of the head of the eviction queue indicates that the seventh cache unit is associated with the seventh cache container.

7. The method for a storage device of claim 6, further comprising:

and checking whether the association relation between the seventh cache unit and the seventh cache container recorded by the elimination message of the elimination queue head is valid, if so, writing the data of the seventh cache unit into a seventh data frame of the NVM chip, and updating a seventh entry recording the index of the seventh cache container in the FTL table by using the address of the seventh data frame.

8. The method for the storage device of claim 6, wherein if the first write command and the second write command combined together are received, adding a combined eviction message to the eviction queue in response to the data indicated by the first write command being written to the eighth cache location and the data indicated by the second write command being written to the ninth cache location;

the combined eviction message indicates that the eighth cache unit is associated with an eighth cache container and indicates that the ninth cache unit is associated with a ninth cache container.

9. The method for a storage device of claim 8, further comprising:

writing data of a tenth cache unit to a fourth data frame of the NVM chip and writing data of an eleventh cache unit to a fifth data frame of the NVM chip according to a combined eviction message obtained from the eviction queue, wherein the combined eviction message indicates that the tenth cache unit is associated with the tenth cache container and indicates that the eleventh cache unit is associated with the eleventh cache container, and wherein the fourth data frame and the fifth data frame have consecutive physical addresses.

10. An information processing apparatus comprising a memory, a processor and a program stored on the memory and executable on the processor, characterized in that the processor implements the method for a storage device of one of the preceding claims 1 to 9 when executing the program.