CN109960667B - Address translation method and device for large-capacity solid-state storage device - Google Patents
Address translation method and device for large-capacity solid-state storage device Download PDFInfo
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Abstract
The application provides an address translation method and device for a large-capacity solid-state storage device. The provided address translation method for read operation comprises the following steps: acquiring a logic address accessed by a read operation; and if the logical address hits in the cached conversion page, acquiring a physical address corresponding to the logical address from the cached conversion page.
Description
Technical Field
The present application relates to solid state storage devices, and in particular, to address translation methods and apparatus for use with mass solid state storage devices.
Background
FIG. 1 illustrates a block diagram of a solid state storage device. The solid state storage device 102 is coupled to a host for providing storage capability for the host. The host and solid state storage device 102 may be coupled by a variety of means including, but not limited to, connecting the host to the solid state storage device 102 via, for example, SATA (Serial Advanced Technology Attachment ), SCSI (Small Computer System Interface, small computer system interface), SAS (Serial Attached SCSI ), IDE (Integrated Drive Electronics, integrated drive electronics), USB (Universal Serial Bus ), PCIE (Peripheral Component Interconnect Express, PCIE, peripheral component interconnect Express), NVMe (NVM Express), ethernet, fibre channel, wireless communications network, and the like. The host may be an information processing device capable of communicating with the storage device in the manner described above, such as a personal computer, tablet, server, portable computer, network switch, router, cellular telephone, personal digital assistant, or the like. The memory device 102 includes an interface 103, a control unit 104, one or more NVM chips 105, and a DRAM (Dynamic Random Access Memory ) 110.
NAND flash memory, phase change memory, feRAM (Ferroelectric RAM, ferroelectric memory), MRAM (Magnetic Random Access Memory, magnetoresistive memory), RRAM (Resistive Random Access Memory, resistive memory), and the like are common NVM.
The interface 103 may be adapted to exchange data with a host by way of, for example, SATA, IDE, USB, PCIE, NVMe, SAS, ethernet, fibre channel, etc.
The control unit 104 is used to control data transfer among the interface 103, NVM chip 105, and DRAM 110, and also for memory management, host logical address to flash physical address mapping, erase balancing, bad block management, etc. The control component 104 can be implemented in a variety of ways, such as software, hardware, firmware, or a combination thereof, for example, the control component 104 can be in the form of an FPGA (Field-programmable gate array, field programmable gate array), an ASIC (Application Specific Integrated Circuit, application-specific integrated circuit), or a combination thereof. The control component 104 may also include a processor or controller in which software is executed to manipulate the hardware of the control component 104 to process IO (Input/Output) commands. Control unit 104 may also be coupled to DRAM 110 and may access data of DRAM 110. FTL tables and/or cached data of IO commands may be stored in the DRAM.
The control section 104 includes a flash interface controller (or referred to as a media interface controller, a flash channel controller) that is coupled to the NVM chip 105 and issues commands to the NVM chip 105 in a manner conforming to an interface protocol of the NVM chip 105 to operate the NVM chip 105 and receive a command execution result output from the NVM chip 105. Known NVM chip interface protocols include "Toggle", "ONFI", and the like.
The memory Target (Target) is one or more Logical Units (LUNs) of shared CE (Chip Enable) signals within the NAND flash package. One or more dies (Die) may be included within the NAND flash package. Typically, the logic unit corresponds to a single die. The logic cell may include multiple planes (planes). Multiple planes within a logic unit may be accessed in parallel, while multiple logic units within a NAND flash memory chip may execute commands and report status independently of each other.
Data is typically stored and read on a storage medium on a page basis. While data is erased in blocks. A block (also called a physical block) contains a plurality of pages. A block contains a plurality of pages. Pages on a storage medium (referred to as physical pages) have a fixed size, e.g., 17664 bytes. The physical pages may also have other sizes.
In solid state storage devices, FTL (Flash Translation Layer ) is utilized to maintain mapping information from logical addresses to physical addresses. The logical addresses constitute the storage space of the solid state storage device as perceived by upper level software such as the operating system. The physical address is an address for accessing a physical storage unit of the solid state storage device. Address mapping may also be implemented in the related art using an intermediate address modality. For example, logical addresses are mapped to intermediate addresses, which in turn are further mapped to physical addresses.
The table structure storing mapping information from logical addresses to physical addresses is called FTL table. FTL tables are important metadata in solid state storage devices. Typically, the data items of the FTL table record address mapping relationships in units of data pages in the solid-state storage device.
FTL tables include a plurality of FTL table entries (or entries). In one case, a correspondence of one logical page address to one physical page is recorded in each FTL table entry. In another case, correspondence between consecutive logical page addresses and consecutive physical pages is recorded in each FTL table entry. In yet another case, a correspondence of logical block addresses to physical block addresses is recorded in each FTL table entry. In still another case, mapping relation between logical block address and physical block address, and/or mapping relation between logical page address and physical page address are recorded in FTL table.
Improved FTL tables and ways in which they are used in solid state storage devices are disclosed in "dftl: A Flash Translation Layer Employing Demand-based Selective Caching of Page-level Address Mappings", which can be derived in its entiretyhttp://www.cse.psu.edu/～buu1/papers/ps/dftl- asplos09.pdfObtained.
Disclosure of Invention
As storage capacity of storage devices increases, there is a need for address translation systems that service mass storage devices. The address conversion system is required to meet one or more of the following requirements, get rid of the limitation on the memory capacity, provide stable and efficient address conversion capability for IO operation, reduce the influence on the service life of the storage device, and be easy to realize. Address translation systems also meet other needs.
According to a first aspect of the present application there is provided a first address translation method for a read operation according to the first aspect of the present application, comprising: acquiring a logic address accessed by a read operation; and if the logical address hits in the cached conversion page, acquiring a physical address corresponding to the logical address from the cached conversion page.
According to a first address translation method for a read operation of the first aspect of the present application, there is provided a second address translation method for a read operation according to the first aspect of the present application, further comprising: and if the logical address does not hit the cached conversion page, reading the conversion page according to the conversion page address acquired from the global conversion directory, and acquiring a physical address corresponding to the logical address from the read conversion page.
According to a first or second address translation method for a read operation of the first aspect of the present application, there is provided a third address translation method for a read operation according to the first aspect of the present application, wherein the cached translation page comprises a plurality of entries, each entry indicating a correspondence of a logical address with a physical address.
According to a third address translation method for read operations of the first aspect of the present application, there is provided a fourth address translation method for read operations according to the first aspect of the present application, wherein the cached translation page is a copy of the translation page stored in the NVM chip in memory.
According to a third or fourth address translation method for a read operation of the first aspect of the present application, there is provided a fifth address translation method for a read operation of the first aspect of the present application, wherein the global translation directory comprises a plurality of entries, each entry indicating a correspondence of a logical address segment to a translation page address, the translation page address being a physical address of a translation page in the NVM chip.
According to a fifth address translation method for a read operation of the first aspect of the present application there is provided a sixth address translation method for a read operation of the first aspect of the present application wherein the entries of the global translation directory are ordered in the order of the logical address segments indicated by the entries.
According to a fifth or sixth address translation method for a read operation of the first aspect of the present application, there is provided a seventh address translation method for a read operation of the first aspect of the present application, wherein each entry of the global translation directory records whether its corresponding translation page has a copy in memory.
According to one of the first to seventh address translation methods for a read operation of the first aspect of the present application, there is provided an eighth address translation method for a read operation according to the first aspect of the present application, wherein the global translation directory is queried to obtain whether the logical address hits the cached translation page or the cached translation page is traversed to obtain whether the logical address hits the cached translation page.
According to a second address translation method for a read operation of the first aspect of the present application, there is provided a ninth address translation method for a read operation according to the first aspect of the present application, further comprising: and if the logic address does not hit the cached conversion page, the cached conversion page is eliminated so as to release the storage space to accommodate the read conversion page.
According to a ninth address translation method for a read operation of the first aspect of the present application, there is provided the tenth address translation method for a read operation of the first aspect of the present application, wherein if the obsolete cached translation pages are of a writable type, the obsolete cached translation pages are written to the NVM chip, and the translation page addresses of the translation pages corresponding to the obsolete cached translation pages are updated in the global translation directory.
According to a ninth or tenth address translation method for a read operation of the first aspect of the present application, there is provided the eleventh address translation method for a read operation of the first aspect of the present application, wherein if the obsolete cached translation pages are of a read-only type, the memory space of the obsolete cached translation pages is released without writing the obsolete cached translation pages to the NVM chip.
According to a second address translation method for a read operation of the first aspect of the present application, there is provided an address translation method for a read operation of the twelfth aspect of the present application, wherein the read translation page is set as a cached translation page.
According to a twelfth address conversion method for a read operation according to the first aspect of the present application, there is provided the thirteenth address conversion method for a read operation according to the first aspect of the present application, wherein the conversion page of the cache set in accordance with the read-out conversion page is set to a read-only type.
According to a first address translation method for a read operation of the first aspect of the present application, there is provided a fourteenth address translation method for a read operation according to the first aspect of the present application, further comprising: if the logical address does not hit the cached translation page, the method also queries whether the logical address hits the cached translation table.
According to a fourteenth address translation method for a read operation of the first aspect of the present application, there is provided a fifteenth address translation method for a read operation according to the first aspect of the present application, further comprising: and if the logic address hits in the cached conversion table, acquiring a physical address corresponding to the logic address from the cached conversion table according to the logic address.
The fourteenth or fifteenth address conversion method for a read operation according to the first aspect of the present application provides the sixteenth address conversion method for a read operation according to the first aspect of the present application, further comprising: if the logical address does not hit the cached conversion table, reading out a conversion page according to the conversion page address acquired from the global conversion directory, and acquiring a physical address corresponding to the logical address from the read-out conversion page.
According to one of the fourteenth to sixteenth address translation methods for a read operation of the first aspect of the present application, there is provided the seventeenth address translation method for a read operation of the first aspect of the present application, wherein the read-out translation page is set to a read-only type.
According to one of the fourteenth to seventeenth address translation methods for a read operation of the first aspect of the present application, there is provided the eighteenth address translation method for a read operation according to the first aspect of the present application, further comprising: updating the read translation page according to the physical address of one or more entry records in the cached translation table.
An eighteenth address translation method for read operations according to the first aspect of the present application provides the nineteenth address translation method for read operations according to the first aspect of the present application, wherein the logical address corresponding to the one or more entries belongs to a logical address field of the read translation page.
According to a nineteenth address translation method for a read operation according to the first aspect of the present application, there is provided an address translation method for a read operation according to the twentieth aspect of the present application, further comprising: the read-out conversion page is set to a writable type.
According to one of the first to twenty address translation methods for a read operation of the first aspect of the present application, there is provided a twenty-first address translation method for a read operation according to the first aspect of the present application, further comprising: and reading out data according to the physical address corresponding to the logical address.
According to a second aspect of the present application, there is provided a first address translation method for a write operation according to the second aspect of the present application, comprising: acquiring a logical address accessed by a write operation and a physical address allocated for the write operation; and if the logic address hits in the cached conversion page, updating the hit cached conversion page according to the logic address and the physical address.
According to a first address translation method for a write operation of the second aspect of the present application, there is provided a second address translation method for a write operation of the second aspect of the present application, wherein if the conversion page of the hit cache is of a read-only type, the conversion page of the hit cache is also set to a writable type.
According to the first or second address translation method for write operation of the second aspect of the present application, there is provided a third address translation method for write operation according to the second aspect of the present application, further comprising: and if the logic address does not hit the cached conversion page, reading the conversion page according to the conversion page address acquired from the global conversion directory, and updating the read conversion page according to the logic address and the physical address.
According to a third address translation method for a write operation of the second aspect of the present application, there is provided a fourth address translation method for a write operation according to the second aspect of the present application, further comprising: and if the logic address does not hit the cached conversion page, the cached conversion page is eliminated so as to release the storage space to accommodate the read conversion page.
According to a fourth address translation method for a write operation of the second aspect of the present application, there is provided the fifth address translation method for a write operation of the second aspect of the present application, wherein if the obsolete cached translation pages are of a writable type, the obsolete cached translation pages are written to the NVM chip, and the translation page addresses of the translation pages corresponding to the obsolete cached translation pages are updated in the global translation directory.
According to a fourth or fifth address translation method for a write operation according to the second aspect of the present application, there is provided a sixth address translation method for a write operation according to the second aspect of the present application, wherein if the retired cached translation page is of a read-only type, the memory space of the retired cached translation page is freed without writing the retired cached translation page to the NVM chip.
According to one of the third to sixth address translation methods for write operations of the second aspect of the present application, there is provided the seventh address translation method for write operations according to the second aspect of the present application, wherein the read translation page is set as a cached translation page.
According to a seventh address conversion method for a write operation of the second aspect of the present application, there is provided an eighth address conversion method for a write operation of the second aspect of the present application, wherein a conversion page of a cache set in accordance with the read-out conversion page is set to a read-only type.
According to one of the first to eighth address translation methods for write operations of the second aspect of the present application, there is provided the ninth address translation method for write operations of the second aspect of the present application, wherein the cached translation page includes a plurality of entries, each entry indicating a correspondence of a logical address with a physical address.
According to a ninth address translation method for write operations of the second aspect of the present application, there is provided the tenth address translation method for write operations of the second aspect of the present application, wherein the cached translation page is a copy of the translation page stored in the NVM chip in the memory.
According to one of the first to tenth address translation methods for a write operation of the second aspect of the present application, there is provided an eleventh address translation method for a write operation of the second aspect of the present application, wherein the global translation directory includes a plurality of entries, each entry indicating a correspondence of a logical address segment and a translation page address, the translation page address being a physical address of a translation page in the NVM chip.
An eleventh address translation method for write operations according to the second aspect of the present application provides the twelfth address translation method for write operations according to the second aspect of the present application, wherein the entries of the global translation directory are ordered in the order of the logical address segments indicated by the entries.
According to an eleventh or twelfth address translation method for write operations of the second aspect of the present application, there is provided an address translation method for write operations according to the thirteenth aspect of the present application, wherein each entry of the global translation directory records whether its corresponding translation page has a copy in memory.
According to one of the first to thirteenth address translation methods for write operations of the second aspect of the present application, there is provided the fourteenth address translation method for write operations of the second aspect of the present application, wherein querying a global translation directory results in whether the logical address hits a cached translation page or traversing the cached translation page results in whether the logical address hits a cached translation page.
According to a first address translation method for a write operation of the second aspect of the present application, there is provided a fifteenth address translation method for a write operation according to the second aspect of the present application, further comprising: if the logical address does not hit the cached conversion page, inquiring whether the logical address hits the cached conversion table, wherein the record of the cached conversion table indicates the corresponding relation between the logical address and the physical address.
According to a fifteenth address conversion method for a write operation according to the second aspect of the present application, there is provided an address conversion method for a write operation according to the sixteenth aspect of the present application, further comprising: if the logic address hits the cached conversion table, the cached conversion table is updated according to the logic address and the physical address.
According to a fifteenth or sixteenth address translation method for a write operation according to the second aspect of the present application, there is provided a seventeenth address translation method for a write operation according to the second aspect of the present application, further comprising: if the logical address does not hit in the cached conversion table, generating a new entry of the cached conversion table to record the logical address and the physical address.
According to one of the fifteenth to seventeenth address translation methods for write operations of the second aspect of the present application, there is provided the eighteenth address translation method for write operations according to the second aspect of the present application, further comprising: in response to the cached translation table lacking storage space to accommodate the new entry, one or more entries of the cached translation table are also retired to free up storage space to accommodate the new entry.
An eighteenth address translation method for write operations according to the second aspect of the present application provides the nineteenth address translation method for write operations according to the second aspect of the present application, wherein if the logical address of the obsolete entry or entries hits the cached translation page, the hit cached page is updated with the logical address and the physical address of the entry or entries, and the entry or entries are removed from the cached translation table.
According to an eighteenth or nineteenth address translation method for a write operation according to the second aspect of the present application, there is provided an address translation method for a write operation according to the twentieth aspect of the present application, wherein if the logical address of the obsolete entry or entries misses a cached translation page, the translation page address corresponding to the logical address segment to which the obsolete entry or entries belongs is acquired from the global translation directory, the translation page is read out according to the translation page address, the hit cache page is updated with the logical address and the physical address of the entry or entries, and the entry or entries are removed from the cached translation table.
According to a nineteenth or twentieth address translation method for a write operation according to the second aspect of the present application, there is provided a twenty-first address translation method for a write operation according to the second aspect of the present application, wherein the read-out translation page is set to a writable type.
According to a third aspect of the present application, there is provided a first storage device according to the third aspect of the present application, comprising a control section, an NVM chip and a memory, the NVM chip comprising a plurality of memory blocks, the memory blocks comprising a data block and a translation block; recording data written into the storage device in the data block; the conversion block records the corresponding relation between a plurality of logical addresses and physical addresses; recording a global conversion catalog and a cached conversion page in a memory; the control unit performs one of the methods provided according to the first or second aspect of the application.
According to a first storage device of a third aspect of the present application, there is provided a second storage device according to the third aspect of the present application, wherein the memory further records a cached translation table.
According to a fourth aspect of the present application there is provided a first memory device according to the fourth aspect of the present application comprising a control unit and a non-volatile memory chip, wherein the control unit performs one of the methods provided according to the first or second aspects of the present application.
According to a fifth aspect of the present application there is provided a program according to the fifth aspect of the present application comprising program code which, when loaded into and executed in a CPU, causes the CPU to perform one of the methods provided according to the first or second aspects of the present application.
According to a sixth aspect of the present application there is provided an address translation system for a read operation according to the first aspect of the present application, comprising: the logic address module is used for acquiring a logic address accessed by a read operation; and the physical address module is used for acquiring the physical address corresponding to the logical address from the cached conversion page if the logical address hits the cached conversion page.
According to a seventh aspect of the present application, there is provided an address translation system for a write operation according to the first aspect of the present application, comprising: the address acquisition module is used for acquiring a logical address accessed by the write operation and a physical address allocated for the write operation; and the updating module is used for updating the cached conversion page according to the logic address and the physical address if the logic address hits the cached conversion page.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings may be obtained according to these drawings for a person having ordinary skill in the art.
FIG. 1 is a block diagram of a solid state storage device of the related art;
FIG. 2 is a schematic diagram of an address translation system of a solid state storage device according to an embodiment of the present application;
FIG. 3A is a flow chart of address translation in response to a read operation according to an embodiment of the present application;
FIG. 3B is a flow chart of address translation in response to a write operation according to an embodiment of the present application;
FIG. 4 is a schematic diagram of an address translation system of a solid state storage device according to yet another embodiment of the present application;
FIG. 5A is a flow chart of address translation in response to a read operation in accordance with the embodiment of FIG. 4; and
FIG. 5B is a flow chart of address translation in response to a write operation in accordance with the embodiment of FIG. 4.
Detailed Description
The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
FIG. 2 is a schematic diagram of an address translation system of a solid state storage device according to an embodiment of the present application. The NVM chip of the solid-state storage device (see also fig. 1, NVM chip 105) provides a plurality of physical blocks. The physical blocks are divided into data blocks and conversion blocks according to the contents stored. The data block records data written to the solid state storage device. The translation block includes a plurality of translation pages, which are pages of, for example, NVM storage media, or storage space in a physical page having a specified size (e.g., 4 KB). The translation pages have physical addresses (page addresses) and the designated translation pages of the solid state storage device are accessible using the physical addresses of the translation pages. For example, in fig. 2, the conversion block includes conversion page a and conversion page b. The conversion page records a plurality of records. Each record is an entry, e.g., FTL table, recording a physical address. The locations recorded in the translation pages and translation blocks implies the logical addresses to which the records correspond. For example, in translation page a, a first record implies a logical address a, the value of the first record is physical address a, and a second record in ascending order of physical addresses implies a logical address a+1, the value of the second record is physical address a1. It should be noted that "logical address a" and "physical address a" in fig. 2 are address mappings recorded by one entry of the FTL table, but "logical address a" and "physical address a" are not related in numerical value optionally. In the conversion page, a plurality of records are ordered according to the physical addresses of the storage records, and the physical addresses corresponding to the continuous plurality of logical addresses are recorded in sequence. "logical address a" and "logical address a+1" are numerically adjacent logical addresses, each indicating a data unit (e.g., 4K) having a specified size. The "physical address a" has no numerical relationship with the "physical address a1" and each may be any value within the address space provided by the NVM chip of the solid-state storage device.
Similarly, in translation page b, the first record implies a logical address b, the value of the first record is physical address b, and the second record, in which the records are stored in ascending order of physical address, implies a logical address b+1, the value of the second record is physical address b1. Further, by way of example, translation page b is adjacent to the physical address of translation page a, and the physical address of translation page b is subsequent, then logical address b implied by the first record of logical address b is adjacent to the last logical address (denoted an) implied by translation page a, and subsequent to logical address an.
According to an embodiment of the application, one or more translation pages record a mapping of each logical address (in data unit granularity) to a physical address of a logical address space provided by a solid state storage device. The contiguous logical address space implied by all of the records of each translation page is referred to as a logical address segment. Alternatively, a portion of the bits of the logical address are used as representing the segment of the logical address. For example, the middle 20 bits of the logical address, so that the logical addresses in the logical address space comprised by the logical address segment do not have to be consecutive.
With continued reference to FIG. 2, various data tables are recorded in the memory of the solid state storage device (see also FIG. 1, e.g., DRAM 110), including a global translation directory and cached translation pages. The cached conversion pages are of two types, namely read-only cached conversion pages and writable cached conversion pages. The cached translation pages are one or more.
The global translation directory includes a plurality of entries, each entry indicating a correspondence of < logical address field, translation page address >. The number of entries of the global translation directory is equivalent to the number of translation pages, each entry recording a physical address (translation page address) of a corresponding translation page in the NVM chip and/or an address of a corresponding cached translation page in memory (e.g., DRAM 110). The entries of the global translation directory are ordered in numerical order of the logical address segments indicated by the entries, such that the locations of the entries in the global translation directory imply the logical address segments indicated by the entries.
The cached translation page is a copy of the translation page in memory. The cached translation page includes a plurality of entries, each entry recording a record in the translation page. Alternatively, a few, but not all, of the conversion pages have copies in memory. The read-only cached translation pages are the same as their corresponding translation pages in the NVM storage medium. The contents of the writable cached translation page are modified relative to its corresponding translation page in the NVM storage medium. So that read-only cached translation pages need not be written to the NVM storage medium when replaced, whereas writable cached translation pages need to be written to the NVM storage medium when replaced.
Optionally, each entry of the global translation directory also records whether its corresponding translation page has a copy in memory (cached translation page), and the address of the copy in memory.
Optionally, a physical block allocation table is also recorded in the memory, including a data block table and a conversion block table, wherein which physical blocks of the NVM chip of the solid-state storage device are used as data blocks and which physical blocks are used as conversion blocks, respectively. And optionally, the physical block allocation table further includes a free block table, recording unused or unallocated physical blocks.
FIG. 3A is a flow chart of address translation in response to a read operation according to an embodiment of the present application.
The read operation indicates that data is to be retrieved from a logical address or logical address range. Embodiments of the present application are described with the example of a read operation accessing a logical address. For a read operation accessing a logical address range, the data retrieved for each address of the logical address range is combined in response to the read operation.
In one example, in response to receiving a read operation, a logical address to be accessed by the read operation is obtained (310), and a global translation directory is queried with a logical address segment where the logical address of the read operation is located (see also FIG. 2), resulting in whether the logical address segment is recorded in a cached translation page (referred to as a cached translation page hit) (340). If the logical address field hits in the cached translation page, the hit cached translation page is accessed, from which a physical address corresponding to the logical address of the read operation is obtained (360), thereby completing the address translation process for the read operation. If the logical address segment misses a cached translation page, a translation page address (denoted TPA) corresponding to the logical address segment is obtained from the global translation directory (350), the translation page address TPA recording the physical address of the translation page in the translation block. And reading the conversion page from the NVM chip according to the conversion page address TPA, and caching the conversion page to obtain a cached conversion page, and obtaining a physical address (PPA) corresponding to the logical address from the read conversion page according to the logical address to be accessed by the read operation (360). Thereby completing the address translation process for the read operation.
And reading data from the NVM chip using the obtained physical address PPA.
Alternatively, instead of querying the global translation directory to obtain whether the logical address segment hits in a cached cache page, the cached translation page is searched to obtain whether the logical address segment accessed by the read operation hits in the cached cache page. Further alternatively, searching the cached translation pages is processed in parallel with querying the global translation directory. In response to receiving a read operation, both the global translation directory is queried to obtain the translation page address TPA and a determination is made as to whether the cached translation table hits. If the cached conversion page hits, the conversion page address TPA is obtained from the cached conversion page; if the cached conversion page is not hit, the conversion page address TPA acquired from the global conversion directory can be obtained earlier and used for reading the conversion page.
Optionally, for a read operation, in response to a cached conversion page miss (340), it is identified whether a memory area of the memory for storing cached conversion pages (referred to as a conversion page cache) also has room to accommodate new conversion pages.
In one example, where the conversion page cache is not full and can accommodate a new conversion page, the conversion page is read from the NVM chip using the conversion page address TPA based on the conversion page address TPA obtained from the global conversion directory, and the conversion page is read and stored in the conversion page cache. So that the read conversion page also becomes the cached conversion page. And acquiring a physical address PPA corresponding to the logical address from the cached conversion page according to the logical address indicated by the read operation, and accessing the NVM chip by using the physical address PPA to read out data. Optionally, the cached translation page is also marked as read-only in type.
In yet another example, the conversion page cache is full and cannot accommodate a new conversion page, and the cached conversion page (denoted as TP) needs to be selected for elimination to obtain that the storage space accommodates the new conversion page. Writing the cached conversion page TP into a conversion block of the NVM chip, recording a physical address carrying the conversion page TP in a global conversion directory, and releasing the conversion page cache of the conversion page TP to obtain a storage space for accommodating a new conversion page. Next, the conversion page is read out from the NVM chip using the conversion page address TPA according to the conversion page address TPA acquired from the global conversion directory, and the conversion page is read out and stored in the conversion page buffer. So that the read conversion page also becomes the cached conversion page. Optionally, the cached translation page is also marked as read-only in type.
In yet another example, to increase read processing speed, solid state storage devices strive to ensure that memory space is available in the conversion page cache at any time to accommodate new conversion pages without eliminating cached conversion pages during processing of the read operation. For example, periodically, or when a specified condition is met (e.g., there are too many conversion pages cached, the conversion page cache remaining space is low, etc.), a process of eliminating the cached conversion pages is initiated to free up conversion page cache space. Furthermore, in the process of reading, if the cached conversion page is not hit, the elimination process (because the storage space is ensured to be available in the conversion page cache at any time to accommodate the new conversion page) is not needed, and the conversion page is directly read out from the NVM chip by using the conversion page address TPA according to the conversion page address TPA obtained from the global conversion directory. .
According to an embodiment of the application, a conversion page of the cache that is eliminated is selected.
As an example, a read-only type cached translation page is selected as the obsolete cached translation page. Since the read-only type of cached translation page is the same copy of the translation page in the NVM chip in memory, the read-only type of cached translation page is eliminated, the cached translation page does not need to be written to the NVM chip, the translation page address TPA of the eliminated translation page does not need to be updated in the global translation directory, and only a new translation page is acquired from the NVM chip.
As yet another example, if there is no translation page of the read-only type of cache, a translation page of the writable type of cache is selected. And writing the cached conversion pages of the writable type into the NVM chip in the elimination process, recording new conversion page addresses TPA of the eliminated cached conversion pages in the global conversion directory, and acquiring the new conversion pages from the NVM chip.
As yet another example, the conversion pages of the obsolete cache are selected based on the number of conversion pages of the read-only type of cache in the conversion page cache and/or the number of conversion pages of the writable type of cache in the conversion page cache. And if the number of the conversion pages of the read-only type cache is larger than the specified threshold value, selecting the conversion pages of the read-only type cache as the conversion pages of the eliminated cache. And if the number of the conversion pages of the read-only type cache is not more than the specified threshold, selecting the conversion pages of the writable type cache as the eliminated conversion pages of the cache.
FIG. 3B is a flow chart of address translation in response to a write operation according to an embodiment of the present application.
The write operation indicates writing data to a logical address or logical address range. Embodiments of the present application are described with the example of a write operation accessing a logical address. For a write operation accessing a logical address range, data is written to each address of the logical address range in response to the write operation.
According to the embodiment of FIG. 3B, in response to receiving a write operation, a logical address to be accessed by the write operation is obtained (370), a physical address is allocated for the write operation, and data is written to the allocated physical address.
The global translation directory (see also FIG. 2) is queried with the logical address segment where the logical address of the write operation is located (380), resulting in whether the logical address segment is recorded in a cached translation page (referred to as a cached translation page hit) (382). If the logical address field hits in a cached translation page, it is further identified whether the type of cached translation page that hit is read-only or writable (384). If the cached translation page that is hit is writable, the logical address of the write operation and the assigned physical address are used to update the hit cache page (395). If the cached translation page that is hit is read-only, the logical address of the write operation and the assigned physical address are used to update 395 the cached translation page that is hit, and the type of cached translation page that is hit is also marked as writable 386. Optionally, the read-only cached translation pages, and the writable cached translation pages, are also updated, each in number.
If the logical address segment corresponding to the logical address of the write operation does not hit the conversion page of the cache, a conversion page address (denoted as TPA) corresponding to the logical address segment is obtained from the global conversion directory, and the conversion page address TPA records the physical address of the conversion page in the conversion block. And reading out the conversion page from the NVM chip according to the conversion page address TPA, and caching the conversion page to obtain a cached conversion page (390), and updating a physical address (PPA) corresponding to the logical address in the read conversion page according to the logical address to be accessed by the write operation and the assigned physical address (395). Thereby completing the address translation process for the write operation. The resulting cached translated page type is also marked as writable (386). Optionally, the read-only cached translation pages, and the writable cached translation pages, are also updated, each in number.
Alternatively, or in addition, in response to a cached conversion page miss (382), it is identified whether a memory area of the memory for storing the cached conversion page (referred to as a conversion page cache) also has room to accommodate the new conversion page. If the conversion page buffer is not full and can accommodate a new conversion page, the conversion page is read from the NVM chip using the conversion page address TPA according to the conversion page address TPA obtained from the global conversion directory, and the conversion page is read and stored in the conversion page buffer. If the conversion page buffer is full and can not accommodate the new conversion page, selecting the buffered conversion page (marked as TP) for elimination so as to acquire the new conversion page accommodated in the storage space.
Further, the obsolete cached translation pages are also selected. The strategy of selecting the obsolete cached translation pages has been described in the embodiment according to fig. 3A.
FIG. 4 is a schematic diagram of an address translation system of a solid state storage device according to yet another embodiment of the present application. The physical block is divided into a data block and a conversion block. The data block records therein data written to the solid state storage device. The conversion block records the correspondence between logical addresses and physical addresses.
With continued reference to FIG. 4, various data tables are recorded in the memory of the solid state storage device (see also FIG. 1, e.g., DRAM 110), including a global translation directory, cached translation pages, and cached translation tables. The cached conversion pages are of two types, namely read-only cached conversion pages and writable cached conversion pages. The cached translation page is a copy of the translation page in memory.
The global translation directory includes a plurality of entries, each entry indicating a correspondence of < logical address field, translation page address >.
The cached translation table includes a plurality of entries, each entry recording a correspondence of < logical address, physical address >. The logical address indicates an address of a data unit having a specified size in the logical address space, and the physical address indicates a physical address of the data unit in the NVM chip. The entries in the cached translation table need not be ordered by logical address. Optionally, the cached translation table is stored with CAM (Content Addressable Memory ), cache (Cache), TLB (Translation Lookaside Buffer, bypass translation Cache), such that the physical address corresponding to the logical address is obtained from the translated Cache table using the logical address as an address. Still alternatively, the cached translation table is stored with a general memory and a data structure that supports fast lookups. According to an embodiment of the present application, the cached translation table is used to carry the update of the write operation to the correspondence of < logical address, physical address >.
FIG. 5A is a flow chart of address translation in response to a read operation in accordance with the embodiment of FIG. 4.
The read operation indicates that data is to be retrieved from a logical address or logical address range. Embodiments of the present application are described with the example of a read operation accessing a logical address.
According to the embodiment of FIG. 5A, in response to receiving a read operation, a logical address to be accessed by the read operation is obtained (510), and a global translation directory (see also FIG. 4) is queried with a logical address segment where the logical address of the read operation is located (515), resulting in whether the logical address segment is recorded in a cached translation page (referred to as a cached translation page hit) (520). Optionally, one or more cached translation pages are traversed to determine whether the logical address field is recorded in the cached translation pages.
If the logical address segment hits in a cached translation page (520), the hit cached translation page is accessed, from which a physical address corresponding to the logical address of the read operation is obtained (540), thereby completing the address translation process for the read operation (550). If the logical address field misses the cached translation page (520), a query is made as to whether the logical address of the read operation hits the cached translation table (525). If the logical address of the read operation hits in the cached translation table (525), a physical address corresponding to the logical address of the read operation is obtained from the cached translation table (535).
In one example, for a logical address of a read operation, it is advantageous to prioritize whether or not it hits a cached translation page relative to whether or not it hits the cached translation table because the cached translation page has more memory space, stores more correspondence of < logical address, physical address >, and thus has a greater chance of being hit relative to the cached translation table. In yet another example, whether the cached translation page is hit is queried in parallel with the cached translation table. And in the event of a hit, acquiring the corresponding physical address from the cached translation page that was hit.
If the logical address of the read operation misses the cached translation table (525), the translation page is read from the NVM chip as a cached translation page (530) based on the translation page address (denoted TPA) corresponding to the logical address segment obtained from the global translation directory. And obtains a physical address (PPA) corresponding to the logical address from the read-out translation page (as a cached translation page) according to the logical address to be accessed by the read operation (540). Thereby completing the address translation process for the read operation. And reading data from the NVM chip using the obtained physical address PPA.
Optionally, after replacing the cached translation page (530) (the translation page read from the NVM chip is denoted as cached translation page CTP 1), the cached translation page CTP 1 is also merged with the cached translation table (537). For example, the cached translation page CTP 1 records the correspondence of each logical address to a physical address in a logical address segment (denoted LR). While in the cached translation table there may be one or more records whose logical addresses belong to the logical address segment LR. The cached translation page CTP 1 is updated with one or more entries in the cached translation table whose logical addresses belong to the logical address segment LR. In other words, the physical address of the corresponding entry in the cached translation page CTP 1 is updated with the physical address of one or more entries in the cached translation table whose logical address belongs to the logical address segment LR. And removing one or more entries in the cached translation table whose logical addresses belong to the logical address field LR from the cached translation table to free up cached translation table space.
Optionally, at step 530, it is identified whether there is room for a new conversion page in the memory area for storing the cached conversion page (referred to as conversion page cache).
In one example, where the conversion page cache is not full and can accommodate a new conversion page, the conversion page is read from the NVM chip using the conversion page address TPA based on the conversion page address TPA obtained from the global conversion directory, and the conversion page is read and stored in the conversion page cache. So that the read conversion page also becomes the cached conversion page. Optionally, the cached translation page is also marked as read-only in type.
In yet another example, the conversion page cache is full and cannot accommodate new conversion pages, or the free space is below a threshold, and the cached conversion pages (denoted as TP) need to be selected for eviction to obtain that the storage space accommodates new conversion pages. Next, the conversion page is read out from the NVM chip using the conversion page address TPA according to the conversion page address TPA acquired from the global conversion directory, and the conversion page is read out and stored in the conversion page buffer. Optionally, the cached translation page is also marked as read-only in type.
In yet another example, to increase read processing speed, solid state storage devices strive to ensure that memory space is available in the conversion page cache at any time to accommodate new conversion pages without eliminating cached conversion pages during processing of the read operation. For example, periodically, or when a specified condition is met (e.g., there are too many conversion pages cached, the conversion page cache remaining space is low, etc.), a process of eliminating the cached conversion pages is initiated to free up conversion page cache space.
FIG. 5B is a flow chart of address translation in response to a write operation in accordance with the embodiment of FIG. 4.
The write operation indicates writing data to a logical address or logical address range. Embodiments of the present application are described with the example of a write operation accessing a logical address.
According to the embodiment of FIG. 5B, in response to receiving a write operation, a logical address to be accessed by the write operation is obtained (560), a physical address is allocated for the write operation, and data is written to the allocated physical address.
The global translation directory (see also FIG. 4) is queried with the logical address segment where the logical address of the write operation is located (565), resulting in whether the logical address segment is recorded in a cached translation page (called a cached translation page hit) (570). Optionally, one or more cached translation pages are traversed to determine whether the logical address field is recorded in the cached translation pages.
If the logical address segment hits in a cached translation page (570), it is further identified whether the type of cached translation page that hit is read-only or writable (572). If the cached translation page that hit is writable (572), the cached translation page that hit is updated with the logical address of the write operation and the assigned physical address (585). If the cached translation page that was hit is read-only (572), the type of cached translation page that was hit is marked as writable (576), and the cached translation page that was hit is updated with the logical address of the write operation and the assigned physical address (585). Optionally, the read-only cached translation pages, and the writable cached translation pages, are also updated, each in number.
If the logical address segment corresponding to the logical address of the write operation does not hit in the cached translation page (570), the cached translation table is queried using the logical address of the write operation, and a determination is made as to whether the logical address is recorded in the cached translation table (referred to as a cached translation table hit) (575). If the logical address of the write hits in the cached translation table, the cached translation table is updated with the logical address of the write and the assigned physical address (594).
In one example, for a logical address of a write operation, it is advantageous to prioritize whether or not it hits a cached translation page (570) relative to whether or not it hits the cached translation table (575) because the cached translation page has more memory space, stores more correspondence of < logical address, physical address >, and thus has a greater chance of being hit relative to the cached translation table. In addition, the logical address and the physical address corresponding to the write operation are preferably updated to the cached translation page compared to the cached translation table. In yet another example, whether the cached translation page is hit is queried in parallel with the cached translation table. And in case of hit of both, updating the physical address corresponding to the hit translation page of the cache.
If the logical address of the write operation does not hit in the cached translation table (575), the memory space for the new entry is obtained from the cached translation table (580) to record the logical address and the physical address corresponding to the write operation in the cached translation table.
In one example, the cached translation table has room to accommodate new entries in which the logical address and physical address corresponding to the write operation are recorded (594). In yet another example, if the space of the cached translation table is below the threshold or a new entry cannot be accommodated, one or more entries of the cached translation table are selected for elimination to obtain that the storage space accommodates the new entry.
To eliminate entries of the cached translation table, in one example, one or more entries whose logical address segments to which the logical address belongs hit the cached translation page(s) are selected, the cached translation page is updated with the physical address of the entries, and the entries are removed from the cached translation table.
In yet another example, the entry(s) of the cached translation table corresponding to which logical address segment is selected for elimination, identifying which logical address segment covers the most entries of the cached translation table. If the logical address segment corresponds to the cached translation page, the cached translation page is updated with the physical address of the entry. If the logical address segment corresponds to a translation page on the NVM chip, the corresponding translation page is read and the translation page is updated with the physical addresses of the entries. And writing the updated translation as a cached translation page (of writable type). And removing the entries of the cached translation table from the cached translation table.
It is again determined whether the logical address corresponding to the write operation hits in the cached translation page (590). If the logical address field hits in the cached translation page (590), processing proceeds to step 572. If the logical address segment misses the cached translation page 590, the cached translation table is updated 594 with the logical address of the write operation and the assigned physical address. The flow of address translation in response to the write operation ends (598).
It will be appreciated that in step 580, if the cached translation table has space to accommodate the new entry, or the entries of the cached translation table are eliminated, the eliminated entries hit the cached translation page, and since the logical address field of the cached translation page has not changed, the logical address and the physical address corresponding to the write operation are directly recorded in the new entry of the cached translation table (594), without going through step 590.
If the elimination of the entries of the cached translation table results in the translation page being read from the NVM chip such that the logical address field of the cached translation page changes in step 580, then it is again determined whether the logical address corresponding to the write operation hits the cached translation page, via step 590.
There is further provided, in accordance with an embodiment of the present application, a solid state storage device including a controller and a nonvolatile memory chip, wherein the controller performs any one of the processing methods provided in the embodiments of the present application.
There is also provided, in accordance with an embodiment of the present application, a program stored on a readable medium, which when executed by a controller of a solid state storage device, causes the solid state storage device to perform any one of the processing methods provided in accordance with the embodiments of the present application.
While preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the application. It will be apparent to those skilled in the art that various modifications and variations can be made to the present application without departing from the spirit or scope of the application. Thus, it is intended that the present application also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.
Claims (31)
1. An address translation method for a read operation, comprising:
acquiring a logic address accessed by a read operation;
inquiring a global conversion catalog according to a logical address segment where the logical address is located and traversing conversion pages of the search cache to be processed in parallel, and judging whether the logical address hits the cache pages of the cache;
If the logical address hits the cached conversion page, acquiring a physical address corresponding to the logical address from the cached conversion page;
the cached conversion page comprises a plurality of entries, wherein each entry indicates the corresponding relation between a logical address and a physical address, and the cached conversion page is a copy of the conversion page stored in the NVM chip in a memory;
the global translation directory includes a plurality of entries, each entry indicating a correspondence between a logical address segment and a translation page address, the translation page address being a physical address of a translation page in the NVM chip.
2. The method of claim 1, wherein entries of the global translation directory are ordered by logical address segment indicated by the entries.
3. The method of claim 1, wherein each entry records whether its corresponding translation page has a copy in memory.
4. The method as recited in claim 1, further comprising:
and if the logic address does not hit the cached conversion page, the cached conversion page is eliminated so as to release the storage space to accommodate the read conversion page.
5. The method of claim 4, wherein,
If the obsolete cached conversion page is of a writable type, writing the obsolete cached conversion page into the NVM chip, and updating the conversion page address of the conversion page corresponding to the obsolete cached conversion page in the global conversion directory.
6. The method according to claim 4 or 5, wherein,
if the retired cached translation page is of a read-only type, freeing up memory space for the retired cached translation page without writing the retired cached translation page to the NVM chip.
7. The method of claim 4, wherein the read translation page is set to a cached translation page.
8. The method of claim 7, wherein the cached conversion page set according to the read-out conversion page is set to a read-only type.
9. The method as recited in claim 1, further comprising: if the logical address does not hit the cached translation page, the method also queries whether the logical address hits the cached translation table.
10. The method as recited in claim 9, further comprising: and if the logic address hits in the cached conversion table, acquiring a physical address corresponding to the logic address from the cached conversion table according to the logic address.
11. The method according to claim 9 or 10, further comprising: if the logical address does not hit the cached conversion table, reading out a conversion page according to the conversion page address acquired from the global conversion directory, and acquiring a physical address corresponding to the logical address from the read-out conversion page.
12. The method of claim 11, wherein the read-out conversion page is set to a read-only type.
13. The method as recited in claim 11, further comprising: updating the read translation page according to the physical address of one or more entry records in the cached translation table.
14. The method of claim 13, wherein the logical address corresponding to the one or more entries belongs to a logical address field of the read translation page.
15. The method as recited in claim 14, further comprising: the read-out conversion page is set to a writable type.
16. The method as recited in claim 15, further comprising: and reading out data according to the physical address corresponding to the logical address.
17. An address translation method for a write operation, the method comprising:
Acquiring a logical address accessed by a write operation and a physical address allocated for the write operation;
if the logical address hits the cached conversion page, updating the hit cached conversion page according to the logical address and the physical address;
the cached conversion page comprises a plurality of entries, wherein each entry indicates the corresponding relation between a logical address and a physical address, and the cached conversion page is a copy of the conversion page stored in the NVM chip in a memory;
wherein obtaining the logical address accessed by the write operation and the physical address allocated for the write operation includes:
the global conversion catalog is queried by a logic address segment where a logic address accessed by the writing operation is located, if the logic address segment hits a conversion page of the cache, a physical address distributed for the writing operation is determined according to the conversion page of the cache; if the cached conversion page is not hit, the cached conversion table is queried, and if the cached conversion table is hit, the physical address allocated for the writing operation is determined according to the cached conversion table; or alternatively
And after inquiring the global conversion catalog, inquiring whether the cached conversion page is hit or not and the cached conversion table in parallel.
18. The method of claim 17, wherein if the cached conversion page that was hit is of a read-only type, further setting the cached conversion page that was hit to a writable type.
19. The method as recited in claim 17, further comprising:
and if the logic address does not hit the cached conversion page, reading the conversion page according to the conversion page address acquired from the global conversion directory, and updating the read conversion page according to the logic address and the physical address.
20. The method of claim 14, wherein if the logical address misses a cached translation page, further discarding the cached translation page to free memory space to accommodate the read translation page.
21. The method of claim 20, wherein if the retired cached translation page is of a writable type, writing the retired cached translation page to the NVM chip and updating a translation page address for the translation page corresponding to the retired cached translation page in the global translation directory.
22. The method of claim 20, wherein if the retired cached translation page is of a read-only type, freeing up memory space for the retired cached translation page without writing the retired cached translation page to the NVM chip.
23. The method of claim 20, wherein the read translation page is set to a cached translation page.
24. The method of claim 23, wherein the cached conversion page set according to the read-out conversion page is set to a read-only type.
25. The method as recited in claim 17, further comprising: if the logic address hits the cached conversion table, the cached conversion table is updated according to the logic address and the physical address.
26. The method as recited in claim 17, further comprising: in response to the cached translation table lacking storage space to accommodate the new entry, one or more entries of the cached translation table are also retired to free up storage space to accommodate the new entry.
27. The method of claim 26, wherein if the logical address of the obsolete one or more entries hits in the cached translation page, updating the hit cache page with the logical address and physical address of the one or more entries, and removing the one or more entries from the cached translation table.
28. The method of claim 17, wherein if the logical address of the retired one or more entries misses a cached translation page, wherein the translation page address corresponding to the logical address segment to which the retired one or more entries belong is obtained from the global translation directory, wherein the translation page is read based on the translation page address, wherein the one or more entries are updated with the logical address and the physical address of the one or more entries, and wherein the one or more entries are removed from the cached translation table.
29. The method as recited in claim 17, further comprising:
if the logical address does not hit in the cached conversion table, generating a new entry of the cached conversion table to record the logical address and the physical address.
30. A memory device comprising a control unit, an NVM chip and a memory, the NVM chip comprising a plurality of memory blocks, the memory blocks comprising data blocks and translation blocks; recording data written into the storage device in the data block; the conversion block records the corresponding relation between a plurality of logical addresses and physical addresses; recording a global conversion catalog and a cached conversion page in a memory;
the control unit performs the method according to one of claims 1-29.
31. The storage device of claim 30, wherein the memory further records a cached translation table.
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