CN104156178A - Data access method for embedded terminal - Google Patents
Data access method for embedded terminal Download PDFInfo
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- CN104156178A CN104156178A CN201410393352.8A CN201410393352A CN104156178A CN 104156178 A CN104156178 A CN 104156178A CN 201410393352 A CN201410393352 A CN 201410393352A CN 104156178 A CN104156178 A CN 104156178A
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Abstract
The invention provides a data access method for an embedded terminal. The data access method includes the steps that a page address is used for converting cache, and the cache and the granularity of address conversion information in an NAND Flash are unified; a global address page conversion table is used for positioning address conversion pages in the NAND Flash, and practical address conversion information is obtained from the address conversion pages; data belonging to the same address conversion page are written into identical data blocks in a concentrated mode based on data of the conversion pages. According to the data access method for the embedded terminal, spatial locality is used for improving the cache hit rate, cache access is optimized, the updating number of the conversion pages is reduced in the recycling process, and the system performance is promoted.
Description
Technical field
The present invention relates to embedded system, particularly a kind of access method of built-in terminal storer.
Background technology
NAND Flash storer has been widely used in all kinds of embedded systems, has that readwrite performance is high, non-volatile, an advantage such as low-power consumption, high density and good shock resistance.At the embedded device for environment on-line analysis, generally adopt NAND to carry out the indication information of storage sensor network institute sensing, therefore, for the built-in terminal of real time environment monitoring, the I/O of storage system has relatively high expectations.But NAND Flash often has some limitations, as " strange land renewal " and the limited erasable number of times of piece.In order to solve these deficiencies, utilize Flash conversion layer software such as the embedded device of above-mentioned site layout project, process exterior I/O request and management Flash.Wherein, address translation is responsible for the logical address that comes from file system to be converted to the physical address in NAND Flash.Therefore, how effectively executive address conversion management transitions information, become a key issue.
Mainly contain the conversion based on the page, the conversion based on page piece and mix conversion in 3 kinds of methods of Flash conversion layer, respectively having relative merits.Based on changing with page as unit executive address conversion, directly locator data of the page.But page address conversion table has been preserved the transitional information of all logical page (LPAGE)s to Physical Page, memory cost is very large.Because the information of address conversion of all renewals all needs to write NAND Flash, these a large amount of operating influences to address translation page the performance of address translation.
Therefore,, for existing the problems referred to above in correlation technique, effective solution is not yet proposed at present.
Summary of the invention
For solving the existing problem of above-mentioned prior art, the present invention proposes a kind of built-in terminal data access method, comprising:
Utilize page address translation cache, the granularity of information of address conversion in buffer memory and NAND Flash is unified;
By the address translation page in the NAND Flash of global address page translation tables location, obtain actual information of address conversion from address translation page;
Utilize the data centralization based on conversion page, the data that belong to same address translation page are written to identical data block.
Preferably, the data cell of described page address translation cache is whole address translation page, unifies thus the granularity of the information of address conversion in NAND Flash and buffer memory, and utilizes temporal locality and the spatial locality of data; The transitional information that each address translation page has comprised 1MB address space, the local data for access frequency in Preset Time higher than preset frequency, only needs accession page address translation caching and does not need to access NAND Flash; In the time that certain conversion page is displaced buffer memory, the information of address conversion of all renewals is updated in NAND Flash in the lump.
Preferably, the address translation page in described NAND Flash is located by global address page translation tables, after reading address conversion page, can obtain actual information of address conversion; Described overall page translation tables is provided with buffer memory index, directly locates the conversion page in buffer memory from global address page translation tables, and page translation tables is directly linked to the translation cache based on the page;
In the time having logical address request, first navigate to the item of overall page translation tables according to the logical address of request, item by the address translation item number that logical address is preserved divided by each conversion page in accession page conversion table, this has safeguarded physical address and the buffer memory index of conversion page in NAND Flash;
If buffer memory index is 1, show not yet buffer memory of this conversion page, need to access NAND Flash and obtain information of address conversion; If buffer memory index is not 1, according to the buffer memory index physical address that directly the address translation page of access cache is asked with acquisition;
Preferably, in the transfer process of described page address, use and do not use at most recently the Replacement Strategy of algorithm as page address translation cache, wherein, if certain conversion page was never updated in buffer memory, will preferentially be displaced buffer memory, to reduce extra conversion page read-write expense; Utilize start address and the global address page translation tables of the address translation page of the displacement item correspondence in buffer memory, to locate the conversion page address of actual storage in NAND Flash, carry out replacement operator.
Preferably, the described data centralization based on conversion page further comprises:
Data write using conversion page corresponding to its logical address as guidance, and logical address is corresponding to the data of same conversion page by being written into identical data block, and in the time that piece reclaims, conversion number of pages corresponding to data block mostly is constant 1 most;
The physical address that each in overall page translation tables is preserved data available page is available page number, wherein, physical address is 1 to represent this not yet distribute data piece, and use empty set of blocks to record empty data blocks all in NAND Flash, in the time having request of data, the empty data block of distributing according to need is given overall page translation tables; In piece reclaims, the empty piece after erasable is recovered to sky set of blocks, and in each data block, the logical address of data is limited in the address space range that corresponding conversion page safeguards; In the NAND Flash starting stage, institute is free data block to belong to sky set of blocks, in overall situation page translation tables, every data available page address is all unallocated state, in the time having write data requests, locate the item of overall page translation tables, if the available page number in item is not 1, directly write data into corresponding data page, upgrade subsequently available page number for the next data available page in institute's distribute data piece, if data block is full, this address is set to 1; If the available page number in is 1, if not yet distribute data piece of this conversion page, check and in empty set of blocks, whether have available empty data block, if exist the physical address of distributing according to need and record the 1st data page as available page number, if do not exist invoking block piece removal process to obtain new empty data block.
The present invention compared to existing technology, has the following advantages:
The address conversion method of optimizing, in the situation that increasing space expense a little, can greatly reduce extra address translation page operations, and improve system performance, reduces the erasable number of times of piece.
Brief description of the drawings
Fig. 1 is according to the process flow diagram of the built-in terminal data access method of the embodiment of the present invention.
Embodiment
Below provide the detailed description to one or more embodiment of the present invention together with illustrating the accompanying drawing of the principle of the invention.Describe the present invention in conjunction with such embodiment, but the invention is not restricted to any embodiment.Scope of the present invention is only defined by the claims, and the present invention contain manyly substitute, amendment and equivalent.Set forth in the following description many details to provide thorough understanding of the present invention.These details are provided for exemplary purposes, and also can realize the present invention according to claims without some or all details in these details.
Generally speaking, there are two subject matters in page address conversion method.First, the transitional information utilization factor of address translation caching is low, is reading after whole conversion page one of them address translation item of a buffer memory.For continuous read-write, certain address translation page may be repeated repeatedly to ask to produce a large amount of expenses.Secondly, in the time of processing write requests, the data of Different Logic address are write in same data block continuously, in the time reclaiming, will produce a large amount of conversion renewals of the page.For the problems referred to above, the present invention has designed a kind of address conversion method of optimization.
An aspect of of the present present invention provides a kind of built-in terminal data access method.Fig. 1 is according to the process flow diagram of the built-in terminal data access method of the embodiment of the present invention.As shown in Figure 1, implement page address of the present invention conversion method and comprise following two aspects:
First, a large amount of address translation page operations that cause for cache miss, by analyzing the reading and writing data characteristic in Flash, design page address translation cache, the granularity of information of address conversion in unique caching and NAND Flash;
Secondly, reclaim for reducing a large amount of address translation renewal of the page expenses that produce, utilize the data centralization method based on conversion page, the data that belong to same address translation page are written to identical data block.Therefore, the renewal expense of the conversion page during by recovery is down to minimum constant value, has improved system performance.
1. page address translation cache
The present invention proposes a kind of page address translation cache technology.The data cell of buffer memory is whole address translation page, has therefore unified the granularity of the information of address conversion in NAND Flash and buffer memory, and makes full use of temporal locality and the spatial locality of data.The transitional information that each address translation page has comprised 1MB address space, as frequent access local data in the short time, only needs accession page address translation caching and does not need to access NAND Flash.Meanwhile, in the time that certain conversion page need to be displaced buffer memory, the information of address conversion of all renewals can be updated in NAND Flash in the lump, has improved the utilization factor of transitional information.
Global address page translation tables is responsible for locating the address translation page in NAND Flash, after reading address conversion page, can obtain actual information of address conversion.Therefore, global address page translation tables is also a page address conversion table.The present invention utilizes overall page translation tables and the page address translation cache in internal memory to have this feature of same transitions Information Granularity, and both access process are merged in design, to improve address translation performance.The present invention has expanded overall page translation tables, has increased buffer memory index, directly locates the conversion page in buffer memory from global address page translation tables, makes page translation tables directly be linked to the translation cache based on the page.In the time having logical address request, first navigate to the item of overall page translation tables according to the logical address of request, because the initial logical address of each is fixed, therefore, the address translation item number that logical address is preserved divided by each conversion page can have access to the item in page translation tables, and this has safeguarded physical address and the buffer memory index of conversion page in NAND Flash.
If buffer memory index is 1, show not yet buffer memory of this conversion page, need to access NAND Flash and obtain information of address conversion; Otherwise, according to the buffer memory index physical address that directly the address translation page of access cache is asked with acquisition.Can see, the new address translation access mode proposing by the inventive method, has simplified the access process of address translation, by buffer memory continuously or the mode of hash search become direct access, saved the cache access time.
The present invention uses and does not use at most recently the Replacement Strategy of algorithm as page address translation cache, wherein, the update times of conversion page be also selective cementation according to one of, if certain conversion page was never updated in buffer memory, it will preferentially be displaced buffer memory, because such replacement operator can not produce extra conversion page read-write expense.Utilize start address and the global address page translation tables of the address translation page of the displacement item correspondence in buffer memory, to locate the conversion page address of actual storage in NAND Flash, carry out replacement operator.
2. the data centralization method based on conversion page
In order further to reduce because information of address conversion upgrades the conversion page expense of bringing, the present invention has designed the data centralization based on conversion page.Data write using conversion page corresponding to its logical address as guidance, and logical address will be written into identical data block corresponding to the data of same conversion page.Therefore, when recovery, conversion number of pages corresponding to data block mostly is constant 1 most, and the expense that consequent extra information of address conversion upgrades is reduced to minimum.
In order to realize data centralization, the present invention continues to expand overall page translation tables, and each in table has been preserved the physical address of data available page, and wherein, physical address is 1 to represent this not yet distribute data piece.Meanwhile, use empty set of blocks to record empty data blocks all in NAND Flash, in the time having request of data, the empty data block of distributing according to need is given overall page translation tables.In recovery, the empty piece after erasable is recovered to sky set of blocks.Data centralization has been optimized the data in data block and has been distributed,, in each data block, the logical address of data is limited in the address space range of corresponding conversion page maintenance, and because the data that address is close are upgraded more together, the method can reduce active page number of copies while recovery indirectly.
In the NAND Flash starting stage, institute is free data block to belong to sky set of blocks, in overall situation page translation tables, every data available page address is all unallocated state, in the time having write data requests, locate the item of overall page translation tables according to computing method mentioned above, if the available page number in item is not 1, directly write data into corresponding data page, upgrade subsequently available page number for the next data available page in institute's distribute data piece, if data block is full, this address is set to 1; Otherwise, if not yet distribute data piece of this conversion page checks in empty set of blocks whether have available empty data block, if exist the physical address of distributing according to need and record the 1st data page as available page number, obtain new empty data block otherwise call to reclaim.
3. the recovery based on data centralization
Because physical block is divided into data block and address conversion block according to storage data type, there are accordingly two kinds of recovery: data block reclaims and conversion block reclaims.In the recovery of data block, in order to ensure that each data block is in a recovery only corresponding conversion page afterwards, the present invention will be multiplexing in recovery based on conversion page data concentration techniques.In address translation, the promoter of request of data is file system, and in recovery, is recover, and both have similar address translation process, because the method can be multiplexing.In the removal process of data block, in the time that recover need to copy an active page, first access global transformation page and change to obtain the physical address of current data available page (available page number), if data available page is (non-1) existing, directly active page is write to data available page; Otherwise, if the data block of current distribution is finished, use swap block as newly assigned data block storage active page.In the time that recovery completes, the empty data block after wiping is as new swap block.
To the recovery of address conversion block, in NAND Flash, safeguard a current available address translation page, be equivalent to unified write pointer, therefore, conversion page will be written in the conversion block of current address in order.When triggering recovery during without assignable address conversion block in NAND Flash, in the time reclaiming, reclaim effective conversion page in piece and will copy to the available address conversion page of write pointers point.Meanwhile, if address translation page is positioned at buffer memory, directly write current conversion block from buffer memory, reduced the conversion renewal of the page operation to the read operation of effective conversion page and buffer memory generation in the future.Finally, the conversion page of close temperature is write back identical conversion block by the displacement of page address translation cache, indirectly reduces the number of the active page in conversion block while recovery, thereby reduced the renewal expense of conversion page.
The permanance that extends NAND Flash for the erasable number of times of equilibrium criterion piece, in NAND Flash, record the erasable number of times of each data block, temperature information that can service data region in overall situation page translation tables, record the access frequency in the corresponding continuous logic of each address translation page space, to access frequency higher than preset frequency divide timing to select " cold " piece that erasable number of times is few in write pointer request, distribute more " heat " piece of erasable number of times to access frequency not higher than preset frequency.Equally, in recovery, the data block of selecting erasable number of times to be less than invalid number of pages is carried out erasable as reclaiming piece.In NAND Flash free time, can carry out exchanges data with erasable number of times between counterbalance weight to hot and cold data block.
In sum, the present invention proposes NAND Flash address translation optimization method.On the one hand, design page address translation cache is unified the transitional information granularity of internal memory and NAND Flash, utilize its spatial locality to improve cache hit rate, meanwhile, merged two kinds of data structures of overall page translation tables and page address translation cache to optimize cache access; On the other hand, the data that information of address conversion belonged to same conversion page write identical data block, have reduced renewal number the Hoisting System performance of conversion page while recovery.
Obviously, it should be appreciated by those skilled in the art, above-mentioned of the present invention each module or each step can realize with general computing system, they can concentrate on single computing system, or be distributed on the network that multiple computing systems form, alternatively, they can be realized with the executable program code of computing system, thereby, they can be stored in storage system and be carried out by computing system.Like this, the present invention is not restricted to any specific hardware and software combination.
Should be understood that, above-mentioned embodiment of the present invention is only for exemplary illustration or explain principle of the present invention, and is not construed as limiting the invention.Therefore any amendment of, making, be equal to replacement, improvement etc., within protection scope of the present invention all should be included in without departing from the spirit and scope of the present invention in the situation that.In addition, claims of the present invention are intended to contain whole variations and the modification in the equivalents that falls into claims scope and border or this scope and border.
Claims (5)
1. a built-in terminal data access method, for realizing the address translation of built-in terminal NAND Flash storer, is characterized in that, comprising:
Utilize page address translation cache, the granularity of information of address conversion in buffer memory and NAND Flash is unified;
By the address translation page in the NAND Flash of global address page translation tables location, obtain actual information of address conversion from address translation page;
Utilize the data centralization based on conversion page, the data that belong to same address translation page are written to identical data block.
2. method according to claim 1, it is characterized in that, the data cell of described page address translation cache is whole address translation page, unifies thus the granularity of the information of address conversion in NAND Flash and buffer memory, and utilizes temporal locality and the spatial locality of data; The transitional information that each address translation page has comprised 1MB address space, the local data for access frequency in Preset Time higher than preset frequency, only needs accession page address translation caching and does not need to access NAND Flash; In the time that certain conversion page is displaced buffer memory, the information of address conversion of all renewals is updated in NAND Flash in the lump.
3. method according to claim 2, is characterized in that, the address translation page in described NAND Flash is located by global address page translation tables, after reading address conversion page, can obtain actual information of address conversion; Described overall page translation tables is provided with buffer memory index, directly locates the conversion page in buffer memory from global address page translation tables, and page translation tables is directly linked to the translation cache based on the page;
In the time having logical address request, first navigate to the item of overall page translation tables according to the logical address of request, item by the address translation item number that logical address is preserved divided by each conversion page in accession page conversion table, this has safeguarded physical address and the buffer memory index of conversion page in NAND Flash;
If buffer memory index is 1, show not yet buffer memory of this conversion page, need to access NAND Flash and obtain information of address conversion; If buffer memory index is not 1, according to the buffer memory index physical address that directly the address translation page of access cache is asked with acquisition.
4. method according to claim 3, it is characterized in that, in the transfer process of described page address, use and do not use at most recently the Replacement Strategy of algorithm as page address translation cache, wherein, if certain conversion page was never updated in buffer memory, will preferentially be displaced buffer memory, to reduce extra conversion page read-write expense; Utilize start address and the global address page translation tables of the address translation page of the displacement item correspondence in buffer memory, to locate the conversion page address of actual storage in NAND Flash, carry out replacement operator.
5. method according to claim 1, is characterized in that, the described data centralization based on conversion page further comprises:
Data write using conversion page corresponding to its logical address as guidance, and logical address is corresponding to the data of same conversion page by being written into identical data block, and in the time that piece reclaims, conversion number of pages corresponding to data block mostly is constant 1 most;
The physical address that each in overall page translation tables is preserved data available page is available page number, wherein, physical address is 1 to represent this not yet distribute data piece, and use empty set of blocks to record empty data blocks all in NAND Flash, in the time having request of data, the empty data block of distributing according to need is given overall page translation tables; In piece reclaims, the empty piece after erasable is recovered to sky set of blocks, and in each data block, the logical address of data is limited in the address space range that corresponding conversion page safeguards; In the NAND Flash starting stage, institute is free data block to belong to sky set of blocks, in overall situation page translation tables, every data available page address is all unallocated state, in the time having write data requests, locate the item of overall page translation tables, if the available page number in item is not 1, directly write data into corresponding data page, upgrade subsequently available page number for the next data available page in institute's distribute data piece, if data block is full, this address is set to 1; If the available page number in is 1, if not yet distribute data piece of this conversion page, check and in empty set of blocks, whether have available empty data block, if exist the physical address of distributing according to need and record the 1st data page as available page number, if do not exist invoking block removal process to obtain new empty data block.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109960667A (en) * | 2017-12-14 | 2019-07-02 | 北京忆恒创源科技有限公司 | The address conversion method and device of large capacity solid storage device |
| CN112783804A (en) * | 2019-11-08 | 2021-05-11 | 华为技术有限公司 | Data access method, device and storage medium |
| CN114676072A (en) * | 2022-05-25 | 2022-06-28 | 阿里巴巴（中国）有限公司 | Data processing method and device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101256536A (en) * | 2007-03-01 | 2008-09-03 | 创惟科技股份有限公司 | Flash memory address translation layer system |
| US20090083478A1 (en) * | 2007-03-28 | 2009-03-26 | Kabushiki Kaisha Toshiba | Integrated memory management and memory management method |
| US20100049905A1 (en) * | 2008-08-25 | 2010-02-25 | Hitachi, Ltd. | Flash memory-mounted storage apparatus |
| CN103425600A (en) * | 2013-08-23 | 2013-12-04 | 中国人民解放军国防科学技术大学 | Address mapping method for flash translation layer of solid state drive |
| CN104156324A (en) * | 2014-08-11 | 2014-11-19 | 四川九成信息技术有限公司 | Program run method for embedded system |
-
2014
- 2014-08-11 CN CN201410393352.8A patent/CN104156178A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101256536A (en) * | 2007-03-01 | 2008-09-03 | 创惟科技股份有限公司 | Flash memory address translation layer system |
| US20090083478A1 (en) * | 2007-03-28 | 2009-03-26 | Kabushiki Kaisha Toshiba | Integrated memory management and memory management method |
| US20100049905A1 (en) * | 2008-08-25 | 2010-02-25 | Hitachi, Ltd. | Flash memory-mounted storage apparatus |
| CN103425600A (en) * | 2013-08-23 | 2013-12-04 | 中国人民解放军国防科学技术大学 | Address mapping method for flash translation layer of solid state drive |
| CN104156324A (en) * | 2014-08-11 | 2014-11-19 | 四川九成信息技术有限公司 | Program run method for embedded system |
Non-Patent Citations (1)
| Title |
|---|
| 张琦等: "一种优化的闪存地址映射方法", 《软件学报》 * |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109960667A (en) * | 2017-12-14 | 2019-07-02 | 北京忆恒创源科技有限公司 | The address conversion method and device of large capacity solid storage device |
| CN109960667B (en) * | 2017-12-14 | 2023-09-15 | 北京忆恒创源科技股份有限公司 | Address translation method and device for large-capacity solid-state storage device |
| CN112783804A (en) * | 2019-11-08 | 2021-05-11 | 华为技术有限公司 | Data access method, device and storage medium |
| CN114676072A (en) * | 2022-05-25 | 2022-06-28 | 阿里巴巴（中国）有限公司 | Data processing method and device |
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Application publication date: 20141119 |