CN110515861B - Memory device for processing flash command and method thereof - Google Patents
Memory device for processing flash command and method thereof Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
- G06F12/0615—Address space extension
- G06F12/063—Address space extension for I/O modules, e.g. memory mapped I/O
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
- G06F12/0646—Configuration or reconfiguration
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0877—Cache access modes
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
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- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/10—Providing a specific technical effect
- G06F2212/1016—Performance improvement
- G06F2212/1021—Hit rate improvement
Abstract
The application provides a solid-state storage device and a method for writing data into the solid-state storage device, wherein the method comprises the following steps: in response to receiving a flush command, obtaining a current time to generate a timestamp associated with the flush command; accessing a cache descriptor; obtaining timestamp data in the cache descriptor; and writing the data of the cache unit indicated by the cache descriptor with the timestamp earlier than that of the flash command into the non-volatile memory.
Description
Technical Field
The present application relates to storage devices, and more particularly, to storage devices utilizing caching to process Flush (Flush) commands.
Background
FIG. 1 illustrates a block diagram of a solid-state storage device. The solid-state storage device 102 is coupled to a host for providing storage capabilities to the host. The host and the solid-state storage device 102 may be coupled by various methods, including but not limited to, connecting the host and the solid-state storage device 102 by, for example, SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), SAS (Serial Attached SCSI), IDE (Integrated Drive Electronics), USB (Universal Serial Bus), PCIE (Peripheral Component Interconnect Express, PCIE, high-speed Peripheral Component Interconnect), NVMe (NVM Express, high-speed nonvolatile storage), ethernet, fiber channel, wireless communication network, etc. The host may be an information processing device, such as a personal computer, tablet, server, portable computer, network switch, router, cellular telephone, personal digital assistant, etc., capable of communicating with the storage device in the manner described above. The solid-state storage device 102 includes an interface 103, a control section 104, one or more NVM chips 105, and a DRAM (Dynamic Random Access Memory) 110.
NAND flash Memory, phase change Memory, FeRAM (Ferroelectric RAM), MRAM (magnetoresistive Memory), RRAM (Resistive Random Access Memory), etc. are common NVM.
The interface 103 may be adapted to exchange data with a host by means such as SATA, IDE, USB, PCIE, NVMe, SAS, ethernet, fibre channel, etc.
The control unit 104 is used to control data transfer between the interface 103, the NVM chip 105, and the DRAM 110, and also to store and manage mapping of host logical addresses to flash physical addresses, erase leveling, bad block management, and the like. The control component 104 can be implemented in various manners of software, hardware, firmware, or a combination thereof, for example, the control component 104 can be in the form of an FPGA (Field-programmable gate array), an ASIC (Application-Specific Integrated Circuit), or a combination thereof. The control component 104 may also include a processor or controller in which software is executed to manipulate the hardware of the control component 104 to process IO (Input/Output) commands. The control component 104 may also be coupled to the DRAM 110 and may access data of the DRAM 110. FTL tables and/or cached IO command data may be stored in the DRAM.
In the conventional solid-state storage device, mapping information from a logical address to a physical address is maintained by using a Flash Translation Layer (FTL). The logical addresses constitute the storage space of the solid-state storage device as perceived by upper-level software, such as an operating system. The physical address is an address for accessing a physical memory location of the solid-state memory device. Address mapping may also be implemented using an intermediate address modality in the related art. E.g. mapping the logical address to an intermediate address, which in turn is further mapped to a physical address.
A table structure storing mapping information from logical addresses to physical addresses is called an FTL table. FTL tables are important metadata in solid state storage devices. Usually, the data entry of the FTL table records the address mapping relationship in the unit of data page in the solid-state storage device.
A flash command is also defined in the NVMe protocol. By means of the Flush command, the storage device is instructed to save to the non-volatile storage medium the data (and its metadata) to be written prior to all commands received by the Flush command.
Solid state storage devices use caching to improve performance. For the write command, after the data indicated by the write command is written into the cache, the write command is indicated to complete the processing. Due to the existence of the cache, when the Flush command is processed, the data in the cache needs to be written into the nonvolatile storage medium, and the process takes too long time. There is a need to reduce or avoid the performance jitter experienced by the host in writing data in the cache to the non-volatile storage media due to the Flush command.
Disclosure of Invention
The solid-state storage device and the method for writing data into the solid-state storage device solve the problem of performance jitter caused by Flush commands when the solid-state storage device writes data.
According to a first aspect of the present application, there is provided a method for writing data to a solid-state storage device, comprising the steps of: in response to receiving a flush command, obtaining a current time to generate a timestamp associated with the flush command; accessing a cache descriptor; obtaining timestamp data in the cache descriptor; and writing the data of the cache unit indicated by the cache descriptor with the timestamp earlier than that of the flash command into the non-volatile memory.
According to a first aspect of the present application, a method for writing data to a solid-state storage device is provided, wherein when data of a cache unit indicated by all cache descriptors with a timestamp earlier than that of a flush command is written into a non-volatile memory, the flush command processing is indicated to be completed.
According to a first aspect of the present application, in a method for writing data to a solid-state storage device, an index of an allocated cache unit, a timestamp indicating a write time of the allocated cache unit, and an address of data in the allocated cache unit are included in a cache descriptor.
A method of writing data to a solid state storage device according to a first aspect of the present application, wherein the address of the data is a logical address or a physical address of a non-volatile memory.
According to a first aspect of the present application, a method for writing data to a solid-state storage device is provided, wherein when a write command is received, a cache unit and a cache descriptor of a dynamic random access memory are allocated for the write command.
A method of writing data to a solid-state storage device according to a first aspect of the present application, wherein, after receiving a flash command, a flag is set to indicate that a flash command is pending; after the flash command processing is completed, the set flag is cleared.
According to a second aspect of the present application, there is also provided a method for writing data to a solid-state storage device, including the steps of: polling a cache descriptor in response to a cache unit of the dynamic random access memory being written with data; and writing the data in the cache unit into the non-volatile memory according to the cache descriptor.
A method of writing data to a solid state storage device according to a second aspect of the present application, wherein a cache unit is released in response to data within the cache unit being written to a non-volatile memory.
According to a third aspect of the present application, there is also provided a method for writing data to a solid-state storage device, including the steps of: in response to receiving a write command, identifying whether the write command hits in a cache location; if the write command hits a cache unit, judging whether the hit cache unit is influenced by a flash command; and if the hit cache unit is influenced by the flash command, temporarily caching the write command to process the write command after the flash command is processed, or distributing a new cache unit which is not influenced by the flash command to the write command.
According to a third aspect of the present application, in a method for writing data into a solid-state storage device, if a write command misses a cache unit, a free cache unit is allocated to the write command, and data corresponding to the write command is stored in the cache unit.
According to a third aspect of the present application, a method for writing data to a solid-state storage device is provided, wherein whether a write command hits in a cache unit is identified by whether a logical address to be accessed by the write command is consistent with a logical address recorded by a cache descriptor.
According to a third aspect of the present application, in a method for writing data to a solid-state storage device, if a hit cache unit is not affected by a flush command, a write command to be written is stored in the hit cache unit, and the write command processing is instructed to be completed.
According to a third aspect of the present application, in a method for writing data to a solid-state storage device, when there is no current flash command to be executed or the current flash command to be executed is smaller than a timestamp of a hit cache unit, it is determined that the hit cache unit is not affected by the flash command.
According to a third aspect of the present application, in a method for writing data into a solid-state storage device, when a current flash command to be executed has a timestamp not less than a timestamp of a hit cache unit, it is determined that the hit cache unit is affected by the flash command.
According to a third aspect of the present application, in a method for writing data to a solid-state storage device, during temporary buffering of the write command, the command continues to be received and processed.
According to a third aspect of the present application, a method for writing data into a solid-state storage device is provided, wherein the cache unit allocated for a write command and not affected by a flush command is any unoccupied cache unit when there is no to-be-executed flush command currently or the unoccupied cache unit of which the timestamp is smaller than that of the cache unit although there is a to-be-executed flush command currently.
According to a third aspect of the present application, after a new cache unit not affected by a flush command is allocated to a write command, a cache descriptor is further allocated to the new cache unit not affected by the flush command.
According to a third aspect of the present application, in a method for writing data to a solid-state storage device, an index of an allocated cache unit, a timestamp indicating a write time of the allocated cache unit, and an address of data in the allocated cache unit are included in the cache descriptor.
According to the method for writing data to the solid-state storage device in the third aspect of the present application, after the data corresponding to the write command is stored in the cache unit, the write command is indicated to be completed.
According to a fourth aspect of the present application, there is also provided a solid-state storage device comprising a dynamic random access memory, a controller and a non-volatile memory, wherein the controller performs the method as described above.
According to a fourth aspect of the present application, there is also provided a program comprising program code which, when loaded into a CPU and executed therein, causes the CPU to perform a method as one of those described above.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings can be obtained by those skilled in the art according to the drawings.
FIG. 1 is a schematic diagram of a solid-state memory device according to the prior art;
FIG. 2 is a schematic structural diagram of a solid-state memory device according to an embodiment of the present application;
FIG. 3 is a cache descriptor according to an embodiment of the present application;
FIGS. 4A-4C are diagrams illustrating handling a Flush command according to an embodiment of the present application;
FIGS. 5A-5D are schematic diagrams of handling a Flush command according to yet another embodiment of the present application;
FIG. 6 is a flow chart illustrating handling of a Flush command using a cache according to an embodiment of the present application;
fig. 7 is a flowchart of processing a Flush command using a cache according to another embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present invention are clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, belong to the protection scope of the present invention.
FIG. 2 illustrates a block diagram of a solid-state storage device according to an embodiment of the present application. The control components of the solid-state storage device include a host interface 210, a CPU 220, an address translation unit 230, and a media interface 240 for accessing the NVM chip 105. The control component is also coupled to an external memory (e.g., DRAM) 260.
The memory of the control unit has a cache descriptor stored therein. One or more of the cache descriptors record the address of the corresponding cache location 265 in the DRAM 260 and the address of the memory device occupying the cache location's data (e.g., a logical address or a physical address at which the memory device is accessible by the host).
The host interface 210 is used to exchange commands and data with a host. For example, the host and the storage device communicate via the NVMe/PCIe protocol, and the host interface 210 processes the PCIe protocol data packet, extracts the NVMe protocol command, and returns a processing result of the NVMe protocol command to the host.
FIG. 3 illustrates a cache descriptor according to an embodiment of the application.
Each cache descriptor is used for describing a cache unit corresponding to the cache descriptor. The cache descriptor records the index of the corresponding cache location (cache location index of fig. 3), the timestamp, and the logical address (LBA). The cache location index indicates the location of the cache location in DRAM 260. The time stamp records the time when the buffer unit is allocated, and the logical address (LBA) records the logical address accessed by the IO command to which the buffer unit is allocated. It will be appreciated that when the host accesses the storage device using physical addresses, the logical address field of the cache unit descriptor is replaced with the record physical address.
Fig. 4A-4C illustrate a schematic diagram of processing a Flush command according to an embodiment of the present application.
FIG. 4A illustrates IO commands received in a command queue in chronological order. The write command (IO W1) is received at the earliest time T1, the write command (IO W2) is received at the next time T2, the Flush command is received, and the write command (IO W3) and the write command (IO W4) are received at the next time T3 and the time T4 in sequence. In fig. 4A, arrows indicate the direction in which time elapses. The time at which the Flush command is received is between time T3 and time T4.
FIG. 4B shows the state of the buffer unit before processing the Flush command. According to the storage device of the embodiment of the application, after receiving the Flush command, the receiving and processing of other IO commands are not stopped. Thus, although the Flush command is received before the write command (IO W3), the write command (IO W3) and the write command (IO W4) still start to be processed, a buffer cell (indicated by ID 3) is allocated to the write command (IO W3), data to be written by the write command (IO W3) is already stored in the buffer cell, and a buffer cell (indicated by ID 4) is allocated to the write command (IO W4), but data to be written by the write command (IO W4) is not yet written to the buffer cell.
FIG. 4C shows the state of the cache molecule after processing the Flush command. In response to receiving the Flush command, the data to be written for all IO commands (see fig. 4A, write command (IO W1) and write command (IO W2)) received prior to receiving the Flush command is written to the non-volatile storage medium (e.g., NVM chip 105, see also fig. 2). The Flush command may then be indicated to the host that processing is complete. Whether the write command (IO W3) and the data to be written by the write command (IO W4) are written to the nonvolatile storage medium at this time is not subject to the semantic constraint of the Flush command.
5A-5D illustrate a schematic diagram of processing a Flush command according to yet another embodiment of the present application.
FIG. 5A is the same as FIG. 4A, showing IO commands received in the command queue in chronological order. A write command (IO W1) is received at the earliest time T1, a write command (IO W2) is received at the next time T2, a Flush command is received, and a write command (IO W3) and a write command (IO W4) are received at the next time T3 and the next time T4 in sequence. In fig. 5A, arrows indicate the direction in which time elapses. The time at which the Flush command is received is between time T3 and time T4.
FIG. 5B illustrates the state of the cache molecule prior to processing the Flush command. According to the storage device of the embodiment of the application, after the Flush command is received, the receiving and processing of other IO commands are not stopped. Thus, although a Flush command is received before the write command (IO W3), processing has started for the write command (IO W3) and the write command (IO W4), a cache location (indicated by ID 3) is allocated for the write command (IO W3), and the data to be written by the write command (IO W3) is not yet stored in the cache location. And a cache location has not been allocated to the write command (IO W4) before the Flush command begins processing.
FIG. 5C shows the state of the buffer unit at some point during the processing of the Flush command. In response to receiving the Flush command, the data to be written for all IO commands (see fig. 5A, write command (IO W1) and write command (IO W2)) received prior to receiving the Flush command is written to the non-volatile storage medium (e.g., NVM chip 105, see also fig. 2). At the time shown in FIG. 5C, the data to be written by the write command (IO W1) has already been written to the non-volatile storage medium, while the data to be written by the write command (IO W2) has not yet been written to the non-volatile storage medium. The data to be written by the write command (IO W3) has not yet been written to the cache location. And the write command (IO W4) has still not yet been allocated a cache location.
FIG. 5D shows the state of the cache molecule after processing the Flush command. The data to be written for all IO commands received prior to receiving the Flush command (see fig. 5A, write command (IO W1) and write command (IO W2)) has been written to the non-volatile storage medium (e.g., NVM chip 105, see also fig. 2). Since the write command (IO W1) is processed, its occupied cache location is freed, and the cache location may be allocated to other write commands. The cache location occupied by the write command (IO W2) has not been released.
The Flush command may then be indicated to the host that processing is complete. Whether the write command (IO W3) and the data to be written by the write command (IO W4) are written to the nonvolatile storage medium at this time is not restricted by the semantics of the Flush command. By way of example, referring to FIG. 5D, the data to be written by the write command (IO W3) has still not been written to the cache location. And a cache location (ID 4) is assigned to the write command (IO W4).
Fig. 6 is a flowchart of processing a Flush command using a cache according to an embodiment of the present application.
The illustrated process flow according to the embodiment of fig. 6 is controlled by, for example, the CPU 220 of fig. 2 and is performed in cooperation with other portions of the control section 104.
In response to an IO command (610) obtained from a host interface, a type of the IO command is identified to distinguish whether the IO command is a write command (620) or a Flush command (670). For write commands, a cache is allocated for the write command, e.g., cache locations and cache descriptors that have not been used are allocated. The address of the allocated buffer unit, a time stamp indicating the current time, and data to be written by the write command are recorded in the buffer descriptor, and the data to be written is stored in the allocated buffer unit (630). So far, although the data corresponding to the write command has not been written to the NVM chip, the host may be indicated that the write command processing is complete (640).
Another task, running in the CPU, is to move the data written to the cache location to the NVM chip (650). For example, in response to the cache unit being written with data, the process of moving the cache unit's data to the NVM chip begins. As yet another example, each cache descriptor is polled to move data of the cache location to which the data is written to the NVM chip in turn. Optionally, in response to the data in the cache location being moved to the NVM chip, the cache location is released so that the timestamp in the cache location is updated (or cleared), and the cache location may be assigned to other write commands.
For an IO command fetched from the host interface, such as a Flush command, the current time is fetched to generate a timestamp associated with the Flush command (680). Data of the cache location indicated by each cache descriptor with a timestamp earlier than that of the Flush command is identified whether all the data is moved to the NVM chip (660) by accessing each cache descriptor. If the data of the cache location indicated by each cache descriptor with a timestamp earlier than the timestamp of the Flush command is moved to the NVM chip, the Flush command processing is indicated to the host as complete (690).
If the data of the cache unit indicated by each cache descriptor with the timestamp earlier than that of the Flush command is not all moved to the NVM chip, for the Flush command, the data of the cache unit indicated by each cache descriptor with the timestamp earlier than that of the Flush command is all moved to the NVM chip (660), and then the Flush command is indicated to the host that the processing is completed (690). It can be understood that, during the period when the data of the cache unit indicated by each cache descriptor with the waiting time stamp earlier than the time stamp of the Flush command is moved to the NVM chip, the flow shown in fig. 6 may be continuously executed, and the IO command is obtained from the host interface and processed.
For example, if a Flush command is received, a flag is set to indicate that there is a Flush command to be processed. And after the IO command is acquired from the host interface every time, if the mark indicating that the Flush command is to be processed exists, accessing each cache descriptor to identify whether the data of the cache unit indicated by each cache descriptor with the timestamp earlier than that of the Flush command is transferred to the NVM chip. If the Flush command is recognized to be processed, the set flag is cleared.
Referring to FIG. 6, by way of example, the task of moving data written to a cache location to the NVM chip is performed continuously, rather than in response to identifying that data of the cache location indicated by cache descriptors having a timestamp earlier than the timestamp of the Flush command has not all been moved to the NVM chip. However, processing of the Flush command relies on moving data in a cache location associated with the Flush command from among the cache locations to the NVM chip. Alternatively, in response to a Flush command being processed, the task of moving the data of the buffer units associated with the Flush command to the NVM chip is preferentially processed to move the data written in these buffer units to the NVM chip as early as possible.
FIG. 7 is a flow diagram of processing a Flush command using caching according to yet another embodiment of the present application.
The situation where the IO write command hits in a cache location is further handled according to the flowchart of the embodiment of fig. 7 on the basis of the flowchart shown in fig. 6.
In response to receiving the write command (720), it is identified whether the write command hits in a cache location (730) by whether the logical address to be accessed by the write command coincides with the logical address of the cache descriptor record.
If the write command misses the cache unit, an idle cache unit is allocated for the write command, a timestamp indicating the current time is recorded in a cache entry corresponding to the cache unit, and data corresponding to the write command is stored in the cache unit (740). And indicating to the host that write command processing is complete (770).
If the write command hits in a cache location, it is further identified whether the hit cache location is affected by the Flush command and the data needs to be written to the cache location of the NVM chip (750). If the hit cache unit is not affected by the Flush command (there is no Flush command to be executed currently, or the Flush command to be executed currently but the timestamp of the Flush command to be executed is smaller than the timestamp of the hit cache unit), the data to be written by the write command is stored in the hit cache unit (760), and the write command processing is indicated to the host (770). If the hit cache unit is affected by the Flush command (the Flush command is currently to be executed, and the timestamp of the Flush command to be executed is not less than the timestamp of the hit cache unit) (750), the write command is temporarily cached (780) and processed after the Flush command is processed. During the period of temporarily caching the write command, other IO commands are obtained from the host interface for processing, so that performance jitter of the storage device caused by the execution of the Flush command is avoided.
Optionally, if the hit cache unit is affected by the Flush command, a new cache unit and a cache descriptor are allocated to the write command, an address of the allocated cache unit, a timestamp indicating the current time are recorded in the cache descriptor, and data to be written by the write command is obtained from the host, the data to be written is stored in the allocated cache unit, and then the write command is indicated to the host that the processing is completed.
Embodiments of the present application also provide a program comprising program code which, when loaded into a host computer and executed thereon, causes the processor of the host computer to perform one of the methods provided above in accordance with embodiments of the present application.
It will be understood that each block of the block diagrams and flowchart illustrations, and combinations of blocks in the block diagrams and flowchart illustrations, respectively, can be implemented by various means including computer program instructions. These computer program instructions may be loaded onto a general purpose computer, special purpose computer, or other programmable data control apparatus to produce a machine, such that the instructions which execute on the computer or other programmable data control apparatus create means for implementing the functions specified in the flowchart block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data control apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including computer-readable instructions for implementing the function specified in the flowchart block or blocks. The computer program instructions may also be loaded onto a computer or other programmable data control apparatus to cause a series of operational operations to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide operations for implementing the functions specified in the flowchart block or blocks.
Accordingly, blocks of the block diagrams and flowchart illustrations support combinations of means for performing the specified functions, combinations of operations for performing the specified functions and program instruction means for performing the specified functions. It will also be understood that each block of the block diagrams and flowchart illustrations, and combinations of blocks in the block diagrams and flowchart illustrations, can be implemented by special purpose hardware-based computer systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
Although the present invention has been described with reference to examples, which are intended to be illustrative only and not to be limiting of the application, changes, additions and/or deletions may be made to the embodiments without departing from the scope of the application.
Many modifications and other embodiments of the application set forth herein will come to mind to one skilled in the art to which these embodiments pertain having the benefit of the teachings presented in the foregoing descriptions and the associated drawings. Therefore, it is to be understood that the application is not to be limited to the specific embodiments disclosed and that modifications and other embodiments are intended to be included within the scope of the appended claims. Although specific terms are employed herein, they are used in a generic and descriptive sense only and not for purposes of limitation.
Claims (6)
1. A method of writing data to a solid state storage device, comprising the steps of:
in response to receiving a flush command, obtaining a current time to generate a timestamp associated with the flush command;
accessing a cache descriptor;
obtaining timestamp data in the cache descriptor;
writing data of a cache unit indicated by a cache descriptor having a timestamp earlier than that of the flush command into a non-volatile memory; and acquiring and processing other IO commands during the period of writing the data of the cache unit indicated by the cache descriptor into the non-volatile memory.
2. The method of writing data to a solid-state storage device of claim 1, wherein the flush command processing is indicated to be complete when data of a cache unit indicated by all cache descriptors having a timestamp earlier than a timestamp of the flush command is written to non-volatile memory.
3. The method of writing data to a solid-state storage device of claim 1 or 2, wherein the cache descriptor includes an index of the allocated cache unit, a timestamp indicating a write time of the allocated cache unit, and an address of the data in the allocated cache unit.
4. The method for writing data to the solid-state storage device according to one of claims 1 to 2, wherein when a write command is received, a cache unit and a cache descriptor of the dynamic random access memory are allocated for the write command.
5. Method of writing data to a solid state storage device according to one of claims 1-2,
after receiving the flash command, setting a flag to indicate that the flash command is to be processed;
after the flash command processing is completed, the set flag is cleared.
6. A solid-state storage device comprising a dynamic random access memory, a controller and a non-volatile memory, wherein the controller performs the method according to one of claims 1 to 5.
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