CN111796759B - Computer readable storage medium and method for fragment data reading on multiple planes - Google Patents
Computer readable storage medium and method for fragment data reading on multiple planes Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0629—Configuration or reconfiguration of storage systems
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0638—Organizing or formatting or addressing of data
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
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- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
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Abstract
The application proposes a computer readable storage medium for fragment data reading on multiple planes for storing computer program code executable by a processing unit, and which computer program code, when executed by the processing unit, implements the steps of: providing a scheduling data table; arranging each memory operation command in the command queue to a memory cell in the scheduling data table according to the physical address information of the memory operation command; selecting two or more memory operation commands for a logic unit number according to the content of the scheduling data table; driving a flash memory interface to complete multi-page read simple operation, and reading the data requested by the selected memory operation command from a logic unit number; and replying the read data to the host. By using the scheduling data table to collect two or more fragment read operations into a multi-page read simple operation, the efficiency of short data read can be improved.
Description
Technical Field
The present application relates to data storage devices, and more particularly to a computer readable storage medium and method for fragment data reading on multiple planes.
Background
Flash memory storage devices are generally classified into NOR flash memory storage devices and NAND flash memory storage devices. The NOR flash memory device is a random access device, and a Host (Host) may provide any address on an address pin that accesses the NOR flash memory device and timely obtain data stored on the address from a data pin of the NOR flash memory device. In contrast, NAND flash memory devices are not random access, but serial access. The NAND flash memory device cannot access any random address like the NOR flash memory device, and instead the host needs to write a serial byte value into the NAND flash memory device to define the type of Command (Command) (e.g., read, write, erase, etc.), and the address used on the Command. The address may point to one page (the smallest block of data for a write operation in a flash memory device) or one block (the smallest block of data for an erase operation in a flash memory device).
Conventional NAND flash memory (NAND flash memory) provides read commands that typically allow the controller to read data across an entire cross-plane page. However, with the length of the cross-plane page (e.g., 16 KB) in the NAND flash memory device having exceeded the data length (e.g., 4 KB) of the logical block address (Logical Block Address LBA) managed by the operating system executed by the host, conventional read operations that each time read an entire cross-plane page of data may reduce the overall performance of the NAND flash memory when processing short data read commands from the host. Therefore, the embodiment of the application provides a computer readable storage medium and a method for fragment data reading on multiple planes, which are used for performing optimized data reading operation on a NAND flash memory with longer cross-plane pages.
Disclosure of Invention
In view of this, how to alleviate or eliminate the drawbacks of the related art is a real problem to be solved.
The application relates to a computer readable storage medium for fragment data reading on multiple planes for storing computer program code executable by a processing unit, and which computer program code, when executed by the processing unit, implements the steps of: providing a scheduling data table; arranging each memory operation command in the command queue to a memory cell in the scheduling data table according to the physical address information of the memory operation command; selecting two or more memory operation commands for a logic unit number according to the content of the scheduling data table; driving a flash memory interface to complete multi-page read simple operation, and reading data requested by selected memory operation commands from a logic unit number; and replying the read data to the host.
The application relates to a method for reading fragment data on multiple planes, which is executed by a processing unit and comprises the following steps: providing a scheduling data table; arranging each memory operation command in the command queue to a memory cell in the scheduling data table according to the physical address information of the memory operation command; selecting two or more memory operation commands for a logic unit number according to the content of the scheduling data table; driving a flash memory interface to complete multi-page read simple operation, and reading data requested by selected memory operation commands from a logic unit number; and replying the read data to the host.
One of the advantages of the above embodiments is that the efficiency of short data reading can be improved by using the schedule data table to collect two or more fragment reading operations into one multi-page reading simplified operation.
Other advantages of the present application will be explained in more detail in connection with the following description and accompanying drawings.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute a limitation on the application.
FIG. 1 is a diagram of a flash memory system architecture according to an embodiment of the present application.
FIG. 2 is a diagram illustrating the connection between the flash memory interface and the logical unit number (Logical Unit Number LUN).
FIG. 3 is a command queue diagram.
FIG. 4 is a schematic diagram of data organization of a LUN.
FIG. 5 is a timing diagram of a segment read of a flash memory interface operation.
FIG. 6 is a schematic diagram of a section in a page.
FIG. 7 is a simplified timing diagram of a multi-page read operation of a flash memory interface.
FIG. 8 is a schematic diagram of an organization of planar and cross-plane pages in a LUN.
FIG. 9 is a diagram illustrating scheduling of memory operation commands according to some embodiments.
FIG. 10 is a flowchart of a memory operation command scheduling method according to an embodiment of the application.
Fig. 11 and 12 are schematic diagrams illustrating memory operation command scheduling according to embodiments of the application.
Fig. 13 and 14 are schematic diagrams illustrating selection of memory operation commands according to embodiments of the application.
[ list of reference numerals ]
100. Flash memory storage system architecture
110. Host machine
130. Controller for controlling a power supply
131. Host interface
133-0, 133-1 processor cores
135. Command queue
136. Data caching
137. Flash memory interface
138 DMA controller
139. Data buffer
150 LUNs
150#0～150#11 LUN
CH#0 to CH#3 channels CH
CE#0 to CE#2 chip enable control signals
CQT, CQH pointer
139#0 access subinterface
410#0-470#m plane
Pages P#0 to P# (n)
490#1 to 490#n superpages
t WB 、t RSNAP 、t DBSY 、t PR Time interval
900. Scheduling data table
S1010-S1090 method steps
1100. 1200 MPR-Lite scheduling data table
Detailed Description
Embodiments of the present application will be described below with reference to the accompanying drawings. In the drawings, like reference numerals designate identical or similar components or process flows.
It should be understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, values, method steps, operation processes, components, and/or groups, but do not preclude the addition of further features, values, method steps, operation processes, components, groups, or groups of the above.
In the present application, terms such as "first," "second," "third," and the like are used for modifying an element in a claim, and are not used for describing a time-first order, a first order, or a first element prior to another element, or a time-second order, in which method steps are performed, but are used for distinguishing between elements having the same name.
It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. Conversely, when an element is described as being "directly connected" or "directly coupled" to another element, there are no intervening elements present. Other words used to describe the relationship between components may also be interpreted in a similar fashion, such as "between" and "directly between" or "adjacent" and "directly adjacent" or the like.
Reference is made to fig. 1. The flash memory storage system architecture 100 includes a Host 110, a Controller 130, and a logical unit number (Logical Block Number, LUN) 150. The system architecture can be implemented in electronic products such as personal computers, notebook computers (notebook PCs), tablet computers, mobile phones, digital cameras, digital video cameras, and the like. The controller 130 may include a multi-core processor 133, which is a single computing component, collocated with two independent processor cores 133-0 and 133-1 for loading program code of firmware or software modules. The processor core 133-0 may communicate with the host 110 through the host interface 131 using universal flash memory storage (Universal Flash Storage, UFS), flash nonvolatile memory (Non-Volatile Memory Express, nvme), universal serial bus (Universal Serial Bus, USB), advanced technology attachment (Advanced Technology Attachment, ATA), serial advanced technology attachment (Serial Advanced Technology Attachment, SATA), peripheral component interconnect express (Peripheral Component Interconnect Express, PCI-E), or other interface protocols. The processor core 133-1 may communicate with the LUN 110 via the flash interface 137 using a Double Data Rate (DDR) communication protocol, such as open NAND flash (Open NAND Flash Interface, ONFI), double Data Rate switch (DDR Toggle), or other interface protocols.
The logical unit number (Logical Unit Number, LUN) 150 provides a large amount of storage space, typically hundreds of Gigabytes, even terabates, available for storing large amounts of user data, such as high resolution pictures, movies, etc. The LUN150 includes a control circuit and a memory array, and the memory units in the memory array may be three-tier units (Triple Level Cells, TLCs) or four-tier units (QLCs). A Data Buffer 139 may be used to Buffer user Data read from LUN150 and to be knocked out to host 110. Referring to fig. 2, the flash memory interface 137 may include four input/output Channels (I/O Channels, hereinafter referred to as Channels CH), including Channels ch#0 to ch#3, each channel CH connecting three LUNs, e.g., channel ch#0 connects LUNs 150#0, 150#4, and 150#8. The processor core 133-1 may drive the flash interface 137 to issue one of the enable signals CE#0 to CE#2 to enable the LUNs 150#0 to 150#3, the LUNs 150#4 to 150#7, or the LUNs 150#8 to 150#11, and then read the user data from the enabled LUNs in a parallel manner. For simplicity of explanation, the following description will be given by taking the channels ch#0 to ch#1 and ce#0 to ce#1 as examples to activate the LUNs 150#0 to 1 and the LUNs 150#4 to 5, but the application is not limited thereto.
The controller 130 may configure a command queue 135 for storing a plurality of flash memory operation commands, such as a Read Page command, a Program Page command, an Erase Block command, and the like. The flash memory operation command may be associated with a Host command (Host Commands) issued by the Host 110 but not yet processed, such as a Host read command, a Host write command, etc., or may be a command issued autonomously by the controller 130.
The command queue 135 may be implemented in static random access memory (Static Random Access Memory, SRAM), comprising a collection of multiple entries (Entry). Each entry in command queue 135 may store one flash memory operation command and related information. The flash memory operation commands in the set may be stored sequentially according to the arrival time. The basic principle of operation of the set is that the flash memory operation command (which may be referred to as enqueuing) is newly added by the processor core 133-0 from the end position (such as the position indicated by the pointer CQT), and the flash memory operation command (which may be referred to as dequeuing) is removed by the processor core 133-1 from the start position (such as the position indicated by the pointer CQH). However, to optimize the data read operation, the first flash memory operation command that is newly added to command queue 135 is not necessarily the first to be removed. In addition, the controller 130 may also use a Stack (Stack) to store the flash memory operation command, which is not limited thereto.
LUN150 contains multiple Planes (Planes), and referring to fig. 4, taking LUN150#0 as an example, it contains 4 Planes (Planes), including: planes 410 to 470. Each plane contains a plurality of Physical Blocks (simply referred to as Blocks), taking the plane 410 as an example, which contains Blocks 410#0-m, m being a positive integer. Each block includes a plurality of Pages (Pages), for example, block 410#0, which includes Pages p#0 through p#n, n being a positive integer. Each page P includes a plurality of NAND Memory Cells (Memory Cells), and the NAND Memory Cells may be three-layered Cells or four-layered Cells. In some embodiments, when each NAND memory cell is a three-level cell and 8 states can be recorded, one word line can include page P#0 (which can be referred to as the lowest bit page, MSB page), page P#1 (which can be referred to as the middle bit page, CSB, center Significant Bit page), and page P#2 (which can be referred to as the highest bit page, LSB page). When each NAND memory cell is a four-tier cell and 16 states can be recorded, a TSB (which may be referred to as a top bit, TSB, top Significant Bit) page is included in addition to the MSB, CSB, and LSB pages. The blocks in one of the different planes in the same LUN150 may virtually form large blocks (Big blocks), and the large blocks (Big blocks) in different LUNs 150 may virtually form Super blocks (Super blocks).
The Data Buffer 136 and/or the Data Buffer 139 may store a Logical-physical mapping table (Logical-Physical Mapping Table, L2P mapping table) to be searched for when reading Data, where the L2P mapping table records mapping information of Logical addresses and physical addresses of each Data. The data buffer 136 may be implemented in SRAM and the data buffer 139 may be implemented in pre-allocated part of dynamic random access memory (Dynamic Random Access Memory, DRAM).
Although the memory cells in each block or page are TLCs or QLCs, the controller 130 may employ a single layer cell (Single Logical Cells, SLCs) mode to program data into the block or page for increasing the speed of data reading and data programming. To facilitate the management of block programming modes, the controller 130 preferably creates and maintains a physical configuration data table (Physical Configuration Table) to record the programming mode of each block, i.e., default mode (TLC or QLC) or SLC mode, and stores the physical configuration data table in the data buffer 136. In the data reading operation, the controller 130 can identify the programming mode of each block or page by searching the physical configuration data table, so that the data of the block or page is read in a proper reading manner.
The controller 130 may output a Read Page command to Read a Page of a block in a plane of the LUN150, or may output a Read Page Multi-plane command to Read data of a Page of a block in a different plane. Sometimes, however, the host 110 does not need an entire page of data, but only 4KB of data in one page. At this time, the controller 130 may use a fragment Read (Snap Read) command to Read a portion of data in one page. For the fragment read operation, refer to fig. 5. Waveform 510 shows the clock type of the data lines DQ [7:0] coupled between the LUN150 and the flash interface 137, with 1 "CMD" clock indicating the primary command sent from the flash interface 137, 5 "Addr" clocks indicating the physical address of the LUN 137 from which reading is desired to be performed from the flash interface 137, and 1 "CMD" clock indicating the Confirm (Confirm) command sent from the flash interface 137, and finally, "DOUT" indicating the data output from the LUN 150. Waveform 520 is an exemplary fragment read command for waveform 510, with a main command of 00h and a validation command of 20h, and therefore LUN150 determines that this operation command is a fragment read command, which is to read a portion of the page data of the specified page (physical address).
The partial page data is, for example, 8KB data in 16KB page data, referring to FIG. 6, where the 8KB data can be selected from three different sections in a page: the length of the first 8KB section 625, the middle 8KB section 645, and the last 8KB section 665, each 8KB section preferably being greater than or equal to 8KB. In addition, the partial page data may be, for example, 4KB data in 16KB page data, that is, the 16KB page is divided into a first 4KB section, a second 4KB section, a third 4KB section and a fourth 4KB section, and the length of each 4KB section is preferably greater than or equal to 4KB.
In addition, since the LUN150 includes multiple Planes (Planes), the controller 130 may output a Multi-Page Read compact (MPR-Lite) command to Read fragment data on pages in the multiple Planes in the LUN150, referring to fig. 6, for example: the first 8KB section 625 in page P#0 of planes 810 and 830, the last 8KB section 665 of page P#1 of planes 830 and 850. The MPR-Lite command can improve the reading performance of the fragment data.
Referring to FIG. 1, taking a data read as an example, the processor core 133-0 may obtain a data read command from the host 110 through the host interface 131, wherein the data read command provides a logical address of the target data. The processor core 133-0 may obtain the page location (physical address) of the target data in the LUN150 by looking up the L2P mapping table and the logical address, and may learn the programming mode of the target data through the physical configuration table. Next, the processor core 133-0 generates a flash memory operation command to the command queue 135, wherein the flash memory operation command includes the physical address of the target data.
The controller 130 may utilize the command queue 135 to store a plurality of flash memory operation commands, such as: 64 flash memory operation commands. The processor core 133-1 may establish and maintain a Scheduling Table 900 and/or a Standby Table 910 in the data cache 136 for ordering the flash memory operation commands in the command queue 135 such that the flash memory operation commands are more efficiently executed. Referring to FIG. 9, for example, command queue 135 currently stores 13 read page commands, numbered "a" through "m", respectively. The processor core 133-1 records the read page command to read the specific LUN150 into a specific field in the schedule 900, for example, the read page commands "b", "a", "d" are placed into the schedule 900 to read the pages of the LUN150#0, the LUN 150#4, and the LUN 150#1, respectively, so that the processor core 133-1 can output the read page commands "b", "a", "d" to the LUN150#0, the LUN 150#4, and the LUN 150#1 in a synchronous and interleaved (interleaved) operation manner. The processor core 133-1 loads the read page commands "c", "e" to "m" into the standby table, and loads the read page commands "e", "c", "g" in the standby table into the schedule table 900 after the read page commands "b", "a", "d" in the schedule table 900 are executed. Then, the read page commands "j", "f", "k" in the standby table are discharged to the schedule 900, and finally, the read page commands "i", "m" in the standby table are discharged to the schedule 900. Thus, 13 read page commands require 4 cycles to complete. In some embodiments, the processor core 133-1 only builds and maintains the schedule 900, and sequentially stores the flash memory operation commands to the schedule 900, and after the processor core 133-1 has executed the first row of flash memory operation commands, continues to execute the next row of flash memory operation commands, and so on.
If the target data is 4KB or 8KB data in a page, then the controller 130 can utilize the command queue 135 to store fragment read commands instead of read page commands. Alternatively, the fragment read command in the command queue 135 is executed as an MPR-Lite command, i.e., a plurality of fragment read commands are integrated into one MPR-Lite command. When the plurality of segment read commands are integrated into one MPR-Lite command, the controller 130 needs to change the plurality of segment read commands into a plurality of read page multi-plane commands, the confirm command is 32h, and the last segment read command is not changed, and the confirm command is 20h, so that the controller 130 can not only execute the segment read commands in a synchronous and staggered operation manner, but also increase the execution efficiency of the segment read commands. Referring to fig. 11, the fragment read command "b" is to read target data in the LUN150#0, the fragment read commands "a" and "h" are to read target data of different planes in the LUN 150#4, and the fragment read commands "d" and "g" are to read target data of different planes in the LUN 150#1, so the controller 130 may execute the fragment read commands "a", "b", "d", "h" and "g" in MPR-Lite commands, and thus the controller 130 may execute 5 fragment read commands together instead of 3 fragment read commands, in other words, MPR-Lite commands may increase the execution efficiency of the fragment read commands by 66%.
In some embodiments, in response to the MPR Lite command as described above, the processor core 133-1 may implement the flash memory operation command ordering function as shown in fig. 10 when loading and executing a particular software or firmware command.
Step S1010: processor core 133-1 provides the MPR-Lite schedule data table in data cache 136. The MPR-Lite schedule data table provides a finer distinction for each LUN than the schedule 900 and the standby table 910 shown in fig. 9, which is advantageous for integrating two or more fragment read commands into one MPR-Lite operation.
Referring to the MPR-Lite schedule data table 1100 shown in FIG. 11, two columns, "Plane0/1" and "Plane2/3" may be included for each LUN for distinguishing fragment read commands into one of the columns of cells according to their physical address to be read. For example, the third column of the MPR-Lite schedule data table 1100 has a memory cell for recording fragment read commands for reading data on the planes 810 and/or 830; and wherein the fourth column of cells is used to record fragment read commands that read data on planes 850 and/or plane 870.
In addition, since data is programmed to the block, a default programming mode may be employed, such as: TLC or QLC mode, or SLC mode may be used. Different programming modes need to use different data reading modes to correctly read data, so when integrating multiple segment read commands into one MPR-Lite command, in order to correctly read data, the target data to be read by multiple segment read commands need to use the same programming mode, so the MPR-Lite schedule data table 1100 can be slightly adjusted to become an MPR-Lite schedule data table 1200, and referring to fig. 12, three columns of "Main P0/1", "SLC P2/3" and "QLC P2/3" can be included for each LUN, for distinguishing each flash memory operation command into one column of storage cells according to the physical address to be read and the mode to be used. For example, the fourth column of the memory cells in MPR-lite schedule data table 1200 is used to record flash memory operation commands to read data on planes 810 and/or 830, regardless of the read mode used; wherein the fifth column of cells is used to record flash memory operation commands that read data on planes 850 and/or 870 using SLC mode; and wherein the sixth column of cells is used to record flash memory operation commands that use QLC mode to read data on plane 850 and/or plane 870.
Next, referring to fig. 10, the processor core 133-1 repeatedly executes a loop (steps S1030 to S1090) for arranging each flash memory operation command in the command queue 135 to an appropriate cell in the MPR-Lite schedule data table. In each round, the details are as follows:
step S1030: processor core 133-1 retrieves physical address information for one or more flash memory operation commands that have not yet been ordered from command queue 135. If a flash memory operation command indicates to read data on Plane 830 and Plane 850, processor core 133-1 may arrange the flash memory operation command to a memory cell in a field associated with Plane 830, such as column "Plane0/1" in FIG. 11 or column "Main P0/1" in FIG. 12.
Step S1070: and arranging each flash memory operation command to an appropriate cell in the MPR-Lite schedule data table according to the physical address and other related information. Referring to the use case of fig. 11, the third column of the MPR-Lite schedule data table 1100 is used to record fragment read commands "a", "c", and "f" for reading data on planes 810 and/or 830; and wherein the fourth column of cells is used to record segment read commands "h" and "i" for reading data on planes 850 and/or plane 870.
In other embodiments of step S1070, other information related to the memory operation command may include what mode the flash memory operation command uses for reading. The processor core 133-1 can search the contents of the physical configuration data table in the data buffer 136, and know what mode the flash memory operation command needs to use for reading according to the programming mode of the block corresponding to the physical address. Referring to the use case of fig. 12, the fourth column of the MPR-Lite schedule data table 1200 is used to record fragment read commands "a" and "f" for reading data on planes 810 and/or 830; wherein the fifth column of cells is used to record segment read commands "h" and "i" that read data on planes 850 and/or 870 using SLC mode; and wherein the sixth column of cells is used to record segment read commands "c" that use QLC mode to read data on plane 850 and/or plane 870.
FIG. 13 shows a use case for selecting operation commands of the flash memory, following the sorting result shown in FIG. 11. For example, in one batch, the processor core 133-1 drives the flash interface 137 to send a read page command to the LUN150#0 for reading the data of the physical address specified by the fragment read command "b"; the read page multi-plane command is sent to LUN 150#4 for reading the data of the physical address specified by segment read commands "a" and "h", the read page multi-plane command is sent to LUN 150#1 for reading the data of the physical address specified by segment read command "d", and the segment read command is sent to LUN 150#1 for reading the data of the physical address specified by memory operation command "g" to form an MPR-lite operation.
FIG. 14 shows a use case for selecting memory operation commands, following the ordering results described in FIG. 12. For example, in one batch, the processor core 133-1 determines that the programming of the target data is SLC mode, and thus, drives the flash interface 137 to send a read page multi-plane command to the LUN150#0 for reading the data of the physical address specified by the fragment read command "b"; the read page multi-plane command is sent to LUN 150#4 for reading the data of the physical address specified by commands "a" and "h" and the segment read command is sent to LUN 150#1 for reading the data of the physical address specified by command "d" to form an MPR-lite operation.
By referring to the sorting result of the MPR-Lite schedule data table, the processor core 133-1 can execute the segment read command as described above batch by batch, but when the processor core 133-1 reads the segment data of the page on the multi-plane by the MPR-Lite command instead, the efficiency of data reading can be improved, and the efficiency of segment read operation can be improved. In the 4K random read Q64/T4 test, the MPR-Lite command may increase the average read data hit rate by approximately 30-50% compared to the segment read command. The hit rate of a read is defined as the fraction of data read from LUN150 through flash interface 137 that is retained for retrieval to host 110. For example, when the 8K data read by the fragment read command is all retained to be returned to the host 110, the hit rate of this read is 100%. When the 8K data read by the fragment read command is only half reserved for the host 110, the hit rate of this read is 50%.
All or part of the steps in the method described in the present application may be implemented in computer program code, such as the operating system of a computer, the driver code of specific hardware in a computer, or software program code. In addition, other types of programs as shown above may also be implemented. Those skilled in the art will not describe the methods of embodiments of the present application in the interest of brevity, which may be written as computer program code. Computer programs for implementing methods according to embodiments of the present application may be stored on a suitable computer readable data carrier, such as a DVD, CD-ROM, USB, hard disk, or may be located on a network server accessible via a network (e.g., the internet, or other suitable carrier).
Although the components described above are included in fig. 1, it is not excluded that many more additional components are used to achieve a better technical result without violating the spirit of the application. Further, although the flowchart of fig. 10 is performed in a specified order, a person skilled in the art can modify the order among these steps without departing from the spirit of the application, and therefore, the application is not limited to using only the order as described above. Furthermore, one skilled in the art may integrate several steps into one step or perform more steps in addition to these steps, sequentially or in parallel, and the application is not limited thereby.
While the application has been illustrated by the above examples, it should be noted that the description is not intended to limit the application. On the contrary, this application covers modifications and similar arrangements apparent to those skilled in the art. Therefore, the protection scope of the present application is defined by the claims.
Claims (8)
1. A computer readable storage medium for fragment data reading on multiple planes of a NAND flash memory having cross plane pages, for storing computer program code executable by a processing unit, the computer program code when executed by the processing unit implementing the steps of:
providing a scheduling data table;
arranging each memory operation command in a command queue to one cell in the schedule data table according to physical address information of the memory operation command;
selecting two or more memory operation commands for a logic unit number according to the content of the scheduling data table, wherein each selected memory operation command requests to read data less than the length of one cross-plane page;
driving a flash memory interface to complete a multi-page read compaction operation, reading data requested by the selected memory operation command from the logical unit number, wherein the multi-page read compaction operation comprises: driving the flash memory interface to send one or more page multi-plane reading commands, then sending a fragment reading command to the logic unit number, and reading data of a physical address designated by the selected memory operation command; and
and replying the read data to the host.
2. The computer-readable storage medium of claim 1, wherein the read page multi-plane command and the fragment read command are each for reading fragment data on different cross-plane pages.
3. The computer-readable storage medium for fragment data reading on a multi-plane of claim 1, wherein the read page multi-plane command and the fragment read command operate in one mode.
4. The computer readable storage medium for fragment data reading on a multiplanar of claim 3, wherein said pattern is a single-tier cell, a three-tier cell, or a four-tier cell pattern.
5. A method for reading fragment data on multiple planes of a NAND flash memory having cross-plane pages, performed by a processing unit, the method comprising:
providing a scheduling data table;
arranging each memory operation command in a command queue to one cell in the schedule data table according to physical address information of the memory operation command;
selecting two or more memory operation commands for a logic unit number according to the content of the scheduling data table, wherein each selected memory operation command requests to read data less than the length of one cross-plane page;
driving a flash memory interface to complete a multi-page read compaction operation, reading data requested by the selected memory operation command from the logical unit number, wherein the multi-page read compaction operation comprises: driving the flash memory interface to send one or more page multi-plane reading commands, then sending a fragment reading command to the logic unit number, and reading data of a physical address designated by the selected memory operation command; and
and replying the read data to the host.
6. The method of claim 5, wherein the wait data ready time required for the read page multi-plane command is shorter than the wait data ready time required for the fragment read command.
7. The method of claim 5, wherein each column of the schedule data table is used to record information of a memory operation command on a specific plane in a specific logical unit number.
8. The method of claim 5, wherein each column in the schedule data table is used to record information of a memory operation command for reading a first plane, a second plane and using a first mode, or the second plane and using a second mode in a specific logical unit number, the first mode being a single-layer unit mode, the second mode being a three-layer unit or a four-layer unit mode.
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| US11756644B2 (en) | 2021-06-23 | 2023-09-12 | International Business Machines Corporation | Triage of multi-plane read requests |
| CN114546289B (en) * | 2022-02-27 | 2023-06-02 | 苏州浪潮智能科技有限公司 | Method, system, equipment and medium for reading data |
| CN114546294B (en) * | 2022-04-22 | 2022-07-22 | 苏州浪潮智能科技有限公司 | Solid state disk reading method, system and related components |
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