WO2019148757A1

WO2019148757A1 - Non-volatile random access memory and method for providing same

Info

Publication number: WO2019148757A1
Application number: PCT/CN2018/093075
Authority: WO
Inventors: 路向峰; 田冰
Original assignee: 北京忆恒创源科技有限公司
Priority date: 2018-01-31
Filing date: 2018-06-27
Publication date: 2019-08-08
Also published as: CN110096452A

Abstract

A non-volatile random access memory (NVRAM) and a method for providing same. The provided non-volatile random access memory comprises: a control component, a random access memory (RAM) and an NVM chip, wherein the control component comprises an NVRAM management module; a part of the random access memory (RAM) and a part of the NVM chip provide an NVRAM service; the NVRAM management module accesses, according to an NVRAM address space, the random access memory (RAM) and NVM chip providing the NVRAM service; the random access memory (RAM) provides an efficient random access capability for the corresponding NVRAM address space; and the NVM chip provides a non-volatility capability for the update of the corresponding NVRAM address space.

Description

Nonvolatile random access memory and method of providing same

Cross-reference to related applications

The present application claims priority to Chinese Patent Application No. 2018100940602, the entire disclosure of which is hereby incorporated by reference.

Technical field

The present application relates to a non-Volatile Random Access Memory (NVRAM) and a method of providing the same.

Background technique

Figure 1 shows a block diagram of a solid state storage device. The solid state storage device 102 is coupled to the host for providing storage capabilities to the host. The host and the solid-state storage device 102 can be coupled in various manners, including but not limited to, for example, SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface). , SAS (Serial Attached SCSI), IDE (Integrated Drive Electronics), USB (Universal Serial Bus), PCIE (Peripheral Component Interconnect Express, PCIe, High Speed Peripheral Component Interconnect) NVMe (NVM Express, high speed nonvolatile storage), Ethernet, Fibre Channel, wireless communication network, etc. are connected to the host and solid state storage device 102. The host may be an information processing device capable of communicating with the storage device in the manner described above, such as a personal computer, tablet, server, portable computer, network switch, router, cellular telephone, personal digital assistant, and the like. The storage device 102 includes an interface 103, a control unit 104, one or more NVM chips 105, and a DRAM (Dynamic Random Access Memory) 110.

NAND flash memory, phase change memory, FeRAM (Ferroelectric RAM), MRAM (Magnetic Random Access Memory), RRAM (Resistive Random Access Memory), XPoint memory, etc. are common NVMs.

The interface 103 can be adapted to exchange data with the host via, for example, SATA, IDE, USB, PCIE, NVMe, SAS, Ethernet, Fibre Channel, and the like.

Control component 104 is used to control data transfers between interface 103, NVM chip 105, and DRAM 110, as well as for storage management, host logical address to flash physical address mapping, erase equalization, bad block management, and the like. The control unit 104 can be implemented in various manners of software, hardware, firmware, or a combination thereof. For example, the control unit 104 can be an FPGA (Field-programmable gate array) or an ASIC (Application Specific Integrated Circuit). Integrated circuit) or a combination thereof. Control component 104 may also include a processor or controller that executes software in the processor or controller to manipulate the hardware of control component 104 to process IO (Input/Output) commands. Control component 104 can also be coupled to DRAM 110 and can access data from DRAM 110. The DRAM can store data for FTL tables and/or cached IO commands.

The control component 104 includes a flash interface controller (or media interface controller, flash channel controller) coupled to the NVM chip 105 and issuing commands to the NVM chip 105 in a manner that follows the interface protocol of the NVM chip 105. To operate the NVM chip 105 and receive the command execution result output from the NVM chip 105. Known NVM chip interface protocols include "Toggle", "ONFI", and the like.

A memory target (Target) is one or more logical units (LUNs, Logic UNit) of a shared CE (Chip Enable) signal within a NAND flash package. One or more dies (Die) may be included in the NAND flash package. Typically, the logic unit corresponds to a single die. The logic unit can include a plurality of planes. Multiple planes within a logical unit can be accessed in parallel, while multiple logical units within a NAND flash chip can execute command and report states independently of each other.

Data is typically stored and read on a storage medium by page. And erase the data by block. A block (also called a physical block) contains multiple pages. A block contains multiple pages. A page on a storage medium (referred to as a physical page) has a fixed size, such as 17,664 bytes. Physical pages can also have other sizes.

In a solid-state storage device, FTL (Flash Translation Layer) is used to maintain mapping information from a logical address to a physical address. The logical address constitutes the storage space of the solid-state storage device perceived by the upper layer software such as the operating system. The physical address is the address of the physical storage unit used to access the solid state storage device. The address mapping can also be implemented in the related art using the intermediate address form. For example, a logical address is mapped to an intermediate address, and the intermediate address is further mapped to a physical address.

A table structure that stores mapping information from a logical address to a physical address is called an FTL table. FTL tables are important metadata in solid state storage devices. Usually, the data items of the FTL table record the address mapping relationship in units of data pages in the solid state storage device.

Each storage unit of the NVM storage medium can store 1 bit or more bits of information. For example, a storage unit that can store 1-bit information is called an SLC (Single Level Cell), and a storage unit that can store 2-bit information is called an MLC (Multiple Level Cell), and can store 3-bit information. The unit is called TLC (Triple Level Cell), and the storage unit that can store 4-bit information is called QLC (quadruple level Cell).

NVRAM is a memory that can be accessed randomly, and the data stored in NVRAM is not lost even if the power is turned off. The data stored in the NVRAM can be accessed again after the next power-up.

Summary of the invention

The present application is intended to provide NVRAM through a solid state storage device, and the provided NVRAM can be accessed by a host coupled to the solid state storage device and/or accessed by a controller of the solid state storage device.

According to a first aspect of the present application, there is provided a first nonvolatile random access memory according to the first aspect of the present application, comprising: a control unit, a random access memory RAM and an NVM chip, wherein the control unit comprises an NVRAM management module, The portion of the random access memory RAM and the portion of the NVM chip provide NVRAM service, and the NVRAM management module accesses the random access memory RAM and the NVM chip that provide the NVRAM service according to the NVRAM address space.

According to a first nonvolatile random access memory of the first aspect of the present application, there is provided a second nonvolatile random access memory according to the first aspect of the present application, wherein a storage space of the NVM chip providing the NVRAM service is organized For a plurality of large blocks, the storage space of the random access memory RAM providing the NVRAM service is organized into a plurality of memory slices, the NVRAM address space being organized into a plurality of small blocks, the NVRAM management module indicating according to the small blocks The chunk or slice of memory accesses the chunk or slice of memory.

According to the first or second nonvolatile random access memory of the first aspect of the present application, there is provided a third nonvolatile random access memory according to the first aspect of the present application, wherein the random access memory RAM is a dynamic random access memory DRAM.

According to a third nonvolatile random access memory of the first aspect of the present application, there is provided a fourth nonvolatile random access memory according to the first aspect of the present application, wherein part or all of the dynamic random access memory DRAM is Static random access memory SRAM replacement.

According to the first or second nonvolatile random access memory of the first aspect of the present application, there is provided a fifth nonvolatile random access memory according to the first aspect of the present application, wherein the NVRAM address space is a continuous address space.

According to the first or second nonvolatile random access memory of the first aspect of the present application, there is provided a sixth nonvolatile random access memory according to the first aspect of the present application, wherein the NVRAM management module maintains an NVRAM address space.

According to a sixth nonvolatile random access memory of the first aspect of the present application, there is provided a seventh nonvolatile random access memory according to the first aspect of the present application, wherein each of the small blocks occupies an area of the NVRAM address space The same size.

According to a sixth or seventh nonvolatile random access memory of the first aspect of the present application, there is provided an eighth nonvolatile random access memory according to the first aspect of the present application, wherein the NVRAM management module is based on an NVRAM address space Address, calculate the small block corresponding to the address.

According to an eighth nonvolatile random access memory of the first aspect of the present application, there is provided a ninth nonvolatile random access memory according to the first aspect of the present application, wherein the NVRAM management module divides the address of the NVRAM address space by The size of the NVRAM address space corresponding to the small block gets the index of the small block.

According to a second nonvolatile random access memory of the first aspect of the present application, there is provided a tenth nonvolatile random access memory according to the first aspect of the present application, wherein the size of the memory chip is the same as the size of the small block.

According to a second nonvolatile random access memory of the first aspect of the present application, there is provided an eleventh nonvolatile random access memory according to the first aspect of the present application, wherein the large block comprises: a base chunk and a large log A block, the base chunk is used to store data, and the log chunk is used to record modifications to the NVRAM address space.

According to an eleventh nonvolatile random access memory of the first aspect of the present application, there is provided a twelfth nonvolatile random access memory according to the first aspect of the present application, wherein the storage space of the large block is organized into a frame .

According to a twelfth nonvolatile random access memory of the first aspect of the present application, there is provided a thirteenth nonvolatile random access memory according to the first aspect of the present application, wherein the NVRAM management module organizes a log chunk frame For the linked list.

According to a twelfth or thirteenth nonvolatile random access memory of the first aspect of the present application, there is provided a fourteenth nonvolatile random access memory according to the first aspect of the present application, wherein the NVRAM management module has a large log Each log chunk frame within the block is organized into a linked list.

According to a twelfth nonvolatile random access memory of the first aspect of the present application, there is provided a fifteenth nonvolatile random access memory according to the first aspect of the present application, wherein the size of the frame is the same as the size of the small block .

According to a twelfth nonvolatile random access memory of the first aspect of the present application, there is provided a sixteenth nonvolatile random access memory according to the first aspect of the present application, wherein, in response to writing to an address NADDR of an NVRAM address space Data D, the NVRAM management module generates a log entry that records <NADDR, D>, and the NVRAM management module writes the log entry to the log chunk frame.

According to the eleventh or twelfth nonvolatile random access memory of the first aspect of the present application, there is provided a seventeenth nonvolatile random access memory according to the first aspect of the present application, wherein the address in response to the address space to the NVRAM NADDR writes data D, and the NVRAM management module records the data D in a memory slice corresponding to the address NADDR.

According to a twelfth nonvolatile random access memory of the first aspect of the present application, there is provided an eighteenth nonvolatile random access memory according to the first aspect of the present application, wherein the random access memory RAM stores a small block conversion A table, the small block conversion table includes a plurality of entries, each entry corresponding to one of the small blocks, the value of the entry recording the address of the underlying chunky frame or the address of the memory slice that provides data for the tile.

According to an eighteenth nonvolatile random access memory of the first aspect of the present application, there is provided a nineteenth nonvolatile random access memory according to the first aspect of the present application, wherein an NVRAM address space address larger than a threshold is mapped as a basis The address of a large block of frames, mapping the NVRAM address space address that is not greater than the threshold to the address of the memory slice.

According to an eighteenth nonvolatile random access memory of the first aspect of the present application, there is provided a twentieth nonvolatile random access memory according to the first aspect of the present application, wherein a flag is recorded in an entry, and a flag bit is used for The value of the indication entry indicates the address of the underlying chunky frame or the address of the memory slice.

According to a twelfth nonvolatile random access memory of the first aspect of the present application, there is provided a twenty-first nonvolatile random access memory according to the first aspect of the present application, wherein the NVRAM management module maintains NVRAM metadata.

According to a twenty-first nonvolatile random access memory of the first aspect of the present application, there is provided a twenty-second nonvolatile random access memory according to the first aspect of the present application, wherein the NVRAM metadata recording log chunk header And a memory slice descriptor header; the log chunk header is an address of the log chunk frame, and indicates a head node of the log chunk frame list; the memory slice descriptor header is a memory slice descriptor address, and indicates The head node of the memory slice descriptor list.

According to a twenty-second nonvolatile random access memory of the first aspect of the present application, there is provided a twenty-third nonvolatile random access memory according to the first aspect of the present application, wherein the memory slice descriptor is used for description Memory chip.

According to a twenty-second or twenty-third nonvolatile random access memory of the first aspect of the present application, there is provided a twenty-fourth nonvolatile random access memory according to the first aspect of the present application, wherein the memory slice descriptor record The basic chunk frame address corresponding to the memory slice.

According to a twenty-second or twenty-third nonvolatile random access memory of the first aspect of the present application, there is provided a twenty-fifth nonvolatile random access memory according to the first aspect of the present application, wherein the memory slice descriptor record The state of the memory chip.

According to a twenty-second or twenty-third nonvolatile random access memory of the first aspect of the present application, there is provided a twenty-sixth nonvolatile random access memory according to the first aspect of the present application, wherein the memory chip and The memory slice descriptors are in one-to-one correspondence.

According to a twenty-second to twenty-sixth nonvolatile random access memory of the first aspect of the present application, there is provided a twenty-seventh nonvolatile random access memory according to the first aspect of the present application, wherein the memory chip description The symbols are organized into linked lists.

According to a second aspect of the present application, there is provided a first method of providing a nonvolatile random access memory according to the second aspect of the present application, comprising the steps of: identifying an accessed NVRAM address space; identifying an address of the accessed NVRAM address space being mapped The address to the basic chunk frame is also the memory slice address; the data to be accessed is obtained from the basic chunk frame or the memory slice according to the recognition result.

According to a first method of providing a nonvolatile random access memory according to a second aspect of the present application, there is provided a second method of providing a nonvolatile random access memory according to the second aspect of the present application, wherein the base chunk frame is located at the NVM A memory cell of a memory block of a chip, which is a memory cell located in a volatile memory.

According to a first or second method of providing a nonvolatile random access memory according to a second aspect of the present application, there is provided a third method of providing a nonvolatile random access memory according to the second aspect of the present application, wherein The address of the NVRAM address space, generates a small block index (ID); accesses the small block conversion table according to the small block index (ID); acquires the small block conversion table entry according to the address of the NVRAM address space to be accessed, and identifies according to the small block conversion table entry The address of the NVRAM address space to be accessed is mapped to the address of the underlying chunky frame or the memory slice address.

According to a third method of providing a nonvolatile random access memory according to the second aspect of the present application, there is provided a fourth method of providing a nonvolatile random access memory according to the second aspect of the present application, wherein the NVRAM address space is provided by a small block Multiple small blocks together provide a complete NVRAM address space.

According to a first to fourth method of providing a nonvolatile random access memory according to a second aspect of the present application, there is provided a method of providing a nonvolatile random access memory according to a fifth aspect of the second aspect of the present application, further comprising: from to be accessed The address of the NVRAM address space generates an offset value, and for data read from the base chunk frame, the data to be accessed is obtained by offset value addressing.

According to a first to fourth method of providing a nonvolatile random access memory according to a second aspect of the present application, there is provided a sixth method of providing a nonvolatile random access memory according to the second aspect of the present application, further comprising: from to be accessed The address of the NVRAM address space generates an offset value, and the data to be accessed is obtained from the memory slice.

According to a third or fourth method of providing a nonvolatile random access memory according to the second aspect of the present application, there is provided a method of providing a nonvolatile random access memory according to the seventh aspect of the second aspect of the present application, wherein if the small block conversion The table entry records the memory slice address, and obtains the data to be accessed from the memory slice; if the small block conversion table entry records the address of the basic large block frame, the memory slice is allocated for the basic large frame frame to be acquired, and will be waiting for The basic chunk frame of the acquired data reads out the data to be accessed and writes the allocated memory slice, and acquires the data to be accessed from the allocated memory slice.

A method of providing a nonvolatile random access memory according to a seventh aspect of the second aspect of the present application, provides a method of providing a nonvolatile random access memory according to the eighth aspect of the second aspect of the present application, further comprising: using the allocated memory The slice address updates the small block conversion table entry.

According to a third aspect of the present application, there is provided a first method of providing a nonvolatile random access memory according to the third aspect of the present application, comprising the steps of: identifying an NVRAM address space to be written data; identifying data to be written The address of the NVRAM address space is mapped to the address of the base chunk frame or the memory slice address; if the address of the NVRAM address space to be written to the data is the memory slice address, data is written to the memory slice; to be written The address of the NVRAM address space of the data is the address of the base chunk frame, and a log entry is generated in which the NVRAM address space address NADDR to be written data and the data D to be written are recorded, and the log entry is written into the log chunk frame. .

According to a first method of providing a nonvolatile random access memory of a third aspect of the present application, there is provided a second method of providing a nonvolatile random access memory according to the third aspect of the present application, wherein the base chunk frame is located at the NVM The storage unit of the storage block of the chip, the log chunk frame is located in the storage unit of the storage block of the NVM chip, and the memory slice is a storage unit located in the volatile memory.

According to a first or second method of providing a nonvolatile random access memory according to a third aspect of the present application, there is provided a third method of providing a nonvolatile random access memory according to the third aspect of the present application, wherein Enter the address of the NVRAM address space of the data, generate a small block index (ID); access the small block conversion table according to the small block index (ID); obtain the small block conversion table entry according to the address of the NVRAM address space to be written data, according to The small block conversion table entry identifies whether the address of the NVRAM address space to which the data is to be written is mapped to the address of the underlying chunky frame or the memory slice address.

According to a third method of providing a nonvolatile random access memory of the third aspect of the present application, there is provided a fourth method of providing a nonvolatile random access memory according to the third aspect of the present application, wherein the NVRAM address space is provided by a small block Multiple small blocks together provide a complete NVRAM address space.

According to a first to fourth method of providing a nonvolatile random access memory of a third aspect of the present application, there is provided a method of providing a nonvolatile random access memory according to a fifth aspect of the third aspect of the present application, further comprising: if the small block The conversion table entry records the memory slice address. After the data is written to the memory slice, a log entry is generated; the log entry is written to the log chunk frame.

According to a fifth method of providing a nonvolatile random access memory of the third aspect of the present application, there is provided a sixth method of providing a nonvolatile random access memory according to the third aspect of the present application, wherein the log entry records to be written The NVRAM address space address of the incoming data is NVRAM and the data D being written.

According to a first to sixth method of providing a nonvolatile random access memory of a third aspect of the present application, there is provided a method of providing a nonvolatile random access memory according to a seventh aspect of the third aspect of the present application, wherein After the address space address NADDR writes the data D to generate a log entry, it indicates that the write data processing to the NVRAM address space is completed.

A method of providing a nonvolatile random access memory according to the first to seventh aspects of the third aspect of the present application, there is provided a method of providing a nonvolatile random access memory according to the eighth aspect of the third aspect of the present invention, wherein a log entry is generated, The log entry is written to the log chunk frame, indicating that the write data processing of the NADDR address space is complete.

According to a fourth aspect of the present application, there is provided a first method of providing a nonvolatile random access memory according to the fourth aspect of the present application, comprising the steps of: identifying an NVRAM address space to be written data; according to data to be written The address of the NVRAM address space generates a log entry that records the NVRAM address space address NVRAM to be written with data and the data D to be written; writes the log entry to the log chunk frame.

According to a first method of providing a nonvolatile random access memory according to a fourth aspect of the present application, there is provided a second method of providing a nonvolatile random access memory according to the fourth aspect of the present application, wherein the log chunk frame is located in the NVM chip The storage unit of the storage block.

According to a first or second method of providing a nonvolatile random access memory according to a fourth aspect of the present application, there is provided a third method for providing a nonvolatile random access memory according to the fourth aspect of the present application, further comprising: identifying that a write is to be performed The address of the NVRAM address space of the incoming data is mapped to the address or the memory slice address of the underlying chunky frame; if the address of the NVRAM address space to which the data is to be written is the memory slice address, data is written to the memory slice.

According to a third method of providing a nonvolatile random access memory according to the fourth aspect of the present application, there is provided a fourth method for providing a nonvolatile random access memory according to the fourth aspect of the present application, wherein the memory chip is located in a volatile The storage unit of the memory.

According to a third or fourth method of providing a nonvolatile random access memory according to the fourth aspect of the present application, there is provided a method of providing a nonvolatile random access memory according to a fifth aspect of the fourth aspect of the present application, wherein Enter the address of the NVRAM address space of the data, generate a small block index (ID); access the small block conversion table according to the small block index (ID); obtain the small block conversion table entry according to the address of the NVRAM address space to be written data, according to The small block conversion table entry identifies whether the address of the NVRAM address space to which the data is to be written is mapped to the address of the underlying chunky frame or the memory slice address.

According to a fifth method of providing a nonvolatile random access memory of the fourth aspect of the present application, there is provided a sixth method of providing a nonvolatile random access memory according to the fourth aspect of the present application, wherein the NVRAM address space is provided by a small block Multiple small blocks together provide a complete NVRAM address space.

According to a fifth or sixth method of providing a nonvolatile random access memory according to the fourth aspect of the present application, there is provided a method of providing a nonvolatile random access memory according to a seventh aspect of the fourth aspect of the present application, wherein the generating is performed concurrently Log entries and generate small block indexes (IDs).

According to a third to seventh method of providing a nonvolatile random access memory according to the fourth aspect of the present application, there is provided a method of providing a nonvolatile random access memory according to the eighth aspect of the fourth aspect of the present application, wherein writing to a memory chip The entry data and the generated log entry are completed, indicating that the write data processing of the NVRAM address space is completed.

According to a fifth aspect of the present application, there is provided a first method for providing a nonvolatile random access memory according to the fifth aspect of the present application, comprising the steps of: scanning a memory slice descriptor linked list in response to powering up; acquiring each memory slice The address of the base chunk frame corresponding to the memory slice recorded in the descriptor; the data is read from the base chunk frame and the read data is written into the memory slice.

According to a first method of providing a nonvolatile random access memory according to a fifth aspect of the present application, there is provided a second method of providing a nonvolatile random access memory according to the fifth aspect of the present application, wherein the base chunk frame is located at the NVM A memory cell of a memory block of a chip, which is a memory cell located in a volatile memory.

According to a second method of providing a nonvolatile random access memory according to a fifth aspect of the present application, there is provided a third method for providing a nonvolatile random access memory according to the fifth aspect of the present application, further comprising: scanning a log chunk frame linked list ; read log entries from log chunks in the log chunk frame list; update the memory slices with log entries.

According to a third method of providing a nonvolatile random access memory according to a fifth aspect of the present application, there is provided a fourth method of providing a nonvolatile random access memory according to the fifth aspect of the present application, wherein the log chunk frame is located at the NVM The memory unit of the memory block of the chip.

According to a fourth method of providing a nonvolatile random access memory according to the fifth aspect of the present application, there is provided a method of providing a nonvolatile random access memory according to the fifth aspect of the fifth aspect of the present application, further comprising: when the power is off, the memory is The slice descriptor is written to the NVM chip.

The non-volatile random access memory and the method for providing the same provided by the present application provide efficient random access for the corresponding NVRAM address space through the memory chip, and the log large block of the log chunk records the log entry <NADDR, D>, Provides non-volatile capabilities for updating the corresponding NVRAM address space.

DRAWINGS

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings to be used in the embodiments or the prior art description will be briefly described below. Obviously, the drawings in the following description are only These are some of the embodiments described in this application, and other figures can be obtained from those of ordinary skill in the art in view of these drawings.

1 is a block diagram of a related art solid state storage device;

2 is a block diagram of an NVRAM provided by an embodiment of the present application;

3 is a schematic diagram of an NVRAM address space provided by an embodiment of the present application;

FIG. 4 shows a small block conversion table provided by an embodiment of the present application;

FIG. 5 is a block diagram showing a data organization for providing an NVRAM service according to an embodiment of the present application;

6A is a flowchart of processing an NVRAM read request provided by an embodiment of the present application;

6B is a flowchart of processing an NVRAM read request provided by another embodiment of the present application;

6C is a flowchart of processing an NVRAM write request provided by another embodiment of the present application;

6D is a flow chart showing processing of an NVRAM write request provided by still another embodiment of the present application;

FIG. 7 is a flowchart of power-on recovery NVRAM provided by an embodiment of the present application.

Detailed ways

The technical solutions in the embodiments of the present application are clearly and completely described in the following with reference to the accompanying drawings in the embodiments of the present application. It is obvious that the described embodiments are a part of the embodiments of the present application, and not all of the embodiments. All other embodiments obtained by a person skilled in the art based on the embodiments of the present application without creative efforts are within the scope of the present application.

2 is a block diagram of an NVRAM provided by an embodiment of the present application.

According to an embodiment of the present application, the NVRAM is provided by the solid state storage device 102. By way of example, the structure of the solid state storage device according to Fig. 2 can be employed. The control component 204 of the solid state storage device 102 also includes an NVRAM management module that provides the NVRAM service 200 by using portions of the DRAM 110 and portions of the NVM chip 105. Alternatively, SRAM is used to partially or completely replace the DRAM. The SRAM can be integrated inside the control component 204. The NVRAM service is provided by using a portion of the DRAM 110 in accordance with the embodiment of FIG. 2, and the SRAM may be used to partially or completely replace the DRAM. The NVRAM management module is implemented by, for example, software running in the CPU of the control unit 204, firmware, and/or hardware as part of the ASIC.

The host is coupled to the solid state storage device 102 via interface 103. The host accesses the NVRAM service 200 provided by the solid state storage device 102 through the interface 103. For example, solid state storage device 102 is coupled to the host via a PCIe interface, mapping the NVRAM to a memory space of the PCIe device. The host accesses the NVRAM service provided by the solid state storage device 102 in a manner that accesses the memory space of the PCIe device, so that the host can use the NVRAM service without modification. As yet another example, NVRAM is provided to the host as a standalone PCIe device.

The NVRAM management module also serves other components of control component 204. For example, other programs running in the CPU of control component 204 may use NVRAM services. These programs use the NVRAM service in a way that accesses local memory (SRAM or DRAM). Alternatively, the NVRAM service is organized as a file or object, and other programs running in the CPU of the control unit 204 use the NVRAM service in a manner that accesses files or objects.

FIG. 3 is a schematic diagram of an NVRAM address space provided by an embodiment of the present application. By way of example, the NVRAM address space is a contiguous address space. The NVRAM management module maintains the NVRAM address space. The direction from top to bottom in Figure 3 is the direction in which the NVRAM address space is incremented. The NVRAM address space includes a plurality of regions of the same size, each of which is referred to as a small block. A plurality of small blocks are shown in Fig. 3, including small block 0, small block 1 ... small block 5. For example, the size of the NVRAM address space corresponding to each tile may be, for example, 512 bytes, 1 KB, or 4 KB. According to the address of the NVRAM address space, the small block corresponding to the address can be calculated. For example, the address of the NVRAM address space is divided by the size of the NVRAM address space corresponding to the small block, and the resulting quotient is the index or small block number (ID) of the small block.

In one embodiment, the host operating with the NVRAM service or other program running in the CPU of control component 204 (collectively referred to as an application) uses NVRAM in the NVRAM address space. For example, the NVRAM address space is directly mapped to the memory space of the PCIe device, and the NVRAM address space address is obtained directly or through a specified offset through the memory space address of the PCIe device.

In another embodiment, the address space used by the application to use the NVRAM service (eg, the storage space of the PCIe device, or the offset value of the file) requires an address of the NVRAM address space through address translation. The NVRAM management module also provides an address translation table for mapping the address space used by the application to the NVRAM address space.

FIG. 4 shows a small block conversion table provided by an embodiment of the present application. The NVRAM management module maintains a small block conversion table. The tile conversion table includes a plurality of entries, each entry corresponding to one of the tiles, and indexed by the tile ID, the value of the entry recording the address of the underlying chunk frame or the address of the memory slice providing the data for the tile. The basic chunk frame and the memory slice will be described in detail later. Optionally, based on the value of the entry, the value is identified to indicate the address of the underlying chunky frame or the address of the memory slice. For example, an entry value greater than a threshold is mapped to an address of a base chunk frame, and an entry value not greater than a threshold is mapped to an address of a memory slice. As yet another example, a flag bit is also recorded in the entry to indicate whether the value of the entry indicates the address of the underlying chunky frame or the address of the memory slice.

The tile conversion table is stored, for example, in DRAM 110 (see also Figure 2) or SRAM. The NVRAM management module calculates a corresponding small block ID according to the accessed NVRAM address space address, and queries the small block conversion table with the small block ID to obtain the address of the basic large frame or the address of the memory slice for providing data for the small block.

FIG. 5 is a block diagram showing the data organization for providing an NVRAM service provided by an embodiment of the present application. By way of example, the NVRAM management module uses portions of the NVM chip 105 (denoted as NVM chip 510) and portions of DRAM 110 (denoted as DRAM 520).

The storage space of the NVM chip 510 is organized into chunks. A large block is a single physical block such as an NVM chip, a plurality of physical blocks of the same physical block number of each plane in the LUN of the NVM chip, or physical blocks from a plurality of LUNs. Optionally, the chunks also include parity data for providing protection for bulk stored data. Still optionally, multiple copies of the data are stored in chunks for providing protection for bulk stored data. Alternatively, the SLC storage unit of the NVM chip 105 is used as the NVM chip 510.

The chunks of storage are organized into frames (see chunk 512). Bulk 512 includes multiple frames. The size of the frame is the same as the size of the small block, so that the data stored in the NVRAM address space corresponding to one small block can be recorded in one frame.

Large chunks include at least two types, basic chunks and large chunks of logs. The basic chunk of the frame is called the base chunk frame. Referring back to Figure 4, the value of the entry of the entry of the small block conversion table is the address of the underlying chunky frame indicating the underlying chunky frame. The underlying chunky frame is accessible based on the address of the underlying chunky frame.

With continued reference to Figure 5, the memory space of DRAM 520 is organized into memory slices. The memory chip is a piece of storage space such as DRAM 520. The size of the memory chip is the same as the size of the small block, so that the data stored in the NVRAM address space corresponding to a small block can be recorded in a memory chip. Referring back to Figure 4, the value of the entry of the small block conversion table records the address of the memory slice, indicating the memory slice. The memory slice can be accessed according to the address of the memory chip.

With continued reference to FIG. 5, the value of the entry (small block 0) of the tile conversion table indicates the address of the base chunk frame located at base chunk 514. The value of the entry (small block 1) of the small block conversion table indicates the address of the memory slice 526. The memory slice 526 is a copy of the base chunk 516 of the base chunk 516 in the DRAM 520 (in FIG. 5, indicated by the dashed line). The NVRAM management module accesses the memory slice 526 by the value of the entry (small block 1) of the small block conversion table as an alternative to the base large block of the access base block 516 to efficiently access the corresponding block 1 in bytes. NVRAM address space.

The log chunk is used to record changes to the NVRAM address space. For example, writing data D to the address NADDR of the NVRAM address space generates a log entry, recording <NADDR, D>. The NVRAM management module writes log entries for <NADDR,D> to the log chunk frame. The NVRAM management module organizes log chunks into, for example, a linked list to facilitate access to multiple log chunks. For example, referring to FIG. 5, one log chunk frame (L1) of log chunk 532 records the address of one log chunk frame (L2) of log chunk 534, and one log chunk frame of log chunk 534 (L3). The address of one log chunk frame (L4) of the log chunk 536 is recorded, and a log chunk frame (L5) of the log chunk 536 records the address of a log chunk frame (L6) of the log chunk 538. Alternatively or further, the address of the log chunk frame (L1) of the log chunk 532 is recorded in the log chunk frame (L2) of the log chunk 534, and the log chunk frame of the log chunk 534 (L3) The address is recorded in the log chunk frame of the log chunk 536 (L4), and the address of the log chunk frame (L5) of the log chunk 536 is recorded in the log chunk frame (L6) of the log chunk 538.

Individual log chunks within the log chunk are also organized into, for example, a linked list. For example, the address of another log frame of log chunk 532 is recorded in one of the log frames of log chunk 532.

Still as an example, the application modifies the NVRAM address space corresponding to the entry of the small block conversion table (small block 1), writes the data D to the address NADDR of the NVRAM address space, and generates the log entry of the recorded <NADDR, D>. A log chunk of the log chunk 538 is written. Since the log chunk 538 is the storage space of the NVM chip, the log written to the log chunk 538 has a non-volatile characteristic. Even if the storage device is powered off, the next time the storage device is powered on, the log chunk 538 can still be read. Log entries for <NADDR,D> are recorded.

In response to the application writing data D to the address NADDR of the NVRAM address space, the NVRAM management module also records the data D in the memory slice 526 corresponding to the address NADDR. Since the memory chip is the storage space provided by the DRAM 520, it can be byte-addressed or randomly accessed, thereby efficiently performing the operation of recording the data D in the memory chip 526.

According to an embodiment of the present application, the memory slice 526 provides the ability to efficiently random access corresponding to the NVRAM address space of the tile 1, while the log chunk frame of the log chunk 538 records the log entry <NADDR, D>, corresponding to The update of the NVRAM address space for Tile 1 provides non-volatile capabilities. The NVRAM address space, which has both random access and non-volatile capabilities, provides NVRAN services to applications.

Optionally, according to an embodiment of the present application, the NVRAM management module also maintains NVRAM metadata. The NVRAM metadata records, for example, a log chunk header and a memory slice descriptor header. The log chunk header is the address of the log chunk frame and indicates the head node of the log chunk frame list. Through the head node of the log chunk frame list, all nodes of the log chunk frame list can be traversed. The memory slice descriptor header is the memory slice descriptor address and indicates the head node of the memory slice descriptor linked list.

Still optionally, the memory slice descriptor is used to describe the memory slice. The used memory chip has a one-to-one correspondence with the memory slice description. Memory descriptors are organized into, for example, linked lists. Still as an example, the memory slice descriptor records the basic chunk frame address corresponding to the memory slice, and the memory slice descriptor also records the state of the memory slice, for example, the memory slice is being written to the data from the base large frame, the memory The slice data is being written to the base chunk frame, and the data of the memory slice is the same or different from its corresponding base chunk frame.

FIG. 6A is a flowchart of processing an NVRAM read request provided by an embodiment of the present application.

The application reads data from NVRAM. In one example, the application reads data from the NVRAM in a manner that accesses memory; in yet another example, the application reads data from the NVRAM in a manner that accesses the file or object.

The NVRAM management module identifies the application to read data from the NVRAM. For example, the NVRAM management module recognizes that the application accesses the NVRAM address space, or the application accesses a file or object that provides the NVRAM service. The NVRAM management module generates a small block index (small block ID) (A610) according to the address of the NVRAM address space to be read by the application. The small block conversion table is queried according to the small block index (see also Figs. 3 - 5) (A620). Based on the value of the small block conversion table entry, it is identified whether the value records the address of the base chunk frame or the address of the memory slice (A630). If the small block conversion table entry records the address of the basic large block frame, the data to be accessed is read from the basic large block frame (A640); if the small block conversion table entry records the memory slice address, the read from the memory slice Data to be accessed (A650).

Optionally, the NVRAM management module also generates an offset value from the address of the NVRAM address space to be read (eg, the specified bit of the address as an offset value). For data read from the base chunk frame, the offset value is used to address the data to be read. For the memory slice, the data in the DRAM 520 is read as a result of the memory slice address plus the offset value (see also Figure 5).

6B shows a flow chart of processing an NVRAM read request in accordance with yet another embodiment of the present application. The application reads data from NVRAM. The NVRAM management module identifies the NVRAM address space to be read by the application. The NVRAM management module generates a small block index (small block ID) (B610) according to the address of the NVRAM address space to be read by the application. The small block conversion table is queried according to the small block index (see also Figs. 3 - 5) (B620). According to the value of the small block conversion table entry, it is identified whether the value records the address of the base large frame or the address of the memory slice (B630). If the small block conversion table entry records the memory slice address, the data to be accessed is read from the memory slice (B650). If the small block conversion table entry records the address of the basic large block frame, and allocates a memory slice for the basic large block frame to be read, the data to be accessed is read from the basic large block frame and written into the allocated memory slice (B640). Read the data to be accessed from the allocated memory slice. And updating the entry of the small block conversion table (B660) with the address of the allocated memory slice to record the allocated memory slice address in the small block conversion table entry corresponding to the address of the NVRAM address space to be read.

Optionally, the allocated memory slice in DRAM 520 is accessed with the assigned memory slice address plus the offset value generated from the address of the NVRAM address space to be read.

6C is a flow chart showing processing of an NVRAM write request provided by another embodiment of the present application.

The application writes data to NVRAM. The NVRAM management module identifies the NVRAM address space in which the application is to write data. The NVRAM management module generates a small block index (small block ID) (C610) according to the address of the NVRAM address space to be written by the application. The small block conversion table is queried according to the small block index (see also FIG. 3 to FIG. 5) (C620). Based on the value of the small block conversion table entry, it is identified whether the value records the address of the base chunk frame or the address of the memory slice (C630). If the small block conversion table entry records the memory slice address, the data is written to the memory slice (C650). If the small block conversion table entry records the address of the base large block frame, a log entry (C640) in which the NVRAM address space address NADDR to be accessed and the written data D are recorded is generated, and the log entry is written to the log. Block frame (C660).

For the case where the small block conversion table entry records the memory slice address, a log is also generated after the data is written to the memory slice. The log records the log entry of the NVRAM address space address NADDR to be accessed and the data D being written, and writes the log entry to the log chunk frame.

Optionally, after the log entry is generated for the write request, the write request processing indicating to the application that the NVRAM address space is completed is completed. The solid state storage device provides backup power to ensure that even if the solid state storage device is powered down, the generated logs are written to the log chunks or recorded on the NVM chip 520.

6D is a flow chart showing processing of an NVRAM write request provided by still another embodiment of the present application. The application writes data to NVRAM. The NVRAM management module identifies the NVRAM address space (D610) to which the application is to write data. The NVRAM management module generates a log entry (D620) that records the NVRAM address space address NADDR to be accessed and the data D to be written, and writes the log entry to the log chunk frame, according to the address of the NVRAM address space to be written by the application. (D630). Optionally, after the log entry is generated for the write request, the write request processing indicating to the application that the NVRAM address space is completed is completed.

The NVRAM management module generates a small block index (small block ID) (D640) according to the address of the NVRAM address space to which the application is to be written. The small block conversion table is also queried according to the small block index (see also FIG. 3 to FIG. 5) (D650). Based on the value of the small block conversion table entry, it is identified whether the value records the address of the base chunk frame or the address of the memory slice (D660). If the small block conversion table entry records the memory slice address, data is also written to the memory slice (D670).

Optionally, the NVRAM management module concurrently performs an operation of generating a log and generating a small block index (small block ID), and completing any one of writing data to the memory chip and generating a log, that is, applying a write request indicating the NVRAM address space. Processing is complete. Thereby reducing the processing delay of the write request of the NVRAM address space.

According to an embodiment of the present application, when the solid state storage device providing the NVRAM service is powered on, the NVRAM management module prepares to provide the NVRAM service through the flow shown in FIG. In response to the power-on, the NVRAM management module scans the memory slice descriptor list (710), and for each memory slice descriptor, obtains the address of the basic large frame corresponding to the memory slice recorded in the memory slice descriptor, and is larger from the base. The block frame reads the data and writes the read data to the memory slice (720).

The NVRAM management module also scans the log chunk frame list. The log entry record is read from the log chunk frame in the log chunk frame list, and the memory slice is updated with the log entry record (730). For example, the log entry record indicates the NVRAM address space address NADDR and the data D to be written, accesses the small block conversion table according to the NVRAM address space address NADDR to obtain the corresponding memory slice, and writes the data D to the memory slice.

As an example, the NVRAM management module obtains the head node of the memory slice descriptor list from the NVRAM metadata, and the head node of the log block frame list.

Optionally, the NVRAM metadata records the tail node of the memory slice descriptor list and the tail node of the log chunk frame list. And when the NVRAM is restored on the solid state storage device, the NVRAM management module obtains the tail node of the memory slice descriptor list from the NVRAM metadata, and the tail node of the log block frame list.

When the solid state storage device is powered down, the NVRAM management module writes the NVRAM metadata, the small block conversion table, and/or the memory slice descriptor to the NVM chip 520 for use in restoring NVRAM the next time power is applied.

According to an embodiment of the present application, a solid state storage device is provided, which includes a controller and a nonvolatile memory chip, wherein the controller performs any one of the processing methods provided by the embodiments of the present application.

A program stored on a readable medium, when executed by a controller of a solid state storage device, causes the solid state storage device to perform any of the processing methods provided in accordance with embodiments of the present application, in accordance with an embodiment of the present application.

While the preferred embodiment of the present application has been described, it will be apparent that those skilled in the art can make further changes and modifications to the embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and the modifications and It will be apparent to those skilled in the art that various modifications and changes can be made in the present application without departing from the spirit and scope of the application. Thus, it is intended that the present invention cover the modifications and variations of the present invention.

Claims

A nonvolatile random access memory comprising: a control component, a random access memory RAM, and an NVM chip, wherein the control component comprises an NVRAM management module, the portion of the random access memory RAM and a portion of the NVM chip providing an NVRAM service, The NVRAM management module accesses a random access memory RAM and an NVM chip that provide NVRAM services according to an NVRAM address space.
The nonvolatile random access memory according to claim 1, wherein a storage space of said NVM chip providing NVRAM service is organized into a plurality of large blocks, and a storage space of a random access memory RAM providing NVRAM service is organized into a plurality of A memory chip, the NVRAM address space is organized into a plurality of small blocks, and the NVRAM management module accesses the large block or the memory chip according to the address of the large block or the memory slice indicated by the small block.
A nonvolatile random access memory according to claim 2, wherein said large block comprises: a base chunk for storing data, and said log chunk is for recording a pair of NVRAM addresses Modification of space.
The nonvolatile random access memory according to any one of claims 1 to 3, wherein the NVRAM management module calculates a small block corresponding to the address according to an address of the NVRAM address space.
The nonvolatile random access memory of claim 4, wherein the NVRAM management module obtains an index of the small block according to the address of the NVRAM address space divided by the size of the NVRAM address space corresponding to the small block.
A nonvolatile random access memory according to claim 3, wherein said large block of storage space is organized into frames.
The nonvolatile random access memory of claim 6, wherein the NVRAM management module generates a log entry in which <NADDR, D> is recorded, in response to writing data D to an address NADDR of the NVRAM address space, the NVRAM management The module writes log entries to the log chunk frame.
The nonvolatile random access memory of claim 7, wherein the NVRAM address space address greater than the threshold is mapped to the address of the base chunk frame, and the NVRAM address space address not greater than the threshold is mapped to the address of the memory slice.
A nonvolatile random access memory according to claim 6, wherein said random access memory RAM stores a small block conversion table including a plurality of entries, each entry corresponding to one of the small blocks, the entry The value of the address records the address of the underlying chunky frame or the address of the memory slice that provides the data for the tile.
A method of providing a non-volatile random access memory includes the following steps:

Identify the NVRAM address space accessed;

Identifying whether the address of the accessed NVRAM address space is mapped to the address of the underlying chunky frame or the memory slice address;

The data to be accessed is obtained from the basic chunk frame or the memory chip according to the recognition result.
A method of providing a nonvolatile random access memory according to claim 10, wherein

Generating a small block index (ID) according to the address of the NVRAM address space to be accessed;

Accessing the small block conversion table according to the small block index (ID);

The small block conversion table entry is obtained according to the address of the NVRAM address space to be accessed, and the address of the NVRAM address space to be accessed is identified according to the small block conversion table entry to be mapped to the address of the base chunk frame or the memory slice address.
The method of providing a non-volatile random access memory according to claim 11, wherein the NVRAM address space is provided by the small blocks, the plurality of small blocks collectively providing a complete NVRAM address space.
The method for providing a nonvolatile random access memory according to claim 11 or 12, wherein if the small block conversion table entry records the memory slice address, the data to be accessed is obtained from the memory slice; if the small block conversion table entry record The address of the basic chunk frame, the memory chunk is allocated for the basic chunk frame of the data to be acquired, and the data to be accessed is read from the basic chunk frame of the data to be acquired into the allocated memory slice, from the allocated memory chip. Get the data to be accessed.
A method of providing a non-volatile random access memory includes the following steps:

Identify the NVRAM address space to be written to the data;

An address identifying the NVRAM address space to be written to the data is mapped to an address or a memory slice address of the underlying chunky frame;

If the address of the NVRAM address space to be written to the data is the memory slice address, the data is written to the memory slice;

If the address of the NVRAM address space to which data is written is the address of the base chunk frame, a log entry is generated in which the NVRAM address space address NADDR to be written data and the data D to be written are written, and the log entry is written. Log in large chunks of frames.
A method of providing a nonvolatile random access memory according to claim 14, wherein

Generating a small block index (ID) according to the address of the NVRAM address space to which data is to be written;

Accessing the small block conversion table according to the small block index (ID);

Obtaining a small block conversion table entry according to an address of an NVRAM address space to which data is to be written, and identifying, based on the small block conversion table entry, an address of an NVRAM address space to which data is to be written is mapped to an address of a base large frame or a memory chip address .
A method of providing a non-volatile random access memory includes the following steps:

Identify the NVRAM address space to be written to the data;

A log entry in which the NVRAM address space address NADDR to be written data and the data D to be written is recorded is generated according to the address of the NVRAM address space to which the data is to be written; the log entry is written to the log chunk frame.