CN108955970B - Micro-stress sensor for bridge monitoring - Google Patents
Micro-stress sensor for bridge monitoring Download PDFInfo
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- CN108955970B CN108955970B CN201810889037.2A CN201810889037A CN108955970B CN 108955970 B CN108955970 B CN 108955970B CN 201810889037 A CN201810889037 A CN 201810889037A CN 108955970 B CN108955970 B CN 108955970B
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- 238000012544 monitoring process Methods 0.000 title claims abstract description 10
- 239000013307 optical fiber Substances 0.000 claims abstract description 28
- 239000003990 capacitor Substances 0.000 claims description 110
- 230000003287 optical effect Effects 0.000 claims description 98
- 238000010606 normalization Methods 0.000 claims description 38
- 230000003044 adaptive effect Effects 0.000 claims description 35
- 238000006243 chemical reaction Methods 0.000 claims description 27
- 239000000919 ceramic Substances 0.000 claims description 12
- 230000005669 field effect Effects 0.000 claims description 12
- 208000030853 Asthma-Chronic Obstructive Pulmonary Disease Overlap Syndrome Diseases 0.000 claims description 9
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- 238000003199 nucleic acid amplification method Methods 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 6
- 238000004891 communication Methods 0.000 claims description 4
- 230000000087 stabilizing effect Effects 0.000 claims description 4
- 238000005086 pumping Methods 0.000 claims description 2
- 239000000835 fiber Substances 0.000 abstract description 24
- 230000008859 change Effects 0.000 description 12
- 230000035882 stress Effects 0.000 description 12
- 238000010586 diagram Methods 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 4
- 238000001228 spectrum Methods 0.000 description 4
- 238000001514 detection method Methods 0.000 description 3
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- 238000005260 corrosion Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01L—MEASURING FORCE, STRESS, TORQUE, WORK, MECHANICAL POWER, MECHANICAL EFFICIENCY, OR FLUID PRESSURE
- G01L1/00—Measuring force or stress, in general
- G01L1/24—Measuring force or stress, in general by measuring variations of optical properties of material when it is stressed, e.g. by photoelastic stress analysis using infrared, visible light, ultraviolet
- G01L1/242—Measuring force or stress, in general by measuring variations of optical properties of material when it is stressed, e.g. by photoelastic stress analysis using infrared, visible light, ultraviolet the material being an optical fibre
- G01L1/246—Measuring force or stress, in general by measuring variations of optical properties of material when it is stressed, e.g. by photoelastic stress analysis using infrared, visible light, ultraviolet the material being an optical fibre using integrated gratings, e.g. Bragg gratings
Abstract
The invention discloses a micro-stress sensor for bridge monitoring, and belongs to the technical field of optical fiber sensors. The main structure of the device comprises a pump source (1), a light wavelength division multiplexer (2), an erbium-doped fiber (3) and the like. The invention uses the sine signal as the modulation signal, does not generate high-frequency interference, and has the characteristics of more reliable work, high sensing precision and the like.
Description
Technical Field
The invention belongs to the technical field of optical fiber sensors, and particularly relates to a micro-stress sensor for bridge monitoring.
Background
The Bragg fiber grating (FBG) has the advantages of electromagnetic interference resistance, chemical corrosion resistance, small transmission loss, small volume, light weight, convenience for large-scale production and the like, and is widely applied to the technical field of sensing. At present, the stress sensor has wide application in the technical field of engineering. Particularly, in emerging fields of nanoparticle interaction, cell mechanics and the like, the micro-stress sensor has urgent requirements, and the micro-stress sensor is not separated from the bridge, the tunnel and the building structure for safety monitoring. Due to the advantages of the fiber Bragg grating, the stress sensor formed by the fiber Bragg grating has higher reliability compared with other sensors, and is more suitable for being used under severe conditions.
The closest prior art to the present invention is the paper "research and implementation of fiber grating sensing system" by doctor's thesis of bang-kai university bang, which provides a bragg fiber grating sensing system based on unbalanced mach zehnder interference demodulation technology (see page 26, fig. 3.6 of the document), the fiber sensing system adopts mach zehnder interference principle, the length of one of the two arms of the interferometer is changed by using a modulation signal provided by piezoelectric ceramic (PZT) to change the output light intensity of the interferometer, the output light intensity of the interferometer is in cosine function law with the change of PZT modulation signal, if an ideal sawtooth wave is used as the modulation signal of PZT, the output of the fiber sensing system is directly cosine wave. The fiber sensing system senses the change of the stress at the measuring point through the Bragg grating and reflects the change of the central wavelength of the reflection spectrum, the change of the central wavelength is reflected as the change of the phase of the output cosine wave after passing through the Mach Zehnder interferometer, and finally the change of the central wavelength of the reflection spectrum of the Bragg fiber grating can be reflected by comparing the phase of the cosine wave with the phase of the sawtooth wave, so that the change of the external stress is measured.
In the above-mentioned sensing system, there is the biggest problem that the sawtooth wave cannot be absolutely ideal, the ideal sawtooth wave falling edge is vertical, and the actual sawtooth wave falling edge always has a certain slope, so that the cosine wave output from the subsequent stage has a high-frequency jitter, and in order to eliminate the high-frequency jitter signal, a band-pass filter (BPF) must be used in the demodulation circuit of the subsequent stage to filter out the direct-current component and the high-frequency component. However, on the one hand, the high frequency component itself affects the phase detection of the cosine wave (the position of the zero-crossing point changes); on the other hand, the frequency of the high-frequency jitter signal is influenced by various factors such as the performance of a PZT driving circuit, the hysteresis characteristic of PZT (the electrical characteristic of PZT is equivalent to a capacitor, and the voltage at two ends of the PZT cannot jump, so that the falling edge of a sawtooth wave cannot be infinitely short) and the elasticity of an optical fiber, the frequency is variable, and the high-frequency jitter signal is difficult to filter; furthermore, when using a filter, in addition to the amplitude-frequency characteristic of the output signal, the phase-frequency characteristic of the signal is also affected, i.e. the filtering is affected by the phase around the cut-off frequency, which is very disadvantageous for fiber sensors that rely on phase changes to measure stress changes. Therefore, further improvements are needed in the existing fiber bragg grating stress sensors.
Disclosure of Invention
In order to overcome the defects of the existing Bragg fiber grating stress sensor, the invention provides the micro-stress sensor for bridge monitoring by using a sinusoidal signal as a PZT driving signal, so that the generation of high-frequency interference signals is avoided, and a filter is not needed when the received signal is processed, so that the influence of the filtering process on the phase is avoided.
The purpose of the invention is realized by the following technical scheme:
a micro-stress sensor for bridge monitoring has the structure that a pumping source 1 is connected with a 980nm end of an optical wavelength division multiplexer 2, a 1550nm end of the optical wavelength division multiplexer 2 is connected with one end of a delay line adjustable optical fiber 11, the other end of the delay line adjustable optical fiber 11 is connected with an input end of a first optical isolator 10, a control end of the delay line adjustable optical fiber 11 is connected with an output port of a level conversion chip 12, and an input end of the level conversion chip 12 is connected with a single chip microcomputer 18; the output end of the first optical isolator 10 is connected with the optical input end of the optical filter 9, the electric control end of the optical filter 9 is connected with the single chip microcomputer 18, the optical output end of the optical filter 9 is connected with the first port of the optical circulator 6, the second port of the optical circulator 6 is connected with one end of the Bragg grating group 8, the third port of the optical circulator 6 is connected with the input end of the first optical coupler 5, 90% of the output end of the first optical coupler 5 is connected with the input end of the second optical isolator 4, the output end of the second optical isolator 4 is connected with one end of the erbium-doped optical fiber 3, and the other end of the erbium-doped optical fiber 3 is connected with the common end of the wavelength division multiplexer 2;
it is characterized in that the structure is also that 10% output end of the first optical coupler 5 is connected with input end of the second optical coupler 6, one output end of the second optical coupler 6 is connected with one input end of the third optical coupler 23, another output end of the second optical coupler 6 is connected with one end of the optical fiber wound on the piezoelectric ceramic 22, another end of the optical fiber wound on the piezoelectric ceramic 22 is connected with another input end of the third optical coupler 23, one output end of the third optical coupler 23 is connected with input end of the first optical detector 24, another output end of the third optical coupler 23 is connected with input end of the second optical detector 25, output end of the first optical detector 24 is connected with one input end of the differential amplifying circuit 26, output end of the second optical detector 25 is connected with another input end of the differential amplifying circuit 26, output end of the differential amplifying circuit 26 is connected with input end of the function conversion circuit 27, the output of the function transformation circuit 27 is connected to the signal input of the adaptive amplitude normalization circuit 28, the signal output of the adaptive amplitude normalization circuit 28 is connected to one input of the phase comparison circuit 29, the output of the reference voltage circuit 30 is connected to the reference voltage input of the adaptive amplitude normalization circuit 28, the output of the phase comparison circuit 29 is connected to the single-chip microcomputer 18, the single-chip microcomputer 18 is connected to the frequency output of the controllable frequency source 20, the signal output end of the controllable frequency source 20 is connected with the other input end of the phase comparison circuit 29 and also connected with the input end of the PZT driving circuit 21, the output end of the PZT driving circuit 21 is connected with the control end of the piezoelectric ceramic 22, the output end of the constant current source circuit 14 is connected with the thermistor 15, the thermistor 15 is connected with the input end of the analog-to-digital conversion circuit 16, and the output end of the analog-to-digital conversion circuit 16 is connected with the singlechip 18; the singlechip 18 is also connected with the input key 13, the serial port communication module 17 and the display screen 19 respectively;
the structure of the function transformation circuit 27 is that one end of a capacitor C3 is connected with the pin 12 of the trigonometric function converter U1 and one end of a resistor R2, and the other end of the capacitor C3 is used as the input end of the function transformation circuit 26, is marked as a port ACOS _ in, and is connected with the output end of the differential amplification circuit 26; the other end of the resistor R2 is grounded; pins 2, 3, 4, 5, 8, 11 and 13 of the trigonometric function converter U1 are grounded, pins 9 and 10 are connected with one end of a capacitor C2 and a-12V power supply, and the other end of the capacitor C2 is grounded; pin 6 of the trigonometric function converter U1 is connected with pin 7, pin 16 is connected with the +12V power supply and one end of the capacitor C1, and the other end of the capacitor C1 is grounded; pin 1 of the trigonometric function converter U1 is connected to the sliding end of the sliding rheostat W1, one end of the sliding rheostat W1 is connected to one end of the resistor R1, the other end of the resistor R1 is connected to pin 14 of the trigonometric function converter U1, and the sliding end of the sliding rheostat W1, which is used as the output end of the function transformation circuit 27, is recorded as port ACOS _ out and is connected to the input end of the adaptive amplitude normalization circuit 28; the model of the trigonometric function converter U1 is AD 639;
the adaptive amplitude normalization circuit 28 has a structure that one end of a capacitor C11 is connected with one end of a resistor R21 and a pin 3 of a chip U2, the other end of the resistor R21 is grounded, and the other end of the capacitor C11 is used as an input end of the adaptive amplitude normalization circuit 28, is recorded as a port ADAPT _ in, and is connected with a port ACOS _ out of a function conversion circuit 27; pin 1, pin 7, pin 8 and pin 14 of the chip U2 are all grounded, pin 2 and pin 4 are both connected with a +5V power supply, pin 11 is connected with pin 12 and is connected with one end of a capacitor C5 and the +5V power supply, and the other end of the capacitor C5 is grounded; pin 13 of the chip U2 is connected with one end of a capacitor C4, and the other end of the capacitor C4 is grounded; pin 9 of the chip U2 is connected with one end of a capacitor C6, and the other end of the capacitor C6 is grounded; pin 5 of the chip U2 is connected with one end of a resistor R20 and a resistor R19, the other end of the resistor R20 is grounded, the other end of the resistor R19 is connected with the output end of the operational amplifier U8 and one end of a resistor R17, the positive power supply end of the operational amplifier U8 is connected with a +5V power supply, and the negative power supply end is grounded; the other end of the resistor R17 is connected with one end of the resistor R15 and one end of the resistor R16 and is connected to the inverting input end of the operational amplifier U8; the non-inverting input end of the operational amplifier U8 is connected with one end of a resistor R18, and the other end of the resistor R18 is connected with a +2.5V power supply; the other end of the resistor R15 is connected with one end of the capacitor C10 and is connected to the output end of the operational amplifier U7; the positive power supply end of the operational amplifier U7 is connected with a +5V power supply, and the negative power supply end is grounded; the other end of the capacitor C10 is connected with one end and the sliding end of the slide rheostat W3 and is connected to the inverting input end of the operational amplifier U7; the non-inverting input end of the operational amplifier U7 is connected with one end of a resistor R14, and the other end of the resistor R14 is connected with a +2.5V power supply; the other end of the slide rheostat W3 is connected with one end of a resistor R13; the other end of the resistor R16 is connected with the sliding end of the sliding rheostat W2 and the output end of the operational amplifier U6, and one end of the sliding rheostat W2 is connected with one end of the resistor R11; the other end of the resistor R11 is connected with one end of the resistor R10 and is connected to the inverting input end of the operational amplifier U6; the positive power supply end of the operational amplifier U6 is connected with a +5V power supply, and the negative power supply end is grounded; the non-inverting input end of the operational amplifier U6 is connected with one end of a resistor R12, and the other end of the resistor R12 is connected with a +2.5V power supply; the other end of the resistor R10 is connected with the other end of the resistor R13 and one end of the resistor R7 and is connected to the output end of the operational amplifier U5; the other end of the resistor R7 is connected with one end of the resistor R6 and is connected to the inverting input end of the operational amplifier U5; the other end of the resistor R6 is connected with the output end of the operational amplifier U4, the positive power supply of the operational amplifier U5 is connected with the +5V power supply, and the negative power supply is grounded; one end of the resistor R8 is connected with one end of the resistor R9 and is connected to the non-inverting input end of the operational amplifier U5, and the other end of the resistor R9 is connected with a +2.5V power supply; the other end of the resistor R8 is used as a reference voltage end of the adaptive amplitude normalization circuit 28 and is connected to a reference voltage output end of the reference voltage circuit 30; pin 10 of the chip U2, which is used as the output terminal of the adaptive amplitude normalization circuit 28 and is denoted as port ADAPT _ out, is connected to one input terminal of the phase comparison circuit 29; a pin 10 of the chip U2 is connected with one end of a capacitor C7, the other end of the capacitor C7 is connected with one end of a resistor R22 and the non-inverting input end of the operational amplifier U3, and the other end of the resistor R22 is grounded; one end of the resistor R3 is connected with one end of the capacitor C8 and the anode of the diode D1 and is connected to the inverting input end of the operational amplifier U3, and the substrate (namely, pin 8) of the operational amplifier U3 is connected to the inverting input end of the operational amplifier U3; the positive power supply of the operational amplifier U3 is connected with a +5V power supply, and the negative power supply is connected with a-5V power supply; the other end of the capacitor C8 is connected with the cathode of the diode D1 and the anode of the diode D2 and is connected to the output end of the operational amplifier U3; the other end of the resistor R3 is connected with one end of a resistor R4 and the inverting input end of the operational amplifier U4, the other end of the resistor R4 is connected with the cathode of a diode D2 and the grid of a field-effect tube Q1, the source of the field-effect tube Q1 is connected with one end of a capacitor C9 and one end of the resistor R5, and the other end of the capacitor C9 is connected with the other end of the resistor R5 and is grounded; the source electrode of the field effect transistor Q1 is connected with the drain electrode of the field effect transistor Q1 and is connected to the non-inverting input end of the operational amplifier U4; the inverting input end of the operational amplifier U4 is connected with the substrate of the operational amplifier U4 and the output end of the operational amplifier U4; the positive power supply of the operational amplifier U3 is connected with a +5V power supply, and the negative power supply is connected with a-5V power supply; the chip U2 is a variable gain amplifier chip, and the model is AD 8367;
the structure of the PHASE comparison circuit 29 is that one end of a capacitor C12 is connected with the non-inverting input end of the operational amplifier U9 and one end of a resistor R23, and the other end of the capacitor C12 is used as one input end of the PHASE comparison circuit 29, is recorded as a port PHASE _ in1, and is connected with a port ADAPT _ out of the adaptive amplitude normalization circuit 28; the other end of the resistor R23 is grounded; the positive power supply end of the operational amplifier U9 is connected with a +5V power supply, the negative power supply end is grounded, the inverted input end is grounded, and the output end is connected with the CLK end of the D trigger U10A; the D port of the D flip-flop U10A is grounded; one end of the capacitor C13 is grounded, and the other end of the capacitor C13 is connected with the PR end of the D flip-flop U10A; one end of the resistor R24 is connected with the PR end of the D flip-flop U10A, and the other end is connected with the Q end of the D flip-flop U10A; the CLR end of the D flip-flop U10A is connected with a +5V power supply, and the Q end of the D flip-flop U10A is not connected with the PR end of the D flip-flop U12A; one end of the capacitor C14 is connected to the non-inverting input terminal of the operational amplifier U11 and one end of the resistor R25, and the other end of the capacitor C14 is used as the other input terminal of the PHASE comparator circuit 29, is recorded as a port PHASE _ in2, and is connected to a port SineM _ out of the controllable frequency source 20; the other end of the resistor R25 is grounded; the positive power supply end of the operational amplifier U11 is connected with a +5V power supply, the negative power supply end is grounded, the inverted input end is grounded, and the output end is connected with the CLK end of the D trigger U10B; the D port of the D flip-flop U10B is grounded; one end of the capacitor C15 is grounded, and the other end of the capacitor C15 is connected with the PR end of the D flip-flop U10B; one end of the resistor R26 is connected with the PR end of the D flip-flop U10B, and the other end is connected with the Q end of the D flip-flop U10B; the CLR end of the D trigger U10B is connected with a +5V power supply, and the Q end of the D trigger U10B is not connected with the CLR end of the D trigger U12A; the D end and the CLK end of the D flip-flop U12A are both grounded, and the Q end is used as the output end of the PHASE comparison circuit 29 and is denoted as a port PHASE _ out;
the structure of the reference voltage circuit 30 is that one end of a resistor R27 is connected with a +5V power supply, the other end is connected with a non-inverting input end of an operational amplifier U13, the anode of a voltage stabilizing diode D3 is grounded, the cathode is connected with the non-inverting input end of the operational amplifier U13, the inverting input end of the operational amplifier U13 is connected with an output end, the positive power supply is connected with the +5V power supply, the negative power supply is grounded, the output end is the +2.5V power supply, and the +2.5V power supply in each module is provided by the output end; one end of the slide rheostat W4 is connected with a +2.5V power supply, the other end of the slide rheostat W4 is grounded, and the slide end of the slide rheostat W14 is connected with the non-inverting input end of the operational amplifier U14; the inverting input terminal of the operational amplifier U14 is connected to its output terminal, the positive power supply terminal is connected to the +5V power supply, the negative power supply terminal is grounded, and the output terminal is used as the output terminal of the reference voltage circuit 30, and is recorded as the port Vref, and is connected to the reference voltage terminal of the adaptive amplitude normalization circuit 28.
The structure of the controllable frequency source circuit 20 is that one end of a resistor R28 is connected with a +12V power supply, the other end is connected with a base electrode of a triode Q2, an emitter electrode of the triode Q2 is connected with one end of a resistor R30, the other end of the resistor R30 is grounded, an anode electrode of an electrolytic capacitor C16 is connected with an emitter electrode of a triode Q2, a cathode electrode of an electrolytic capacitor C16 is grounded, one end of a resistor R29 is connected with a base electrode of a triode Q2, the other end is grounded, one end of a capacitor C18 is connected with a base electrode of a triode Q2, the other end is used as a signal output end of the controllable frequency source circuit 20 and is marked as a port SinM _ out, the signal output end is connected with a port PHASE _ in2 of a PHASE comparison circuit 29 and an input end of a PZT driving circuit 21, one end of the capacitor C17 is connected with a SinM _ out, the other end of a capacitor C17 is connected with a collector electrode of a triode Q2, one end of, the other end of the inductor L2 is connected with a +12V power supply, one end of the capacitor C19 is connected with a port SinM _ out, the other end of the inductor L2 is connected with a non-inverting input stage of the operational amplifier U15, one end of the resistor R32 is grounded, the other end of the resistor R32 is connected with a non-inverting input stage of the operational amplifier U15, an inverting input stage of the operational amplifier U15 is connected with one end of the resistor R31, the other end of the resistor R31 is grounded, the output end of the operational amplifier U15 serving as a frequency output end of the controllable frequency source circuit 20 and recorded as a port FrqM _ out and connected with the single chip microcomputer 18, the positive power supply end of the.
The pump source 1 is preferably a 980nm laser source.
The thermistor 15 is preferably a 10k Ω @25 ℃ negative temperature coefficient thermistor.
Has the advantages that:
1. the invention uses the sine signal as the modulation signal, and compared with the prior art which uses the sawtooth wave signal for modulation, the invention can not generate high-frequency interference, so that the sensing system can work more reliably.
2. The invention uses the self-adaptive amplitude normalization circuit to automatically convert the amplitude of the demodulated signal into the amplitude suitable for the phase comparison circuit to compare, so that the phase detection error is smaller, and the sensing precision of the whole sensing system is effectively improved.
3. Compared with the prior art, the frequency of the modulation signal is adjustable, so that the sensing system has wider application occasions.
4. The invention has the function of temperature compensation and effectively overcomes the influence of the ambient temperature on the sensing parameters.
Drawings
Fig. 1 is an overall schematic block diagram of the present invention.
Fig. 2 is a schematic circuit diagram of a function conversion circuit used in the present invention.
Fig. 3 is a schematic circuit diagram of an adaptive amplitude normalization circuit used in the present invention.
Fig. 4 is a schematic circuit diagram of a phase comparison circuit used in the present invention.
Fig. 5 is a schematic circuit diagram of a reference voltage circuit used in the present invention.
Fig. 6 is a schematic circuit diagram of a controllable frequency source for use with the present invention.
Detailed Description
The operation principle of the present invention is further explained with reference to the drawings, and it should be understood that the component parameters marked in the drawings are the preferred parameters used in the following embodiments, and do not limit the scope of the present invention.
EXAMPLE 1 Overall Structure of the invention
As shown in fig. 1, the overall structure of the present invention includes that a pump source 1(980nm laser, maximum output power of 1W) is connected to a 980nm end of an optical wavelength division multiplexer 2(980/1550nm wavelength division multiplexer), a 1550nm end of the optical wavelength division multiplexer 2 is connected to one end of a delay line tunable optical fiber 11 (VDL-40-15-S9-1-FA type electric optical fiber delay line of the mitsunchawa sun optical technology co., ltd.), the other end of the delay line tunable optical fiber 11 is connected to an input end of a first optical isolator 10(1550nm polarization independent optical isolator), a control end of the delay line tunable optical fiber 11 is connected to an output port of a level conversion chip 12(MAX232), and an input end of the level conversion chip 12 is connected to a single chip microcomputer 18(STC89C 51); the output end of the first optical isolator 10 is connected with the optical input end of an optical filter 9 (produced by Micron Optics, model number FFP-TF-1060-010G0200-2.0), the electrical control end of the optical filter 9 is connected with a single chip microcomputer 18, the optical output end of the optical filter 9 is connected with one end of an optical circulator 7 (PIOC 3-15 of shanghai hanyu corporation), the second port of the optical circulator 7 is connected with one end of a bragg grating group 8 (three bragg gratings with reflectivity of ninety percent, bandwidth of 0.6nm, central wavelength of 1550nm, 1560nm and 1630nm respectively), the third port of the optical circulator 7 is connected with the input end of a first optical coupler 5(1 × 2 standard single-mode optical coupler, splitting ratio of 10: 90), wherein the relationship of 3 ports of the optical circulator 7 is as follows: the light entering the first port can only be output from the second port, the light entering the second port can only be output from the third port, and the light entering the third port can only be output from the first port. The 90% output end of the first optical coupler 5 is connected with the input end of a second optical isolator 4 (1310/1480/1550 nm polarization independent optical isolator manufactured by shanghai vasta optical fiber communication technology limited), the output end of the second optical isolator 4 is connected with one end of an erbium-doped optical fiber 3 (a high-performance 980nm pumped C-Band erbium-doped optical fiber manufactured by Nufern corporation of America, the model is EDFC-980-HP, 3 meters), and the other end of the erbium-doped optical fiber 3 is connected with the common end of a wavelength division multiplexer 2. The above structure constitutes the basic light source portion and the sensing portion of the optical fiber sensor.
The structure also includes that 10% output end of the first optical coupler 5 is connected with input end of a second optical coupler 6(1 × 2 standard single mode optical coupler with splitting ratio of 50: 50), one output end of the second optical coupler 6 is connected with one input end of a third optical coupler 23(2 × 2 standard single mode optical coupler with splitting ratio of 50: 50), another output end of the second optical coupler 6 is connected with one end of an optical fiber wound on a piezoelectric ceramic 22 (cylindrical piezoelectric ceramic with outer diameter of 50mm, inner diameter of 40mm and height of 50mm), another end of the optical fiber wound on the piezoelectric ceramic 22 is connected with another input end of the third optical coupler 23, one output end of the third optical coupler 23 is connected with input end of a first optical detector 24 (LSIPD-LD 50 type optical detector of Beijing optical technology, Inc.), another output end of the third optical coupler 23 is connected with a second optical detector 25 (LSIPD-50 type optical detector of Beijing optical technology, Inc Device), the output of the first photodetector 24 is connected to one input of a differential amplifier circuit 26, the output of the second photodetector 25 is connected to the other input of the differential amplifier circuit 26, the output of the differential amplifier circuit 26 is connected to the input of a function converter circuit 27, the output of the function converter circuit 27 is connected to the signal input of an adaptive amplitude normalization circuit 28, the signal output of the adaptive amplitude normalization circuit 28 is connected to one input of a phase comparator circuit 29, the output of a reference voltage circuit 30 is connected to the reference voltage input of the adaptive amplitude normalization circuit 28, the output of the phase comparator circuit 29 is connected to the single-chip microcomputer 18, the single-chip microcomputer 18 is connected to the frequency output of a controllable frequency source 20, the signal output of the controllable frequency source 20 is connected to the other input of the phase comparator circuit 29, the device is also connected with the input end of a PZT driving circuit 21 (a device manufactured by the subject group, and the specific structure is shown in patent ZL200710055865.8), the output end of the PZT driving circuit 21 is connected with the control end of the piezoelectric ceramic 22, the output end of a constant current source circuit 14 is connected with a thermistor 15(10k omega @25 ℃), the thermistor 15 is connected with the input end of an analog-to-digital conversion circuit 16, and the output end of the analog-to-digital conversion circuit 16 is connected with a single chip microcomputer 18; the single chip 18 is also connected with the input key 13, the serial port communication module 17(MAX232) and the display screen 19 respectively.
The structure of the function transformation circuit 27 is that one end of a capacitor C3 is connected with the pin 12 of the trigonometric function converter U1 and one end of a resistor R2, and the other end of the capacitor C3 is used as the input end of the function transformation circuit 26, is recorded as a port ACOS _ in, and is connected with the output end of the difference amplification circuit 17; the other end of the resistor R2 is grounded; pins 2, 3, 4, 5, 8, 11 and 13 of the trigonometric function converter U1 are grounded, pins 9 and 10 are connected with one end of a capacitor C2 and a-12V power supply, and the other end of the capacitor C2 is grounded; pin 6 of the trigonometric function converter U1 is connected with pin 7, pin 16 is connected with the +12V power supply and one end of the capacitor C1, and the other end of the capacitor C1 is grounded; pin 1 of the trigonometric function converter U1 is connected to the sliding end of the sliding rheostat W1, one end of the sliding rheostat W1 is connected to one end of the resistor R1, the other end of the resistor R1 is connected to pin 14 of the trigonometric function converter U1, and the sliding end of the sliding rheostat W1, which is used as the output end of the function transformation circuit 27, is recorded as port ACOS _ out and is connected to the input end of the adaptive amplitude normalization circuit 28; the model of the trigonometric function converter U1 is AD 639; the circuit has an inverse cosine transform function, and performs an inverse cosine process on a signal output from the differential amplifier circuit 26.
Since the amplitude of the signal output by the functional conversion circuit 27 is small and is influenced by a plurality of parameters in the circuit and the circuit, the size is not fixed, the invention designs the adaptive amplitude normalization circuit 28 for normalizing the amplitude of the signal output by the functional conversion circuit 27 to the optimal size so as to further improve the demodulation precision. The adaptive amplitude normalization circuit 28 has a structure that one end of a capacitor C11 is connected with one end of a resistor R21 and a pin 3 of a chip U2, the other end of the resistor R21 is grounded, and the other end of the capacitor C11 is used as an input end of the adaptive amplitude normalization circuit 28, is recorded as a port ADAPT _ in, and is connected with a port ACOS _ out of a function conversion circuit 27; pin 1, pin 7, pin 8 and pin 14 of the chip U2 are all grounded, pin 2 and pin 4 are both connected with a +5V power supply, pin 11 is connected with pin 12 and is connected with one end of a capacitor C5 and the +5V power supply, and the other end of the capacitor C5 is grounded; pin 13 of the chip U2 is connected with one end of a capacitor C4, and the other end of the capacitor C4 is grounded; pin 9 of the chip U2 is connected with one end of a capacitor C6, and the other end of the capacitor C6 is grounded; pin 5 of the chip U2 is connected with one end of a resistor R20 and a resistor R19, the other end of the resistor R20 is grounded, the other end of the resistor R19 is connected with the output end of the operational amplifier U8 and one end of a resistor R17, the positive power supply end of the operational amplifier U8 is connected with a +5V power supply, and the negative power supply end is grounded; the other end of the resistor R17 is connected with one end of the resistor R15 and one end of the resistor R16 and is connected to the inverting input end of the operational amplifier U8; the non-inverting input end of the operational amplifier U8 is connected with one end of a resistor R18, and the other end of the resistor R18 is connected with a +2.5V power supply; the other end of the resistor R15 is connected with one end of the capacitor C10 and is connected to the output end of the operational amplifier U7; the positive power supply end of the operational amplifier U7 is connected with a +5V power supply, and the negative power supply end is grounded; the other end of the capacitor C10 is connected with one end and the sliding end of the slide rheostat W3 and is connected to the inverting input end of the operational amplifier U7; the non-inverting input end of the operational amplifier U7 is connected with one end of a resistor R14, and the other end of the resistor R14 is connected with a +2.5V power supply; the other end of the slide rheostat W3 is connected with one end of a resistor R13; the other end of the resistor R16 is connected with the sliding end of the sliding rheostat W2 and the output end of the operational amplifier U6, and one end of the sliding rheostat W2 is connected with one end of the resistor R11; the other end of the resistor R11 is connected with one end of the resistor R10 and is connected to the inverting input end of the operational amplifier U6; the positive power supply end of the operational amplifier U6 is connected with a +5V power supply, and the negative power supply end is grounded; the non-inverting input end of the operational amplifier U6 is connected with one end of a resistor R12, and the other end of the resistor R12 is connected with a +2.5V power supply; the other end of the resistor R10 is connected with the other end of the resistor R13 and one end of the resistor R7 and is connected to the output end of the operational amplifier U5; the other end of the resistor R7 is connected with one end of the resistor R6 and is connected to the inverting input end of the operational amplifier U5; the other end of the resistor R6 is connected with the output end of the operational amplifier U4, the positive power supply of the operational amplifier U5 is connected with the +5V power supply, and the negative power supply is grounded; one end of the resistor R8 is connected with one end of the resistor R9 and is connected to the non-inverting input end of the operational amplifier U5, and the other end of the resistor R9 is connected with a +2.5V power supply; the other end of the resistor R8 is used as a reference voltage end of the adaptive amplitude normalization circuit 28 and is connected to a reference voltage output end of the reference voltage circuit 30; pin 10 of the chip U2, which is used as the output terminal of the adaptive amplitude normalization circuit 28 and is denoted as port ADAPT _ out, is connected to one input terminal of the phase comparison circuit 29; a pin 10 of the chip U2 is connected with one end of a capacitor C7, the other end of the capacitor C7 is connected with one end of a resistor R22 and the non-inverting input end of the operational amplifier U3, and the other end of the resistor R22 is grounded; one end of the resistor R3 is connected with one end of the capacitor C8 and the anode of the diode D1 and is connected to the inverting input end of the operational amplifier U3, and the substrate (namely, pin 8) of the operational amplifier U3 is connected to the inverting input end of the operational amplifier U3; the positive power supply of the operational amplifier U3 is connected with a +5V power supply, and the negative power supply is connected with a-5V power supply; the other end of the capacitor C8 is connected with the cathode of the diode D1 and the anode of the diode D2 and is connected to the output end of the operational amplifier U3; the other end of the resistor R3 is connected with one end of a resistor R4 and the inverting input end of the operational amplifier U4, the other end of the resistor R4 is connected with the cathode of a diode D2 and the grid of a field-effect tube Q1, the source of the field-effect tube Q1 is connected with one end of a capacitor C9 and one end of the resistor R5, and the other end of the capacitor C9 is connected with the other end of the resistor R5 and is grounded; the source electrode of the field effect transistor Q1 is connected with the drain electrode of the field effect transistor Q1 and is connected to the non-inverting input end of the operational amplifier U4; the inverting input end of the operational amplifier U4 is connected with the substrate of the operational amplifier U4 and the output end of the operational amplifier U4; the positive power supply of the operational amplifier U3 is connected with a +5V power supply, and the negative power supply is connected with a-5V power supply; the chip U2 is a variable gain amplifier chip with model number AD 8367.
Example 4 phase comparison Circuit
The structure of the PHASE comparison circuit 29 is that one end of a capacitor C12 is connected with the non-inverting input end of the operational amplifier U9 and one end of a resistor R23, and the other end of the capacitor C12 is used as one input end of the PHASE comparison circuit 29, is recorded as a port PHASE _ in1, and is connected with a port ADAPT _ out of the adaptive amplitude normalization circuit 28; the other end of the resistor R23 is grounded; the positive power supply end of the operational amplifier U9 is connected with a +5V power supply, the negative power supply end is grounded, the inverted input end is grounded, and the output end is connected with the CLK end of the D trigger U10A; the D port of the D flip-flop U10A is grounded; one end of the capacitor C13 is grounded, and the other end of the capacitor C13 is connected with the PR end of the D flip-flop U10A; one end of the resistor R24 is connected with the PR end of the D flip-flop U10A, and the other end is connected with the Q end of the D flip-flop U10A; the CLR end of the D flip-flop U10A is connected with a +5V power supply, and the Q end of the D flip-flop U10A is not connected with the PR end of the D flip-flop U12A; one end of the capacitor C14 is connected to the non-inverting input terminal of the operational amplifier U11 and one end of the resistor R25, and the other end of the capacitor C14 is used as the other input terminal of the PHASE comparator circuit 29, is recorded as a port PHASE _ in2, and is connected to a port SineM _ out of the controllable frequency source 20; the other end of the resistor R25 is grounded; the positive power supply end of the operational amplifier U11 is connected with a +5V power supply, the negative power supply end is grounded, the inverted input end is grounded, and the output end is connected with the CLK end of the D trigger U10B; the D port of the D flip-flop U10B is grounded; one end of the capacitor C15 is grounded, and the other end of the capacitor C15 is connected with the PR end of the D flip-flop U10B; one end of the resistor R26 is connected with the PR end of the D flip-flop U10B, and the other end is connected with the Q end of the D flip-flop U10B; the CLR end of the D trigger U10B is connected with a +5V power supply, and the Q end of the D trigger U10B is not connected with the CLR end of the D trigger U12A; the D end and the CLK end of the D trigger U12A are both grounded, and the Q end is used as the output end of the PHASE comparison circuit 29, is recorded as a port PHASE _ out and is connected with the singlechip 18; the circuit compares the phase of the standard sine wave output by the controllable frequency source 20 with the phase of the sine wave output by the adaptive amplitude normalization circuit 28 (the phase of the sine wave is influenced by the environment detected by the Bragg grating group 8), and sends the comparison result to the single chip microcomputer 18, and the single chip microcomputer 18 calculates the stress change at the Bragg grating group 8 according to the phase difference.
EXAMPLE 5 reference Voltage Circuit
The structure of the reference voltage circuit 30 is that one end of a resistor R27 is connected with a +5V power supply, the other end is connected with a non-inverting input end of an operational amplifier U13, the anode of a voltage stabilizing diode D3 is grounded, the cathode is connected with the non-inverting input end of the operational amplifier U13, the inverting input end of the operational amplifier U13 is connected with an output end, the positive power supply is connected with the +5V power supply, the negative power supply is grounded, the output end is the +2.5V power supply, and the +2.5V power supply in each module is provided by the output end; one end of the slide rheostat W4 is connected with a +2.5V power supply, the other end of the slide rheostat W4 is grounded, and the slide end of the slide rheostat W14 is connected with the non-inverting input end of the operational amplifier U14; the inverting input terminal of the operational amplifier U14 is connected to its output terminal, the positive power supply terminal is connected to the +5V power supply, the negative power supply terminal is grounded, and the output terminal is used as the output terminal of the reference voltage circuit 30, and is recorded as the port Vref, and is connected to the reference voltage terminal of the adaptive amplitude normalization circuit 28. This circuit provides +2.5V voltage and a reference voltage to the adaptive amplitude normalization circuit 28.
EXAMPLE 6 controllable frequency Source
The structure of the controllable frequency source circuit 20 is that one end of a resistor R28 is connected with a +12V power supply, the other end is connected with a base electrode of a triode Q2, an emitter electrode of the triode Q2 is connected with one end of a resistor R30, the other end of the resistor R30 is grounded, an anode electrode of an electrolytic capacitor C16 is connected with an emitter electrode of a triode Q2, a cathode electrode of an electrolytic capacitor C16 is grounded, one end of a resistor R29 is connected with a base electrode of a triode Q2, the other end is grounded, one end of a capacitor C18 is connected with a base electrode of a triode Q2, the other end is used as a signal output end of the controllable frequency source circuit 20 and is marked as a port SinM _ out, the signal output end is connected with a port PHASE _ in2 of a PHASE comparison circuit 29 and an input end of a PZT driving circuit 21, one end of the capacitor C17 is connected with a SinM _ out, the other end of a capacitor C17 is connected with a collector electrode of a triode Q2, one end of, the other end of the inductor L2 is connected with a +12V power supply, one end of the capacitor C19 is connected with a port SinM _ out, the other end of the inductor L2 is connected with a non-inverting input stage of the operational amplifier U15, one end of the resistor R32 is grounded, the other end of the resistor R32 is connected with a non-inverting input stage of the operational amplifier U15, an inverting input stage of the operational amplifier U15 is connected with one end of the resistor R31, the other end of the resistor R31 is grounded, the output end of the operational amplifier U15 serving as a frequency output end of the controllable frequency source circuit 20 and recorded as a port FrqM _ out and connected with the single chip microcomputer 18, the positive power supply end of the. The module outputs a standard sine wave with adjustable frequency to provide a required sine signal for the demodulation part of the invention.
Example 7 working principle of the invention
The working principle of the present invention will be described with reference to the above embodiments and the accompanying drawings. When the device works, the Bragg fiber grating group 8 is placed at a position of a bridge where stress change needs to be monitored, a fiber laser annular cavity formed by the erbium-doped fiber 3, the optical isolator 4 and the like provides a broadband light source for the Bragg fiber grating group 8, each Bragg fiber grating has a specific reflection spectrum, different gratings have different peak wavelengths, when the stress of a certain measured point changes, the peak wavelength of the reflection spectrum of the Bragg fiber grating at the position can be correspondingly shifted, reflected light enters the Mach Zehnder interferometer formed by the second optical coupler 6, the piezoelectric ceramic 22 and the third optical coupler 23, and the controllable frequency source 20 provides a control signal sin (omega t) for the Mach Zehnder interferometer, and the signal is influenced by the light reflected by the Bragg fiber gratings in the interferometer and then passes through the first optical detector 24, The second photodetector 25 converts the electrical signal into a signal, and after differential amplification, sin (ω t + Δ θ) is obtained after the inverse cosine transform of the function transformation circuit 27, the amplitude of the signal is adjusted to a proper value after passing through the adaptive amplitude normalization circuit 28, the phase of the signal at this time is changed compared with the sine signal sin (ω t) generated by the controllable frequency source 20, the phase difference between the signal and the sine signal is detected by the phase comparison circuit 29 and sent to the single chip microcomputer 18, the phase difference actually reflects the stress change of the measured point, and finally the stress detection of the measured point is realized. The invention does not use the sawtooth wave in the modulation and demodulation process, thereby avoiding the high-frequency jitter signal caused by the falling edge of the sawtooth wave, and the band-pass filter is not needed to be used for filtering in the demodulation circuit, thereby avoiding the influence on the amplitude-frequency characteristic and the phase-frequency characteristic of the output signal. The invention uses standard sine wave signal as PZT modulating signal, when demodulating the modulating signal, it uses function conversion circuit 27 and self-adapting amplitude normalization circuit 28 skillfully, recovers the modulating signal into sine signal whose phase is controlled by Bragg grating group 8 and whose amplitude is suitable, when comparing the phase in phase comparison circuit 29, it can compare the phase difference between the controlled signal and the original signal, thus accurately reflecting the stress parameter detected by the sensing head (i.e. Bragg grating group 8).
Because the ring cavity of the fiber laser is susceptible to the influence of the environmental temperature (generally not at the same position as the sensing probe of the fiber bragg grating group 8) when in work, the fiber laser also has a temperature compensation function and consists of a constant current source circuit 14, a thermistor 15 and an analog-to-digital conversion circuit 16. The thermistor 15 is a temperature sensitive device, and when the ambient temperature changes, the resistance value of the thermistor changes, so that the output current is changed, and the output current is converted into a digital signal by the analog-to-digital conversion circuit 16 and is input into the single chip 18, so as to compensate the error of the measurement result caused by the change of the ambient temperature of the annular cavity of the fiber laser.
Claims (3)
1. A micro stress sensor for bridge monitoring has the structure that a pumping source (1) is connected with a 980nm end of an optical wavelength division multiplexer (2), a 1550nm end of the optical wavelength division multiplexer (2) is connected with one end of a delay line adjustable optical fiber (11), the other end of the delay line adjustable optical fiber (11) is connected with an input end of a first optical isolator (10), a control end of the delay line adjustable optical fiber (11) is connected with an output port of a level conversion chip (12), and an input end of the level conversion chip (12) is connected with a single chip microcomputer (18); the output end of the first optical isolator (10) is connected with the optical input end of the optical filter (9), the electric control end of the optical filter (9) is connected with the single chip microcomputer (18), the optical output end of the optical filter (9) is connected with the first port of the optical circulator (7), the second port of the optical circulator (7) is connected with one end of the Bragg grating group (8), the third port of the optical circulator (7) is connected with the input end of the first optical coupler (5), 90% of the output end of the first optical coupler (5) is connected with the input end of the second optical isolator (4), the output end of the second optical isolator (4) is connected with one end of the erbium-doped optical fiber (3), and the other end of the erbium-doped optical fiber (3) is connected with the common end of the wavelength division multiplexer (2);
the optical coupler is characterized in that the structure is also provided, wherein 10% of the output end of the first optical coupler (5) is connected with the input end of the second optical coupler (6), one output end of the second optical coupler (6) is connected with one input end of the third optical coupler (23), the other output end of the second optical coupler (6) is connected with one end of an optical fiber wound on the piezoelectric ceramic (22), the other end of the optical fiber wound on the piezoelectric ceramic (22) is connected with the other input end of the third optical coupler (23), one output end of the third optical coupler (23) is connected with the input end of the first optical detector (24), the other output end of the third optical coupler (23) is connected with the input end of the second optical detector (25), the output end of the first optical detector (24) is connected with one input end of the differential amplification circuit (26), the output end of the second optical detector (25) is connected with the other input end of the differential amplification circuit (26), the output end of the differential amplification circuit (26) is connected with the input end of the function conversion circuit (27), the output end of the function conversion circuit (27) is connected with the signal input end of the adaptive amplitude normalization circuit (28), the signal output end of the adaptive amplitude normalization circuit (28) is connected with one input end of the phase comparison circuit (29), the output end of the reference voltage circuit (30) is connected with the reference voltage input end of the adaptive amplitude normalization circuit (28), the output end of the phase comparison circuit (29) is connected with the single chip microcomputer (18), the single chip microcomputer (18) is connected with the frequency output end of the controllable frequency source (20), the signal output end of the controllable frequency source (20) is connected with the other input end of the phase comparison circuit (29) and also connected with the input end of the PZT driving circuit (21), the output end of the PZT driving circuit (21) is connected with the control end of the piezoelectric ceramic (22), the output end of the constant current source circuit (14) is connected with the thermistor (15), the thermistor (15) is connected with the input end of the analog-to-digital conversion circuit (16), and the output end of the analog-to-digital conversion circuit (16) is connected with the singlechip (18); the singlechip (18) is also connected with an input key (13), a serial port communication module (17) and a display screen (19) respectively;
the structure of the function conversion circuit (27) is that one end of a capacitor C3 is connected with a pin 12 of a trigonometric function converter U1 and one end of a resistor R2, and the other end of the capacitor C3 is used as the input end of the function conversion circuit (27), is recorded as a port ACOS _ in and is connected with the output end of the differential amplification circuit (26); the other end of the resistor R2 is grounded; pins 2, 3, 4, 5, 8, 11 and 13 of the trigonometric function converter U1 are grounded, pins 9 and 10 are connected with one end of a capacitor C2 and a-12V power supply, and the other end of the capacitor C2 is grounded; pin 6 of the trigonometric function converter U1 is connected with pin 7, pin 16 is connected with the +12V power supply and one end of the capacitor C1, and the other end of the capacitor C1 is grounded; pin 1 of the trigonometric function converter U1 is connected with the sliding end of a sliding rheostat W1, one end of a sliding rheostat W1 is connected with one end of a resistor R1, the other end of the resistor R1 is connected with a pin 14 of a trigonometric function converter U1, and the sliding end of a sliding rheostat W1 is used as the output end of a function transformation circuit (27), is recorded as a port ACOS _ out and is connected with the input end of an adaptive amplitude normalization circuit (28); the model of the trigonometric function converter U1 is AD 639;
the adaptive amplitude normalization circuit (28) is structurally characterized in that one end of a capacitor C11 is connected with one end of a resistor R21 and a pin 3 of a chip U2, the other end of the resistor R21 is grounded, and the other end of the capacitor C11 is used as an input end of the adaptive amplitude normalization circuit (28), is recorded as a port ADAPT _ in and is connected with a port ACOS _ out of a function conversion circuit (27); pin 1, pin 7, pin 8 and pin 14 of the chip U2 are all grounded, pin 2 and pin 4 are both connected with a +5V power supply, pin 11 is connected with pin 12 and is connected with one end of a capacitor C5 and the +5V power supply, and the other end of the capacitor C5 is grounded; pin 13 of the chip U2 is connected with one end of a capacitor C4, and the other end of the capacitor C4 is grounded; pin 9 of the chip U2 is connected with one end of a capacitor C6, and the other end of the capacitor C6 is grounded; pin 5 of the chip U2 is connected with one end of a resistor R20 and a resistor R19, the other end of the resistor R20 is grounded, the other end of the resistor R19 is connected with the output end of the operational amplifier U8 and one end of a resistor R17, the positive power supply end of the operational amplifier U8 is connected with a +5V power supply, and the negative power supply end is grounded; the other end of the resistor R17 is connected with one end of the resistor R15 and one end of the resistor R16 and is connected to the inverting input end of the operational amplifier U8; the non-inverting input end of the operational amplifier U8 is connected with one end of a resistor R18, and the other end of the resistor R18 is connected with a +2.5V power supply; the other end of the resistor R15 is connected with one end of the capacitor C10 and is connected to the output end of the operational amplifier U7; the positive power supply end of the operational amplifier U7 is connected with a +5V power supply, and the negative power supply end is grounded; the other end of the capacitor C10 is connected with one end and the sliding end of the slide rheostat W3 and is connected to the inverting input end of the operational amplifier U7; the non-inverting input end of the operational amplifier U7 is connected with one end of a resistor R14, and the other end of the resistor R14 is connected with a +2.5V power supply; the other end of the slide rheostat W3 is connected with one end of a resistor R13; the other end of the resistor R16 is connected with the sliding end of the sliding rheostat W2 and the output end of the operational amplifier U6, and one end of the sliding rheostat W2 is connected with one end of the resistor R11; the other end of the resistor R11 is connected with one end of the resistor R10 and is connected to the inverting input end of the operational amplifier U6; the positive power supply end of the operational amplifier U6 is connected with a +5V power supply, and the negative power supply end is grounded; the non-inverting input end of the operational amplifier U6 is connected with one end of a resistor R12, and the other end of the resistor R12 is connected with a +2.5V power supply; the other end of the resistor R10 is connected with the other end of the resistor R13 and one end of the resistor R7 and is connected to the output end of the operational amplifier U5; the other end of the resistor R7 is connected with one end of the resistor R6 and is connected to the inverting input end of the operational amplifier U5; the other end of the resistor R6 is connected with the output end of the operational amplifier U4, the positive power supply of the operational amplifier U5 is connected with the +5V power supply, and the negative power supply is grounded; one end of the resistor R8 is connected with one end of the resistor R9 and is connected to the non-inverting input end of the operational amplifier U5, and the other end of the resistor R9 is connected with a +2.5V power supply; the other end of the resistor R8 is used as a reference voltage end of the adaptive amplitude normalization circuit (28) and is connected with a reference voltage output end of the reference voltage circuit (30); pin 10 of the chip U2, which is used as the output terminal of the adaptive amplitude normalization circuit (28), is marked as port ADAPT _ out and is connected to one input terminal of the phase comparison circuit (29); a pin 10 of the chip U2 is connected with one end of a capacitor C7, the other end of the capacitor C7 is connected with one end of a resistor R22 and the non-inverting input end of the operational amplifier U3, and the other end of the resistor R22 is grounded; one end of the resistor R3 is connected with one end of the capacitor C8 and the anode of the diode D1 and is connected to the inverting input end of the operational amplifier U3, and the substrate of the operational amplifier U3 is connected to the inverting input end of the operational amplifier U3; the positive power supply of the operational amplifier U3 is connected with a +5V power supply, and the negative power supply is connected with a-5V power supply; the other end of the capacitor C8 is connected with the cathode of the diode D1 and the anode of the diode D2 and is connected to the output end of the operational amplifier U3; the other end of the resistor R3 is connected with one end of a resistor R4 and the inverting input end of the operational amplifier U4, the other end of the resistor R4 is connected with the cathode of a diode D2 and the grid of a field-effect tube Q1, the source of the field-effect tube Q1 is connected with one end of a capacitor C9 and one end of the resistor R5, and the other end of the capacitor C9 is connected with the other end of the resistor R5 and is grounded; the source electrode of the field effect transistor Q1 is connected with the drain electrode of the field effect transistor Q1 and is connected to the non-inverting input end of the operational amplifier U4; the inverting input end of the operational amplifier U4 is connected with the substrate of the operational amplifier U4 and the output end of the operational amplifier U4; the positive power supply of the operational amplifier U3 is connected with a +5V power supply, and the negative power supply is connected with a-5V power supply; the chip U2 is a variable gain amplifier chip, and the model is AD 8367;
the structure of the PHASE comparison circuit (29) is that one end of a capacitor C12 is connected with the non-inverting input end of an operational amplifier U9 and one end of a resistor R23, the other end of the capacitor C12 is used as one input end of the PHASE comparison circuit (29), is recorded as a port PHASE _ in1 and is connected with a port ADAPT _ out of the self-adaptive amplitude normalization circuit (28); the other end of the resistor R23 is grounded; the positive power supply end of the operational amplifier U9 is connected with a +5V power supply, the negative power supply end is grounded, the inverted input end is grounded, and the output end is connected with the CLK end of the D trigger U10A; the D port of the D flip-flop U10A is grounded; one end of the capacitor C13 is grounded, and the other end of the capacitor C13 is connected with the PR end of the D flip-flop U10A; one end of the resistor R24 is connected with the PR end of the D flip-flop U10A, and the other end is connected with the Q end of the D flip-flop U10A; the CLR end of the D flip-flop U10A is connected with a +5V power supply, and the Q end of the D flip-flop U10A is not connected with the PR end of the D flip-flop U12A; one end of the capacitor C14 is connected with the non-inverting input end of the operational amplifier U11 and one end of the resistor R25, the other end of the capacitor C14 is used as the other input end of the PHASE comparison circuit (29), is recorded as a port PHASE _ in2 and is connected with a port Sinem _ out of the controllable frequency source (20); the other end of the resistor R25 is grounded; the positive power supply end of the operational amplifier U11 is connected with a +5V power supply, the negative power supply end is grounded, the inverted input end is grounded, and the output end is connected with the CLK end of the D trigger U10B; the D port of the D flip-flop U10B is grounded; one end of the capacitor C15 is grounded, and the other end of the capacitor C15 is connected with the PR end of the D flip-flop U10B; one end of the resistor R26 is connected with the PR end of the D flip-flop U10B, and the other end is connected with the Q end of the D flip-flop U10B; the CLR end of the D trigger U10B is connected with a +5V power supply, and the Q end of the D trigger U10B is not connected with the CLR end of the D trigger U12A; the D end and the CLK end of the D trigger U12A are both grounded, and the Q end is used as the output end of the PHASE comparison circuit (29), is recorded as a port PHASE _ out and is connected with the singlechip 18;
the reference voltage circuit (30) is structurally characterized in that one end of a resistor R27 is connected with a +5V power supply, the other end of the resistor R27 is connected with a non-inverting input end of an operational amplifier U13, the anode of a voltage stabilizing diode D3 is grounded, the cathode of the voltage stabilizing diode D3 is connected with the non-inverting input end of an operational amplifier U13, the inverting input end of the operational amplifier U13 is connected with an output end, the positive power supply is connected with the +5V power supply, the negative power supply is grounded, the output end of the operational amplifier U13 is the +2.5V power supply; one end of the slide rheostat W4 is connected with a +2.5V power supply, the other end of the slide rheostat W4 is grounded, and the slide end of the slide rheostat W14 is connected with the non-inverting input end of the operational amplifier U14; the inverting input end of the operational amplifier U14 is connected with the output end thereof, the positive power supply is connected with the +5V power supply, the negative power supply is grounded, the output end is used as the output end of the reference voltage circuit (30), is marked as a port Vref and is connected with the reference voltage end of the adaptive amplitude normalization circuit (28);
the structure of the controllable frequency source circuit (20) is that one end of a resistor R28 is connected with a +12V power supply, the other end is connected with the base of a triode Q2, the emitter of a triode Q2 is connected with one end of a resistor R30, the other end of a resistor R30 is grounded, the anode of an electrolytic capacitor C16 is connected with the emitter of a triode Q2, the cathode of an electrolytic capacitor C16 is grounded, one end of a resistor R29 is connected with the base of a triode Q2, the other end is grounded, one end of a capacitor C18 is connected with the base of a triode Q2, the other end is used as a sinusoidal signal output end of the controllable frequency source (20) and is marked as a port SinM _ out, the port SinM _ out is connected with a port PHASE _ in2 of a PHASE comparison circuit (29) and is also connected with the input end of a PZT driving circuit (21), one end of a capacitor C17 is connected with the port SinM _ out, the other end of a capacitor C17 is connected with the collector of a triode, one end of an inductor L2 is connected with a port SinM _ out, the other end of the inductor L2 is connected with a +12V power supply, one end of a capacitor C19 is connected with the port SinM _ out, the other end of the capacitor C19 is connected with the in-phase input stage of an operational amplifier U15, one end of a resistor R32 is grounded, the other end of the resistor R15 is connected with the in-phase input stage of an operational amplifier U15, the reverse phase input stage of the operational amplifier U734 is connected with one end of a resistor R31, the other end of the resistor R31 is grounded, the output end of the operational amplifier U15 serves as the frequency output end of a controllable frequency source (20) and is recorded as a port FrqM _ out and is connected with a single chip microcomputer (18).
2. A micro-stress sensor for bridge monitoring according to claim 1, wherein the pump source (1) is a 980nm laser source.
3. A micro-stress sensor for bridge monitoring according to claim 1 or 2, wherein the thermistor (15) is a negative temperature coefficient thermistor with a resistance of 10k Ω at 25 ℃.
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| Optical Wavelength Discriminator with Uniform Fiber Bragg Grating for Demodulation of Bipolar Signals;Zdzislaw Kaczmarek;《Proceedings of the international conference modern problems of radio engineering，telecommunications and computer science，2004》;20040228;第112-114页 * |
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