CN109029774B

CN109029774B - Multipoint temperature sensing system formed by Bragg gratings

Info

Publication number: CN109029774B
Application number: CN201810889039.1A
Authority: CN
Inventors: 吴戈; 张栋
Original assignee: Jilin University
Current assignee: Jilin University
Priority date: 2018-08-07
Filing date: 2018-08-07
Publication date: 2020-05-22
Anticipated expiration: 2038-08-07
Also published as: CN109029774A

Abstract

The invention discloses a multipoint temperature sensing system formed by Bragg gratings, and belongs to the technical field of optical fiber sensors. The main structure of the device comprises a pump source (1), a light wavelength division multiplexer (2), an erbium-doped fiber (3) and the like. The invention uses the sine signal as the modulation signal, does not generate high-frequency interference, and has the characteristics of more reliable work, high sensing precision, wide application range and the like.

Description

Multipoint temperature sensing system formed by Bragg gratings

Technical Field

The invention belongs to the technical field of optical fiber sensors, and particularly relates to a multipoint temperature sensing system formed by Bragg gratings.

Background

The Bragg fiber grating (FBG) has the advantages of electromagnetic interference resistance, chemical corrosion resistance, small transmission loss, small volume, light weight, convenience for large-scale production and the like, and is widely applied to the technical field of sensing. At present, the temperature sensor plays an important role in safety production, and is especially important for monitoring temperature in high-risk places such as mines. However, most of the conventional temperature sensors are realized by the change of electrical signals, and the temperature sensors based on the change of electrical signals are greatly limited in practical application, so that on one hand, the use of electrical signals can cause additional potential safety hazards to certain environments (such as coal mines), and on the other hand, the temperature sensors are greatly interfered by the environment and are inconvenient to transmit when used in severe environments. Due to the advantages of the fiber Bragg grating, the temperature sensor formed by the fiber Bragg grating has higher reliability compared with other sensors, and is more suitable for being used under severe conditions.

The closest prior art to the present invention is the "research and implementation of fiber grating sensing system" by doctor graduation thesis of bang-kai university bang, which provides a fiber bragg grating sensing system based on unbalanced michelson interferometric demodulation technology (see page 24, fig. 3.4 of the document), the fiber sensing system adopts unbalanced michelson interferometric principle, one of the two arms of the interferometer changes the length of the arm by using a modulation signal provided by piezoelectric ceramics (PZT), so as to change the output light intensity of the interferometer, the output light intensity of the interferometer is in cosine function law with the change of PZT modulation signal, if an ideal sawtooth wave is used as the modulation signal of PZT, the output of the fiber sensing system is directly cosine wave. The fiber sensing system senses the change of stress or temperature at a measuring point through the Bragg grating and reflects the change of the central wavelength of the reflection spectrum, the change of the central wavelength is reflected as the change of the phase of an output cosine wave after passing through the unbalanced Michelson interferometer, and finally the change of the central wavelength of the reflection spectrum of the Bragg grating can be reflected by comparing the phase of the cosine wave with the phase of the sawtooth wave, so that the change of the external stress (or temperature) is measured.

In the above-mentioned sensing system, there is the biggest problem that the sawtooth wave cannot be absolutely ideal, the ideal sawtooth wave falling edge is vertical, and the actual sawtooth wave falling edge always has a certain slope, so that the cosine wave output from the subsequent stage has a high-frequency jitter, and in order to eliminate the high-frequency jitter signal, a band-pass filter (BPF) must be used in the demodulation circuit of the subsequent stage to filter out the direct-current component and the high-frequency component. However, on the one hand, the high frequency component itself affects the phase detection of the cosine wave (the position of the zero-crossing point changes); on the other hand, the frequency of the high-frequency jitter signal is influenced by various factors such as the performance of a PZT driving circuit, the hysteresis characteristic of PZT (the electrical characteristic of PZT is equivalent to a capacitor, and the voltage at two ends of the PZT cannot jump, so that the falling edge of a sawtooth wave cannot be infinitely short) and the elasticity of an optical fiber, the frequency is variable, and the high-frequency jitter signal is difficult to filter; furthermore, when using a filter, in addition to the amplitude-frequency characteristic of the output signal, the phase-frequency characteristic of the signal is also affected, i.e. the filtering is affected by the phase around the cut-off frequency, which is very disadvantageous for fiber sensors that rely on phase changes to measure stress changes. Therefore, further improvements are needed in the existing fiber bragg grating temperature sensors.

Disclosure of Invention

In order to overcome the defects of the conventional Bragg fiber grating temperature sensor, the invention provides a multipoint temperature sensing system formed by a Bragg grating using a sinusoidal signal as a PZT driving signal, so that the generation of high-frequency interference signals is avoided, and a filter is not needed when the received signal is processed, so that the influence of a filtering process on the phase is avoided.

The purpose of the invention is realized by the following technical scheme:

a multipoint temperature sensing system formed by Bragg gratings structurally comprises a pumping source 1, an optical wavelength division multiplexer 2, a first optical isolator 10, a second optical isolator, a first PZT driving circuit 12, a second PZT driving circuit 13 and a singlechip 18, wherein the pumping source 1 is connected with a 980nm end of the optical wavelength division multiplexer 2, a 1550nm end of the optical wavelength division multiplexer 2 is connected with one end of an optical fiber wound on the first PZT 11, the other end of the optical fiber wound on the first PZT 11 is connected with the input end of the first optical isolator, the control end of the first PZT 11 is connected with the output port of the first PZT driving circuit 12, the input end of the first PZT driving circuit 12 is connected with the output port of the first digital-to; the output end of the first optical isolator 10 is connected with the optical input end of the optical filter 9, the electric control end of the optical filter 9 is connected with the single chip microcomputer 18, the optical output end of the optical filter 9 is connected with the first port of the optical circulator 7, the second port of the optical circulator 7 is connected with one end of the Bragg grating group 8, the third port of the optical circulator 7 is connected with the input end of the first optical coupler 5, 90% of the output end of the first optical coupler 5 is connected with the input end of the second optical isolator 4, the output end of the second optical isolator 4 is connected with one end of the erbium-doped optical fiber 3, and the other end of the erbium-doped optical fiber 3 is connected with the common end of the optical wavelength division multiplexer 2; the output of 10% of the output end of the first optical coupler 5 is connected with the input end of the second optical coupler 6, one output end of the second optical coupler 6 is connected with the input end of the second faraday rotator 25, the other output end of the second optical coupler 6 is connected with one end of the optical fiber wound on the second piezoelectric ceramic 23, the other end of the optical fiber wound on the second piezoelectric ceramic 23 is connected with the input end of the first faraday rotator 24, and the other output end of the second optical coupler 6 is connected with the input end of the second photoelectric conversion circuit 26; it is characterized in that the structure is also such that the output terminal of the second photoelectric conversion circuit 26 is connected to the input terminal of the function conversion circuit 27, the output terminal of the function conversion circuit 27 is connected to one input terminal of the adaptive amplitude normalization circuit 28, the output terminal of the reference voltage circuit 30 is connected to the other input terminal of the adaptive amplitude normalization circuit 28, and the output terminal of the adaptive amplitude normalization circuit 28 is connected to one input terminal of the phase comparison circuit 29; the input end of the controllable frequency source 21 is connected with the single chip microcomputer 18, the output end of the controllable frequency source is connected with the other input end of the phase comparison circuit 29, and the output end of the phase comparison circuit 29 is connected with the single chip microcomputer 18; the output end of the controllable frequency source 21 is also connected with the input end of a second PZT driving circuit 22, and the output end of the second PZT driving circuit 22 is connected with the control end of a second piezoelectric ceramic 23; the output end of the constant current source circuit 15 is connected with the thermistor 16, the thermistor 16 is connected with the input end of the analog-to-digital conversion circuit 17, and the output end of the analog-to-digital conversion circuit 17 is connected with the singlechip 18; the singlechip 20 is also connected with the input keys 14, the serial port communication module 19 and the display screen 20 respectively;

the structure of the function transformation circuit 27 is that one end of a capacitor C3 is connected with the pin 12 of the trigonometric function converter U1 and one end of a resistor R2, and the other end of the capacitor C3 is used as the input end of the function transformation circuit 27, is recorded as a port ACOS _ in, and is connected with the output end of the second photoelectric conversion circuit 26; the other end of the resistor R2 is grounded;

pins

2, 3, 4, 5, 8, 11 and 13 of the trigonometric function converter U1 are grounded,

pins

9 and 10 are connected with one end of a capacitor C2 and a-12V power supply, and the other end of the capacitor C2 is grounded; pin 6 of the trigonometric function converter U1 is connected with pin 7, pin 16 is connected with the +12V power supply and one end of the capacitor C1, and the other end of the capacitor C1 is grounded; pin 1 of the trigonometric function converter U1 is connected to the sliding end of the sliding rheostat W1, one end of the sliding rheostat W1 is connected to one end of the resistor R1, the other end of the resistor R1 is connected to pin 14 of the trigonometric function converter U1, and the sliding end of the sliding rheostat W1, which is used as the output end of the function transformation circuit 27, is recorded as port ACOS _ out and is connected to the input end of the adaptive amplitude normalization circuit 28; the model of the trigonometric function converter U1 is AD 639;

the adaptive amplitude normalization circuit 28 has a structure that one end of a capacitor C11 is connected with one end of a resistor R21 and a pin 3 of a chip U2, the other end of the resistor R21 is grounded, and the other end of the capacitor C11 is used as an input end of the adaptive amplitude normalization circuit 28, is recorded as a port ADAPT _ in, and is connected with a port ACOS _ out of a function conversion circuit 27; pin 1, pin 7, pin 8 and pin 14 of the chip U2 are all grounded, pin 2 and pin 4 are both connected with a +5V power supply, pin 11 is connected with pin 12 and is connected with one end of a capacitor C5 and the +5V power supply, and the other end of the capacitor C5 is grounded; pin 13 of the chip U2 is connected with one end of a capacitor C4, and the other end of the capacitor C4 is grounded; pin 9 of the chip U2 is connected with one end of a capacitor C6, and the other end of the capacitor C6 is grounded; pin 5 of the chip U2 is connected with one end of a resistor R20 and a resistor R19, the other end of the resistor R20 is grounded, the other end of the resistor R19 is connected with the output end of the operational amplifier U8 and one end of a resistor R17, the positive power supply end of the operational amplifier U8 is connected with a +5V power supply, and the negative power supply end is grounded; the other end of the resistor R17 is connected with one end of the resistor R15 and one end of the resistor R16 and is connected to the inverting input end of the operational amplifier U8; the non-inverting input end of the operational amplifier U8 is connected with one end of a resistor R18, and the other end of the resistor R18 is connected with a +2.5V power supply; the other end of the resistor R15 is connected with one end of the capacitor C10 and is connected to the output end of the operational amplifier U7; the positive power supply end of the operational amplifier U7 is connected with a +5V power supply, and the negative power supply end is grounded; the other end of the capacitor C10 is connected with one end and the sliding end of the slide rheostat W3 and is connected to the inverting input end of the operational amplifier U7; the non-inverting input end of the operational amplifier U7 is connected with one end of a resistor R14, and the other end of the resistor R14 is connected with a +2.5V power supply; the other end of the slide rheostat W3 is connected with one end of a resistor R13; the other end of the resistor R16 is connected with the sliding end of the sliding rheostat W2 and the output end of the operational amplifier U6, and one end of the sliding rheostat W2 is connected with one end of the resistor R11; the other end of the resistor R11 is connected with one end of the resistor R10 and is connected to the inverting input end of the operational amplifier U6; the positive power supply end of the operational amplifier U6 is connected with a +5V power supply, and the negative power supply end is grounded; the non-inverting input end of the operational amplifier U6 is connected with one end of a resistor R12, and the other end of the resistor R12 is connected with a +2.5V power supply; the other end of the resistor R10 is connected with the other end of the resistor R13 and one end of the resistor R7 and is connected to the output end of the operational amplifier U5; the other end of the resistor R7 is connected with one end of the resistor R6 and is connected to the inverting input end of the operational amplifier U5; the other end of the resistor R6 is connected with the output end of the operational amplifier U4, the positive power supply of the operational amplifier U5 is connected with the +5V power supply, and the negative power supply is grounded; one end of the resistor R8 is connected with one end of the resistor R9 and is connected to the non-inverting input end of the operational amplifier U5, and the other end of the resistor R9 is connected with a +2.5V power supply; the other end of the resistor R8 is used as a reference voltage end of the adaptive amplitude normalization circuit 28 and is connected to a reference voltage output end of the reference voltage circuit 30; pin 10 of the chip U2, which is used as the output terminal of the adaptive amplitude normalization circuit 28 and is denoted as port ADAPT _ out, is connected to one input terminal of the phase comparison circuit 29; a pin 10 of the chip U2 is connected with one end of a capacitor C7, the other end of the capacitor C7 is connected with one end of a resistor R22 and the non-inverting input end of the operational amplifier U3, and the other end of the resistor R22 is grounded; one end of the resistor R3 is connected with one end of the capacitor C8 and the anode of the diode D1 and is connected to the inverting input end of the operational amplifier U3, and the substrate (namely, pin 8) of the operational amplifier U3 is connected to the inverting input end of the operational amplifier U3; the positive power supply of the operational amplifier U3 is connected with a +5V power supply, and the negative power supply is connected with a-5V power supply; the other end of the capacitor C8 is connected with the cathode of the diode D1 and the anode of the diode D2 and is connected to the output end of the operational amplifier U3; the other end of the resistor R3 is connected with one end of a resistor R4 and the inverting input end of the operational amplifier U4, the other end of the resistor R4 is connected with the cathode of a diode D2 and the grid of a field-effect tube Q1, the source of the field-effect tube Q1 is connected with one end of a capacitor C9 and one end of the resistor R5, and the other end of the capacitor C9 is connected with the other end of the resistor R5 and is grounded; the source electrode of the field effect transistor Q1 is connected with the drain electrode of the field effect transistor Q1 and is connected to the non-inverting input end of the operational amplifier U4; the inverting input end of the operational amplifier U4 is connected with the substrate of the operational amplifier U4 and the output end of the operational amplifier U4; the positive power supply of the operational amplifier U3 is connected with a +5V power supply, and the negative power supply is connected with a-5V power supply; the chip U2 is a variable gain amplifier chip, and the model is AD 8367;

the structure of the PHASE comparison circuit 29 is that one end of a capacitor C12 is connected with the non-inverting input end of the operational amplifier U9 and one end of a resistor R23, and the other end of the capacitor C12 is used as one input end of the PHASE comparison circuit 29, is recorded as a port PHASE _ in1, and is connected with a port ADAPT _ out of the adaptive amplitude normalization circuit 28; the other end of the resistor R23 is grounded; the positive power supply end of the operational amplifier U9 is connected with a +5V power supply, the negative power supply end is grounded, the inverted input end is grounded, and the output end is connected with the CLK end of the D trigger U10A; the D port of the D flip-flop U10A is grounded; one end of the capacitor C13 is grounded, and the other end of the capacitor C13 is connected with the PR end of the D flip-flop U10A; one end of the resistor R24 is connected with the PR end of the D flip-flop U10A, and the other end is connected with the Q end of the D flip-flop U10A; the CLR end of the D flip-flop U10A is connected with a +5V power supply, and the Q end of the D flip-flop U10A is not connected with the PR end of the D flip-flop U12A; one end of the capacitor C14 is connected to the non-inverting input terminal of the operational amplifier U11 and one end of the resistor R25, and the other end of the capacitor C14 is used as the other input terminal of the PHASE comparison circuit 29, is recorded as a port PHASE _ in2, and is connected to a port SineM _ out of the controllable frequency source 21; the other end of the resistor R25 is grounded; the positive power supply end of the operational amplifier U11 is connected with a +5V power supply, the negative power supply end is grounded, the inverted input end is grounded, and the output end is connected with the CLK end of the D trigger U10B; the D port of the D flip-flop U10B is grounded; one end of the capacitor C15 is grounded, and the other end of the capacitor C15 is connected with the PR end of the D flip-flop U10B; one end of the resistor R26 is connected with the PR end of the D flip-flop U10B, and the other end is connected with the Q end of the D flip-flop U10B; the CLR end of the D trigger U10B is connected with a +5V power supply, and the Q end of the D trigger U10B is not connected with the CLR end of the D trigger U12A; the D end and the CLK end of the D flip-flop U12A are both grounded, and the Q end is used as the output end of the PHASE comparison circuit 29 and is denoted as a port PHASE _ out;

the structure of the reference voltage circuit 30 is that one end of a resistor R27 is connected with a +5V power supply, the other end is connected with a non-inverting input end of an operational amplifier U13, the anode of a voltage stabilizing diode D3 is grounded, the cathode is connected with the non-inverting input end of the operational amplifier U13, the inverting input end of the operational amplifier U13 is connected with an output end, the positive power supply is connected with the +5V power supply, the negative power supply is grounded, the output end is the +2.5V power supply, and the +2.5V power supply in each module is provided by the output end; one end of the slide rheostat W4 is connected with a +2.5V power supply, the other end of the slide rheostat W4 is grounded, and the slide end of the slide rheostat W14 is connected with the non-inverting input end of the operational amplifier U14; the inverting input terminal of the operational amplifier U14 is connected to its output terminal, the positive power supply terminal is connected to the +5V power supply, the negative power supply terminal is grounded, and the output terminal is used as the output terminal of the reference voltage circuit 30, and is recorded as the port Vref, and is connected to the reference voltage terminal of the adaptive amplitude normalization circuit 28.

The structure of the controllable frequency source 21 is that one end of a resistor R28 is connected with a +12V power supply, and the other end is connected with the base electrode of a triode Q2; one end of the resistor R29 is connected with the base electrode of the triode Q2, and the other end is grounded; one end of the resistor R30 is connected with +12V, and the other end is connected with the collector of the triode Q2; one end of the capacitor C17 is connected with the collector of the triode Q2, and the other end is connected with a pin 2 of the chip U15; one end of the resistor R31 is connected with the emitter of the triode Q2, and the other end is connected with the anode of the electrolytic capacitor C16; the negative electrode of the electrolytic capacitor C16 is grounded; one end of the capacitor C18 is connected with a pin 2 of the chip U15, and the other end is connected with a pin 2 of the chip U16; one end of the capacitor C19 is connected to pin 2 of the chip U16, and the other end is used as the output end of the controllable frequency source 21 and is marked as a port SineM _ out; the base electrode of the triode Q2 is connected with the port SineM _ out; one end of the capacitor C20 is connected with a pin 5 of the chip U15, and the other end of the capacitor C20 is grounded; one end of the capacitor C21 is connected with a pin 5 of the chip U16, and the other end of the capacitor C21 is grounded; pin 1 and pin 10 of the chip U15 are connected with a +5V power supply, and pin 3, pin 4 and pin 6 are grounded; pin 9 is connected with one end of a resistor R32, pin 8 is connected with one end of a resistor R33, and pin 7 is connected with one end of a resistor R34; the other end of the resistor R32 is used as an input port of the controllable frequency source 21 and is denoted as a port SineM _ in 1; the other end of the resistor R33 serves as another input port of the controllable frequency source 21, and is denoted as a port SineM _ in 2; the port SineM _ in1 and the port SineM _ in2 are connected with the input end of the singlechip 18; the other end of the resistor R34 is connected with a +5V power supply; pin 1 and pin 10 of the chip U16 are connected with a +5V power supply, and pin 3, pin 4 and pin 6 are grounded; pin 9 is connected with one end of a resistor R35, pin 8 is connected with one end of a resistor R36, and pin 7 is connected with one end of a resistor R37; the other end of the resistor R35 is connected with a port SineM _ in 1; the other end of the resistor R36 is connected with a port SineM _ in 2; the other end of the resistor R37 is connected with a +5V power supply.

The pump source 1 is preferably a 980nm laser source.

The Bragg grating group 8 is preferably composed of 3 Bragg gratings, the reflectivity of each grating is 90%, the bandwidth is 0.6nm, and the central wavelength is 1550nm, 1560nm and 1630nm respectively.

Has the advantages that:

1. the invention uses the sine signal as the modulation signal, and compared with the prior art which uses the sawtooth wave signal for modulation, the invention can not generate high-frequency interference, so that the sensing system can work more reliably.

2. The invention uses the self-adaptive amplitude normalization circuit to automatically convert the amplitude of the demodulated signal into the amplitude suitable for the phase comparison circuit to compare, so that the phase detection error is smaller, and the sensing precision of the whole sensing system is effectively improved.

3. Compared with the prior art, the frequency of the modulation signal is adjustable, so that the sensing system has wider application occasions.

4. The invention has the function of temperature compensation and effectively overcomes the influence of the ambient temperature on the sensing parameters.

Drawings

Fig. 1 is an overall schematic block diagram of the present invention.

Fig. 2 is a schematic circuit diagram of a function conversion circuit used in the present invention.

Fig. 3 is a schematic circuit diagram of an adaptive amplitude normalization circuit used in the present invention.

Fig. 4 is a schematic circuit diagram of a phase comparison circuit used in the present invention.

Fig. 5 is a schematic circuit diagram of a reference voltage circuit used in the present invention.

Fig. 6 is a schematic circuit diagram of a controllable frequency source for use with the present invention.

Detailed Description

The operation principle of the present invention is further explained with reference to the drawings, and it should be understood that the component parameters marked in the drawings are the preferred parameters used in the following embodiments, and do not limit the scope of the present invention.

EXAMPLE 1 Overall Structure of the invention

As shown in FIG. 1, the overall structure of the present invention is that a pump source 1 (a VENUS series 980nm high power single mode pump light source of Shanghai Kentite laser technology Limited, model VLSS-980-B, maximum single mode output power of 1200mW) is connected to a 980nm end of an optical wavelength division multiplexer 2 (a fused tapered 980/1550nm pump optical wavelength division multiplexing coupler manufactured by Shanghai Vast optical fiber communication technology Limited), a 1550nm end of the optical wavelength division multiplexer 2 is connected to one end of an optical fiber wound on a first piezoelectric ceramic 11 (a cylindrical piezoelectric ceramic, outer diameter of 50mm, inner diameter of 40mm, height of 50mm), the other end of the optical fiber wound on the first piezoelectric ceramic 11 is connected to an input end of a first optical isolator 10 (a 1310/1480/1550nm polarization independent optical isolator manufactured by Shanghai Hanyu optical fiber communication technology Limited), a control end of the first piezoelectric ceramic 11 is connected to an output port of a first PZT driving circuit 12, the input end of the first PZT driving circuit 12 is connected with the output port of the first digital-to-analog conversion circuit 13, and the input port of the first digital-to-analog conversion circuit 13 is connected with the singlechip 18(STC89C 51); the output end of the first optical isolator 10 is connected with the optical input end of an optical filter 9 (made by Micron Optics, model number FFP-TF-1060-010G0200-2.0), the electric control end of the optical filter 9 is connected with a singlechip 18, the optical output end of the optical filter 9 is connected with one end of an optical circulator 7 (PIOC 3-15 optical circulator made by Shanghai Hangyu Co., Ltd.), the second port of the optical circulator 7 is connected with one end of a Bragg grating group 8 (Bragg gratings with reflectivity of ninety percent, bandwidth of 0.6nm, central wavelength of 1550nm, 1560nm and 1630nm respectively), the third port of the optical circulator 7 is connected with the input end of a first optical coupler 5 (made by OZ-OPTICS, model number FUSED-12-1064-7/125-90/10-3U-3mm, splitting ratio of 90:10), the 90% output end of the first optical coupler 5 is connected with the input end of a second optical isolator 4 (1310/1480/1550 nm polarization independent optical isolator manufactured by shanghai vasta optical fiber communication technology limited), the output end of the second optical isolator 4 is connected with one end of an erbium-doped optical fiber 3 (a high-performance 980nm pumped C-Band erbium-doped optical fiber manufactured by Nufern corporation of America, the model is EDFC-980-HP, 3 meters), and the other end of the erbium-doped optical fiber 3 is connected with the common end of the optical wavelength division multiplexer 2. The above structure constitutes the basic light source portion and the sensing portion of the optical fiber sensor. The 10% output of the first optical coupler 5 is connected to the input of a second optical coupler 6(2 × 2 standard single-mode optical coupler with a splitting ratio of 50: 50), one output of the second optical coupler 6 is connected to the input of a second faraday rotator 25 (MFI-1310 manufactured by THORLABS), the other output of the second optical coupler 6 is connected to one end of an optical fiber wound on a second piezoelectric ceramic 23 (cylindrical piezoelectric ceramic, 50mm in outer diameter, 40mm in inner diameter, and 50mm in height), the other end of the optical fiber wound on the second piezoelectric ceramic 23 is connected to the input of a first faraday rotator 24 (MFI-1310 manufactured by THORLABS), and the other output of the second optical coupler 6 is connected to the input of a second photoelectric conversion circuit 26. The second optical coupler 6, the first faraday rotator mirror 24, the second faraday rotator mirror 25, and the second piezoelectric ceramic 23 together constitute a michelson interference structure.

The present invention also has a configuration in which the output terminal of the second photoelectric conversion circuit 26 is connected to the input terminal of the function conversion circuit 27, the output terminal of the function conversion circuit 27 is connected to one input terminal of the adaptive amplitude normalization circuit 28, the output terminal of the reference voltage circuit 30 is connected to the other input terminal of the adaptive amplitude normalization circuit 28, and the output terminal of the adaptive amplitude normalization circuit 28 is connected to one input terminal of the phase comparison circuit 29; the input end of the controllable frequency source 21 is connected with the single chip microcomputer 18, the output end of the controllable frequency source is connected with the other input end of the phase comparison circuit 29, and the output end of the phase comparison circuit 29 is connected with the single chip microcomputer 18; the output of the controllable frequency source 21 is further connected to an input of a second PZT drive circuit 22, and an output of the second PZT drive circuit 22 is connected to a control terminal of a second piezoelectric ceramic 23. The above structure constitutes the demodulation section of the sensor. The output end of the constant current source circuit 15 is connected with the thermistor 16, the thermistor 16 is connected with the input end of the analog-to-digital conversion circuit 17, and the output end of the analog-to-digital conversion circuit 17 is connected with the singlechip 18. The above structure provides the temperature compensation function for the present invention. The single chip 18 is also connected to the input key 14, the serial communication module 19(MAX232), and the display screen 20, respectively, and is used for setting parameters, communicating with a computer, displaying information, and the like.

Embodiment 2 function conversion circuit

pins

9 and 10 are connected with one end of a capacitor C2 and a-12V power supply, and the other end of the capacitor C2 is grounded; pin 6 of the trigonometric function converter U1 is connected with pin 7, pin 16 is connected with the +12V power supply and one end of the capacitor C1, and the other end of the capacitor C1 is grounded; pin 1 of the trigonometric function converter U1 is connected to the sliding end of the sliding rheostat W1, one end of the sliding rheostat W1 is connected to one end of the resistor R1, the other end of the resistor R1 is connected to pin 14 of the trigonometric function converter U1, and the sliding end of the sliding rheostat W1, which is used as the output end of the function transformation circuit 27, is recorded as port ACOS _ out and is connected to the input end of the adaptive amplitude normalization circuit 28; the model of the trigonometric function converter U1 is AD 639; the circuit has an inverse cosine transform function, and performs an inverse cosine process on a signal output from the second photoelectric conversion circuit 26.

Embodiment 3 adaptive amplitude normalization circuit

Since the amplitude of the signal output by the functional conversion circuit 27 is small and is influenced by a plurality of parameters in the circuit and the circuit, the size is not fixed, the invention designs the adaptive amplitude normalization circuit 28 for normalizing the amplitude of the signal output by the functional conversion circuit 27 to the optimal size so as to further improve the demodulation precision. The specific structure is that one end of a capacitor C11 is connected with one end of a resistor R21 and a pin 3 of a chip U2, the other end of the resistor R21 is grounded, and the other end of the capacitor C11 is used as an input end of an adaptive amplitude normalization circuit 28, is recorded as a port ADAPT _ in, and is connected with a port ACOS _ out of a function conversion circuit 27; pin 1, pin 7, pin 8 and pin 14 of the chip U2 are all grounded, pin 2 and pin 4 are both connected with a +5V power supply, pin 11 is connected with pin 12 and is connected with one end of a capacitor C5 and the +5V power supply, and the other end of the capacitor C5 is grounded; pin 13 of the chip U2 is connected with one end of a capacitor C4, and the other end of the capacitor C4 is grounded; pin 9 of the chip U2 is connected with one end of a capacitor C6, and the other end of the capacitor C6 is grounded; pin 5 of the chip U2 is connected with one end of a resistor R20 and a resistor R19, the other end of the resistor R20 is grounded, the other end of the resistor R19 is connected with the output end of the operational amplifier U8 and one end of a resistor R17, the positive power supply end of the operational amplifier U8 is connected with a +5V power supply, and the negative power supply end is grounded; the other end of the resistor R17 is connected with one end of the resistor R15 and one end of the resistor R16 and is connected to the inverting input end of the operational amplifier U8; the non-inverting input end of the operational amplifier U8 is connected with one end of a resistor R18, and the other end of the resistor R18 is connected with a +2.5V power supply; the other end of the resistor R15 is connected with one end of the capacitor C10 and is connected to the output end of the operational amplifier U7; the positive power supply end of the operational amplifier U7 is connected with a +5V power supply, and the negative power supply end is grounded; the other end of the capacitor C10 is connected with one end and the sliding end of the slide rheostat W3 and is connected to the inverting input end of the operational amplifier U7; the non-inverting input end of the operational amplifier U7 is connected with one end of a resistor R14, and the other end of the resistor R14 is connected with a +2.5V power supply; the other end of the slide rheostat W3 is connected with one end of a resistor R13; the other end of the resistor R16 is connected with the sliding end of the sliding rheostat W2 and the output end of the operational amplifier U6, and one end of the sliding rheostat W2 is connected with one end of the resistor R11; the other end of the resistor R11 is connected with one end of the resistor R10 and is connected to the inverting input end of the operational amplifier U6; the positive power supply end of the operational amplifier U6 is connected with a +5V power supply, and the negative power supply end is grounded; the non-inverting input end of the operational amplifier U6 is connected with one end of a resistor R12, and the other end of the resistor R12 is connected with a +2.5V power supply; the other end of the resistor R10 is connected with the other end of the resistor R13 and one end of the resistor R7 and is connected to the output end of the operational amplifier U5; the other end of the resistor R7 is connected with one end of the resistor R6 and is connected to the inverting input end of the operational amplifier U5; the other end of the resistor R6 is connected with the output end of the operational amplifier U4, the positive power supply of the operational amplifier U5 is connected with the +5V power supply, and the negative power supply is grounded; one end of the resistor R8 is connected with one end of the resistor R9 and is connected to the non-inverting input end of the operational amplifier U5, and the other end of the resistor R9 is connected with a +2.5V power supply; the other end of the resistor R8 is used as a reference voltage end of the adaptive amplitude normalization circuit 28 and is connected to a reference voltage output end of the reference voltage circuit 30; pin 10 of the chip U2, which is used as the output terminal of the adaptive amplitude normalization circuit 28 and is denoted as port ADAPT _ out, is connected to one input terminal of the phase comparison circuit 29; a pin 10 of the chip U2 is connected with one end of a capacitor C7, the other end of the capacitor C7 is connected with one end of a resistor R22 and the non-inverting input end of the operational amplifier U3, and the other end of the resistor R22 is grounded; one end of the resistor R3 is connected with one end of the capacitor C8 and the anode of the diode D1 and is connected to the inverting input end of the operational amplifier U3, and the substrate (namely, pin 8) of the operational amplifier U3 is connected to the inverting input end of the operational amplifier U3; the positive power supply of the operational amplifier U3 is connected with a +5V power supply, and the negative power supply is connected with a-5V power supply; the other end of the capacitor C8 is connected with the cathode of the diode D1 and the anode of the diode D2 and is connected to the output end of the operational amplifier U3; the other end of the resistor R3 is connected with one end of a resistor R4 and the inverting input end of the operational amplifier U4, the other end of the resistor R4 is connected with the cathode of a diode D2 and the grid of a field-effect tube Q1, the source of the field-effect tube Q1 is connected with one end of a capacitor C9 and one end of the resistor R5, and the other end of the capacitor C9 is connected with the other end of the resistor R5 and is grounded; the source electrode of the field effect transistor Q1 is connected with the drain electrode of the field effect transistor Q1 and is connected to the non-inverting input end of the operational amplifier U4; the inverting input end of the operational amplifier U4 is connected with the substrate of the operational amplifier U4 and the output end of the operational amplifier U4; the positive power supply of the operational amplifier U3 is connected with a +5V power supply, and the negative power supply is connected with a-5V power supply; the chip U2 is a variable gain amplifier chip with model number AD 8367.

Example 4 phase comparison Circuit

As shown in fig. 4, the PHASE comparator 29 used in the present invention has a structure that one end of a capacitor C12 is connected to the non-inverting input terminal of the operational amplifier U9 and one end of a resistor R23, and the other end of the capacitor C12 is used as an input terminal of the PHASE comparator 29, which is denoted as a port PHASE _ in1 and connected to a port ADAPT _ out of the adaptive amplitude normalization circuit 28; the other end of the resistor R23 is grounded; the positive power supply end of the operational amplifier U9 is connected with a +5V power supply, the negative power supply end is grounded, the inverted input end is grounded, and the output end is connected with the CLK end of the D trigger U10A; the D port of the D flip-flop U10A is grounded; one end of the capacitor C13 is grounded, and the other end of the capacitor C13 is connected with the PR end of the D flip-flop U10A; one end of the resistor R24 is connected with the PR end of the D flip-flop U10A, and the other end is connected with the Q end of the D flip-flop U10A; the CLR end of the D flip-flop U10A is connected with a +5V power supply, and the Q end of the D flip-flop U10A is not connected with the PR end of the D flip-flop U12A; one end of the capacitor C14 is connected to the non-inverting input terminal of the operational amplifier U11 and one end of the resistor R25, and the other end of the capacitor C14 is used as the other input terminal of the PHASE comparison circuit 29, is recorded as a port PHASE _ in2, and is connected to a port SineM _ out of the controllable frequency source 21; the other end of the resistor R25 is grounded; the positive power supply end of the operational amplifier U11 is connected with a +5V power supply, the negative power supply end is grounded, the inverted input end is grounded, and the output end is connected with the CLK end of the D trigger U10B; the D port of the D flip-flop U10B is grounded; one end of the capacitor C15 is grounded, and the other end of the capacitor C15 is connected with the PR end of the D flip-flop U10B; one end of the resistor R26 is connected with the PR end of the D flip-flop U10B, and the other end is connected with the Q end of the D flip-flop U10B; the CLR end of the D trigger U10B is connected with a +5V power supply, and the Q end of the D trigger U10B is not connected with the CLR end of the D trigger U12A; the D terminal and the CLK terminal of the D flip-flop U12A are both grounded, and the Q terminal serves as the output terminal of the PHASE comparison circuit 29 and is denoted as a port PHASE _ out. The circuit compares the phase of the standard sine wave output by the controllable frequency source 21 with the phase of the sine wave output by the adaptive amplitude normalization circuit 28 (the phase of the sine wave is influenced by the environment detected by the Bragg grating group 8), and sends the comparison result to the singlechip 18, and the singlechip 18 calculates the temperature change at the Bragg grating group 8 according to the phase difference.

EXAMPLE 5 reference Voltage Circuit

As shown in fig. 5, the reference voltage circuit 30 has a structure that one end of a resistor R27 is connected to a +5V power supply, the other end is connected to a non-inverting input terminal of an operational amplifier U13, an anode of a zener diode D3 is grounded, a cathode of the resistor R is connected to a non-inverting input terminal of an operational amplifier U13, an inverting input terminal of the operational amplifier U13 is connected to an output terminal, the positive power supply is connected to the +5V power supply, the negative power supply is grounded, the output terminal is a +2.5V power supply, and the +2.5V power supply in each module is provided by the output; one end of the slide rheostat W4 is connected with a +2.5V power supply, the other end of the slide rheostat W4 is grounded, and the slide end of the slide rheostat W14 is connected with the non-inverting input end of the operational amplifier U14; the inverting input terminal of the operational amplifier U14 is connected to its output terminal, the positive power supply terminal is connected to the +5V power supply, the negative power supply terminal is grounded, and the output terminal is used as the output terminal of the reference voltage circuit 30, and is recorded as the port Vref, and is connected to the reference voltage terminal of the adaptive amplitude normalization circuit 28.

EXAMPLE 6 controllable frequency Source

As shown in fig. 6, the structure of the controllable frequency source 21 used in the present invention is that one end of the resistor R28 is connected to the +12V power supply, and the other end is connected to the base of the transistor Q2; one end of the resistor R29 is connected with the base electrode of the triode Q2, and the other end is grounded; one end of the resistor R30 is connected with +12V, and the other end is connected with the collector of the triode Q2; one end of the capacitor C17 is connected with the collector of the triode Q2, and the other end is connected with a pin 2 of the chip U15; one end of the resistor R31 is connected with the emitter of the triode Q2, and the other end is connected with the anode of the electrolytic capacitor C16; the negative electrode of the electrolytic capacitor C16 is grounded; one end of the capacitor C18 is connected with a pin 2 of the chip U15, and the other end is connected with a pin 2 of the chip U16; one end of the capacitor C19 is connected to pin 2 of the chip U16, and the other end is used as the output end of the controllable frequency source 21 and is marked as a port SineM _ out; the base electrode of the triode Q2 is connected with the port SineM _ out; one end of the capacitor C20 is connected with a pin 5 of the chip U15, and the other end of the capacitor C20 is grounded; one end of the capacitor C21 is connected with a pin 5 of the chip U16, and the other end of the capacitor C21 is grounded; pin 1 and pin 10 of the chip U15 are connected with a +5V power supply, and pin 3, pin 4 and pin 6 are grounded; pin 9 is connected with one end of a resistor R32, pin 8 is connected with one end of a resistor R33, and pin 7 is connected with one end of a resistor R34; the other end of the resistor R32 is used as an input port of the controllable frequency source 21 and is denoted as a port SineM _ in 1; the other end of the resistor R33 serves as another input port of the controllable frequency source 21, and is denoted as a port SineM _ in 2; the port SineM _ in1 and the port SineM _ in2 are connected with the input end of the singlechip 18; the other end of the resistor R34 is connected with a +5V power supply; pin 1 and pin 10 of the chip U16 are connected with a +5V power supply, and pin 3, pin 4 and pin 6 are grounded; pin 9 is connected with one end of a resistor R35, pin 8 is connected with one end of a resistor R36, and pin 7 is connected with one end of a resistor R37; the other end of the resistor R35 is connected with a port SineM _ in 1; the other end of the resistor R36 is connected with a port SineM _ in 2; the other end of the resistor R37 is connected with a +5V power supply. The module outputs a standard sine wave with adjustable frequency to provide a required sine signal for the demodulation part of the invention.

Example 7 working principle of the invention

The working principle of the present invention will be described with reference to the above embodiments and the accompanying drawings. When the fiber bragg grating temperature monitoring device works, the fiber bragg grating group 8 is placed at each position (such as a sensitive position in a mine) where temperature change needs to be monitored, the arrangement grid grating group 8 is composed of 3 (or other numbers of the fiber bragg gratings according to needs) of different reflection spectrums, and temperature monitoring can be carried out on 3 (or more) targets at the same time. The ring cavity of the fiber laser composed of the erbium-doped fiber 3, the optical isolator 4, etc. provides a broadband light source for the fiber bragg grating group 8, each fiber bragg grating has a specific reflection spectrum, different gratings have different peak wavelengths of the reflection spectrum, when the temperature of a certain measured point changes, the peak wavelength of the reflection spectrum of the fiber bragg grating at the position can shift correspondingly, the reflection light enters into the michelson interferometer composed of the second optical coupler 6, the second piezoelectric ceramic 23, the first faraday rotating mirror 24 and the second faraday rotating mirror 25, and the controllable frequency source 21 provides a control signal sin (ω t) for the michelson interferometer, the signal is influenced by the light reflected by the fiber bragg grating in the interferometer, then is converted into an electric signal by the second photoelectric conversion circuit 26, and sin (ω t + Δ θ) is obtained after the inverse cosine conversion of the function conversion circuit 27, the amplitude of the signal is adjusted to a proper value (controlled by a reference voltage circuit 30) after passing through the self-adaptive amplitude normalization circuit 28, the phase of the signal is changed compared with a sine signal sin (ω t) generated by the controllable frequency source 21, the phase difference between the signal and the sine signal sin (ω t) is detected by the phase comparison circuit 29 and is sent to the singlechip 18, the phase difference reflects the temperature change of the measured point, and the temperature detection of the measured point is finally realized. The invention does not use the sawtooth wave in the modulation and demodulation process, thereby avoiding the high-frequency jitter signal caused by the falling edge of the sawtooth wave, and the band-pass filter is not needed to be used for filtering in the demodulation circuit, thereby avoiding the influence on the amplitude-frequency characteristic and the phase-frequency characteristic of the output signal. The invention uses the standard sine wave signal as PZT modulating signal, when demodulating the modulating signal, it uses the function transforming circuit 27 and the self-adapting amplitude normalization circuit 28 skillfully, recovers the modulating signal into the sine signal whose phase is controlled by the Bragg grating group 8 and the amplitude is suitable, when comparing the phase in the phase comparing circuit 29, it can compare the phase difference between the controlled signal and the original signal very accurately, thus accurately reflecting the environment parameter detected by the sensing head (i.e. the Bragg grating group 8).

Because the ring cavity of the fiber laser is susceptible to the influence of the environmental temperature (generally not at the same position as the sensing probe of the fiber bragg grating group 8) when in work, the fiber laser also has a temperature compensation function and consists of a constant current source circuit 15, a thermistor 16 and an analog-to-digital conversion circuit 17. The thermistor 16 is a temperature sensitive device, and when the ambient temperature changes, the resistance value of the thermistor will change, and since the constant current source circuit 15 provides constant current for the thermistor, the change of the resistance value of the thermistor 16 will cause the change of the voltage generated at the two ends of the thermistor, and the change is converted into a digital signal by the analog-to-digital conversion circuit 17 to be input into the single chip 18, so as to compensate the error brought to the measurement result by the change of the ambient temperature of the fiber laser annular cavity.

Claims

1. A multipoint temperature sensing system formed by Bragg gratings has the structure that a pumping source (1) is connected with a 980nm end of an optical wavelength division multiplexer (2), a 1550nm end of the optical wavelength division multiplexer (2) is connected with one end of an optical fiber wound on first piezoelectric ceramics (11), the other end of the optical fiber wound on the first piezoelectric ceramics (11) is connected with an input end of a first optical isolator (10), a control end of the first piezoelectric ceramics (11) is connected with an output port of a first PZT driving circuit (12), an input end of the first PZT driving circuit (12) is connected with an output port of a first digital-to-analog conversion circuit (13), and an input port of the first digital-to-analog conversion circuit (13) is connected with a single chip microcomputer (18); the output end of the first optical isolator (10) is connected with the optical input end of the optical filter (9), the electric control end of the optical filter (9) is connected with the single chip microcomputer (18), the optical output end of the optical filter (9) is connected with the first port of the optical circulator (7), the second port of the optical circulator (7) is connected with one end of the Bragg grating group (8), the third port of the optical circulator (7) is connected with the input end of the first optical coupler (5), 90% of the output end of the first optical coupler (5) is connected with the input end of the second optical isolator (4), the output end of the second optical isolator (4) is connected with one end of the erbium-doped optical fiber (3), and the other end of the erbium-doped optical fiber (3) is connected with the common end of the optical wavelength division multiplexer (2); the 10% output end of the first optical coupler (5) is connected with the input end of the second optical coupler (6), one output end of the second optical coupler (6) is connected with the input end of the second Faraday rotator mirror (25), the other output end of the second optical coupler (6) is connected with one end of an optical fiber wound on the second piezoelectric ceramic (23), the other end of the optical fiber wound on the second piezoelectric ceramic (23) is connected with the input end of the first Faraday rotator mirror (24), and the other output end of the second optical coupler (6) is connected with the input end of the second photoelectric conversion circuit (26);

the output end of the second photoelectric conversion circuit (26) is connected with the input end of a function conversion circuit (27), the output end of the function conversion circuit (27) is connected with one input end of an adaptive amplitude normalization circuit (28), the output end of a reference voltage circuit (30) is connected with the other input end of the adaptive amplitude normalization circuit (28), and the output end of the adaptive amplitude normalization circuit (28) is connected with one input end of a phase comparison circuit (29); the input end of the controllable frequency source (21) is connected with the singlechip (18), the output end of the controllable frequency source is connected with the other input end of the phase comparison circuit (29), and the output end of the phase comparison circuit (29) is connected with the singlechip (18); the output end of the controllable frequency source (21) is also connected with the input end of a second PZT driving circuit (22), and the output end of the second PZT driving circuit (22) is connected with the control end of a second piezoelectric ceramic (23); the output end of the constant current source circuit (15) is connected with the thermistor (16), the thermistor (16) is connected with the input end of the analog-to-digital conversion circuit (17), and the output end of the analog-to-digital conversion circuit (17) is connected with the singlechip (18); the singlechip (20) is also connected with the input key (14), the serial port communication module (19) and the display screen (20) respectively;

the structure of the function conversion circuit (27) is that one end of a capacitor C3 is connected with the pin 12 of the trigonometric function converter U1 and one end of a resistor R2, and the other end of the capacitor C3 is used as the input end of the function conversion circuit (27) and is marked as a port ACOS _ in which is connected with the output end of the second photoelectric conversion circuit (26); the other end of the resistor R2 is grounded; pins 2, 3, 4, 5, 8, 11 and 13 of the trigonometric function converter U1 are grounded, pins 9 and 10 are connected with one end of a capacitor C2 and a-12V power supply, and the other end of the capacitor C2 is grounded; pin 6 of the trigonometric function converter U1 is connected with pin 7, pin 16 is connected with the +12V power supply and one end of the capacitor C1, and the other end of the capacitor C1 is grounded; pin 1 of the trigonometric function converter U1 is connected with the sliding end of a sliding rheostat W1, one end of a sliding rheostat W1 is connected with one end of a resistor R1, the other end of the resistor R1 is connected with a pin 14 of a trigonometric function converter U1, and the sliding end of a sliding rheostat W1 is used as the output end of a function transformation circuit (27), is recorded as a port ACOS _ out and is connected with the input end of an adaptive amplitude normalization circuit (28); the model of the trigonometric function converter U1 is AD 639;

the adaptive amplitude normalization circuit (28) is structurally characterized in that one end of a capacitor C11 is connected with one end of a resistor R21 and a pin 3 of a chip U2, the other end of the resistor R21 is grounded, and the other end of the capacitor C11 is used as an input end of the adaptive amplitude normalization circuit (28), is recorded as a port ADAPT _ in and is connected with a port ACOS _ out of a function conversion circuit (27); pin 1, pin 7, pin 8 and pin 14 of the chip U2 are all grounded, pin 2 and pin 4 are both connected with a +5V power supply, pin 11 is connected with pin 12 and is connected with one end of a capacitor C5 and the +5V power supply, and the other end of the capacitor C5 is grounded; pin 13 of the chip U2 is connected with one end of a capacitor C4, and the other end of the capacitor C4 is grounded; pin 9 of the chip U2 is connected with one end of a capacitor C6, and the other end of the capacitor C6 is grounded; pin 5 of the chip U2 is connected with one end of a resistor R20 and a resistor R19, the other end of the resistor R20 is grounded, the other end of the resistor R19 is connected with the output end of the operational amplifier U8 and one end of a resistor R17, the positive power supply end of the operational amplifier U8 is connected with a +5V power supply, and the negative power supply end is grounded; the other end of the resistor R17 is connected with one end of the resistor R15 and one end of the resistor R16 and is connected to the inverting input end of the operational amplifier U8; the non-inverting input end of the operational amplifier U8 is connected with one end of a resistor R18, and the other end of the resistor R18 is connected with a +2.5V power supply; the other end of the resistor R15 is connected with one end of the capacitor C10 and is connected to the output end of the operational amplifier U7; the positive power supply end of the operational amplifier U7 is connected with a +5V power supply, and the negative power supply end is grounded; the other end of the capacitor C10 is connected with one end and the sliding end of the slide rheostat W3 and is connected to the inverting input end of the operational amplifier U7; the non-inverting input end of the operational amplifier U7 is connected with one end of a resistor R14, and the other end of the resistor R14 is connected with a +2.5V power supply; the other end of the slide rheostat W3 is connected with one end of a resistor R13; the other end of the resistor R16 is connected with the sliding end of the sliding rheostat W2 and the output end of the operational amplifier U6, and one end of the sliding rheostat W2 is connected with one end of the resistor R11; the other end of the resistor R11 is connected with one end of the resistor R10 and is connected to the inverting input end of the operational amplifier U6; the positive power supply end of the operational amplifier U6 is connected with a +5V power supply, and the negative power supply end is grounded; the non-inverting input end of the operational amplifier U6 is connected with one end of a resistor R12, and the other end of the resistor R12 is connected with a +2.5V power supply; the other end of the resistor R10 is connected with the other end of the resistor R13 and one end of the resistor R7 and is connected to the output end of the operational amplifier U5; the other end of the resistor R7 is connected with one end of the resistor R6 and is connected to the inverting input end of the operational amplifier U5; the other end of the resistor R6 is connected with the output end of the operational amplifier U4, the positive power supply of the operational amplifier U5 is connected with the +5V power supply, and the negative power supply is grounded; one end of the resistor R8 is connected with one end of the resistor R9 and is connected to the non-inverting input end of the operational amplifier U5, and the other end of the resistor R9 is connected with a +2.5V power supply; the other end of the resistor R8 is used as a reference voltage end of the adaptive amplitude normalization circuit (28) and is connected with a reference voltage output end of the reference voltage circuit (30); pin 10 of the chip U2, which is used as the output terminal of the adaptive amplitude normalization circuit (28), is marked as port ADAPT _ out and is connected to one input terminal of the phase comparison circuit (29); a pin 10 of the chip U2 is connected with one end of a capacitor C7, the other end of the capacitor C7 is connected with one end of a resistor R22 and the non-inverting input end of the operational amplifier U3, and the other end of the resistor R22 is grounded; one end of the resistor R3 is connected with one end of the capacitor C8 and the anode of the diode D1 and is connected to the inverting input end of the operational amplifier U3, and the substrate of the operational amplifier U3 is connected to the inverting input end of the operational amplifier U3; the positive power supply of the operational amplifier U3 is connected with a +5V power supply, and the negative power supply is connected with a-5V power supply; the other end of the capacitor C8 is connected with the cathode of the diode D1 and the anode of the diode D2 and is connected to the output end of the operational amplifier U3; the other end of the resistor R3 is connected with one end of a resistor R4 and the inverting input end of the operational amplifier U4, the other end of the resistor R4 is connected with the cathode of a diode D2 and the grid of a field-effect tube Q1, the source of the field-effect tube Q1 is connected with one end of a capacitor C9 and one end of the resistor R5, and the other end of the capacitor C9 is connected with the other end of the resistor R5 and is grounded; the source electrode of the field effect transistor Q1 is connected with the drain electrode of the field effect transistor Q1 and is connected to the non-inverting input end of the operational amplifier U4; the inverting input end of the operational amplifier U4 is connected with the substrate of the operational amplifier U4 and the output end of the operational amplifier U4; the positive power supply of the operational amplifier U3 is connected with a +5V power supply, and the negative power supply is connected with a-5V power supply; the chip U2 is a variable gain amplifier chip, and the model is AD 8367;

the structure of the PHASE comparison circuit (29) is that one end of a capacitor C12 is connected with the non-inverting input end of an operational amplifier U9 and one end of a resistor R23, the other end of the capacitor C12 is used as one input end of the PHASE comparison circuit (29), is recorded as a port PHASE _ in1 and is connected with a port ADAPT _ out of the self-adaptive amplitude normalization circuit (28); the other end of the resistor R23 is grounded; the positive power supply end of the operational amplifier U9 is connected with a +5V power supply, the negative power supply end is grounded, the inverted input end is grounded, and the output end is connected with the CLK end of the D trigger U10A; the D port of the D flip-flop U10A is grounded; one end of the capacitor C13 is grounded, and the other end of the capacitor C13 is connected with the PR end of the D flip-flop U10A; one end of the resistor R24 is connected with the PR end of the D flip-flop U10A, and the other end is connected with the Q end of the D flip-flop U10A; the CLR end of the D flip-flop U10A is connected with a +5V power supply, and the Q end of the D flip-flop U10A is not connected with the PR end of the D flip-flop U12A; one end of the capacitor C14 is connected with the non-inverting input end of the operational amplifier U11 and one end of the resistor R25, the other end of the capacitor C14 is used as the other input end of the PHASE comparison circuit (29), is recorded as a port PHASE _ in2 and is connected with a port Sinem _ out of the controllable frequency source (21); the other end of the resistor R25 is grounded; the positive power supply end of the operational amplifier U11 is connected with a +5V power supply, the negative power supply end is grounded, the inverted input end is grounded, and the output end is connected with the CLK end of the D trigger U10B; the D port of the D flip-flop U10B is grounded; one end of the capacitor C15 is grounded, and the other end of the capacitor C15 is connected with the PR end of the D flip-flop U10B; one end of the resistor R26 is connected with the PR end of the D flip-flop U10B, and the other end is connected with the Q end of the D flip-flop U10B; the CLR end of the D trigger U10B is connected with a +5V power supply, and the Q end of the D trigger U10B is not connected with the CLR end of the D trigger U12A; the D end and the CLK end of the D flip-flop U12A are both grounded, and the Q end is used as the output end of the PHASE comparison circuit (29) and is marked as a port PHASE _ out;

the reference voltage circuit (30) is structurally characterized in that one end of a resistor R27 is connected with a +5V power supply, the other end of the resistor R27 is connected with a non-inverting input end of an operational amplifier U13, the anode of a voltage stabilizing diode D3 is grounded, the cathode of the voltage stabilizing diode D3 is connected with the non-inverting input end of an operational amplifier U13, the inverting input end of the operational amplifier U13 is connected with an output end, the positive power supply is connected with the +5V power supply, the negative power supply is grounded, the output end of the operational amplifier U13 is the +2.5V power supply; one end of the slide rheostat W4 is connected with a +2.5V power supply, the other end of the slide rheostat W4 is grounded, and the slide end of the slide rheostat W14 is connected with the non-inverting input end of the operational amplifier U14; the inverting input end of the operational amplifier U14 is connected with the output end thereof, the positive power supply is connected with the +5V power supply, the negative power supply is grounded, the output end is used as the output end of the reference voltage circuit (30), is marked as a port Vref and is connected with the reference voltage end of the adaptive amplitude normalization circuit (28);

the structure of the controllable frequency source (21) is that one end of a resistor R28 is connected with a +12V power supply, and the other end is connected with the base electrode of a triode Q1; one end of the resistor R29 is connected with the base electrode of the triode Q1, and the other end is grounded; one end of the resistor R30 is connected with +12V, and the other end is connected with the collector of the triode Q2; one end of the capacitor C17 is connected with the collector of the triode Q2, and the other end is connected with a pin 2 of the chip U15; one end of the resistor R31 is connected with the emitter of the triode Q1, and the other end is connected with the anode of the electrolytic capacitor C16; the negative electrode of the electrolytic capacitor C16 is grounded; one end of the capacitor C18 is connected with a pin 2 of the chip U15, and the other end is connected with a pin 2 of the chip U16; one end of the capacitor C19 is connected with pin 2 of the chip U16, and the other end is used as the output end of the controllable frequency source (21) and is marked as a port Sinem _ out; the base electrode of the triode Q2 is connected with the port SineM _ out; one end of the capacitor C20 is connected with a pin 5 of the chip U15, and the other end of the capacitor C20 is grounded; one end of the capacitor C21 is connected with a pin 5 of the chip U16, and the other end of the capacitor C21 is grounded; pin 1 and pin 10 of the chip U15 are connected with a +5V power supply, and pin 3, pin 4 and pin 6 are grounded; pin 9 is connected with one end of a resistor R32, pin 8 is connected with one end of a resistor R33, and pin 7 is connected with one end of a resistor R34; the other end of the resistor R32 is used as an input port of the controllable frequency source (21) and is marked as a port SineM _ in 1; the other end of the resistor R33 is used as the other input port of the controllable frequency source (21) and is marked as a port SineM _ in 2; the port SineM _ in1 and the port SineM _ in2 are connected with the input end of the single chip microcomputer (18); the other end of the resistor R34 is connected with a +5V power supply; pin 1 and pin 10 of the chip U16 are connected with a +5V power supply, and pin 3, pin 4 and pin 6 are grounded; pin 9 is connected with one end of a resistor R35, pin 8 is connected with one end of a resistor R36, and pin 7 is connected with one end of a resistor R37; the other end of the resistor R35 is connected with a port SineM _ in 1; the other end of the resistor R36 is connected with a port SineM _ in 2; the other end of the resistor R37 is connected with a +5V power supply; the models of the chip U15 and the chip U16 are AD 5272-20.

2. The multipoint temperature sensing system of claim 1, wherein said pump source (1) is a 980nm laser source.

3. The multipoint temperature sensing system of a bragg grating according to claim 1 or 2, wherein the group of bragg gratings (8) is preferably formed by 3 bragg gratings, each having a reflectivity of 90%, a bandwidth of 0.6nm and a central wavelength of 1550nm, 1560nm and 1630nm, respectively.