CN109238533B

CN109238533B - Micro-stress sensor based on phase comparison

Info

Publication number: CN109238533B
Application number: CN201810889091.7A
Authority: CN
Inventors: 汝玉星; 毕琳旭; 杨忠岗; 孙茂强; 于广安
Original assignee: Jilin University
Current assignee: Jilin University
Priority date: 2018-08-07
Filing date: 2018-08-07
Publication date: 2020-05-05
Anticipated expiration: 2038-08-07
Also published as: CN109238533A

Abstract

The invention discloses a micro-stress sensor based on phase comparison, and belongs to the technical field of optical fiber sensors. The main structure of the device comprises a pump source (1), a light wavelength division multiplexer (2), an erbium-doped fiber (3) and the like. The invention uses the sine signal as the modulation signal, does not generate high-frequency interference, and has the characteristics of more reliable work, high sensing precision, wide application range and the like.

Description

Micro-stress sensor based on phase comparison

Technical Field

The invention belongs to the technical field of optical fiber sensors, and particularly relates to a micro-stress sensor based on phase comparison.

Background

The Bragg fiber grating (FBG) has the advantages of electromagnetic interference resistance, chemical corrosion resistance, small transmission loss, small volume, light weight, convenience for large-scale production and the like, and is widely applied to the technical field of sensing. At present, the stress sensor has wide application in the technical field of engineering. Particularly, in emerging fields of nanoparticle interaction, cell mechanics and the like, the micro-stress sensor has urgent requirements, and the micro-stress sensor is not separated from the bridge, the tunnel and the building structure for safety monitoring. Due to the advantages of the fiber Bragg grating, the stress sensor formed by the fiber Bragg grating has higher reliability compared with other sensors, and is more suitable for being used under severe conditions.

The closest prior art to the present invention is the "research and implementation of fiber grating sensing system" by doctor graduation thesis of bang-kai university bang, which provides a fiber bragg grating sensing system based on unbalanced michelson interferometric demodulation technology (see page 24, fig. 3.4 of the document), the fiber sensing system adopts unbalanced michelson interferometric principle, one of the two arms of the interferometer changes the length of the arm by using a modulation signal provided by piezoelectric ceramics (PZT), so as to change the output light intensity of the interferometer, the output light intensity of the interferometer is in cosine function law with the change of PZT modulation signal, if an ideal sawtooth wave is used as the modulation signal of PZT, the output of the fiber sensing system is directly cosine wave. The fiber sensing system senses the change of stress or temperature at a measuring point through the Bragg grating and reflects the change of the central wavelength of the reflection spectrum, the change of the central wavelength is reflected as the change of the phase of an output cosine wave after passing through the unbalanced Michelson interferometer, and finally the change of the central wavelength of the reflection spectrum of the Bragg grating can be reflected by comparing the phase of the cosine wave with the phase of the sawtooth wave, so that the change of the external stress is measured.

In the above-mentioned sensing system, there is the biggest problem that the sawtooth wave cannot be absolutely ideal, the ideal sawtooth wave falling edge is vertical, and the actual sawtooth wave falling edge always has a certain slope, so that the cosine wave output from the subsequent stage has a high-frequency jitter, and in order to eliminate the high-frequency jitter signal, a band-pass filter (BPF) must be used in the demodulation circuit of the subsequent stage to filter out the direct-current component and the high-frequency component. However, on the one hand, the high frequency component itself affects the phase detection of the cosine wave (the position of the zero-crossing point changes); on the other hand, the frequency of the high-frequency jitter signal is influenced by various factors such as the performance of a PZT driving circuit, the hysteresis characteristic of PZT (the electrical characteristic of PZT is equivalent to a capacitor, and the voltage at two ends of the PZT cannot jump, so that the falling edge of a sawtooth wave cannot be infinitely short) and the elasticity of an optical fiber, the frequency is variable, and the high-frequency jitter signal is difficult to filter; furthermore, when using a filter, in addition to the amplitude-frequency characteristic of the output signal, the phase-frequency characteristic of the signal is also affected, i.e. the filtering is affected by the phase around the cut-off frequency, which is very disadvantageous for fiber sensors that rely on phase changes to measure stress changes. Therefore, further improvements are needed in the existing fiber bragg grating stress sensors.

Disclosure of Invention

In order to overcome the defects of the existing Bragg fiber grating stress sensor, the invention provides the phase comparison-based micro-stress sensor which uses a sinusoidal signal as a PZT driving signal, so that the generation of high-frequency interference signals is avoided, and a filter is not needed when the received signal is processed, so that the influence of the filtering process on the phase is avoided.

The purpose of the invention is realized by the following technical scheme:

a micro-stress sensor based on phase comparison has the structure that a pumping source 1 is connected with the 980nm end of an optical wavelength division multiplexer 2, the 1550nm end of the optical wavelength division multiplexer 2 is connected with one end of an optical fiber wound on a first piezoelectric ceramic 11, the other end of the optical fiber wound on the first piezoelectric ceramic 11 is connected with the input end of a first optical isolator 10, the control end of the first piezoelectric ceramic 11 is connected with the output port of a first PZT driving circuit 12, the input end of the first PZT driving circuit 12 is connected with the output port of a digital-to-analog conversion circuit 13, and the input port of the digital-to-analog conversion circuit 13 is connected with a single chip microcomputer 16; the output end of the first optical isolator 10 is connected with the optical input end of the optical filter 9, the electric control end of the optical filter 9 is connected with the single chip microcomputer 16, the optical output end of the optical filter 9 is connected with the first port of the optical circulator 7, the second port of the optical circulator 7 is connected with one end of the Bragg grating group 8, the third port of the optical circulator 7 is connected with the input end of the first optical coupler 5, 90% of the output end of the first optical coupler 5 is connected with the input end of the second optical isolator 4, the output end of the second optical isolator 4 is connected with one end of the erbium-doped optical fiber 3, and the other end of the erbium-doped optical fiber 3 is connected with the common end of the optical wavelength division multiplexer 2; the output of 10% of the output end of the first optical coupler 5 is connected with the input end of the second optical coupler 6, one output end of the second optical coupler 6 is connected with the input end of the second faraday rotator 23, the other output end of the second optical coupler 6 is connected with one end of the optical fiber wound on the second piezoelectric ceramic 21, the other end of the optical fiber wound on the second piezoelectric ceramic 21 is connected with the input end of the first faraday rotator 22, and the other output end of the second optical coupler 6 is connected with the input end of the second photoelectric conversion circuit 24;

it is characterized in that the structure is also such that the output terminal of the second photoelectric conversion circuit 24 is connected to the input terminal of the function conversion circuit 25, the output terminal of the function conversion circuit 25 is connected to one input terminal of the adaptive amplitude normalization circuit 26, the output terminal of the reference voltage circuit 28 is connected to the other input terminal of the adaptive amplitude normalization circuit 26, and the output terminal of the adaptive amplitude normalization circuit 26 is connected to one input terminal of the phase comparison circuit 27; the input end of the controllable frequency source 19 is connected with the single chip microcomputer 16, the output end of the controllable frequency source is connected with the other input end of the phase comparison circuit 27, and the output end of the phase comparison circuit 27 is connected with the single chip microcomputer 16; the output end of the controllable frequency source 19 is also connected with the input end of a second PZT driving circuit 20, and the output end of the second PZT driving circuit 20 is connected with the control end of a second piezoelectric ceramic 21; the temperature sensor 15 is connected with the singlechip 16; the single chip microcomputer 16 is also respectively connected with the input key 14, the serial port communication module 17 and the display screen 18;

the structure of the function conversion circuit 25 is that one end of a capacitor C3 is connected with the pin 12 of the trigonometric function converter U1 and one end of a resistor R2, and the other end of the capacitor C3 is used as the input end of the function conversion circuit 25, is recorded as a port ACOS _ in, and is connected with the output end of the second photoelectric conversion circuit 24; the other end of the resistor R2 is grounded;

pins

2, 3, 4, 5, 8, 11 and 13 of the trigonometric function converter U1 are grounded,

pins

9 and 10 are connected with one end of a capacitor C2 and a-12V power supply, and the other end of the capacitor C2 is grounded; pin 6 of the trigonometric function converter U1 is connected with pin 7, pin 16 is connected with the +12V power supply and one end of the capacitor C1, and the other end of the capacitor C1 is grounded; pin 1 of the trigonometric function converter U1 is connected with the sliding end of the sliding rheostat W1, one end of the sliding rheostat W1 is connected with one end of a resistor R1, the other end of the resistor R1 is connected with the pin 14 of the trigonometric function converter U1, and the sliding end of the sliding rheostat W1 is used as the output end of the function transformation circuit 25, is recorded as a port ACOS _ out, and is connected with the input end of the adaptive amplitude normalization circuit 26; the model of the trigonometric function converter U1 is AD 639;

the adaptive amplitude normalization circuit 26 has a structure that one end of a capacitor C11 is connected with one end of a resistor R21 and a pin 3 of a chip U2, the other end of the resistor R21 is grounded, and the other end of the capacitor C11 is used as an input end of the adaptive amplitude normalization circuit 26, is recorded as a port ADAPT _ in, and is connected with a port ACOS _ out of the function conversion circuit 25; pin 1, pin 7, pin 8 and pin 14 of the chip U2 are all grounded, pin 2 and pin 4 are both connected with a +5V power supply, pin 11 is connected with pin 12 and is connected with one end of a capacitor C5 and the +5V power supply, and the other end of the capacitor C5 is grounded; pin 13 of the chip U2 is connected with one end of a capacitor C4, and the other end of the capacitor C4 is grounded; pin 9 of the chip U2 is connected with one end of a capacitor C6, and the other end of the capacitor C6 is grounded; pin 5 of the chip U2 is connected with one end of a resistor R20 and a resistor R19, the other end of the resistor R20 is grounded, the other end of the resistor R19 is connected with the output end of the operational amplifier U8 and one end of a resistor R17, the positive power supply end of the operational amplifier U8 is connected with a +5V power supply, and the negative power supply end is grounded; the other end of the resistor R17 is connected with one end of the resistor R15 and one end of the resistor R16 and is connected to the inverting input end of the operational amplifier U8; the non-inverting input end of the operational amplifier U8 is connected with one end of a resistor R18, and the other end of the resistor R18 is connected with a +2.5V power supply; the other end of the resistor R15 is connected with one end of the capacitor C10 and is connected to the output end of the operational amplifier U7; the positive power supply end of the operational amplifier U7 is connected with a +5V power supply, and the negative power supply end is grounded; the other end of the capacitor C10 is connected with one end and the sliding end of the slide rheostat W3 and is connected to the inverting input end of the operational amplifier U7; the non-inverting input end of the operational amplifier U7 is connected with one end of a resistor R14, and the other end of the resistor R14 is connected with a +2.5V power supply; the other end of the slide rheostat W3 is connected with one end of a resistor R13; the other end of the resistor R16 is connected with the sliding end of the sliding rheostat W2 and the output end of the operational amplifier U6, and one end of the sliding rheostat W2 is connected with one end of the resistor R11; the other end of the resistor R11 is connected with one end of the resistor R10 and is connected to the inverting input end of the operational amplifier U6; the positive power supply end of the operational amplifier U6 is connected with a +5V power supply, and the negative power supply end is grounded; the non-inverting input end of the operational amplifier U6 is connected with one end of a resistor R12, and the other end of the resistor R12 is connected with a +2.5V power supply; the other end of the resistor R10 is connected with the other end of the resistor R13 and one end of the resistor R7 and is connected to the output end of the operational amplifier U5; the other end of the resistor R7 is connected with one end of the resistor R6 and is connected to the inverting input end of the operational amplifier U5; the other end of the resistor R6 is connected with the output end of the operational amplifier U4, the positive power supply of the operational amplifier U5 is connected with the +5V power supply, and the negative power supply is grounded; one end of the resistor R8 is connected with one end of the resistor R9 and is connected to the non-inverting input end of the operational amplifier U5, and the other end of the resistor R9 is connected with a +2.5V power supply; the other end of the resistor R8 is used as a reference voltage end of the adaptive amplitude normalization circuit 26 and is connected to a reference voltage output end of the reference voltage circuit 28; pin 10 of the chip U2, which is used as the output terminal of the adaptive amplitude normalization circuit 26 and is denoted as port ADAPT _ out, is connected to one input terminal of the phase comparison circuit 27; a pin 10 of the chip U2 is connected with one end of a capacitor C7, the other end of the capacitor C7 is connected with one end of a resistor R22 and the non-inverting input end of the operational amplifier U3, and the other end of the resistor R22 is grounded; one end of the resistor R3 is connected with one end of the capacitor C8 and the anode of the diode D1 and is connected to the inverting input end of the operational amplifier U3, and the substrate (namely, pin 8) of the operational amplifier U3 is connected to the inverting input end of the operational amplifier U3; the positive power supply of the operational amplifier U3 is connected with a +5V power supply, and the negative power supply is connected with a-5V power supply; the other end of the capacitor C8 is connected with the cathode of the diode D1 and the anode of the diode D2 and is connected to the output end of the operational amplifier U3; the other end of the resistor R3 is connected with one end of a resistor R4 and the inverting input end of the operational amplifier U4, the other end of the resistor R4 is connected with the cathode of a diode D2 and the grid of a field-effect tube Q1, the source of the field-effect tube Q1 is connected with one end of a capacitor C9 and one end of the resistor R5, and the other end of the capacitor C9 is connected with the other end of the resistor R5 and is grounded; the source electrode of the field effect transistor Q1 is connected with the drain electrode of the field effect transistor Q1 and is connected to the non-inverting input end of the operational amplifier U4; the inverting input end of the operational amplifier U4 is connected with the substrate of the operational amplifier U4 and the output end of the operational amplifier U4; the positive power supply of the operational amplifier U3 is connected with a +5V power supply, and the negative power supply is connected with a-5V power supply; the chip U2 is a variable gain amplifier chip, and the model is AD 8367;

the structure of the PHASE comparison circuit 27 is that one end of a capacitor C12 is connected with the non-inverting input end of the operational amplifier U9 and one end of a resistor R23, and the other end of the capacitor C12 is used as one input end of the PHASE comparison circuit 27, is recorded as a port PHASE _ in1, and is connected with a port ADAPT _ out of the adaptive amplitude normalization circuit 26; the other end of the resistor R23 is grounded; the positive power supply end of the operational amplifier U9 is connected with a +5V power supply, the negative power supply end is grounded, the inverted input end is grounded, and the output end is connected with the CLK end of the D trigger U10A; the D port of the D flip-flop U10A is grounded; one end of the capacitor C13 is grounded, and the other end of the capacitor C13 is connected with the PR end of the D flip-flop U10A; one end of the resistor R24 is connected with the PR end of the D flip-flop U10A, and the other end is connected with the Q end of the D flip-flop U10A; the CLR end of the D flip-flop U10A is connected with a +5V power supply, and the Q end of the D flip-flop U10A is not connected with the PR end of the D flip-flop U12A; one end of the capacitor C14 is connected to the non-inverting input terminal of the operational amplifier U11 and one end of the resistor R25, and the other end of the capacitor C14 is used as the other input terminal of the PHASE comparison circuit 27, which is recorded as a port PHASE _ in2 and connected to a port SineM _ out of the controllable frequency source 19; the other end of the resistor R25 is grounded; the positive power supply end of the operational amplifier U11 is connected with a +5V power supply, the negative power supply end is grounded, the inverted input end is grounded, and the output end is connected with the CLK end of the D trigger U10B; the D port of the D flip-flop U10B is grounded; one end of the capacitor C15 is grounded, and the other end of the capacitor C15 is connected with the PR end of the D flip-flop U10B; one end of the resistor R26 is connected with the PR end of the D flip-flop U10B, and the other end is connected with the Q end of the D flip-flop U10B; the CLR end of the D trigger U10B is connected with a +5V power supply, and the Q end of the D trigger U10B is not connected with the CLR end of the D trigger U12A; the D end and the CLK end of the D flip-flop U12A are both grounded, and the Q end is used as the output end of the PHASE comparison circuit 27 and is denoted as a port PHASE _ out;

the structure of the reference voltage circuit 28 is that one end of a resistor R27 is connected with a +5V power supply, the other end is connected with a non-inverting input end of an operational amplifier U13, the anode of a voltage stabilizing diode D3 is grounded, the cathode is connected with the non-inverting input end of the operational amplifier U13, the inverting input end of the operational amplifier U13 is connected with an output end, the positive power supply is connected with the +5V power supply, the negative power supply is grounded, the output end is the +2.5V power supply, and the +2.5V power supply in each module is provided by the output end; one end of the slide rheostat W4 is connected with a +2.5V power supply, the other end of the slide rheostat W4 is grounded, and the slide end of the slide rheostat W14 is connected with the non-inverting input end of the operational amplifier U14; the inverting input end of the operational amplifier U14 is connected with the output end thereof, the positive power supply is connected with the +5V power supply, the negative power supply end is grounded, the output end is used as the output end of the reference voltage circuit 28, is marked as a port Vref and is connected with the reference voltage end of the adaptive amplitude normalization circuit 26;

the structure of the controllable frequency source 19 is that one end of a resistor R28 is connected with a +12V power supply, and the other end is connected with the base electrode of a triode Q1; one end of the resistor R29 is connected with the base electrode of the triode Q2, and the other end is grounded; one end of the resistor R30 is connected with +12V, and the other end is connected with the collector of the triode Q2; the anode of the electrolytic capacitor C17 is connected with the collector of the triode Q2, and the cathode is connected with the base of the triode Q3; one end of the resistor R31 is connected with the emitter of the triode Q2, and the other end is connected with the anode of the electrolytic capacitor C16; one end of the resistor R32 is connected with the anode of the electrolytic capacitor C16, and the other end is grounded; the negative electrode of the electrolytic capacitor C16 is grounded; one end of the resistor R33 is connected with a +12V power supply, and the other end is connected with the base electrode of the triode Q3; one end of the resistor R34 is connected with the base electrode of the triode Q3, and the other end is grounded; one end of the resistor R35 is connected with a +12V power supply, and the other end is connected with the collector of the triode Q3; one end of the resistor R36 is connected with the emitting electrode of the triode Q3, and the other end is grounded; the anode of the electrolytic capacitor C18 is connected with the emitter of the triode Q3, and the cathode is grounded; the anode of the electrolytic capacitor C19 is connected with the collector of the triode Q3, and the cathode is connected with one end of the thermistor Rt 1; the other end of the thermistor Rt1 is connected with the emitter of a triode Q2; the anode of the electrolytic capacitor C20 is connected with the collector of the triode Q3, and the cathode is connected with the pin 2 of the chip U15; one end of the capacitor C21 is connected with a pin 3 of the chip U15, and the other end is connected with a pin 2 of the chip U16; one end of the capacitor C22 is connected with pin 2 of the chip U16, and the other end is grounded; the anode of the electrolytic capacitor C23 is connected with the pin 2 of the chip U16, and the cathode is connected with the base electrode of the triode Q2; one end of the capacitor C24 is connected with a pin 5 of the chip U15, and the other end of the capacitor C24 is grounded; one end of the capacitor C25 is connected with a pin 5 of the chip U16, and the other end of the capacitor C25 is grounded; pin 1 and pin 10 of the chip U15 are connected with a +5V power supply, and pin 4 and pin 6 are grounded; pin 9 is connected with one end of a resistor R37, pin 8 is connected with one end of a resistor R38, and pin 7 is connected with one end of a resistor R39; the other end of the resistor R37 is used as an input port of the controllable frequency source 19 and is marked as a port Sinem _ in 1; the other end of the resistor R38 is used as another input port of the controllable frequency source 19, and is denoted as a port SineM _ in 2; the port SineM _ in1 and the port SineM _ in2 are connected with the input end of the singlechip 16; the other end of the resistor R39 is connected with a +5V power supply; pin 1 and pin 10 of the chip U10 are connected with a +5V power supply, and pin 4 and pin 6 are grounded; pin 9 is connected with one end of a resistor R40, pin 8 is connected with one end of a resistor R41, and pin 7 is connected with one end of a resistor R42; the other end of the resistor R40 is connected with a port SineM _ in 1; the other end of the resistor R41 is connected with a port SineM _ in 2; the other end of the resistor R42 is connected with a +5V power supply; the cathode of the electrolytic capacitor C18 serves as the output port of the controllable frequency source 19 and is denoted as SineM _ out.

The pump source 1 is preferably a 980nm laser source.

The temperature sensor 15 is preferably a DS18B20 digital temperature sensor.

Has the advantages that:

1. the invention uses the sine signal as the modulation signal, and compared with the prior art which uses the sawtooth wave signal for modulation, the invention can not generate high-frequency interference, so that the sensing system can work more reliably.

2. The invention uses the self-adaptive amplitude normalization circuit to automatically convert the amplitude of the demodulated signal into the amplitude suitable for the phase comparison circuit to compare, so that the phase detection error is smaller, and the sensing precision of the whole sensing system is effectively improved.

3. Compared with the prior art, the frequency of the modulation signal is adjustable, so that the sensing system has wider application occasions.

4. The invention has the function of temperature compensation and effectively overcomes the influence of the ambient temperature on the sensing parameters.

Drawings

Fig. 1 is an overall schematic block diagram of the present invention.

Fig. 2 is a schematic circuit diagram of a function conversion circuit used in the present invention.

Fig. 3 is a schematic circuit diagram of an adaptive amplitude normalization circuit used in the present invention.

Fig. 4 is a schematic circuit diagram of a phase comparison circuit used in the present invention.

Fig. 5 is a schematic circuit diagram of a reference voltage circuit used in the present invention.

Fig. 6 is a schematic circuit diagram of a controllable frequency source for use with the present invention.

Detailed Description

The operation principle of the present invention is further explained with reference to the drawings, and it should be understood that the component parameters marked in the drawings are the preferred parameters used in the following embodiments, and do not limit the scope of the present invention.

EXAMPLE 1 Overall Structure of the invention

As shown in FIG. 1, the overall structure of the present invention comprises a pump source 1 (a VENUS series 980nm high power single mode pump light source of Shanghai Kentite laser technology Co., Ltd., type VLSS-980-B, maximum single mode output power of 1200mW) connected to a 980nm end of an optical wavelength division multiplexer 2 (a fused tapered 980/1550nm pump optical wavelength division multiplexing coupler manufactured by Shanghai Hangyu optical fiber communication technology Co., Ltd.), a 1550nm end of the optical wavelength division multiplexer 2 connected to one end of an optical fiber wound on a first piezoelectric ceramic 11 (a 1310/1480/1550nm polarization independent optical isolator manufactured by Shanghai Hangyu optical fiber communication technology Co., Ltd.), the other end of the optical fiber wound on the first piezoelectric ceramic 11 connected to an input end of a first optical isolator 10 (a 1310/1480/1550nm polarization independent optical isolator manufactured by Shanghai optical fiber communication technology Co., Ltd.), the control end of the first piezoelectric ceramic 11 is connected with the output port of the first PZT driving circuit 12, the input end of the first PZT driving circuit 12 is connected with the output port of the digital-to-analog conversion circuit 13, and the input port of the digital-to-analog conversion circuit 13 is connected with the single chip microcomputer 16; the output end of the first optical isolator 10 is connected with the optical input end of an optical filter 9 (made by Micron Optics, model number FFP-TF-1060-010G0200-2.0), the electric control end of the optical filter 9 is connected with a singlechip 16, the optical output end of the optical filter 9 is connected with one end of an optical circulator 7 (PIOC 3-15 optical circulator made by Shanghai Hangyu Co., Ltd.), the second port of the optical circulator 7 is connected with one end of a Bragg grating group 8 (Bragg gratings with reflectivity of ninety percent, bandwidth of 0.6nm, central wavelength of 1550nm, 1560nm and 1630nm respectively), the third port of the optical circulator 7 is connected with the input end of a first optical coupler 5 (made by OZ-OPTICS, model number FUSED-12-1064-7/125-90/10-3U-3mm, splitting ratio of 90:10), the 90% output end of the first optical coupler 5 is connected with the input end of a second optical isolator 4 (1310/1480/1550 nm polarization independent optical isolator manufactured by shanghai vasta optical fiber communication technology limited), the output end of the second optical isolator 4 is connected with one end of an erbium-doped optical fiber 3 (a high-performance 980nm pumped C-Band erbium-doped optical fiber manufactured by Nufern corporation of America, the model is EDFC-980-HP, 3 meters), and the other end of the erbium-doped optical fiber 3 is connected with the common end of the optical wavelength division multiplexer 2. The above structure constitutes the basic light source portion and the sensing portion of the optical fiber sensor. The 10% output of the first optical coupler 5 is connected to the input of a second optical coupler 6(2 × 2 standard single-mode optical coupler with a splitting ratio of 50: 50), one output of the second optical coupler 6 is connected to the input of a second faraday rotator 23 (MFI-1310 manufactured by THORLABS), the other output of the second optical coupler 6 is connected to one end of an optical fiber wound on a second piezoelectric ceramic 21 (cylindrical piezoelectric ceramic, 50mm in outer diameter, 40mm in inner diameter, and 50mm in height), the other end of the optical fiber wound on the second piezoelectric ceramic 21 is connected to the input of a first faraday rotator 22 (MFI-1310 manufactured by THORLABS), and the other output of the second optical coupler 6 is connected to the input of a second photoelectric conversion circuit 24. The second optical coupler 6, the first faraday rotator 22, the second faraday rotator 23, and the second piezoelectric ceramic 21 together constitute a michelson interference structure.

The present invention also has a configuration in which the output terminal of the second photoelectric conversion circuit 24 is connected to the input terminal of the function conversion circuit 25, the output terminal of the function conversion circuit 25 is connected to one input terminal of the adaptive amplitude normalization circuit 26, the output terminal of the reference voltage circuit 28 is connected to the other input terminal of the adaptive amplitude normalization circuit 26, and the output terminal of the adaptive amplitude normalization circuit 26 is connected to one input terminal of the phase comparison circuit 27; the input end of the controllable frequency source 19 is connected with the single chip microcomputer 16(STC89C51), the output end is connected with the other input end of the phase comparison circuit 27, and the output end of the phase comparison circuit 27 is connected with the single chip microcomputer 16; the output of the controllable frequency source 19 is further connected to an input of a second PZT drive circuit 20, the output of the second PZT drive circuit 20 being connected to a control terminal of a second piezoelectric ceramic 21. The above structure constitutes the demodulation section of the sensor. The temperature sensor (15DS18B20) is connected with the singlechip 16, and provides a temperature compensation function for the invention. The single chip microcomputer 16 is also connected with an input key 14, a serial port communication module (17MAX232) and a display screen 18 respectively, and is used for setting parameters, communicating with a computer, displaying information and other functions.

Embodiment 2 function conversion circuit

pins

9 and 10 are connected with one end of a capacitor C2 and a-12V power supply, and the other end of the capacitor C2 is grounded; pin 6 of the trigonometric function converter U1 is connected with pin 7, pin 16 is connected with the +12V power supply and one end of the capacitor C1, and the other end of the capacitor C1 is grounded; pin 1 of the trigonometric function converter U1 is connected with the sliding end of the sliding rheostat W1, one end of the sliding rheostat W1 is connected with one end of a resistor R1, the other end of the resistor R1 is connected with the pin 14 of the trigonometric function converter U1, and the sliding end of the sliding rheostat W1 is used as the output end of the function transformation circuit 25, is recorded as a port ACOS _ out, and is connected with the input end of the adaptive amplitude normalization circuit 26; the model of the trigonometric function converter U1 is AD 639; the circuit has an inverse cosine transform function, and performs inverse cosine processing on a signal output by the second photoelectric conversion circuit 24.

Embodiment 3 adaptive amplitude normalization circuit

Since the amplitude of the signal output by the functional conversion circuit 25 is small and is influenced by a plurality of parameters in a circuit and a light path, and the size is not fixed, the invention designs the self-adaptive amplitude normalization circuit 26 for normalizing the amplitude of the signal output by the functional conversion circuit 25 into the optimal size so as to further improve the demodulation precision. The specific structure is that one end of a capacitor C11 is connected with one end of a resistor R21 and a pin 3 of a chip U2, the other end of the resistor R21 is grounded, and the other end of the capacitor C11 is used as an input end of an adaptive amplitude normalization circuit 26, is recorded as a port ADAPT _ in and is connected with a port ACOS _ out of a function conversion circuit 25; pin 1, pin 7, pin 8 and pin 14 of the chip U2 are all grounded, pin 2 and pin 4 are both connected with a +5V power supply, pin 11 is connected with pin 12 and is connected with one end of a capacitor C5 and the +5V power supply, and the other end of the capacitor C5 is grounded; pin 13 of the chip U2 is connected with one end of a capacitor C4, and the other end of the capacitor C4 is grounded; pin 9 of the chip U2 is connected with one end of a capacitor C6, and the other end of the capacitor C6 is grounded; pin 5 of the chip U2 is connected with one end of a resistor R20 and a resistor R19, the other end of the resistor R20 is grounded, the other end of the resistor R19 is connected with the output end of the operational amplifier U8 and one end of a resistor R17, the positive power supply end of the operational amplifier U8 is connected with a +5V power supply, and the negative power supply end is grounded; the other end of the resistor R17 is connected with one end of the resistor R15 and one end of the resistor R16 and is connected to the inverting input end of the operational amplifier U8; the non-inverting input end of the operational amplifier U8 is connected with one end of a resistor R18, and the other end of the resistor R18 is connected with a +2.5V power supply; the other end of the resistor R15 is connected with one end of the capacitor C10 and is connected to the output end of the operational amplifier U7; the positive power supply end of the operational amplifier U7 is connected with a +5V power supply, and the negative power supply end is grounded; the other end of the capacitor C10 is connected with one end and the sliding end of the slide rheostat W3 and is connected to the inverting input end of the operational amplifier U7; the non-inverting input end of the operational amplifier U7 is connected with one end of a resistor R14, and the other end of the resistor R14 is connected with a +2.5V power supply; the other end of the slide rheostat W3 is connected with one end of a resistor R13; the other end of the resistor R16 is connected with the sliding end of the sliding rheostat W2 and the output end of the operational amplifier U6, and one end of the sliding rheostat W2 is connected with one end of the resistor R11; the other end of the resistor R11 is connected with one end of the resistor R10 and is connected to the inverting input end of the operational amplifier U6; the positive power supply end of the operational amplifier U6 is connected with a +5V power supply, and the negative power supply end is grounded; the non-inverting input end of the operational amplifier U6 is connected with one end of a resistor R12, and the other end of the resistor R12 is connected with a +2.5V power supply; the other end of the resistor R10 is connected with the other end of the resistor R13 and one end of the resistor R7 and is connected to the output end of the operational amplifier U5; the other end of the resistor R7 is connected with one end of the resistor R6 and is connected to the inverting input end of the operational amplifier U5; the other end of the resistor R6 is connected with the output end of the operational amplifier U4, the positive power supply of the operational amplifier U5 is connected with the +5V power supply, and the negative power supply is grounded; one end of the resistor R8 is connected with one end of the resistor R9 and is connected to the non-inverting input end of the operational amplifier U5, and the other end of the resistor R9 is connected with a +2.5V power supply; the other end of the resistor R8 is used as a reference voltage end of the adaptive amplitude normalization circuit 26 and is connected to a reference voltage output end of the reference voltage circuit 28; pin 10 of the chip U2, which is used as the output terminal of the adaptive amplitude normalization circuit 26 and is denoted as port ADAPT _ out, is connected to one input terminal of the phase comparison circuit 27; a pin 10 of the chip U2 is connected with one end of a capacitor C7, the other end of the capacitor C7 is connected with one end of a resistor R22 and the non-inverting input end of the operational amplifier U3, and the other end of the resistor R22 is grounded; one end of the resistor R3 is connected with one end of the capacitor C8 and the anode of the diode D1 and is connected to the inverting input end of the operational amplifier U3, and the substrate (namely, pin 8) of the operational amplifier U3 is connected to the inverting input end of the operational amplifier U3; the positive power supply of the operational amplifier U3 is connected with a +5V power supply, and the negative power supply is connected with a-5V power supply; the other end of the capacitor C8 is connected with the cathode of the diode D1 and the anode of the diode D2 and is connected to the output end of the operational amplifier U3; the other end of the resistor R3 is connected with one end of a resistor R4 and the inverting input end of the operational amplifier U4, the other end of the resistor R4 is connected with the cathode of a diode D2 and the grid of a field-effect tube Q1, the source of the field-effect tube Q1 is connected with one end of a capacitor C9 and one end of the resistor R5, and the other end of the capacitor C9 is connected with the other end of the resistor R5 and is grounded; the source electrode of the field effect transistor Q1 is connected with the drain electrode of the field effect transistor Q1 and is connected to the non-inverting input end of the operational amplifier U4; the inverting input end of the operational amplifier U4 is connected with the substrate of the operational amplifier U4 and the output end of the operational amplifier U4; the positive power supply of the operational amplifier U3 is connected with a +5V power supply, and the negative power supply is connected with a-5V power supply; the chip U2 is a variable gain amplifier chip, and the model is AD 8367;

example 4 phase comparison Circuit

As shown in fig. 4, the PHASE comparator 27 used in the present invention has a structure that one end of a capacitor C12 is connected to the non-inverting input terminal of the operational amplifier U9 and one end of a resistor R23, and the other end of the capacitor C12 is used as an input terminal of the PHASE comparator 27, which is denoted as a port PHASE _ in1, and is connected to a port ADAPT _ out of the adaptive amplitude normalization circuit 26; the other end of the resistor R23 is grounded; the positive power supply end of the operational amplifier U9 is connected with a +5V power supply, the negative power supply end is grounded, the inverted input end is grounded, and the output end is connected with the CLK end of the D trigger U10A; the D port of the D flip-flop U10A is grounded; one end of the capacitor C13 is grounded, and the other end of the capacitor C13 is connected with the PR end of the D flip-flop U10A; one end of the resistor R24 is connected with the PR end of the D flip-flop U10A, and the other end is connected with the Q end of the D flip-flop U10A; the CLR end of the D flip-flop U10A is connected with a +5V power supply, and the Q end of the D flip-flop U10A is not connected with the PR end of the D flip-flop U12A; one end of the capacitor C14 is connected to the non-inverting input terminal of the operational amplifier U11 and one end of the resistor R25, and the other end of the capacitor C14 is used as the other input terminal of the PHASE comparison circuit 27, which is recorded as a port PHASE _ in2 and connected to a port SineM _ out of the controllable frequency source 19; the other end of the resistor R25 is grounded; the positive power supply end of the operational amplifier U11 is connected with a +5V power supply, the negative power supply end is grounded, the inverted input end is grounded, and the output end is connected with the CLK end of the D trigger U10B; the D port of the D flip-flop U10B is grounded; one end of the capacitor C15 is grounded, and the other end of the capacitor C15 is connected with the PR end of the D flip-flop U10B; one end of the resistor R26 is connected with the PR end of the D flip-flop U10B, and the other end is connected with the Q end of the D flip-flop U10B; the CLR end of the D trigger U10B is connected with a +5V power supply, and the Q end of the D trigger U10B is not connected with the CLR end of the D trigger U12A; the D terminal and the CLK terminal of the D flip-flop U12A are both grounded, and the Q terminal serves as the output terminal of the PHASE comparison circuit 27 and is denoted as a port PHASE _ out. The circuit compares the phase of the standard sine wave output by the controllable frequency source 19 with the phase of the sine wave output by the adaptive amplitude normalization circuit 26 (the phase of the sine wave is influenced by the environment detected by the Bragg grating group 8), and sends the comparison result to the singlechip 16, and the singlechip 16 calculates the stress change at the Bragg grating group 8 according to the phase difference.

EXAMPLE 5 reference Voltage Circuit

As shown in fig. 5, the reference voltage circuit 28 has a structure in which one end of a resistor R27 is connected to a +5V power supply, the other end is connected to a non-inverting input terminal of an operational amplifier U13, an anode of a zener diode D3 is grounded, a cathode of the zener diode D3 is connected to the non-inverting input terminal of the operational amplifier U13, an inverting input terminal of the operational amplifier U13 is connected to an output terminal, the positive power supply is connected to the +5V power supply, the negative power supply is grounded, the output terminal is a +2.5V power supply, and the +2.5V power supply in each module is; one end of the slide rheostat W4 is connected with a +2.5V power supply, the other end of the slide rheostat W4 is grounded, and the slide end of the slide rheostat W14 is connected with the non-inverting input end of the operational amplifier U14; the inverting input terminal of the operational amplifier U14 is connected to its output terminal, the positive power supply terminal is connected to the +5V power supply, the negative power supply terminal is grounded, and the output terminal is used as the output terminal of the reference voltage circuit 28, is recorded as the port Vref, and is connected to the reference voltage terminal of the adaptive amplitude normalization circuit 26.

EXAMPLE 6 controllable frequency Source

As shown in fig. 6, the controllable frequency source 19 used in the present invention has a structure that one end of a resistor R28 is connected to a +12V power supply, and the other end is connected to the base of a transistor Q1; one end of the resistor R29 is connected with the base electrode of the triode Q2, and the other end is grounded; one end of the resistor R30 is connected with +12V, and the other end is connected with the collector of the triode Q2; the anode of the electrolytic capacitor C17 is connected with the collector of the triode Q2, and the cathode is connected with the base of the triode Q3; one end of the resistor R31 is connected with the emitter of the triode Q2, and the other end is connected with the anode of the electrolytic capacitor C16; one end of the resistor R32 is connected with the anode of the electrolytic capacitor C16, and the other end is grounded; the negative electrode of the electrolytic capacitor C16 is grounded; one end of the resistor R33 is connected with a +12V power supply, and the other end is connected with the base electrode of the triode Q3; one end of the resistor R34 is connected with the base electrode of the triode Q3, and the other end is grounded; one end of the resistor R35 is connected with a +12V power supply, and the other end is connected with the collector of the triode Q3; one end of the resistor R36 is connected with the emitting electrode of the triode Q3, and the other end is grounded; the anode of the electrolytic capacitor C18 is connected with the emitter of the triode Q3, and the cathode is grounded; the anode of the electrolytic capacitor C19 is connected with the collector of the triode Q3, and the cathode is connected with one end of the thermistor Rt 1; the other end of the thermistor Rt1 is connected with the emitter of a triode Q2; the anode of the electrolytic capacitor C20 is connected with the collector of the triode Q3, and the cathode is connected with the pin 2 of the chip U15; one end of the capacitor C21 is connected with a pin 3 of the chip U15, and the other end is connected with a pin 2 of the chip U16; one end of the capacitor C22 is connected with pin 2 of the chip U16, and the other end is grounded; the anode of the electrolytic capacitor C23 is connected with the pin 2 of the chip U16, and the cathode is connected with the base electrode of the triode Q2; one end of the capacitor C24 is connected with a pin 5 of the chip U15, and the other end of the capacitor C24 is grounded; one end of the capacitor C25 is connected with a pin 5 of the chip U16, and the other end of the capacitor C25 is grounded; pin 1 and pin 10 of the chip U15 are connected with a +5V power supply, and pin 4 and pin 6 are grounded; pin 9 is connected with one end of a resistor R37, pin 8 is connected with one end of a resistor R38, and pin 7 is connected with one end of a resistor R39; the other end of the resistor R37 is used as an input port of the controllable frequency source 19 and is marked as a port Sinem _ in 1; the other end of the resistor R38 is used as another input port of the controllable frequency source 19, and is denoted as a port SineM _ in 2; the port SineM _ in1 and the port SineM _ in2 are connected with the input end of the singlechip 16; the other end of the resistor R39 is connected with a +5V power supply; pin 1 and pin 10 of the chip U10 are connected with a +5V power supply, and pin 4 and pin 6 are grounded; pin 9 is connected with one end of a resistor R40, pin 8 is connected with one end of a resistor R41, and pin 7 is connected with one end of a resistor R42; the other end of the resistor R40 is connected with a port SineM _ in 1; the other end of the resistor R41 is connected with a port SineM _ in 2; the other end of the resistor R42 is connected with a +5V power supply; the cathode of the electrolytic capacitor C18 serves as the output port of the controllable frequency source 19 and is denoted as SineM _ out. The module outputs a standard sine wave with adjustable frequency to provide a required sine signal for the demodulation part of the invention.

Example 7 working principle of the invention

The working principle of the present invention will be described with reference to the above embodiments and the accompanying drawings. When the device works, the fiber bragg grating group 8 is placed at each position (such as a bridge, a building load-bearing column and the like) needing to monitor stress change, a fiber laser annular cavity formed by the erbium-doped fiber 3, the optical isolator 4 and the like provides a broadband light source for the fiber bragg grating group 8, each fiber bragg grating has a specific reflection spectrum, different gratings have different peak wavelengths, when the stress of a certain measured object changes, the peak wavelength of the reflection spectrum of the fiber bragg grating at the position can be correspondingly shifted, the reflection light enters a michelson interferometer formed by the second optical coupler 6, the second piezoelectric ceramic 21, the first faraday rotating mirror 22 and the second faraday rotating mirror 23, and the controllable frequency source 19 provides a control signal sin (omega t) for the michelson interferometer, and the signal is influenced by the light reflected by the fiber bragg grating in the interferometer, the signal is converted into an electric signal by a second photoelectric conversion circuit 24 and subjected to inverse cosine transform by a function conversion circuit 25 to obtain sin (ω t + Δ θ), the amplitude of the signal is adjusted to a proper value (controlled by a reference voltage circuit 28) after passing through a self-adaptive amplitude normalization circuit 26, the phase of the signal is changed compared with a sine signal sin (ω t) generated by a controllable frequency source 19, the phase difference between the signal and the sine signal sin (ω t) is detected by a phase comparison circuit 27 and is sent to a single chip microcomputer 16, the phase difference reflects the stress change of a measured point actually, and finally the stress detection of the measured point is realized. The invention does not use the sawtooth wave in the modulation and demodulation process, thereby avoiding the high-frequency jitter signal caused by the falling edge of the sawtooth wave, and the band-pass filter is not needed to be used for filtering in the demodulation circuit, thereby avoiding the influence on the amplitude-frequency characteristic and the phase-frequency characteristic of the output signal. The invention utilizes the standard sine wave signal as the PZT modulating signal, when the modulating signal is demodulated, the modulating signal is skillfully restored to the sine signal which has the phase controlled by the Bragg grating group 8 and the proper amplitude by using the function conversion circuit 25 and the self-adaptive amplitude normalization circuit 26, so that when the phase comparison is carried out in the phase comparison circuit 27, the phase difference between the controlled signal and the original signal can be very accurately compared, thereby accurately reflecting the environmental parameters detected by the sensing head (namely the Bragg grating group 8).

Because the ring cavity of the fiber laser is susceptible to the influence of the environmental temperature (generally not in the same position as the sensing probe of the fiber bragg grating group 8) when working, the invention also designs a temperature compensation function, when the environmental temperature changes, the temperature converter 15 can convert the temperature change into a digital signal and input the digital signal into the singlechip 16, and the digital signal is used for compensating the error brought to the measurement result by the change of the environmental temperature of the ring cavity of the fiber laser.

Claims

1. A micro-stress sensor based on phase comparison has the structure that a pumping source (1) is connected with the 980nm end of an optical wavelength division multiplexer (2), the 1550nm end of the optical wavelength division multiplexer (2) is connected with one end of an optical fiber wound on first piezoelectric ceramics (11), the other end of the optical fiber wound on the first piezoelectric ceramics (11) is connected with the input end of a first optical isolator (10), the control end of the first piezoelectric ceramics (11) is connected with the output port of a first PZT driving circuit (12), the input end of the first PZT driving circuit (12) is connected with the output port of a digital-to-analog conversion circuit (13), and the input port of the digital-to-analog conversion circuit (13) is connected with a single chip microcomputer (16); the output end of the first optical isolator (10) is connected with the optical input end of the optical filter (9), the electric control end of the optical filter (9) is connected with the single chip microcomputer (16), the optical output end of the optical filter (9) is connected with the first port of the optical circulator (7), the second port of the optical circulator (7) is connected with one end of the Bragg grating group (8), the third port of the optical circulator (7) is connected with the input end of the first optical coupler (5), 90% of the output end of the first optical coupler (5) is connected with the input end of the second optical isolator (4), the output end of the second optical isolator (4) is connected with one end of the erbium-doped optical fiber (3), and the other end of the erbium-doped optical fiber (3) is connected with the common end of the optical wavelength division multiplexer (2); the output of 10% of the output end of the first optical coupler (5) is connected with the input end of a second optical coupler (6), one output end of the second optical coupler (6) is connected with the input end of a second Faraday rotator mirror (23), the other output end of the second optical coupler (6) is connected with one end of an optical fiber wound on a second piezoelectric ceramic (21), the other end of the optical fiber wound on the second piezoelectric ceramic (21) is connected with the input end of a first Faraday rotator mirror (22), and the other output end of the second optical coupler (6) is connected with the input end of a second photoelectric conversion circuit (24);

the output end of the second photoelectric conversion circuit (24) is connected with the input end of a function conversion circuit (25), the output end of the function conversion circuit (25) is connected with one input end of an adaptive amplitude normalization circuit (26), the output end of a reference voltage circuit (28) is connected with the other input end of the adaptive amplitude normalization circuit (26), and the output end of the adaptive amplitude normalization circuit (26) is connected with one input end of a phase comparison circuit (27); the input end of the controllable frequency source (19) is connected with the single chip microcomputer (16), the output end of the controllable frequency source is connected with the other input end of the phase comparison circuit (27), and the output end of the phase comparison circuit (27) is connected with the single chip microcomputer (16); the output end of the controllable frequency source (19) is also connected with the input end of a second PZT driving circuit (20), and the output end of the second PZT driving circuit (20) is connected with the control end of a second piezoelectric ceramic (21); the temperature sensor (15) is connected with the singlechip (16); the single chip microcomputer (16) is also connected with an input key (14), a serial port communication module (17) and a display screen (18) respectively;

the structure of the function conversion circuit (25) is that one end of a capacitor C3 is connected with a pin 12 of a trigonometric function converter U1 and one end of a resistor R2, and the other end of the capacitor C3 is used as an input end of the function conversion circuit (25), is recorded as a port ACOS _ in and is connected with an output end of a second photoelectric conversion circuit (24); the other end of the resistor R2 is grounded; pins 2, 3, 4, 5, 8, 11 and 13 of the trigonometric function converter U1 are grounded, pins 9 and 10 are connected with one end of a capacitor C2 and a-12V power supply, and the other end of the capacitor C2 is grounded; pin 6 of the trigonometric function converter U1 is connected with pin 7, pin 16 is connected with the +12V power supply and one end of the capacitor C1, and the other end of the capacitor C1 is grounded; pin 1 of the trigonometric function converter U1 is connected with the sliding end of a sliding rheostat W1, one end of a sliding rheostat W1 is connected with one end of a resistor R1, the other end of the resistor R1 is connected with a pin 14 of a trigonometric function converter U1, and the sliding end of a sliding rheostat W1 is used as the output end of a function transformation circuit (25), is recorded as a port ACOS _ out and is connected with the input end of an adaptive amplitude normalization circuit (26); the model of the trigonometric function converter U1 is AD 639;

the adaptive amplitude normalization circuit (26) is structurally characterized in that one end of a capacitor C11 is connected with one end of a resistor R21 and a pin 3 of a chip U2, the other end of the resistor R21 is grounded, and the other end of the capacitor C11 is used as an input end of the adaptive amplitude normalization circuit (26), is recorded as a port ADAPT _ in and is connected with a port ACOS _ out of the function conversion circuit (25); pin 1, pin 7, pin 8 and pin 14 of the chip U2 are all grounded, pin 2 and pin 4 are both connected with a +5V power supply, pin 11 is connected with pin 12 and is connected with one end of a capacitor C5 and the +5V power supply, and the other end of the capacitor C5 is grounded; pin 13 of the chip U2 is connected with one end of a capacitor C4, and the other end of the capacitor C4 is grounded; pin 9 of the chip U2 is connected with one end of a capacitor C6, and the other end of the capacitor C6 is grounded; pin 5 of the chip U2 is connected with one end of a resistor R20 and a resistor R19, the other end of the resistor R20 is grounded, the other end of the resistor R19 is connected with the output end of the operational amplifier U8 and one end of a resistor R17, the positive power supply end of the operational amplifier U8 is connected with a +5V power supply, and the negative power supply end is grounded; the other end of the resistor R17 is connected with one end of the resistor R15 and one end of the resistor R16 and is connected to the inverting input end of the operational amplifier U8; the non-inverting input end of the operational amplifier U8 is connected with one end of a resistor R18, and the other end of the resistor R18 is connected with a +2.5V power supply; the other end of the resistor R15 is connected with one end of the capacitor C10 and is connected to the output end of the operational amplifier U7; the positive power supply end of the operational amplifier U7 is connected with a +5V power supply, and the negative power supply end is grounded; the other end of the capacitor C10 is connected with one end and the sliding end of the slide rheostat W3 and is connected to the inverting input end of the operational amplifier U7; the non-inverting input end of the operational amplifier U7 is connected with one end of a resistor R14, and the other end of the resistor R14 is connected with a +2.5V power supply; the other end of the slide rheostat W3 is connected with one end of a resistor R13; the other end of the resistor R16 is connected with the sliding end of the sliding rheostat W2 and the output end of the operational amplifier U6, and one end of the sliding rheostat W2 is connected with one end of the resistor R11; the other end of the resistor R11 is connected with one end of the resistor R10 and is connected to the inverting input end of the operational amplifier U6; the positive power supply end of the operational amplifier U6 is connected with a +5V power supply, and the negative power supply end is grounded; the non-inverting input end of the operational amplifier U6 is connected with one end of a resistor R12, and the other end of the resistor R12 is connected with a +2.5V power supply; the other end of the resistor R10 is connected with the other end of the resistor R13 and one end of the resistor R7 and is connected to the output end of the operational amplifier U5; the other end of the resistor R7 is connected with one end of the resistor R6 and is connected to the inverting input end of the operational amplifier U5; the other end of the resistor R6 is connected with the output end of the operational amplifier U4, the positive power supply of the operational amplifier U5 is connected with the +5V power supply, and the negative power supply is grounded; one end of the resistor R8 is connected with one end of the resistor R9 and is connected to the non-inverting input end of the operational amplifier U5, and the other end of the resistor R9 is connected with a +2.5V power supply; the other end of the resistor R8 is used as a reference voltage end of the adaptive amplitude normalization circuit (26) and is connected with a reference voltage output end of the reference voltage circuit (28); pin 10 of the chip U2 is used as the output terminal of the adaptive amplitude normalization circuit (26), which is marked as port ADAPT _ out, and is connected with one input terminal of the phase comparison circuit (27); a pin 10 of the chip U2 is connected with one end of a capacitor C7, the other end of the capacitor C7 is connected with one end of a resistor R22 and the non-inverting input end of the operational amplifier U3, and the other end of the resistor R22 is grounded; one end of the resistor R3 is connected with one end of the capacitor C8 and the anode of the diode D1 and is connected to the inverting input end of the operational amplifier U3, and the substrate of the operational amplifier U3 is connected to the inverting input end of the operational amplifier U3; the positive power supply of the operational amplifier U3 is connected with a +5V power supply, and the negative power supply is connected with a-5V power supply; the other end of the capacitor C8 is connected with the cathode of the diode D1 and the anode of the diode D2 and is connected to the output end of the operational amplifier U3; the other end of the resistor R3 is connected with one end of a resistor R4 and the inverting input end of the operational amplifier U4, the other end of the resistor R4 is connected with the cathode of a diode D2 and the grid of a field-effect tube Q1, the source of the field-effect tube Q1 is connected with one end of a capacitor C9 and one end of the resistor R5, and the other end of the capacitor C9 is connected with the other end of the resistor R5 and is grounded; the source electrode of the field effect transistor Q1 is connected with the drain electrode of the field effect transistor Q1 and is connected to the non-inverting input end of the operational amplifier U4; the inverting input end of the operational amplifier U4 is connected with the substrate of the operational amplifier U4 and the output end of the operational amplifier U4; the positive power supply of the operational amplifier U3 is connected with a +5V power supply, and the negative power supply is connected with a-5V power supply; the chip U2 is a variable gain amplifier chip, and the model is AD 8367;

the structure of the PHASE comparison circuit (27) is that one end of a capacitor C12 is connected with the non-inverting input end of an operational amplifier U9 and one end of a resistor R23, the other end of the capacitor C12 is used as one input end of the PHASE comparison circuit (27), is recorded as a port PHASE _ in1 and is connected with a port ADAPT _ out of the adaptive amplitude normalization circuit (26); the other end of the resistor R23 is grounded; the positive power supply end of the operational amplifier U9 is connected with a +5V power supply, the negative power supply end is grounded, the inverted input end is grounded, and the output end is connected with the CLK end of the D trigger U10A; the D port of the D flip-flop U10A is grounded; one end of the capacitor C13 is grounded, and the other end of the capacitor C13 is connected with the PR end of the D flip-flop U10A; one end of the resistor R24 is connected with the PR end of the D flip-flop U10A, and the other end is connected with the Q end of the D flip-flop U10A; the CLR end of the D flip-flop U10A is connected with a +5V power supply, and the Q end of the D flip-flop U10A is not connected with the PR end of the D flip-flop U12A; one end of the capacitor C14 is connected with the non-inverting input end of the operational amplifier U11 and one end of the resistor R25, the other end of the capacitor C14 is used as the other input end of the PHASE comparison circuit (27), is recorded as a port PHASE _ in2 and is connected with a port Sinem _ out of the controllable frequency source (19); the other end of the resistor R25 is grounded; the positive power supply end of the operational amplifier U11 is connected with a +5V power supply, the negative power supply end is grounded, the inverted input end is grounded, and the output end is connected with the CLK end of the D trigger U10B; the D port of the D flip-flop U10B is grounded; one end of the capacitor C15 is grounded, and the other end of the capacitor C15 is connected with the PR end of the D flip-flop U10B; one end of the resistor R26 is connected with the PR end of the D flip-flop U10B, and the other end is connected with the Q end of the D flip-flop U10B; the CLR end of the D trigger U10B is connected with a +5V power supply, and the Q end of the D trigger U10B is not connected with the CLR end of the D trigger U12A; the D end and the CLK end of the D flip-flop U12A are both grounded, and the Q end is used as the output end of the PHASE comparison circuit (27) and is marked as a port PHASE _ out;

the reference voltage circuit (28) is structurally characterized in that one end of a resistor R27 is connected with a +5V power supply, the other end of the resistor R27 is connected with a non-inverting input end of an operational amplifier U13, the anode of a voltage stabilizing diode D3 is grounded, the cathode of the voltage stabilizing diode D3 is connected with the non-inverting input end of an operational amplifier U13, the inverting input end of the operational amplifier U13 is connected with an output end, the positive power supply is connected with the +5V power supply, the negative power supply is grounded, the output end of the operational amplifier U13 is the +2.5V power supply; one end of the slide rheostat W4 is connected with a +2.5V power supply, the other end of the slide rheostat W4 is grounded, and the slide end of the slide rheostat W14 is connected with the non-inverting input end of the operational amplifier U14; the inverting input end of the operational amplifier U14 is connected with the output end thereof, the positive power supply is connected with the +5V power supply, the negative power supply is grounded, the output end is used as the output end of the reference voltage circuit (28), is marked as a port Vref and is connected with the reference voltage end of the self-adaptive amplitude normalization circuit (26);

the structure of the controllable frequency source (19) is that one end of a resistor R28 is connected with a +12V power supply, and the other end is connected with the base electrode of a triode Q1; one end of the resistor R29 is connected with the base electrode of the triode Q2, and the other end is grounded; one end of the resistor R30 is connected with +12V, and the other end is connected with the collector of the triode Q2; the anode of the electrolytic capacitor C17 is connected with the collector of the triode Q2, and the cathode is connected with the base of the triode Q3; one end of the resistor R31 is connected with the emitter of the triode Q2, and the other end is connected with the anode of the electrolytic capacitor C16; one end of the resistor R32 is connected with the anode of the electrolytic capacitor C16, and the other end is grounded; the negative electrode of the electrolytic capacitor C16 is grounded; one end of the resistor R33 is connected with a +12V power supply, and the other end is connected with the base electrode of the triode Q3; one end of the resistor R34 is connected with the base electrode of the triode Q3, and the other end is grounded; one end of the resistor R35 is connected with a +12V power supply, and the other end is connected with the collector of the triode Q3; one end of the resistor R36 is connected with the emitting electrode of the triode Q3, and the other end is grounded; the anode of the electrolytic capacitor C18 is connected with the emitter of the triode Q3, and the cathode is grounded; the anode of the electrolytic capacitor C19 is connected with the collector of the triode Q3, and the cathode is connected with one end of the thermistor Rt 1; the other end of the thermistor Rt1 is connected with the emitter of a triode Q2; the anode of the electrolytic capacitor C20 is connected with the collector of the triode Q3, and the cathode is connected with the pin 2 of the chip U15; one end of the capacitor C21 is connected with a pin 3 of the chip U15, and the other end is connected with a pin 2 of the chip U16; one end of the capacitor C22 is connected with pin 2 of the chip U16, and the other end is grounded; the anode of the electrolytic capacitor C23 is connected with the pin 2 of the chip U16, and the cathode is connected with the base electrode of the triode Q2; one end of the capacitor C24 is connected with a pin 5 of the chip U15, and the other end of the capacitor C24 is grounded; one end of the capacitor C25 is connected with a pin 5 of the chip U16, and the other end of the capacitor C25 is grounded; pin 1 and pin 10 of the chip U15 are connected with a +5V power supply, and pin 4 and pin 6 are grounded; pin 9 is connected with one end of a resistor R37, pin 8 is connected with one end of a resistor R38, and pin 7 is connected with one end of a resistor R39; the other end of the resistor R37 is used as an input port of the controllable frequency source (19) and is marked as a port SineM _ in 1; the other end of the resistor R38 is used as the other input port of the controllable frequency source (19) and is marked as a port Sinem _ in 2; the port SineM _ in1 and the port SineM _ in2 are connected with the input end of the singlechip 16; the other end of the resistor R39 is connected with a +5V power supply; pin 1 and pin 10 of the chip U10 are connected with a +5V power supply, and pin 4 and pin 6 are grounded; pin 9 is connected with one end of a resistor R40, pin 8 is connected with one end of a resistor R41, and pin 7 is connected with one end of a resistor R42; the other end of the resistor R40 is connected with a port SineM _ in 1; the other end of the resistor R41 is connected with a port SineM _ in 2; the other end of the resistor R42 is connected with a +5V power supply; the cathode of the electrolytic capacitor C18 is used as the output port of the controllable frequency source (19) and is marked as SineM _ out; the models of the chip U15 and the chip U16 are AD 5272-50.

2. A phase comparison based microstress sensor according to claim 1, characterized in that said pump source (1) is a 980nm laser source.

3. A phase comparison based microstress sensor according to claim 1 or 2, characterized in that said temperature sensor (15) is a DS18B20 digital temperature sensor.