CN106708416A - Data reconstruction method and system, and memory control circuit unit - Google Patents

Data reconstruction method and system, and memory control circuit unit Download PDF

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Publication number
CN106708416A
CN106708416A CN201510776032.5A CN201510776032A CN106708416A CN 106708416 A CN106708416 A CN 106708416A CN 201510776032 A CN201510776032 A CN 201510776032A CN 106708416 A CN106708416 A CN 106708416A
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China
Prior art keywords
information
entity
logical mappings
logical
logic
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CN201510776032.5A
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CN106708416B (en
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王声翰
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Phison Electronics Corp
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Phison Electronics Corp
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0614—Improving the reliability of storage systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/062—Securing storage systems

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

The invention provides a data reconstruction method and system, and a memory control circuit unit. The method comprises the steps of reading entity-logic mapping information in a rewritable nonvolatile memory module and time information corresponding to the entity-logic mapping information; sorting the entity-logic mapping information according to the time information corresponding to the entity-logic mapping information; and reconstructing a logic-entity mapping table according to the sorted entity-logic mapping information, and restoring the reconstructed logic-entity mapping table in a buffer memory. When the logic-entity mapping table is disrupted due to damage of the rewritable nonvolatile memory module, the logic-entity mapping table can be reconstructed according to the existing entity-logic mapping information, so that data stored in the rewritable nonvolatile memory module is identified.

Description

Data re-establishing method and system and its memorizer control circuit unit
Technical field
The invention relates to a kind of data re-establishing method, and can reconstructed mapped table in particular to one kind Data re-establishing method and system and its memorizer control circuit unit.
Background technology
Digital camera, mobile phone and MP3 player are very rapid in growth over the years so that disappear Expense person also rapidly increases the demand of storage media.Due to reproducible nonvolatile memorizer module (example Such as, flash memory) there is data non-volatile, power saving, small volume, and the spy such as mechanical structure Property, so being especially suitable for being built into above-mentioned illustrated various portable multimedia devices.
In order to carry out data access, by the use of reproducible nonvolatile memorizer module as storage media Memory storage apparatus can be recorded in logic-entity the mapping relations between logical address and physical address In mapping table.In general, when memory storage apparatus are write data to, more new logic-reality in the lump is understood Map information in body mapping table.However, memory storage apparatus are after a particular period of use, Entity during reproducible nonvolatile memorizer module may be made because of human factor or other reasonses is erased Unit is damaged.If the entity erased cell of damage stores logic-entity mapping just, will cause The situation of the data in memory storage apparatus cannot normally be accessed.Therefore, logic-entity how is rebuild to reflect Data in firing table and then acquirement memory storage apparatus, are this art personnel's subject under discussion of concern.
The content of the invention
The present invention provides a kind of data re-establishing method and system and its memorizer control circuit unit, when can answer When the formula non-volatile memory module of writing is damaged and damages logic-entity mapping, can be according to existing Entity-logical mappings information reconstruction logic-entity mapping, and then recognize duplicative non-volatile memories The data stored in device module.
Data re-establishing method of the invention, for memory storage apparatus.This memory storage apparatus has Reproducible nonvolatile memorizer module, and this reproducible nonvolatile memorizer module has multiple Entity erased cell.Notebook data method for reconstructing is stored in type nonvolatile mould including reading Entity-logical mappings information in block and the temporal information corresponding to entity-logical mappings information, and root According to temporal information re-ordering entity-logical mappings information.Notebook data method for reconstructing also includes according to ordering reality Body-logical mappings information sets up multiple logic-entity map informations to produce logic-entity mapping, and During this logic-entity mapping restored into the buffer storage of memory storage apparatus.
It is above-mentioned that logic-entity mapping is restored into memory storage in one example of the present invention embodiment Step in the buffer storage of device includes reading data volume according to corresponding to the maximum of reading instruction Logical address number is calculated, and according to logical address number by multiple logic-entities of logic-entity mapping Map information writes into the buffer storage of memory storage apparatus in batches.
In one example of the present invention embodiment, when above-mentioned temporal information includes write time information and arranges Between information.
In one example of the present invention embodiment, above-mentioned entity-logical mappings information include first instance- Logical mappings information and second instance-logical mappings information.It is above-mentioned according to temporal information sort this little entity- The step of logical mappings information, is included according to write time information sorting entity-logical mappings information.If the First write time information of one entity-logical mappings information and the second of second instance-logical mappings information Write time information is identical, the first finishing time information and second according to first instance-logical mappings information The second finishing time information sorting first instance-logical mappings information and second of entity-logical mappings information Entity-logical mappings information.
In one example of the present invention embodiment, above-mentioned entity-logical mappings information include the 3rd entity- Logical mappings information and four entities-logical mappings information.It is above-mentioned to be believed according to ordering entity-logical mappings If the step of breath sets up logic-entity map information to produce logic-entity mapping also includes that the 3rd is real Body-logical mappings information and four entities-logical mappings information include identical logical address, and the 4th entity The temporal information of-logical mappings information sorts after the temporal information of three entities-logical mappings information, root According to four entities-logical mappings information updating logic-entity mapping.
In one example of the present invention embodiment, above-mentioned each entity erased cell has multiple entity journeys Sequence unit, wherein this little entity program unit include first instance programmed cell and second instance journey Sequence unit.Above-mentioned data re-establishing method also includes reading after the step of producing logic-entity mapping Take the first information and the first logical address of first instance programmed cell, wherein first instance sequencing list Five entities-logical mappings information corresponding to unit is not yet stored to type nonvolatile mould In block.Furthermore, the second instance journey that the first logical address is mapped is read always according to logic-entity mapping The second information in sequence unit.If the first information is differed with the second information, more new logic-entity reflects The first logical address in firing table maps to first instance programmed cell.
In one example of the present invention embodiment, above-mentioned data re-establishing method is stored in reading and can make carbon copies Also include that host computer system will be come from before entity-logical mappings information in formula nonvolatile memory Data reconstruction control code is loaded into the buffer storage of memory storage apparatus.This data reconstruction control code Can run and be stored in type nonvolatile mould with according at least the one of host computer system instruction reading Entity-logical mappings information in block.
In one example of the present invention embodiment, above-mentioned entity-logical mappings information is stored in making carbon copies Data bit area in an at least entity erased cell of formula non-volatile memory module, and time letter Breath is stored in the redundancy ratio special zone in this entity erased cell.
In one example of the present invention embodiment, above-mentioned data re-establishing method also includes record entity-logic Map information is in buffer storage.Also, the entity in buffer storage-logical mappings letter will be recorded Temporal information corresponding to breath and entity-logical mappings information is stored to duplicative non-volatile memories In device module.
Memorizer control circuit unit of the invention, is configured at memory storage apparatus, for controlling to store The reproducible nonvolatile memorizer module of device storage device, wherein this duplicative non-volatile memories Device module has multiple entity erased cells.This memorizer control circuit unit includes HPI, storage Device interface and memory management circuitry.HPI is electrically connected to host computer system.Memory interface is electrical It is connected to reproducible nonvolatile memorizer module.Memory management circuitry is electrically connected to HPI With memory interface.Memory management circuitry reads and is stored in reproducible nonvolatile memorizer module Entity-logical mappings information and the temporal information corresponding to entity-logical mappings information, and according to when Between information sorting entity-logical mappings information.Separately, memory management circuitry always according to ordering entity- Logical mappings information sets up multiple logic-entity map informations to produce logic-entity mapping, and will patrol Volume-entity mapping is loaded into the buffer storage of memory storage apparatus.
In one example of the present invention embodiment, above-mentioned memory management circuitry reads according to corresponding to one The maximum data volume that reads of instruction calculates logical address number, and according to logical address number by logic-reality The buffering that the multiple logics-entity map information of body mapping table is loaded into memory storage apparatus in batches is deposited In reservoir.
In one example of the present invention embodiment, above-mentioned temporal information includes write time information and arrangement Temporal information.
In one example of the present invention embodiment, above-mentioned entity-logical mappings information include first instance- Logical mappings information and second instance-logical mappings information.When above-mentioned memory management circuitry is according to write-in Between information sorting entity-logical mappings information.If the first write time of first instance-logical mappings information The information memory management identical, above-mentioned with the second write time information of second instance-logical mappings information Circuit reflects always according to the first finishing time information of first instance-logical mappings information with second instance-logic The the second finishing time information sorting first instance-logical mappings information and second instance-logic for penetrating information are reflected Penetrate information.
In one example of the present invention embodiment, above-mentioned entity-logical mappings information include the 3rd entity- Logical mappings information and four entities-logical mappings information.If three entities-logical mappings information and the 4th Entity-logical mappings information includes identical logical address, and four entities-logical mappings information sorting exists After three entities-logical mappings information, above-mentioned memory management circuitry is reflected always according to four entities-logic Penetrate information updating logic-entity mapping.
In one example of the present invention embodiment, above-mentioned each entity erased cell has multiple entity journeys Sequence unit, wherein this little entity program unit include first instance programmed cell and second instance journey Sequence unit.Above-mentioned memory management circuitry also read first instance programmed cell the first information and First logical address, the wherein five entities-logical mappings information corresponding to this first instance programmed cell Not yet store into reproducible nonvolatile memorizer module.Furthermore, above-mentioned memory management circuitry In the second instance programmed cell mapped always according to logic-the first logical address of entity mapping reading The second information.If the first information is differed with the second information, memory management circuitry more new logic-reality The first logical address in body mapping table maps to first instance programmed cell.
In one example of the present invention embodiment, above-mentioned memory management circuitry will also come from main frame system The data reconstruction control code of system is loaded into the buffer storage of memory storage apparatus.This data reconstruction control Code processed can run so that above-mentioned memory management circuitry reads storage according at least the one of host computer system instruction Entity-logical mappings information in reproducible nonvolatile memorizer module.
In one example of the present invention embodiment, above-mentioned entity-logical mappings information is stored in making carbon copies Data bit area in an at least entity erased cell of formula non-volatile memory module, and time letter Breath is stored in the redundancy ratio special zone in this entity erased cell.
In one example of the present invention embodiment, above-mentioned memory management circuitry record entity-logical mappings Information in buffer storage, and will record entity-logical mappings information in buffer storage and Temporal information corresponding to entity-logical mappings information is stored to reproducible nonvolatile memorizer module In.
Data reconstruction system of the invention includes host computer system and memory storage apparatus.Host computer system has Data reconstruction unit.Memory storage apparatus include connecting interface unit, duplicative non-volatile memories Device module and memorizer control circuit unit.Connecting interface unit is electrically connected to host computer system.Can make carbon copies Formula non-volatile memory module has multiple entity erased cells.Memorizer control circuit unit electrically connects It is connected to connecting interface unit and reproducible nonvolatile memorizer module.Data reconstruction unit is transmitted at least One reads instruction to memory storage apparatus, and memorizer control circuit unit reads according to this reading instruction Entity-logical mappings information for being stored in reproducible nonvolatile memorizer module and corresponding to reality The temporal information of body-logical mappings information is with response to this reading instruction.Data reconstruction unit is always according to the time Information sorting entity-logical mappings information.Separately, data reconstruction unit reflects always according to ordering entity-logic Information is penetrated to set up multiple logic-entity map informations to produce logic-entity mapping, and by logic-reality Body mapping table is restored in the buffer storage of memory storage apparatus.
In one example of the present invention embodiment, above-mentioned data reconstruction unit refers to according to corresponding to a reading The maximum data volume that reads of order calculates logical address number, and according to logical address number by logic-entity Multiple logics-entity the map information of mapping table writes to the buffer-stored of memory storage apparatus in batches In device.
In one example of the present invention embodiment, above-mentioned temporal information includes write time information and arrangement Temporal information.
In one example of the present invention embodiment, above-mentioned entity-logical mappings information include first instance- Logical mappings information and second instance-logical mappings information.When above-mentioned data reconstruction unit is always according to write-in Between information sorting entity-logical mappings information.If the first write time of first instance-logical mappings information The information data reconstruction list identical, above-mentioned with the second write time information of second instance-logical mappings information First finishing time information and second instance-logical mappings of the unit always according to first instance-logical mappings information The second finishing time information sorting first instance-logical mappings information and second instance-logical mappings of information Information.
In one example of the present invention embodiment, above-mentioned entity-logical mappings information include the 3rd entity- Logical mappings information and four entities-logical mappings information.If three entities-logical mappings information and the 4th Entity-logical mappings information includes identical logical address, and four entities-logical mappings information sorting exists After three entities-logical mappings information, above-mentioned data reconstruction unit is according to four entities-logical mappings letter Breath more new logic-entity mapping.
In one example of the present invention embodiment, above-mentioned each entity erased cell has multiple entity journeys Sequence unit, wherein this little entity program unit include first instance programmed cell and second instance journey Sequence unit.Above-mentioned data reconstruction unit transmission first reads instruction to memory storage apparatus, and on The memorizer control circuit unit stated reads first instance programmed cell is read in instruction first according to first Information and the first logical address read instruction with response to first, and first instance programmed cell institute is right Five entities answered-logical mappings information is not yet stored into reproducible nonvolatile memorizer module.Again Person, above-mentioned data reconstruction unit is read always according to the first logical address and logic-entity mapping transmission second Instruction fetch to memory storage apparatus, and above-mentioned memorizer control circuit unit read always according to second and refer to Order reads the second information in the second instance programmed cell that is mapped of the first logical address with response to the Second reading instruction fetch.If the first information is differed with the second information, above-mentioned data reconstruction unit updates patrols Volume-entity mapping in the first logical address map to first instance programmed cell.
In one example of the present invention embodiment, above-mentioned data reconstruction unit also transmits data reconstruction control Code memorizer control circuit unit to memory storage apparatus and above-mentioned is also by this data reconstruction control code It is loaded into the buffer storage of memory storage apparatus.This data reconstruction control code can be run so that above-mentioned Memorizer control circuit unit according to the reading of above-mentioned data reconstruction unit instruct reading be stored in and can answer Write the entity-logical mappings information in formula non-volatile memory module.
In one example of the present invention embodiment, above-mentioned entity-logical mappings information is stored in making carbon copies Data bit area in an at least entity erased cell of formula non-volatile memory module, and time letter Breath is to store the redundancy ratio special zone in this entity erased cell.
In one example of the present invention embodiment, above-mentioned memorizer control circuit unit record entity-logic Map information will record the entity-logical mappings information in buffer storage in buffer storage And the temporal information corresponding to entity-logical mappings information is stored to type nonvolatile In module.
Based on above-mentioned, it is damaged in reproducible nonvolatile memorizer module and logic-reality cannot be accessed During body mapping table, can be according to entity-logical mappings of the storage in reproducible nonvolatile memorizer module Information, the logic-entity mapping needed for reconstructing access data.Also, logic-the entity that will can be rebuild Mapping table stores the buffer storage to memory storage apparatus for access, and then correctly reads storage Data in reproducible nonvolatile memorizer module.
It is that features described above of the invention and advantage can be become apparent, special embodiment below, and coordinate Accompanying drawing is described in detail below.
Brief description of the drawings
Fig. 1 is host computer system according to shown by an embodiment, memory storage apparatus and input/output (I/O) schematic diagram of device；
Fig. 2 is host computer system according to shown by another embodiment, memory storage apparatus and input/output (I/O) schematic diagram of device；
Fig. 3 is the schematic diagram of the host computer system according to shown by another embodiment and memory storage apparatus；
Fig. 4 is the summary square of the host computer system according to shown by an embodiment and memory storage apparatus Figure；
Fig. 5 is the schematic block diagram of the memorizer control circuit unit according to shown by an embodiment；
Fig. 6 and Fig. 7 is the example schematic of the management entity erased cell according to shown by an embodiment；
Fig. 8 is the entity-logical mappings letter of storage according to shown by an embodiment in entity erased cell The schematic diagram of breath and temporal information；
Fig. 9 is the general write operation of correspondence according to shown by an embodiment and storage entity-logical mappings letter The schematic diagram of breath；
Figure 10 A are the corresponding garbage collection operations according to shown by an embodiment and storage entity-logic is reflected Penetrate the schematic diagram of information；
Figure 10 B are the corresponding garbage collection operations according to shown by another embodiment and storage entity-logic The schematic diagram of map information；
Figure 11 is the schematic diagram for setting up logic-entity mapping according to shown by an embodiment；
Figure 12 A and 12B be ratio according to shown by an embodiment to user's data with more new logic-reality The schematic diagram of body mapping table；
Figure 13 is the flow chart of the data re-establishing method according to shown by an embodiment.
Description of reference numerals：
10：Memory storage apparatus；
11：Host computer system；
12：Input/output (I/O) device；
110：System bus；
111：Processor；
112：Random access memory (RAM)；
113：Read-only storage (ROM)；
114：Data transmission interface；
20：Motherboard；
201：Portable disk；
202：Memory card；
203：Solid state hard disc；
204：Radio memory storage device；
205：GPS module；
206：NIC；
207：Radio transmitting device；
208：Keyboard；
209：Screen；
210：Loudspeaker；
30：Memory storage apparatus；
31：Host computer system；
32：SD card；
33：CF cards；
34：Embedded storage device；
341：Embedded multi-media card；
342：Embedded type multi-core piece sealed storage device；
402：Connecting interface unit；
404：Memorizer control circuit unit；
406：Reproducible nonvolatile memorizer module；
408：Data reconstruction unit；
410 (0)~410 (N), PBA (0)~PBA (3)：Entity erased cell；
502：Memory management circuitry；
504：HPI；
506：Memory interface；
508：Buffer storage；
510：Electric power management circuit；
512：Error checking and correcting circuit；
602：Data field；
604：Idle area；
606：System area；
608：Substitution area；
LBA (0)~LBA (H)：Logic unit；
LZ (0)~LZ (M)：Logic region；
LA (0)~LA (E)：Logical address；
PA (0-0)~PA (0-2), PA (1-0)~PA (1-2), PA (2-0)~PA (2-2), PA (3-0)~PA (3-2)： Physical address；
910 (0)~910 (E)：Logical program unit；
410 (F-0)~410 (F-F)：Entity program unit；
920：Region；
1101：Entity-logical mappings finish message table；
1102、1201、1202：Logic-entity mapping；
D (0)~D (E), D1~D6：Data；
921~926：Entity-logical mappings information；
S1301、S1303、S1305、S1307：Step.
Specific embodiment
In general, memory storage apparatus (also referred to as, storage system) include that duplicative is non- Volatile and controller (also referred to as, controlling circuit unit).It is commonly stored device storage device To be used together with host computer system so that host computer system can write data into memory storage apparatus or from Data are read in memory storage apparatus.
Fig. 1 is host computer system according to shown by an embodiment, memory storage apparatus and input/output (I/O) schematic diagram of device, and Fig. 2 is host computer system, the memory according to shown by another embodiment The schematic diagram of storage device and input/output (I/O) device.
Fig. 1 and Fig. 2 is refer to, host computer system 11 generally comprises processor 111, random access memory (random access memory, referred to as：RAM) 112, read-only storage (read only memory, Referred to as：ROM) 113 and data transmission interface 114.Processor 111, random access memory 112, Read-only storage 113 and data transmission interface 114 are all electrically connected to system bus (system bus) 110.
In this exemplary embodiment, host computer system 11 is by data transmission interface 114 and memory storage Device 10 is electrically connected with.For example, host computer system 11 can be write data into by data transmission interface 114 Data are read to memory storage apparatus 10 or from memory storage apparatus 10.Additionally, host computer system 11 are electrically connected with I/O devices 12 by system bus 110.For example, host computer system 11 can pass through Output signal is sent to I/O devices 12 or receives input signal from I/O devices 12 by system bus 110.
In this exemplary embodiment, processor 111, random access memory 112, read-only storage 113 And data transmission interface 114 is on the motherboard 20 for may be provided at host computer system 11.Data transmission interface 114 number can be one or more.By data transmission interface 114, motherboard 20 can be by having Line or wireless mode are electrically connected to memory storage apparatus 10.Memory storage apparatus 10 can be for example Portable disk 201, memory card 202, solid state hard disc (Solid State Drive, abbreviation：SSD) 203 or wireless Memory storage apparatus 204.Radio memory storage device 204 can be for example close range wireless communication (Near Field Communication Storage, referred to as：NFC) memory storage apparatus, wireless biography Very (WiFi) memory storage apparatus, bluetooth (Bluetooth) memory storage apparatus or low-power consumption is blue The memory based on various wireless communication technique such as tooth memory storage apparatus (for example, iBeacon) Storage device.Additionally, motherboard 20 can also be electrically connected to global positioning system by system bus 110 System (Global Positioning System, referred to as：GPS) module 205, NIC 206, wireless The various I/O devices such as transmitting device 207, keyboard 208, screen 209, loudspeaker 210.For example, one In exemplary embodiment, motherboard 20 can be by the access wireless memory storage apparatus of radio transmitting device 207 204。
In an exemplary embodiment, mentioned host computer system is substantially to match somebody with somebody with memory storage apparatus Close with any system of data storage.Although in above-mentioned exemplary embodiment, host computer system is with computer system Unite to explain, however, Fig. 3 is the host computer system and memory storage according to shown by another embodiment The schematic diagram of device.Fig. 3 is refer to, in another exemplary embodiment, host computer system 31 can also be several The systems such as code-phase machine, video camera, communication device, audio player, video player or panel computer, And SD card 32, CF cards 33 or the embedded storage device that memory storage apparatus 30 can be used for it The various non-volatile memory storage devices such as 34.Embedded storage device 34 includes built-in multimedia Card (embedded MMC, referred to as：EMMC) 341 and/or embedded type multi-core piece sealed storage device (embedded Multi Chip Package, referred to as：EMCP) 342 etc. is all types of straight by memory module Connect the embedded storage device on the substrate for being electrically connected at host computer system.
Fig. 4 is the summary square of the host computer system according to shown by an embodiment and memory storage apparatus Figure.
Fig. 4 is refer to, memory storage apparatus 10 include that connecting interface unit 402, memory controls electricity Road unit 404 and reproducible nonvolatile memorizer module 406.
In this exemplary embodiment, connecting interface unit 402 is to be compatible to Serial Advanced Technology Attachment (Serial Advanced Technology Attachment, referred to as：SATA) standard.However, it is necessary to be appreciated that, The invention is not restricted to this, connecting interface unit 402 can also meet parallel advanced technology annex (Parellel Advanced Technology Attachment, referred to as：PATA) standard, Electrical and Electronic engineer association Meeting (Institute of Electrical and Electronic Engineers, referred to as：IEEE) 1394 standards, High-speed peripheral interconnecting interface (Peripheral Component Interconnect Express, referred to as：PCI Express) standard, USB (Universal Serial Bus, abbreviation：USB) standard, super A high speed generation (Ultra High Speed-I, referred to as：UHS-I) interface standard, the generation of ultrahigh speed two (Ultra High Speed-II, referred to as：UHS-II) interface standard, secure digital (Secure Digital, abbreviation：SD) Interface standard, memory stick (Memory Stick, abbreviation：MS) interface standard, multi-chip package (Multi-Chip Package) interface standard, multimedia storage card (Multi Media Card, abbreviation： MMC) interface standard, built-in multimedia storage card (Embedded Multimedia Card, abbreviation： EMMC) interface standard, general flash memory (Universal Flash Storage, abbreviation：UFS) interface Standard, the encapsulation of embedded type multi-core piece (embedded Multi Chip Package, abbreviation：EMCP) connect Mouth standard, compact flash (Compact Flash, abbreviation：CF) interface standard, integrated driving electronics connect Mouthful (Integrated Device Electronics, referred to as：IDE) standard or other suitable standards.At this In exemplary embodiment, connecting interface unit 402 can be encapsulated in one with memorizer control circuit unit 404 In chip, or connecting interface unit 402 is to be laid in a chip comprising memorizer control circuit unit Outward.
Memorizer control circuit unit 404 is used to perform in the form of hardware or the multiple of form of firmware implementation is patrolled Volume door or control instruction, and according to the instruction of host computer system 11 in type nonvolatile mould The write-in of data is carried out in block 406, is read and the running such as erase.
Reproducible nonvolatile memorizer module 406 is electrically connected to memorizer control circuit unit 404, and the data write to host system 11.Type nonvolatile mould Block 406 has entity erased cell 410 (0)~410 (N).For example, entity erased cell 410 (0)~410 (N) Same memory crystal grain (die) can be belonged to or belong to different memory crystal grains.Each entity is erased Unit has a plurality of entity program units respectively, wherein belonging to the entity of same entity erased cell Programmed cell can be written independently and simultaneously be erased.However, it is necessary to be appreciated that, the present invention Not limited to this, each entity erased cell is can be by 64 entity program units, 256 entity programs Change unit or other any entity program units are constituted.
In more detail, entity erased cell is the least unit erased.The list that is, each entity is erased First memory cell being erased in the lump containing minimal amount.Entity program unit is the minimum of sequencing Unit.That is, entity program unit is the minimum unit for writing data.Each entity program unit leads to Often include data bit area and redundancy ratio special zone.Data bit area includes multiple entity access addresses and is used to deposit The data of user, and redundancy ratio special zone are stored up to the data of storage system (for example, control information and mistake Miss more code).In this exemplary embodiment, meeting in the data bit area of each entity program unit Comprising 8 entity access addresses, and a size for entity access address is 512 bytes (byte). However, in other exemplary embodiments, the more or less entity of number can be also included in data bit area Access address, the present invention is not intended to limit the size and number of entity access address.For example, in an example In embodiment, entity erased cell is physical blocks, and entity program unit is physical page or reality Body sector, but the present invention is not limited.
In this exemplary embodiment, reproducible nonvolatile memorizer module 406 is multilayered memory unit (Multi Level Cell, referred to as：MLC) NAND type flash memory module (that is, one storage 2 flash memory modules of data bit can be stored in unit).However, the invention is not restricted to this, Reproducible nonvolatile memorizer module 406 may also be individual layer memory cell (Single Level Cell, Referred to as：SLC) NAND type flash memory module (that is, can store 1 number in one memory cell According to the flash memory module of bit), plural layer memory cell (Trinary Level Cell, referred to as：TLC) NAND type flash memory module (that is, can store 3 quick flashings of data bit in one memory cell Memory module), other flash memory modules or other there is the memory module of identical characteristics.
In this exemplary embodiment, host computer system 11 is by data reconstruction unit 408 come transfer control instruction To memory storage apparatus 10 to carry out data reconstruction, and memorizer control circuit unit 404 can perform it is right Should operate with response to the instruction received from host computer system.For example, data reconstruction unit 408 include with The data reconstruction application program of software code implementation, it can be in the operating system of host computer system 11 (operation system, referred to as：OS operation in).In this exemplary embodiment, host computer system 11 Operating system for Microsoft (Microsoft) company form (Windows) operating system.However, It will be appreciated that the invention is not restricted to this, it is can also be applied to Linux, Mac or other operations In system.
Fig. 5 is the schematic block diagram of the memorizer control circuit unit according to shown by an exemplary embodiment.
Fig. 5 is refer to, memorizer control circuit unit 404 connects including memory management circuitry 502, main frame Mouthfuls 504 with memory interface 506, buffer storage 508, electric power management circuit 510 and error checking with Correcting circuit 512.
Memory management circuitry 502 controls the overall operation of circuit unit 404 to control memory.Tool For body, memory management circuitry 502 has multiple control instructions, and in memory storage apparatus 10 During running, the running such as this little control instruction can be performed carrying out the write-in of data, reads and erase.
In this exemplary embodiment, the control instruction of memory management circuitry 502 is to come real with form of firmware Make.For example, memory management circuitry 502 has microprocessor unit (not shown) and read-only storage (not shown), and this little control instruction is programmed in so far read-only storage.Work as memory storage Device 10 operate when, this little control instruction can be performed by microprocessor unit with carry out data write-in, The running such as read and erase.
In another exemplary embodiment of the invention, the control instruction of memory management circuitry 502 can also journey Sequence code form is stored in the specific region of reproducible nonvolatile memorizer module 406 (for example, storage The system area of storage system data is exclusively used in device module) in.Additionally, memory management circuitry 502 has There are microprocessor unit (not shown), read-only storage (not shown) and random access memory (not Show).Particularly, this read-only storage has driving code, and when memorizer control circuit unit 404 When being enabled, microprocessor unit can first carry out this and drive code section non-volatile will be stored in duplicative Control instruction in memory module 406 is loaded into the random access memory of memory management circuitry 502 In.Afterwards, microprocessor unit can operate this little control instruction carrying out the write-in of data, read and smear Operated except waiting.
Additionally, in another exemplary embodiment of the invention, the control instruction of memory management circuitry 502 Implementation can be come with an example, in hardware.For example, memory management circuitry 502 includes that microcontroller, storage are single First management circuit, memory write circuit, memory reading circuitry, memory are erased at circuit and data Reason circuit.Storage Unit Management circuit, memory write circuit, memory reading circuitry, memory are smeared Except circuit and data processing circuit are electrically connected to microcontroller.Wherein, Storage Unit Management circuit is used To manage the entity erased cell of reproducible nonvolatile memorizer module 406；Memory write circuit It is used to assign write instruction to reproducible nonvolatile memorizer module 406 write data into can answer In writing formula non-volatile memory module 406；Memory reading circuitry is used to non-volatile to duplicative Memory module 406 is assigned reading instruction and is read with from reproducible nonvolatile memorizer module 406 Data；Memory circuit of erasing is used to assign finger of erasing to reproducible nonvolatile memorizer module 406 Order is erased with by data from reproducible nonvolatile memorizer module 406；And data processing circuit is used With process be intended to write it is to the data of reproducible nonvolatile memorizer module 406 and non-from duplicative The data read in volatile 406.
HPI 504 is electrically connected to memory management circuitry 502 and the company of being electrically connected to Connection interface unit 402, to receive and recognize instruction and data that host computer system 11 transmitted.That is, The instruction that host computer system 11 is transmitted can be sent to memory management electricity with data by HPI 504 Road 502.In this exemplary embodiment, HPI 504 is to be compatible to SATA standard.However, must It is appreciated that the invention is not restricted to this, HPI 504 can also be compatible to PATA standards, IEEE 1394 standards, PCI Express standards, USB standard, UHS-I interface standards, UHS-II interface marks Standard, SD standards, MS standards, MMC standards, CF standards, IDE standards or other suitable numbers According to transmission standard.
Memory interface 506 is electrically connected to memory management circuitry 502 and is used to access to make carbon copies Formula non-volatile memory module 406.That is, being intended to write to type nonvolatile The data of module 406 can be converted to reproducible nonvolatile memorizer module by memory interface 506 The 406 receptible forms of institute.
Buffer storage 508 is electrically connected to memory management circuitry 502 and is configured to temporarily store come from The data of host computer system 11 and the number for instructing or coming from reproducible nonvolatile memorizer module 406 According to.
Electric power management circuit 510 is electrically connected to memory management circuitry 502 and is used to control storage The power supply of device storage device 10.
Error checking is electrically connected to memory management circuitry 502 and is used to hold with correcting circuit 512 Row error checking and correction program are ensuring the correctness of data.Specifically, memory management circuitry is worked as 502 from host computer system 11 when receiving write instruction, and error checking can be corresponding with correcting circuit 512 The data of this write instruction produce corresponding error checking and correcting code (Error Checking and Correcting Code, referred to as：ECC Code), and memory management circuitry 502 can will correspondence this write The data for entering instruction are write to type nonvolatile mould with corresponding error checking and correcting code In block 406.Afterwards, when memory management circuitry 502 from reproducible nonvolatile memorizer module 406 Can simultaneously read the corresponding error checking of this data and correcting code during middle reading data, and error checking with Correcting circuit 512 can perform error checking and school according to this error checking and correcting code to the data for being read Positive program.
Fig. 6 and Fig. 7 is the example schematic of the management entity erased cell according to shown by an embodiment.
It will be appreciated that the entity for being described herein reproducible nonvolatile memorizer module 406 is erased During the running of unit, application entity erased cell is come with the word such as " extraction ", " packet ", " division ", " association " It is concept in logic.That is, the entity erased cell of reproducible nonvolatile memorizer module Physical location do not change, but the entity to reproducible nonvolatile memorizer module is smeared in logic Except unit is operated.
Fig. 6 is refer to, memorizer control circuit unit 404 (or memory management circuitry 502) can be by reality Body erased cell 410 (0)~410 (N) is logically grouped into data field 602, idle area 604, system area 606 With substitution area 608.
It is to store to come from that data field 602 is logically belonged to the entity erased cell in idle area 604 The data of host computer system 11.Specifically, the entity erased cell of data field 602 is regarded as having stored The entity erased cell of data, and the entity erased cell in idle area 604 is to replacement data area 602 Entity erased cell.That is, work as receiving write instruction with the number to be write from host computer system 11 According to when, memory management circuitry 502 can extract entity erased cell from idle area 604, and by number According to write-in to the entity erased cell for being extracted, with the entity erased cell in replacement data area 602.
The entity erased cell for logically belonging to system area 606 is to record system data.For example, being System data include that the manufacturer on reproducible nonvolatile memorizer module is non-with model, duplicative The entity erased cell number of volatile, the entity program unit of each entity erased cell Number etc..
It is to replace journey for bad entity erased cell to logically belong to replace the entity erased cell in area 608 Sequence, with replacing damaged entity erased cell.Specifically, if still having in substitution area 608 normal Entity erased cell and data field 602 entity erased cell damage when, memory management circuitry 502 Can extract normal entity erased cell from substitution area 608 to change the entity erased cell of damage.
Particularly, data field 602, idle area 604, system area 606 and the entity in substitution area 608 are erased The quantity of unit can be different according to different memory specifications.Further, it is necessary to be appreciated that, In the running of memory storage apparatus 10, entity erased cell associate to data field 602, idle area 604, System area 606 can dynamically change with the packet relation in substitution area 608.For example, when in idle area 604 Entity erased cell damage and the entity erased cell in substituted area 608 when replacing, then substitution area originally 608 entity erased cell can be associated to idle area 604.
Fig. 7 is refer to, memorizer control circuit unit 404 (or memory management circuitry 502) can be configured Logic unit LBA (0)~LBA (H) is mapping the entity erased cell of data field 602, each of which logic Unit has multiple logical subunits to map the entity program unit of corresponding entity erased cell.And And, the data in the logic unit to be write data to of host computer system 11 or renewal are stored in logic unit When, memorizer control circuit unit 404 (or memory management circuitry 502) can be carried from idle area 604 Take an entity erased cell to write data, with the entity erased cell of data field 602 of rotating.At this In exemplary embodiment, logical subunit can be logical page (LPAGE) or logic sector.
In order to which entity erased cell is the data for recognizing each logic unit be stored in, in this example reality Apply in example, memorizer control circuit unit 404 (or memory management circuitry 502) can record logic unit With the mapping between entity erased cell.Also, when host computer system 11 is intended to access number in logical subunit According to when, memorizer control circuit unit 404 (or memory management circuitry 502) can confirm that this logic is single Logic unit belonging to unit, and data are accessed in the entity erased cell that this logic unit is mapped. For example, in this exemplary embodiment, memorizer control circuit unit 404 (or memory management circuitry 502) Can logic-entity mapping be stored in reproducible nonvolatile memorizer module 406 to record each patrolling Collect the entity erased cell that unit is mapped, and the memorizer control circuit unit 404 when data to be accessed Logic-entity mapping can be loaded into buffer storage 508 to tie up by (or memory management circuitry 502) Shield.
It is noted that because the finite capacity of buffer storage 508 cannot all logics of stored record The mapping table of the mapping relations of unit, therefore, in this exemplary embodiment, memorizer control circuit unit Logic unit LBA (0)~LBA (H) can be grouped into multiple logics by 404 (or memory management circuitries 502) Region LZ (0)~LZ (M), and for each logic region configures a logic-entity mapping.Particularly, When memorizer control circuit unit 404 (or memory management circuitry 502) is intended to update certain logic unit During mapping, the logic-entity mapping for corresponding to the logic region belonging to this logic unit can be loaded on buffering Memory 508 is updated.
In this exemplary embodiment, the reproducible nonvolatile memorizer module of memory storage apparatus 10 406 is that ((page based) also referred to as based on the page) is carried out based on entity program unit Management.For example, when write instruction is performed, no matter data are write to which logic unit institute at present Corresponding logical program unit, memorizer control circuit unit 404 (or memory management circuitry 502) Can all be write in the way of an entity program unit continues an entity program unit data ( Referred to as random writing mechanism).Specifically, hereinafter also referred to random writing mechanism can be from idle area 604 It is middle to extract an entity erased cell for sky as entity erased cell (the also referred to as start reality for using at present Body erased cell) write data.Also, when the entity erased cell that this is used at present has been fully written, Memorizer control circuit unit 404 (or memory management circuitry 502) can be extracted from idle area 604 again Another empty entity erased cell as the entity erased cell for using at present, to continue to write to data.
In this exemplary embodiment, memorizer control circuit unit 404 (or memory management circuitry 502) A region can be also marked off in buffer storage 508 to record multiple entities-logical mappings information.Entity - logical mappings information is that record is used to the solid element of data storage to the mapping relations of logic unit.You Afterwards, memorizer control circuit unit 404 (or memory management circuitry 502) again can deposit record in buffering Entity-logical mappings information Store in reservoir 508 is to reproducible nonvolatile memorizer module 406 In.For example, write certain the entity erased cell into idle area 604 corresponding to by certain pen data, then Entity-logical mappings information corresponding to this pen data can be first recorded in buffer storage 508, thereafter It is stored to again in the entity program unit in this entity erased cell.
Particularly, in this exemplary embodiment, the temporal information on entity-logical mappings information also can one And be stored in entity erased cell, to represent the generation time of this entity-logical mappings information.For example, Temporal information can write the time to entity erased cell to set according to by write-in data, or also can root Factually body-logical mappings information is written into the time into entity erased cell to set.Additionally, memory Control circuit unit 404 (or memory management circuitry 502) can be by entity-logical mappings information Store extremely The data bit area of entity erased cell, and the temporal information for corresponding to entity-logical mappings information is deposited Store up to the redundancy ratio special zone of entity erased cell.
Fig. 8 is the entity-logical mappings letter of storage according to shown by an embodiment in entity erased cell The schematic diagram of breath and temporal information.
Fig. 8 is refer to, entity-logical mappings information is stored in the data bit area of entity erased cell simultaneously And the information including presentation-entity unit Yu the mapping relations of logic unit, temporal information is stored in entity The redundancy ratio special zone of erased cell and the time including representing this mapping relations of correspondence.Implement in this example In example, the entity-logical mappings information stored in entity erased cell can record this entity erased cell institute The logical address of mapping, and certain mapping relations be according to logical address in this entity erased cell Actual storage address distinguish.However, in another exemplary embodiment, in entity-logical mappings information The mapping of solid element and logic unit can also be included being recognized different from above-mentioned information or determination methods Relation.
Additionally, in this exemplary embodiment, temporal information may include write time information and finishing time letter Breath.Write time information and finishing time information it is predeterminable be preset value.And when the general write operation of execution And when needing storage entity-logical mappings information, memorizer control circuit unit 404 (or memory management electricity Road 502) understand with the execution time of the general write operation of correspondence set the write-in of entity-logical mappings information Temporal information.In addition, being operated (for example, data merge or refuse collection when data preparation is performed in background (garbage collection) etc.) and when needing storage entity-logical mappings information, memorizer control circuit list First 404 (or memory management circuitries 502) can be set with the execution time of corresponding data housekeeping operation in addition Determine the finishing time information of entity-logical mappings information.
For example, corresponding to general write operation, the write time of meeting more novel entities-logical mappings information Information.And correspond to the data preparation operation performed in background, not only can more novel entities-logical mappings information Write time information, can also more novel entities-logical mappings information finishing time information.Temporal information can Set with the sequence valve (such as 1,2,3 ... etc.) being incremented by according to the priority of the execution time of operation. For example, the preset value of write time information and finishing time information is 0.Corresponding to general write operation, Can be sequentially sequence by corresponding write time information setting according to the execution time order and function of general write operation Numerical value 1,2,3 ... etc..Corresponding to data preparation operation, the execution time elder generation that can be operated according to data preparation Afterwards, by corresponding finishing time information setting it is sequentially sequential digit values 1,2,3 ... etc..Additionally, another In one exemplary embodiment, finishing time information can also be reset after the completion of data preparation operation.Example Such as, it is assumed that the execution time order and function that finishing time information is operated according to data preparation, sequentially by corresponding arrangement Temporal information is set as 1,2,3.When data preparation operation is performed next time, corresponding finishing time letter Breath can set since 1.
It is noted that in this exemplary embodiment, although temporal information is to include the write time simultaneously Information and finishing time information, however, in another exemplary embodiment, temporal information also can only include writing Angle of incidence information, without including finishing time information.
Fig. 9 is the general write operation of correspondence according to shown by an embodiment and storage entity-logical mappings letter The schematic diagram of breath.
Fig. 9 is refer to, memorizer control circuit unit 404 (or memory management circuitry 502) can be received Write instruction and write-in data D (the 0)~D (E) for corresponding to this write instruction.In this exemplary embodiment, it is Assuming that this write instruction indicates for write-in data D (0)~D (E) to write logical program unit 910 (0)~910 (E).
Memorizer control circuit unit 404 (or memory management circuitry 502) can be non-volatile from duplicative Property memory module 406 in extract at least one entity erased cell write this write-in data.For example, Memorizer control circuit unit 404 (or memory management circuitry 502) will write data D (0)~D (E) and deposit In storage to the entity program unit 410 (F-0)~410 (F-E) of entity erased cell 410 (F).In this example In embodiment, memorizer control circuit unit 404 (or memory management circuitry 502) can be in buffer-stored Region 920 is marked off in device 508.Also, memorizer control circuit unit 404 (or memory management electricity Road 502) can correspond to write data D (0)~D (E) entity-logical mappings information 921 be temporarily stored in it is slow In the region 920 rushed in memory 508, the entity-logical mappings in region 920 will be recorded again thereafter Information 921 is stored into entity erased cell 410 (F).For example, entity-logical mappings information 921 is note The logical address of the logical program unit 910 (0)~910 (E) corresponding to write-in data D (0)~D (E) is recorded LA (0)~LA (E).
Specifically, memorizer control circuit unit 404 (or memory management circuitry 502) will can write Data D (0)~D (E) is stored to the data bit area of entity program unit 410 (F-0)~410 (F-E), and And will be corresponding to the logical address of the logical program unit 910 (0)~910 (E) of write-in data D (0)~D (E) LA (0)~LA (E) records are in the redundancy ratio special zone of entity program unit 410 (F-0)~410 (F-E).Thereafter, Memorizer control circuit unit 404 (or memory management circuitry 502) can be by buffer storage 508 Entity-logical mappings information 921 is stored to entity program unit 410 (F-F).As shown in figure 9, entity- Logical mappings information 921 is stored to the data bit area of entity program unit 410 (F-F).In this model In example embodiment, memorizer control circuit unit 404 (or memory management circuitry 502) is by entity-patrol When volume map information 921 stores the data bit area to entity program unit 410 (F-F), in the lump can will Temporal information corresponding to entity-logical mappings information 921 is stored to entity program unit 410 (F-F) Redundancy ratio special zone.Because this exemplary embodiment corresponds to general write operation, therefore can set write-in Temporal information represents time of entity-logical mappings information 921, for example, by write time information setting It is 1.And finishing time information can then be set to preset value, such as 0, or set according to actual demand, This is not any limitation as.It is noted that in this exemplary embodiment, entity program unit and logic Programmed cell is man-to-man mapping relations, however, in other exemplary embodiments, entity program Unit may also be one-to-many mapping with logical program unit.For example, feelings of the write-in data through overcompression Condition, an entity program unit may correspond to multiple logical program units.
Figure 10 A are the corresponding garbage collection operations according to shown by an embodiment and storage entity-logic is reflected Penetrate the schematic diagram of information.Figure 10 B are the corresponding garbage collection operations according to shown by another embodiment and deposit Store up the schematic diagram of entity-logical mappings information.
Figure 10 A are refer to, when to entity erased cell 410 (0) and the execution rubbish of entity erased cell 410 (1) When rubbish collects operation, memorizer control circuit unit 404 (or memory management circuitry 502) can be by entity Valid data in erased cell 410 (0) and entity erased cell 410 (1) are moved to another entity and erased In unit.For example, memorizer control circuit unit 404 (or memory management circuitry 502) smears entity Except the valid data D3 in valid data D1, the D2 in unit 410 (0) and entity erased cell 410 (1) Store to the data bit area of entity erased cell 410 (F+1).Memorizer control circuit unit 404 (or Memory management circuitry 502) also by logical address (that is, the logical address corresponding to this little valid data LA (0), LA (2), LA (3)) store to redundancy ratio special zone.Also, memorizer control circuit unit 404 (or memory management circuitry 502) meeting will be on the entity-logical mappings of entity erased cell 410 (F+1) Information 922 is stored into entity erased cell 410 (F+1).Therefore, entity erased cell 410 (F+1) meeting Storage valid data D1 and corresponding logical address LA (0), valid data D2 and corresponding logical address LA (2), valid data D3 and corresponding logical address LA (3) and entity-logical mappings information 922. In this exemplary embodiment, entity-logical mappings information 922 is to have recorded valid data D1, D2, D3 Corresponding logical address (that is, logical address LA (0), LA (2), LA (3)).Due to this example reality Apply example and correspond to garbage collection operations, therefore memorizer control circuit unit 404 (or memory management Circuit 502) write time information and finishing time information can be set to represent entity-logical mappings information 922 Time.For example, in the present embodiment, using only an entity erased cell (i.e. entity erased cell (F+1) it is) to complete garbage collection operations, therefore, will be corresponding to the finishing time of entity erased cell (F+1) Information setting is 1.And write time information can set according to the time sequencing corresponding to general write operation It is fixed.For example, in this exemplary embodiment, the write time information of entity-logical mappings information 922 can set It is set to 3.However, in another exemplary embodiment, write time information can also be set as according to actual demand Other values.
Refer to Figure 10 B, be stored when multiple entity erased cells need to be extracted from idle area valid data with (for example, extracting two entity erased cells from idle area to be stored with when completing a garbage collection operations Data are imitated to discharge three entity erased cells), memorizer control circuit unit 404 (or memory Management circuit 502) can be extracted to store the time sequencing of valid data according to this little entity erased cell Sequentially set finishing time information.As shown in Figure 10 B, it is assumed that memorizer control circuit unit 404 (or Memory management circuitry 502) entity erased cell 410 (F+1) need to be extracted and 410 (F+2) carry out storage entity The valid data of erased cell 410 (0), 410 (1) and 410 (2), could complete this garbage collection operations. Memorizer control circuit unit 404 (or memory management circuitry 502) can be by entity erased cell 410 (0) Valid data D1, D2 and the valid data D3 of entity erased cell 410 (1) store to entity and erase list 410 (F+1) of unit, and entity-logical mappings information 922 is stored to entity erased cell 410 (F+1), And by write time information setting be 4, and by finishing time information setting be 1.Furthermore, memory control Circuit unit processed 404 (or memory management circuitry 502) can be by the significant figure of entity erased cell 410 (1) Stored to entity erased cell according to valid data D5, D6 of D4 and entity erased cell 410 (2) 410 (F+2), and entity-logical mappings information 926 is stored to entity erased cell 410 (F+1), with And write time information is similarly set as 4, and be 2 by finishing time information setting.In this example reality Apply in example, entity-logical mappings information 922 is to have recorded patrolling corresponding to valid data D1, D2, D3 Collect address (that is, logical address LA (0), LA (2), LA (3)), and entity-logical mappings information 926 Be have recorded corresponding to valid data D4, D5, D6 logical address (that is, logical address LA (5), LA(6)、LA(8)).Additionally, it is noted that in this exemplary embodiment, completing a rubbish During rubbish collects operation, when being extracted the write-in of all entity erased cells to store valid data Between information can be set to identical value.
In above-mentioned exemplary embodiment, memorizer control circuit unit 404 (or memory management circuitry 502) It is by the entity in buffer storage 508-logical mappings information Store to related entity erased cell. However, in other exemplary embodiments, memorizer control circuit unit 404 (or memory management circuitry 502) entity in buffer storage 508-logical mappings information Store to special entity can also be erased In unit, this special entity erased cell is to be specifically used to storage entity-logical mappings information.
In this exemplary embodiment, memorizer control circuit unit 404 (or memory management circuitry 502) Meeting is in reasonable time point using entity-logical mappings information come more new logic-entity mapping.For example, working as When space in buffer storage 508 for storage entity-logical mappings information has been expired, memory control electricity Entity-logic of road unit 404 (or memory management circuitry 502) meeting in buffer storage 508 Map information carrys out more new logic-entity mapping, and the logic-entity mapping after renewal is restored to and can answered In writing formula non-volatile memory module 406.
However, it is non-volatile duplicative may to occur after memory storage apparatus 10 are using a period of time Property the situation about damaging of memory module 406, make stored logic-entity mapping damage and cannot be normal Access data.Therefore, in this exemplary embodiment, if logic-entity mapping has been damaged, can pass through Entity-logical mappings the information of reproducible nonvolatile memorizer module 406 is arranged to rebuild logic-reality Body mapping table, so recognize reproducible nonvolatile memorizer module 406 stored data (for example, User's data).
Figure 11 is the schematic diagram for setting up logic-entity mapping according to shown by an embodiment.
When needing to rebuild data, host computer system 11 can assign control instruction and indicate memorizer control circuit list First 404 (or memory management circuitries 502) perform respective operations.For example, memorizer control circuit unit 404 (or memory management circuitries 502) can be deposited according to the reading instruction reading for coming from host computer system 11 Entity-logical mappings information and corresponding temporal information in all entity erased cells are stored up, and will be read The entity for taking-logical mappings information and temporal information are in response to host computer system 11.Further, main frame system 11 temporal informations that can be according to corresponding to entity-logical mappings information are united to arrange entity-logical mappings letter Breath.In this exemplary embodiment, it is assumed that the entity for being read-logical mappings information includes being smeared corresponding to entity Except the entity-logical mappings information of unit PBA (0)~PBA (3).The entity of entity erased cell PBA (0)- Logical mappings information includes logical address LA (0), LA (1), LA (2), and corresponding to logical address LA (0), LA (1), the write time information of LA (2) and finishing time information are respectively 1 and 0.Entity is smeared Except the entity-logical mappings information of unit PBA (1) includes logical address LA (3), LA (4), LA (5), and And corresponding to logical address LA (3), LA (4), the write time information of LA (5) and finishing time information point Wei 2 and 0.The entity of entity erased cell PBA (2)-logical mappings information include logical address LA (1), LA (2), LA (4), and during corresponding to LA (1), LA (2), the write time information of LA (4) with arranging Between information be respectively 3 and 0.The entity of entity erased cell PBA (3)-logical mappings information is included logically Location LA (0), LA (3), LA (5), and corresponding to logical address LA (0), LA (3), LA (5) write-in Temporal information and finishing time information are respectively 4 and 1.Host computer system 11 is according to write time information and whole Reason temporal information is by entity-logical address map information sequence as shown in the sorting table 1101 of Figure 11.Need note Meaning, in this exemplary embodiment, the reality marked in entity-logical mappings finish message table 1101 Body address counterlogic address is only the signal of entity-logical mappings information, in practical operation, entity-logic Map information can be recorded based on logical address, and this part illustrates in foregoing teachings, no longer goes to live in the household of one's in-laws on getting married herein State.
Additionally, in this exemplary embodiment, host computer system 11 can first compare corresponding to entity-logical mappings The write time information of information, if write time information is identical, then compares finishing time information.Another In one exemplary embodiment, it is also possible to determined different from above-mentioned determination methods with write time information or whole Reason temporal information carrys out re-ordering entity-logical mappings information.
As shown in entity-logical mappings finish message table 1101, in this exemplary embodiment, logical address LA (0) can map to entity erased cell PBA (0) and entity erased cell PBA (3), logical address LA (1) And LA (2) can map to entity erased cell PBA (0) and entity erased cell PBA (2), logical address LA (4) can map to entity erased cell PBA (1) and entity erased cell PBA (2), logical address LA (3) And LA (5) can map to entity erased cell PBA (1) and entity erased cell PBA (3).Therefore, store Device controls circuit unit 404 (or memory management circuitry 502) newest to identify according to temporal information Mapping relations.For example, the mapping relations on logical address LA (0), host computer system 11 is according to write-in Temporal information decision logic address LA (0) maps to entity erased cell PBA (3) (the corresponding write time 4) it is newest mapping relations that information is, base this set up logical address LA (0) and map to physical address The logic of PA (3-0)-entity map information is simultaneously recorded in logic-entity mapping 1102.In the same manner, close In the mapping relations of logical address LA (1), host computer system 11 is according to write time information decision logic address It is newest mapping that LA (1) maps to entity erased cell PBA (2) (corresponding write time information is 3) Relation, base this set up logic-entity map information that logical address LA (1) maps to physical address PA (2-0) And record in logic-entity mapping 1102.By that analogy, host computer system 11 can be according to ranked The sorting table 1101 of entity-logical address map information sets up multiple logics-entity map information to produce Logic-entity mapping 1102.
In this exemplary embodiment, host computer system 11 is according to entity-logical mappings finish message table 1101 Scan ordering entity-logical address mapping letter one by one (that is, by legacy data to new data) from front to back Breath, and newest mapping relations are recorded in logic-entity mapping 1102.For example, host computer system 11 scanning to physical address PA (0-1) map to the map information of logical address LA (1) when, can be by logically The mapping relations that location LA (1) maps to physical address PA (0-1) are recorded in logic-entity mapping 1102. Thereafter, when host computer system 11 scans the mapping that logical address LA (1) is mapped to physical address PA (2-0) During information, the mapping relations that can map to physical address PA (2-0) with logical address LA (1) carry out more new logic - entity mapping 1102.
In another exemplary embodiment, host computer system 11 is also dependent on entity-logical mappings finish message table 1101 scan ordering entity-logical address one by one (that is, by new data to legacy data) back to front reflects Information is penetrated, and newest mapping relations are recorded in logic-entity mapping 1102.For example, main frame System 11 scanning to physical address PA (2-2) map to the map information of logical address LA (4) when, you can Judge that this map information is the newest mapping relations of counterlogic address LA (4), and by logical address The mapping relations that LA (4) maps to physical address PA (2-2) are recorded in logic-entity mapping 1102. Thereafter, when host computer system 11 scans the mapping that logical address LA (4) are mapped to physical address PA (1-1) During information, will not more new logic-entity mapping 1102.
Although memorizer control circuit unit 404 (or memory management circuitry 502) will write data Store to entity erased cell, can be by corresponding entity-logical mappings information Store to the reality for writing data In body erased cell.If but there is System Operation problem (for example, power-off) during write-in data so that Though write-in data have been stored to entity erased cell, entity-logical mappings information is not yet stored to entity and smeared Except in unit.Consequently, it is possible to memorizer control circuit unit 404 (or memory management circuitry 502) will Entity program unit that cannot directly from this entity erased cell (for example, in entity erased cell most The latter entity program unit being programmed) the middle entity-logical mappings for obtaining this entity erased cell Information.
Therefore, when memorizer control circuit unit 404 (or memory management circuitry 502) cannot be from certain reality When obtaining entity-logical mappings information in the entity program unit of body erased cell, memorizer control circuit Unit 404 (or memory management circuitry 502) can one by one be read in units of specific data volume size The user's data and corresponding redundancy ratio special zone that data bit area is stored in this entity erased cell are deposited The logical address of storage.Memorizer control circuit unit 404 (or memory management circuitry 502) can be from current Logic-the entity mapping set up finds out the physical address that this logical address is mapped, and reads storage and exist User's data of this physical address.Host computer system 11 and then can judge to be by comparing user's data No map information that need to be in more new logic-entity mapping.
Figure 12 A and 12B are with more new logic-entity according to shown by an embodiment than to user's data The schematic diagram of mapping table.
Figure 12 A are refer to, in this exemplary embodiment, host computer system 11 is according to from entity erased cell The entity that may be read into-logical mappings information establishes logic-entity mapping 1201.For not obtaining reality The entity erased cell of body-logical mappings information, host computer system 11 can assign reading instruction to indicate storage Device controls circuit unit 404 (or memory management circuitry 502) to be deposited in reading this little entity erased cell User's data and logical address of storage.It is with the big of entity program unit in this exemplary embodiment It is small to read user's data for unit.For example, Figure 12 B, entity erased cell 410 (3) be refer to Do not store corresponding entity-logical mappings information, memorizer control circuit unit 404 (or memory management Circuit 502) user's data and corresponding logical address of entity erased cell 410 (3) can be read.For example, Logical address LA (0) corresponding data D4, logical address LA (1) corresponding data D2, logical address LA (2) Corresponding data D3.
Referring to Figure 12 A and 12B, memorizer control circuit unit 404 (or memory management electricity Road 502) logic-entity mapping 1201 for having set up at present can be inquired about, with find out it is read-out logically The physical address of location mapping.For example, in logic-entity mapping 1201, logical address LA (0) mappings To physical address PA (2-0) (that is, the entity program unit 410 (2-0) of entity erased cell 410 (2)), Memorizer control circuit unit 404 (or memory management circuitry 502) can read entity program unit The data D1 that 410 (2-0) are stored.
Host computer system 11 can compare the data D4 and entity erased cell in entity erased cell 410 (3) Data D1 in 410 (2), and judge data to differ and need more new logic-entity mapping 1201.It is main Machine system 11 can be patrolled with the mapping relations of logical address LA (0) according to entity erased cell 410 (3) to update Volume-entity mapping 1201.Figure 12 B are refer to, in logic-entity mapping 1202 in the updated, The map information of logical address LA (0) can be updated to map to physical address PA (3-0) that (that is, entity is smeared Except the entity program unit 410 (3-0) of unit 410 (3)).
Then, memorizer control circuit unit 404 (or memory management circuitry 502) may proceed to for real Next record user's data in body erased cell 410 (3) are compared.For example, entity erased cell Data D2 in 410 (3) entity program unit 410 (3-1) is to correspond to logical address LA (1). In logic-entity mapping 1202, logical address LA (1) is to map to physical address PA (2-1) (i.e., The entity program unit 410 (2-1) of entity erased cell 410 (2)), memorizer control circuit unit 404 (or memory management circuitry 502) can read the data D2 that entity program unit 410 (2-1) is stored.
Host computer system 11 can compare the data D2 and entity erased cell in entity erased cell 410 (3) Data D2 in 410 (2), and judge that data are identical without more new logic-entity mapping 1202.
It is noted that in the logic-entity mapping of this exemplary embodiment, with logical address correspondence Physical address is only to illustrate come the mapping relations represented between logic unit and solid element.Actually also may be used To be indicated different from aforesaid way.
Logic-the entity mapping rebuild by above-mentioned exemplary embodiment will may include newest logic-reality Body map information.And then, host computer system 11 can be according to the logic-entity mapping rebuild by duplicative Data in non-volatile memory module 406 correctly read.
It is by host computer system 11 in the process for rebuilding logic-entity mapping in above-mentioned exemplary embodiment To perform the computing of correlation.Host computer system 11 can indicate memory to control electricity by assigning control instruction Road unit 404 (or memory management circuitry 502) performs corresponding operating.This little control instruction can be had Not in the special instruction of general instruction, for example, manufacturer's instruction (vender command).Therefore, it is main The data reconstruction control code that machine system 11 can will be used to rebuild data is sent to memory storage apparatus 10, Memorizer control circuit unit 404 (or memory management circuitry 502) can carry this data reconstruction control code Enter into buffer storage 508 to run.This data reconstruction control code can be run and make memorizer control circuit Unit 404 (or memory management circuitry 502) can perform corresponding according to the special instruction of host computer system 11 Operation.However, passing through firmware in other exemplary embodiments, or by memory storage apparatus 10 Code runs and performs the related operation in the process for rebuilding logic-entity mapping.
Furthermore, the speed of data being read to be lifted, the logic-entity mapping of reconstruction can be also loaded into In the buffer storage 508 of memory storage apparatus 10, memorizer control circuit unit 404 is set (or to deposit Reservoir manages circuit 502) logic-entity mapping in buffer storage 508 can be directly accessed to read Store the user's data in reproducible nonvolatile memorizer module 406.For example, host computer system 11 can be used manufacturer's instruction that the map information in the logic-entity mapping of reconstruction is restored into storage in batches In the buffer storage 508 of device storage device 10.Thereafter, host computer system 11 can assign general reading and refer to Order non-easily indicate memorizer control circuit unit 404 (or memory management circuitry 502) to read duplicative User's data in the property lost memory module 406.
It is noted that the map information write every time to memory storage apparatus 10 can be according to one in batches As read that instruction can read maximum read data volume to determine.For example, host computer system 11 can be according to general Read the maximum of instruction and read the logical address number that data volume can read, and according to patrolling for being calculated Address number is collected to write to memory storage dress the map information of respective amount in logic-entity mapping In putting 10 buffer storage.After write-in map information, host computer system 11 can assign general reading and refer to Order indicates memorizer control circuit unit 404 (or memory management circuitry 502) by this little map information institute Corresponding user's data once read.
Figure 13 is the data re-establishing method flow chart according to shown by an embodiment.
Figure 13 is refer to, in step S1301, storage is read in type nonvolatile mould Entity-logical mappings information in block and the temporal information corresponding to entity-logical mappings information.In step In S1303, according to the read entity-logical mappings information of the temporal information sequence read.In step In S1305, logic-entity mapping is produced according to ordering entity-logical mappings information.In step In S1307, produced logic-entity mapping is restored to the buffer storage of memory storage apparatus In.
In another exemplary embodiment, before step S1301, also including record entity-logical mappings letter In breath to the buffer storage of memory storage apparatus, and entity-logical mappings information is multiple real record Multiple logical addresses of body erased cell.Thereafter, entity-logical mappings letter of the record in buffer storage It is non-volatile that breath and the temporal information corresponding to entity-logical mappings information can be stored to duplicative In memory module.
In another exemplary embodiment, before step S1301, also including data reconstruction control code is carried Enter to the buffer storage of memory storage apparatus.Also, above-mentioned steps have been described in detail as above, herein Repeat no more.
In sum, the present invention understands recording time information in the lump in storage entity-logical mappings information, Use the new and old of identification entity-logical mappings information.Thereafter, cannot correctly be deposited in logic-entity mapping When taking, logic-entity map information can be set up according to newest entity-logical mappings information.Thereby, may be used Logic-entity mapping needed for correctly reconstructing access data, and can be according to the logic-entity rebuild Mapping table correctly reads the user's data in reproducible nonvolatile memorizer module.In addition, Logic-the entity mapping of reconstruction can be also stored back into the buffer storage of memory storage apparatus, thus The efficiency of data is read in lifting.
Finally it should be noted that：Various embodiments above is merely illustrative of the technical solution of the present invention, rather than right Its limitation；Although being described in detail to invention with reference to foregoing embodiments, the common skill of this area Art personnel should be understood：It can still modify to the technical scheme described in foregoing embodiments, Or equivalent is carried out to which part or all technical characteristic；And these modifications or replacement, and The scope of the essence disengaging various embodiments of the present invention technical scheme of appropriate technical solution is not made.

Claims (27)

1. a kind of data re-establishing method, for memory storage apparatus, the memory storage apparatus have One reproducible nonvolatile memorizer module, the reproducible nonvolatile memorizer module has many Individual entity erased cell, it is characterised in that the data re-establishing method includes：
Reading is stored in the multiple entity-logical mappings in the reproducible nonvolatile memorizer module Information and the multiple temporal informations corresponding to those entities-logical mappings information；
Sorted those entities-logical mappings information according to those temporal informations；
Multiple logic-entity map informations are set up to produce according to ordering those entities-logical mappings information Raw logic-entity mapping；And
During the logic-entity mapping restored into the buffer storage of the memory storage apparatus.
2. data re-establishing method according to claim 1, it is characterised in that by the logic-reality The step that body mapping table is restored in the buffer storage of the memory storage apparatus includes：
Logical address number is calculated according to corresponding to the maximum data volume that reads for reading instruction, and according to institute Logical address number is stated to write the multiple logics-entity map information of the logic-entity mapping in batches Into the buffer storage of the memory storage apparatus.
3. data re-establishing method according to claim 1, it is characterised in that the temporal information bag Include write time information and finishing time information.
4. data re-establishing method according to claim 3, it is characterised in that those entity-logics Map information includes first instance-logical mappings information and second instance-logical mappings information, wherein basis should A little temporal informations sort those entities-logical mappings information the step of include：
According to those write time information sortings those entities-logical mappings information；And
If the first write time information of the first instance-logical mappings information and the second instance- Second write time information of logical mappings information is identical, according to the first instance-logical mappings information Second finishing time information sorting of the first finishing time information and the second instance-logical mappings information The first instance-logical mappings information and the second instance-logical mappings information.
5. data re-establishing method according to claim 1, it is characterised in that those entity-logics Map information includes three entities-logical mappings information and four entities-logical mappings information, wherein according to Sequence those entities-logical mappings information set up those logics-entity map information with produce the logic- The step of entity mapping, also includes：
If three entities-logical mappings information and four entities-logical mappings information include phase With logical address, and four entities-logical mappings information temporal information sort the described 3rd After the temporal information of entity-logical mappings information, according to four entities-logical mappings information updating institute State logic-entity mapping.
6. data re-establishing method according to claim 1, it is characterised in that each entity is erased list Unit has multiple entity program units, and those entity program units include first instance programmed cell And second instance programmed cell, wherein after the step of producing the logic-entity mapping, also wrapping Include：
The first information and one first logical address of the first instance programmed cell are read, wherein described Five entities-logical mappings information corresponding to first instance programmed cell is not yet stored to described and answered In writing formula non-volatile memory module；
The second instance that first logical address is mapped is read according to the logic-entity mapping The second information in programmed cell；And
If the first information is differed with second information, in the renewal logic-entity mapping First logical address map to the first instance programmed cell.
7. data re-establishing method according to claim 1, it is characterised in that be stored in institute in reading Before stating those entities-logical mappings information in reproducible nonvolatile memorizer module, also include：
The data reconstruction control code that the host computer system will be come from is loaded into the memory storage apparatus In the buffer storage, and the data reconstruction control code can be run with according to the host computer system Those entities that at least one instruction reading is stored in the reproducible nonvolatile memorizer module-patrol Collect map information.
8. data re-establishing method according to claim 1, it is characterised in that those entity-logics Map information is stored in an at least entity erased cell of the reproducible nonvolatile memorizer module In data bit area, and those temporal informations are stored in an at least entity erased cell Redundancy ratio special zone.
9. data re-establishing method according to claim 1, it is characterised in that also include：
Record those entities-logical mappings information in said buffer memory；
Those entities-logical mappings information that will be recorded in the buffer storage and those entities-patrol Those temporal informations corresponding to map information are collected to store to the reproducible nonvolatile memorizer module In.
10. a kind of memorizer control circuit unit, is configured at memory storage apparatus, described for controlling The reproducible nonvolatile memorizer module of memory storage apparatus, the duplicative is non-volatile to be deposited Memory modules have multiple entity erased cells, it is characterised in that the memorizer control circuit unit bag Include：
HPI, is electrically connected to host computer system；
Memory interface, is electrically connected to the reproducible nonvolatile memorizer module；And
Memory management circuitry, is electrically connected to the HPI and the memory interface,
Wherein, the memory management circuitry reads and is stored in the type nonvolatile mould Multiple entities-logical mappings information in block and corresponding to those entities-logical mappings information it is multiple when Between information,
Wherein, the memory management circuitry sorts those entities-logical mappings letter according to those temporal informations Breath,
Wherein, the memory management circuitry sets up many according to ordering those entities-logical mappings information Individual logic-entity map information to produce logic-entity mapping,
Wherein, the logic-entity mapping is loaded into the memory and deposited by the memory management circuitry In the buffer storage of storage device.
11. memorizer control circuit units according to claim 10, it is characterised in that described to deposit Reservoir manages circuit and calculates logical address number according to corresponding to the maximum data volume that reads for reading instruction, and And according to the logical address number by the multiple logics-entity map information of the logic-entity mapping It is loaded into batches in the buffer storage of the memory storage apparatus.
12. memorizer control circuit units according to claim 10, it is characterised in that when described Between information include write time information and finishing time information.
13. memorizer control circuit units according to claim 12, it is characterised in that those realities Body-logical mappings information includes first instance-logical mappings information and second instance-logical mappings information,
Wherein described memory management circuitry according to those write time information sortings, reflect by those entity-logics Penetrate information,
Wherein, if the first write time information and described second of the first instance-logical mappings information Second write time information of entity-logical mappings information is identical, and the memory management circuitry is according to First finishing time information of first instance-logical mappings information and the second instance-logical mappings information The second finishing time information sorting described in first instance-logical mappings information and the second instance-logic Map information.
14. memorizer control circuit units according to claim 10, it is characterised in that those realities Body-logical mappings information includes three entities-logical mappings information and four entities-logical mappings information,
If wherein described three entities-logical mappings information and four entities-logical mappings packet Include identical logical address, and four entities-logical mappings information sorting the 3rd entity- After logical mappings information, the memory management circuitry according to four entities-logical mappings information more New logic-the entity mapping.
15. memorizer control circuit units according to claim 10, it is characterised in that Mei Yishi Body erased cell has multiple entity program units, and those entity program units include first instance journey Sequence unit and second instance programmed cell,
Wherein the memory management circuitry reads the first information and the of the first instance programmed cell One logical address, wherein the five entities-logical mappings information corresponding to the first instance programmed cell Not yet store into the reproducible nonvolatile memorizer module,
Wherein, the memory management circuitry reads first logic according to the logic-entity mapping The second information in the second instance programmed cell that address is mapped,
Wherein, if the first information is differed with second information, the memory management circuitry First logical address updated in the logic-entity mapping maps to the first instance program Change unit.
16. memorizer control circuit units according to claim 10, it is characterised in that described to deposit The data reconstruction control code that reservoir management circuit will come from the host computer system is loaded into the memory and deposits In the buffer storage of storage device,
Wherein, the data reconstruction control code can be run so that the memory management circuitry is according to the master Those that be stored in the reproducible nonvolatile memorizer module are read at least one instruction of machine system Entity-logical mappings information.
17. memorizer control circuit units according to claim 10, it is characterised in that those realities Body-logical mappings information is stored in an at least entity of the reproducible nonvolatile memorizer module Data bit area in erased cell, and those temporal informations are stored in an at least entity and erase Redundancy ratio special zone in unit.
18. memorizer control circuit units according to claim 10, it is characterised in that described to deposit Reservoir management circuit records those entities-logical mappings information in said buffer memory, and will record Those entities-logical mappings information and those entities-logical mappings information in said buffer memory Those corresponding temporal informations are stored into the reproducible nonvolatile memorizer module.
A kind of 19. data reconstruction systems, it is characterised in that including：
Host computer system, with data reconstruction unit；
Memory storage apparatus, including：
Connecting interface unit, is electrically connected to the host computer system；
Reproducible nonvolatile memorizer module, with multiple entity erased cells；And
Memorizer control circuit unit, is electrically connected to the connecting interface unit non-with the duplicative Volatile,
Wherein, the data reconstruction unit transmission at least reads instruction to the memory storage apparatus, And the memorizer control circuit unit according at least one read instruction reading be stored in described in can make carbon copies Multiple entities-logical mappings information in formula non-volatile memory module and corresponding to those entities-patrol Collect multiple temporal informations of map information and read instruction with response to described at least one,
Wherein, the data reconstruction unit sorts those entities-logical mappings letter according to those temporal informations Breath,
Wherein, the data reconstruction unit sets up multiple according to ordering those entities-logical mappings information Logic-entity map information to produce logic-entity mapping,
Wherein, the logic-entity mapping is restored to the memory storage by the data reconstruction unit In the buffer storage of device.
20. data reconstruction systems according to claim 19, it is characterised in that the data reconstruction Unit calculates a logical address number according to the maximum data volume that reads that instruction is read corresponding to, and Multiple logics-entity the map information of the logic-entity mapping is divided according to the logical address number Criticize and write into the buffer storage of the memory storage apparatus.
21. data reconstruction systems according to claim 19, it is characterised in that the temporal information Including write time information and finishing time information.
22. data reconstruction systems according to claim 21, it is characterised in that those entities-patrol Collecting map information includes first instance-logical mappings information and second instance-logical mappings information,
Wherein described data reconstruction unit is according to those entity-logical mappings of those write time information sortings Information,
Wherein, if the first write time information and described second of the first instance-logical mappings information Second write time information of entity-logical mappings information is identical, and the data reconstruction unit is according to described First finishing time information of one entity-logical mappings information and the second instance-logical mappings information First instance-logical mappings information described in second finishing time information sorting and the second instance-logic are reflected Penetrate information.
23. data reconstruction systems according to claim 19, it is characterised in that those entities-patrol Collecting map information includes three entities-logical mappings information and four entities-logical mappings information,
If wherein described three entities-logical mappings information and four entities-logical mappings packet Include identical logical address, and four entities-logical mappings information sorting the 3rd entity- After logical mappings information, the data reconstruction unit is according to four entities-logical mappings information updating Logic-the entity mapping.
24. data reconstruction systems according to claim 19, it is characterised in that each entity is erased Unit has multiple entity program units, and those entity program units include first instance sequencing list Unit and second instance programmed cell,
Instruction to the memory storage apparatus, and institute is read in wherein described data reconstruction unit transmission first State memorizer control circuit unit and read the instruction reading first instance programmed cell according to described first The first information and the first logical address with response to described first read instruction, wherein the first instance Five entities-logical mappings information corresponding to programmed cell not yet stores non-easily to the duplicative In the property lost memory module,
Wherein, the data reconstruction unit is according to first logical address and the logic-entity mapping Transmission second reads instruction to the memory storage apparatus, and the memorizer control circuit unit according to The second reading instruction is read in the second instance programmed cell that first logical address is mapped Second information reads instruction with response to described second,
Wherein, if the first information is differed with second information, the data reconstruction unit is more First logical address in the new logic-entity mapping maps to the first instance sequencing Unit.
25. data reconstruction systems according to claim 19, it is characterised in that the data reconstruction Unit transmits data reconstruction control code to the memory storage apparatus, and the memorizer control circuit list Be loaded into the data reconstruction control code in the buffer storage of the memory storage apparatus by unit,
Wherein, the data reconstruction control code can be run so that the memorizer control circuit unit is according to institute State described at least the one of data reconstruction unit and read instruction reading and be stored in that the duplicative is non-volatile to be deposited Those entities-logical mappings information in memory modules.
26. data reconstruction systems according to claim 19, it is characterised in that those entities-patrol At least entity that volume map information is stored in the reproducible nonvolatile memorizer module is erased list Data bit area in unit, and those temporal informations are stored in an at least entity erased cell Redundancy ratio special zone.
27. data reconstruction systems according to claim 19, it is characterised in that the memory control Circuit unit processed records those entities-logical mappings information in said buffer memory, and record is existed Those entities-logical mappings information and those entities in the buffer storage-logical mappings information institute Corresponding those temporal informations are stored into the reproducible nonvolatile memorizer module.
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