CN104679437A

CN104679437A - Data writing method, memory control circuit unit and memory storage device

Info

Publication number: CN104679437A
Application number: CN201310615699.8A
Authority: CN
Inventors: 梁鸣仁
Original assignee: Phison Electronics Corp
Current assignee: Phison Electronics Corp
Priority date: 2013-11-27
Filing date: 2013-11-27
Publication date: 2015-06-03
Anticipated expiration: 2033-11-27
Also published as: CN104679437B

Abstract

The invention discloses a data writing method used for a re-writable nonvolatile memory module, a memory control circuit unit and a memory storage device, wherein the re-writable nonvolatile memory module comprises a plurality of entity erasing units. The data writing method includes that at least grouping the entity erasing units into a data zone and a leisure zone; configuring a plurality of logic units to map the entity erasing units of the data zone; dynamically keeping a certain number of entity erasing units for being exclusively used in writing ordinal data. The data writing method is capable of quickly writing ordinal data under a management mechanism based on pages.

Description

Method for writing data, memorizer control circuit unit and memorizer memory devices

Technical field

The invention relates to a kind of method for writing data for type nonvolatile, memorizer control circuit unit and memorizer memory devices.

Background technology

Digital camera, mobile phone and MP3 are very rapid in growth over the years, and the demand of consumer to Storage Media is also increased rapidly.Due to type nonvolatile (rewritable non-volatile memory) there is data non-volatile, power saving, the characteristic such as volume is little, mechanical structure, read or write speed are fast, be most suitable for portable electronic product, such as notebook computer.Solid state hard disc is exactly a kind of memorizer memory devices using short-access storage as Storage Media.Therefore, short-access storage industry becomes a ring quite popular in electronic industry in recent years.

Flash memory module has multiple entity erased cell and each entity erased cell has multiple entity program unit (physical page), must be sequentially written in data when wherein writing data in entity erased cell according to entity program unit.In addition, the entity program unit being written into data could again for writing data after must first being erased.Particularly, entity erased cell is the least unit of erasing, and entity program unit is the minimum unit of sequencing (also claiming to write).Therefore, in the management of flash memory module, entity erased cell can be divided into data field and free area.

The entity erased cell of data field is the data stored stored by host computer system.Specifically, the logic access address that host computer system can access by the memorizer control circuit unit in memorizer memory devices is converted to the logical page (LPAGE) of logical blocks and the logical page (LPAGE) of logical blocks is mapped to the entity program unit of the entity erased cell of data field.That is, the entity erased cell in the management data district of flash memory module is regarded as by the entity erased cell (such as, having stored the data that host computer system writes) used.Such as, memorizer control circuit unit can use logic to turn physical address mapping table to record the mapping relations of the entity erased cell of logical blocks and data field, and the logical page (LPAGE) wherein in logical blocks is the entity program unit of the corresponding entity erased cell mapped.

The entity erased cell of free area is in order to the entity erased cell in replacement data district.Specifically, as mentioned above, the entity erased cell of written data just can again for writing data after must being erased, and therefore, the entity erased cell of free area is designed to write random data to replace the entity erased cell of mapping logic block.Therefore, the entity erased cell in free area is empty or spendable entity erased cell, i.e. no record data or be labeled as invalid data useless.

That is, the entity program unit of the entity erased cell of data field and free area is the logical page (LPAGE) carrying out mapping logic block with substitute mode, to store the data that host computer system writes.Such as, when host computer system is a certain logical page (LPAGE) of a certain logical blocks of correspond to memories storage device for writing the logic access address of random data, the memorizer control circuit unit of memorizer memory devices can extract one or more entity erased cell from free area, this random data is write in the entity program unit of extracted entity erased cell, and the entity erased cell of write data is associated to data field.

Particularly, during memorizer memory devices operation, when the entity erased cell of free area fast depleted time, valid data at least one entity erased cell in data field to arrange to data field in other entity erased cell not by (hereinafter referred to as " valid data union operation ") in the entity program unit that uses by the memorizer control circuit unit of memorizer memory devices, to perform erase operation for use to the entity erased cell only storing invalid data and the entity erased cell after erasing be associated to free area, continue to make the mechanism of replacement operation to maintain to perform follow-up write instruction.

But, it is relatively consuming time for performing above-mentioned data consolidation procedure, therefore, if host computer system requires to write mass data at short notice (such as, because indicating the data storing in memory buffer by power-off to the request of type nonvolatile) and the entity erased cell of free area fast depleted time, the needs at substantial time is carried out data consolidation procedure by the memorizer control circuit unit of memorizer memory devices, and the write of data cannot be completed within the schedule time, and make the Missing data stored by system.

Summary of the invention

The invention provides a kind of method for writing data, memorizer control circuit unit and memorizer memory devices, it can shorten the time of write sequence data.

Accordingly, the present invention one exemplary embodiment proposes a kind of wiring method for reproducible nonvolatile memorizer module data, and wherein this reproducible nonvolatile memorizer module comprises multiple entity erased cell.Notebook data wiring method comprises: this little entity erased cell is at least grouped into data field and free area; Configure multiple logical block to map the entity erased cell of this data field; And the entity erased cell dynamically maintaining the predetermined quantity among this little entity erased cell is to be exclusively used in write sequence data.

In one example of the present invention embodiment, the above-mentioned entity erased cell dynamically maintaining a predetermined quantity among this little entity erased cell comprises to the step being exclusively used in write sequence data: minimum threshold value is added the value that above-mentioned predetermined quantity obtains reclaims threshold value to set garbage.In addition, said method also comprises: the write instruction receiving at least one first logical block of instruction write first data so far among a little logical block from host computer system; Judge whether the first data are alphabetic data or random data; And when if the first data are alphabetic data, at least one first instance erased cell is extracted from the entity erased cell of free area, by the first data write so far at least one first instance erased cell, this at least one first instance erased cell is associated to data field, adjusts above-mentioned garbage according to the number of this at least one first instance erased cell and minimum threshold value and reclaim threshold value.Wherein, when the value that the number that the garbage recovery threshold value before adjusting deducts at least one first instance erased cell obtains is greater than minimum threshold value, the value that the number that the garbage recovery threshold value before the garbage recovery threshold value after adjustment can be set to adjustment deducts at least one first instance erased cell obtains; And when the garbage before adjusting reclaims that value that the threshold value number that deducts at least one first instance erased cell obtains is non-is greater than minimum threshold value, the garbage after adjustment reclaims threshold value can be set minimum threshold value for this reason.

In one example of the present invention embodiment, the above-mentioned entity erased cell dynamically maintaining a predetermined quantity among this little entity erased cell also comprises to the step being exclusively used in write sequence data: if when the first data are random data, at least one second instance erased cell is extracted, by these first data write so far at least one second instance erased cell and this at least one second instance erased cell is associated to data field from the entity erased cell of free area.

In one example of the present invention embodiment, the above-mentioned entity erased cell dynamically maintaining a predetermined quantity among this little entity erased cell also comprises to the step being exclusively used in write sequence data: judge whether the number of the entity erased cell of free area is not more than garbage and reclaims threshold value; And if when the number of the entity erased cell of free area is not more than garbage recovery threshold value, perform data consolidation procedure so that at least one entity erased cell of data field is associated to free area.

In one example of the present invention embodiment, above-mentioned execution data consolidation procedure comprises with the step that at least one entity erased cell of data field is associated to free area: from the entity erased cell of data field, select one the 3rd entity erased cell; If when the 3rd entity erased cell has at least one valid data, these at least one valid data are copied to 1 this data field the 4th entity erased cell from the 3rd entity erased cell; And the 3rd entity erased cell and the 3rd entity erased cell after erasing is associated to free area of erasing.

In one example of the present invention embodiment, the capacity of above-mentioned logical block equals the capacity of the entity erased cell of data field, and the capacity of the entity erased cell of above-mentioned predetermined quantity is less than or equal to the capacity of those logical blocks.

The present invention one exemplary embodiment proposes a kind of memorizer control circuit unit for controlling reproducible nonvolatile memorizer module, and wherein reproducible nonvolatile memorizer module has multiple entity erased cell.Memorizer control circuit unit comprises host interface, memory interface and memory management circuitry.Host interface is in order to be electrically connected to host computer system.Memory interface is in order to be electrically connected to reproducible nonvolatile memorizer module.Memory management circuitry is electrically connected to host interface and memory interface.Memory management circuitry, in order to this little entity erased cell is at least grouped into data field and free area, configures multiple logical block to map the entity erased cell of this data field.And the entity erased cell dynamically maintaining the predetermined quantity among this little entity erased cell is to be exclusively used in write sequence data.

In one example of the present invention embodiment, minimum threshold value is added that the value that above-mentioned predetermined quantity obtains reclaims threshold value to set garbage by above-mentioned memory management circuitry.In addition, memory management circuitry receives the write instruction of at least one first logical block of instruction write first data so far among a little logical block and judges whether the first data are alphabetic data or random data from host computer system.If when wherein the first data are alphabetic data, memory management circuitry extracts at least one first instance erased cell from free area, by the first data write so far at least one first instance erased cell, this at least one first instance erased cell is associated to data field, and adjusts garbage according to the number of this at least one first instance erased cell and minimum threshold value and reclaim threshold value.Wherein, when the value that the number that the garbage recovery threshold value before adjusting deducts at least one first instance erased cell obtains is greater than minimum threshold value, the value that the number that the garbage recovery threshold value before the garbage recovery threshold value after adjustment can be set to adjustment deducts at least one first instance erased cell obtains; And when the garbage before adjusting reclaims that value that the threshold value number that deducts at least one first instance erased cell obtains is non-is greater than minimum threshold value, the garbage after adjustment reclaims threshold value can be set minimum threshold value for this reason.

In one example of the present invention embodiment, if when the first data are random data, memory management circuitry extracts at least one second instance erased cell from this free area, by the first data write so far at least one second instance erased cell and this at least one second instance erased cell is associated to data field.

In one example of the present invention embodiment, above-mentioned memory management circuitry judges whether the number of the entity erased cell of free area is not more than garbage and reclaims threshold value.If when the number of the entity erased cell of free area is not more than garbage recovery threshold value, memory management circuitry performs data consolidation procedure so that at least one entity erased cell of data field is associated to free area.

In one example of the present invention embodiment, in execution data consolidation procedure so that at least one entity erased cell of data field is associated in the operation of free area, memory management circuitry selects the 3rd entity erased cell from the entity erased cell of data field, and the 3rd entity erased cell and the 3rd entity erased cell after erasing is associated to free area of erasing.In addition, if when the 3rd entity erased cell has at least one valid data, these at least one valid data were first copied to the 4th entity erased cell data field by memory management circuitry before the 3rd entity erased cell of erasing from the 3rd entity erased cell.

The present invention one exemplary embodiment proposes a kind of memorizer memory devices, and it comprises connecting interface unit, reproducible nonvolatile memorizer module and memorizer control circuit unit.Connecting interface unit is in order to be electrically connected to host computer system.Reproducible nonvolatile memorizer module has multiple entity erased cell.Memorizer control circuit unit is electrically connected to connecting interface unit and reproducible nonvolatile memorizer module.Memorizer control circuit unit, in order to this little entity erased cell is at least grouped into data field and free area, configures multiple logical block to map the entity erased cell of this data field.And the entity erased cell dynamically maintaining the predetermined quantity among this little entity erased cell is to be exclusively used in write sequence data.

In one example of the present invention embodiment, minimum threshold value is added that the value that above-mentioned predetermined quantity obtains reclaims threshold value to set garbage by above-mentioned memorizer control circuit unit.In addition, memorizer control circuit unit receives the write instruction of at least one first logical block of instruction write first data so far among a little logical block and judges whether the first data are alphabetic data or random data from host computer system.If when wherein the first data are alphabetic data, memorizer control circuit unit extracts at least one first instance erased cell from free area, by the first data write so far at least one first instance erased cell, this at least one first instance erased cell is associated to data field, and adjusts garbage according to the number of this at least one first instance erased cell and minimum threshold value and reclaim threshold value.Wherein, when the value that the number that the garbage recovery threshold value before adjusting deducts at least one first instance erased cell obtains is greater than minimum threshold value, the value that the number that the garbage recovery threshold value before the garbage recovery threshold value after adjustment can be set to adjustment deducts at least one first instance erased cell obtains; And when the garbage before adjusting reclaims that value that the threshold value number that deducts at least one first instance erased cell obtains is non-is greater than minimum threshold value, the garbage after adjustment reclaims threshold value can be set minimum threshold value for this reason.

In one example of the present invention embodiment, if when the first data are random data, memorizer control circuit unit extracts at least one second instance erased cell from this free area, by the first data write so far at least one second instance erased cell and this at least one second instance erased cell is associated to data field.

In one example of the present invention embodiment, whether the number of the entity erased cell of above-mentioned memorizer control circuit unit judges free area is not more than garbage is reclaimed threshold value.If when the number of the entity erased cell of free area is not more than garbage recovery threshold value, memorizer control circuit unit performs data consolidation procedure so that at least one entity erased cell of data field is associated to free area.

In one example of the present invention embodiment, in execution data consolidation procedure so that at least one entity erased cell of data field is associated in the operation of free area, memorizer control circuit unit selects the 3rd entity erased cell from the entity erased cell of data field, and the 3rd entity erased cell and the 3rd entity erased cell after erasing is associated to free area of erasing.In addition, if when the 3rd entity erased cell has at least one valid data, these at least one valid data were first copied to the 4th entity erased cell data field by memorizer control circuit unit before the 3rd entity erased cell of erasing from the 3rd entity erased cell.

Based on above-mentioned, method for writing data, memorizer control circuit unit and memorizer memory devices, by dynamically maintaining the entity erased cell being exclusively used in alphabetic data, avoid performing data consolidation procedure to shorten the time writing a large amount of alphabetic data thus.

For above-mentioned feature and advantage of the present invention can be become apparent, special embodiment below, and coordinate accompanying drawing to be described in detail below.

Accompanying drawing explanation

Fig. 1 is host computer system shown by an exemplary embodiment and memorizer memory devices;

Fig. 2 is the schematic diagram of computer, input/output device and memorizer memory devices shown by exemplary embodiment of the present invention;

Fig. 3 is the schematic diagram of host computer system shown by exemplary embodiment of the present invention and memorizer memory devices;

Fig. 4 illustrates the schematic block diagram of the memorizer memory devices shown in Fig. 1;

Fig. 5 is the schematic block diagram of the memorizer control circuit unit shown by an exemplary embodiment;

Fig. 6 and Fig. 7 is the example schematic of the management entity block shown by the first exemplary embodiment;

Fig. 8 ~ 20 are the examples writing random data with random writing mechanism shown by the present invention one exemplary embodiment;

Figure 21 illustrates to perform valid data consolidation procedure to complete the simplification example of follow-up write instruction;

Figure 22 ~ 23 are the examples to be sequentially written in machine-processed write sequence data shown by the present invention one exemplary embodiment;

Figure 24 ~ 27 are another examples writing random data with random writing mechanism shown by the present invention one exemplary embodiment;

Figure 28 is the process flow diagram of the method for writing data shown by the present invention one exemplary embodiment.

Description of reference numerals:

1000: host computer system;

1100: computer;

1102: microprocessor;

1104: random access memory;

1106: input/output device;

1108: system bus;

1110: data transmission interface;

1202: mouse;

1204: keyboard;

1206: display;

1208: printer;

1212: portable hard drive;

1214: storage card;

1216: solid state hard disc;

1310: digital camera;

1312:SD card;

1314:MMC card;

1316: memory stick;

1318:CF card;

1320: embedded storage device;

100: memorizer memory devices;

102: connecting interface unit;

104: memorizer control circuit unit;

106: reproducible nonvolatile memorizer module;

202: memory management circuitry;

204: host interface;

206: memory interface;

208: memory buffer;

210: electric power management circuit;

212: bug check and correcting circuit;

410 (0) ~ 410 (N): entity erased cell;

502: system region;

504: data field;

506: free area;

508: replace district;

LBA (0) ~ LBA (H): logical block;

LZ (0) ~ LZ (M): logic region;

SD1 ~ SD6: alphabetic data;

RD1 ~ RD16: random data;

S2801, S2803, S2805, S2807, S2809, S2811, S2813: the step of method for writing data.

Embodiment

Reproducible nonvolatile memorizer module entity erased cell can be at least grouped into data field and free area by the method for writing data that the present invention proposes, configure multiple logical block with the entity erased cell in mapping (enum) data district, and with the entity erased cell dynamically maintaining the predetermined quantity in reproducible nonvolatile memorizer module to be exclusively used in write sequence data.Particularly, the number of the entity erased cell in above-mentioned data field can be lowered and make the spendable memorizer memory devices capacity of user (namely, logical address or unit) reduce, and reduced capacity be retained as be exclusively used in write sequence data, make thus by the duplicative non-volatile memory device of random writing structure (memory management architecture also referred to as based on the page) can effectively shorten by host computer system a large amount of alphabetic datas of storing of wish write to time of reproducible nonvolatile memorizer module.In order to be well understood to the present invention, below will be described with exemplary embodiment.

Generally speaking, memorizer memory devices (also claiming, memory storage system) comprises reproducible nonvolatile memorizer module and controller (also claiming, control circuit).Usual memorizer memory devices uses together with host computer system, data can be write to memorizer memory devices or read data from memorizer memory devices to make host computer system.

Fig. 1 is host computer system shown by an exemplary embodiment and memorizer memory devices.

Please refer to Fig. 1, host computer system 1000 generally comprises computer 1100 and I/O (input/output is called for short I/O) device 1106.Computer 1100 comprises microprocessor 1102, random access memory (random access memory is called for short RAM) 1104, system bus 1108 and data transmission interface 1110.Input/output device 1106 comprises as the mouse 1202 of Fig. 2, keyboard 1204, display 1206 and printer 1208.It must be appreciated, the unrestricted input/output device 1106 of the device shown in Fig. 2, input/output device 1106 can also comprise other devices.

In embodiments of the present invention, memorizer memory devices 100 is electrically connected by data transmission interface 1110 other elements with host computer system 1000.Data can be write to memorizer memory devices 100 by microprocessor 1102, random access memory 1104 with the operation of input/output device 1106 or read data from memorizer memory devices 100.Such as, memorizer memory devices 100 can be the type nonvolatile storage device of portable hard drive 1212, storage card 1214 or solid state hard disc (Solid State Drive is called for short SSD) 1216 grades as shown in Figure 2.

Generally speaking, host computer system 1000 is to coordinate any system with storage data substantially with memorizer memory devices 100.Although in this exemplary embodiment, host computer system 1000 explains with computer system, but host computer system 1000 can be the systems such as digital camera, video camera, communicator, audio player or video player in another exemplary embodiment of the present invention.Such as, when host computer system is digital camera (video camera) 1310, type nonvolatile storage device is then its SD card 1312 used, mmc card 1314, memory stick (memory stick) 1316, CF card 1318 or embedded storage device 1320 (as shown in Figure 3).Embedded storage device 1320 comprises embedded multi-media card (Embedded MMC is called for short eMMC).It is worth mentioning that, embedded multi-media card is directly electrically connected on the substrate of host computer system.

Fig. 4 illustrates the schematic block diagram of the memorizer memory devices shown in Fig. 1.

Please refer to Fig. 4, memorizer memory devices 100 comprises connecting interface unit 102, memorizer control circuit unit 104 and reproducible nonvolatile memorizer module 106.

In this exemplary embodiment, connecting interface unit 102 is compatible to advanced annex (Serial Advanced Technology Attachment, the abbreviate SAT A) standard of sequence.But, it must be appreciated, the present invention is not limited thereto, connecting interface unit 102 also can be meet advanced annex arranged side by side (Parellel Advanced Technology Attachment, be called for short PATA) standard, Institute of Electrical and Electric Engineers (Institute of Electrical and Electronic Engineers, be called for short IEEE) 1394 standards, high-speed peripheral component connecting interface (Peripheral Component Interconnect Express, be called for short PCIExpress) standard, universal serial bus (Universal Serial Bus, be called for short USB) standard, a hypervelocity generation (Ultra High Speed-I, be called for short UHS-I) interface standard, hypervelocity two generation (Ultra High Speed-II, be called for short UHS-II) interface standard, secure digital (Secure Digital, be called for short SD) interface standard, memory stick (Memory Stick, be called for short MS) interface standard, Multi Media Card (Multi Media Card, be called for short MMC) interface standard, small-sized (Compact Flash fast, be called for short CF) interface standard, integrated driving electrical interface (Integrated Device Electronics, be called for short IDE) standard or other be applicable to standard.In this exemplary embodiment, connecting interface unit can with memorizer control circuit unit package in a chip, or is laid in one and comprises outside the chip of memorizer control circuit unit.

Memorizer control circuit unit 104 in order to perform in the form of hardware or multiple logic gate that form of firmware realizes or steering order, and according to the instruction of host computer system 1000 carry out in reproducible nonvolatile memorizer module 106 data write, read and the operation such as to erase.

Reproducible nonvolatile memorizer module 106 is electrically connected to memorizer control circuit unit 104, and in order to store the data that host computer system 1000 writes.Reproducible nonvolatile memorizer module 106 has entity erased cell 410 (0) ~ 410 (N).Such as, entity erased cell 410 (0) ~ 410 (N) can belong to same memory crystal grain (die) or belong to different memory crystal grain.Each entity erased cell has a plurality of entity program unit respectively, and the entity program unit wherein belonging to same entity erased cell can be written independently and side by side be erased.But it must be appreciated, the present invention is not limited thereto, each entity erased cell can be made up of 64 entity program unit, 256 entity program unit or other any entity program unit.

In more detail, entity erased cell is the least unit of erasing.Also namely, each entity erased cell contain minimal amount in the lump by the memory cell of erasing.Entity program unit is the minimum unit of sequencing.That is, entity program unit is the minimum unit of write data.Each entity program unit generally includes data bit district and redundancy ratio special zone.Data bit district comprises multiple entity access address in order to store the data of user, and redundancy ratio special zone is in order to the data (such as, control information and error correcting code) of stocking system.In this exemplary embodiment, 4 entity access addresses in the data bit district of each entity program unit, can be comprised, and the size of an entity access address is 512 bytes (byte).But in other exemplary embodiment, can comprise the more or less entity access address of number in data bit district, the present invention does not limit size and the number of entity access address yet.Such as, in an exemplary embodiment, entity erased cell is physical blocks, and entity program unit is physical page or entity sector, but the present invention is not as limit.

In this exemplary embodiment, reproducible nonvolatile memorizer module 106 is multistage memory cell (Multi Level Cell, be called for short MLC) NAND flash memory module (that is, the flash memory module of 2 Bit datas can be stored in a memory cell).But, the present invention is not limited thereto, reproducible nonvolatile memorizer module 106 may also be single-order memory cell (Single Level Cell, being called for short SLC) NAND flash memory module is (namely, the flash memory module of 1 Bit data can be stored in a memory cell), Complex Order memory cell (Trinary Level Cell, be called for short TLC) NAND flash memory module (that is, the flash memory module of 3 Bit datas can be stored in a memory cell), other flash memory module or other there is the memory module of identical characteristics.

Fig. 5 is the schematic block diagram of the memorizer control circuit unit shown by an exemplary embodiment.

Please refer to Fig. 5, memorizer control circuit unit 104 comprises memory management circuitry 202, host interface 204 and memory interface 206.

Memory management circuitry 202 is in order to the integrated operation of control store control circuit unit 104.Specifically, memory management circuitry 202 has multiple steering order, and when memorizer memory devices 100 operates, this little steering order can be performed to carry out data write, read and the operation such as to erase.

In this exemplary embodiment, the steering order of memory management circuitry 202 realizes with form of firmware.Such as, memory management circuitry 202 has microprocessor unit (not shown) and ROM (read-only memory) (not shown), and this little steering order is burned onto in this ROM (read-only memory).When memorizer memory devices 100 operates, this little steering order can by microprocessor unit perform to carry out data write, read and the operation such as to erase.

In another exemplary embodiment of the present invention, the steering order of memory management circuitry 202 also can procedure code pattern be stored in the specific region (such as, being exclusively used in the system region of storage system data in memory module) of reproducible nonvolatile memorizer module 106.In addition, memory management circuitry 202 has microprocessor unit (not shown), ROM (read-only memory) (not shown) and random access memory (not shown).Particularly, this ROM (read-only memory) has driving code, and when memorizer control circuit unit 104 is by driving, microprocessor unit first can perform this and drive code section the steering order be stored in reproducible nonvolatile memorizer module 106 to be loaded in the random access memory of memory management circuitry 202.Afterwards, microprocessor unit can run this little steering order with carry out data write, read and the operation such as to erase.

In addition, in another exemplary embodiment of the present invention, the steering order of memory management circuitry 202 also can an example, in hardware realize.Such as, memory management circuitry 202 comprises microcontroller, memory cell management circuit, storer write circuit, memory reading circuitry, storer erase circuit and data processing circuit.Erase circuit and data processing circuit of memory cell management circuit, storer write circuit, memory reading circuitry, storer is electrically connected to microcontroller.Wherein, memory cell management circuit is in order to manage the entity erased cell of reproducible nonvolatile memorizer module 106; Storer write circuit is in order to assign write instruction data to be write in reproducible nonvolatile memorizer module 106 to reproducible nonvolatile memorizer module 106; Memory reading circuitry is in order to assign reading command to read data from reproducible nonvolatile memorizer module 106 to reproducible nonvolatile memorizer module 106; Storer erases circuit in order to assign instruction of erasing to reproducible nonvolatile memorizer module 106 data to be erased from reproducible nonvolatile memorizer module 106; And data processing circuit is in order to the data processed for writing to reproducible nonvolatile memorizer module 106 and the data read from reproducible nonvolatile memorizer module 106.

Host interface 204 is electrically connected to memory management circuitry 202 and in order to receive and to identify the instruction that transmits of host computer system 1000 and data.That is, the instruction that transmits of host computer system 1000 and data can be sent to memory management circuitry 202 by host interface 204.In this exemplary embodiment, host interface 204 is compatible to SATA standard.But, it must be appreciated and the present invention is not limited thereto, host interface 204 also can be compatible to PATA standard, IEEE1394 standard, PCI Express standard, USB standard, UHS-I interface standard, UHS-II interface standard, SD standard, MS standard, MMC standard, CF standard, IDE standard or other data transmission standards be applicable to.

Memory interface 206 is electrically connected to memory management circuitry 202 and in order to access reproducible nonvolatile memorizer module 106.That is, the data for writing to reproducible nonvolatile memorizer module 106 can be converted to the receptible form of reproducible nonvolatile memorizer module 106 via memory interface 206.

In the present invention one exemplary embodiment, memorizer control circuit unit 104 also comprises memory buffer 208, electric power management circuit 210 and bug check and correcting circuit 212.

Memory buffer 208 is electrically connected to memory management circuitry 202 and comes from the data and instruction of host computer system 1000 in order to temporary or come from the data of reproducible nonvolatile memorizer module 106.

Electric power management circuit 210 is electrically connected to memory management circuitry 202 and in order to the power supply of control store storage device 100.

Bug check and correcting circuit 212 are electrically connected to memory management circuitry 202 and in order to execution error inspection and correction program to guarantee the correctness of data.Specifically, when memory management circuitry 202 receives write instruction from host computer system 1000, bug check and correcting circuit 212 can be that the corresponding data that this writes instruction produce corresponding bug check and correcting code (Error Checking and Correcting Code, be called for short ECC Code), and the data of this write instruction corresponding can write in reproducible nonvolatile memorizer module 106 with corresponding bug check and correcting code by memory management circuitry 202.Afterwards, can read bug check corresponding to these data and correcting code when memory management circuitry 202 reads data from reproducible nonvolatile memorizer module 106, and bug check and correcting circuit 212 can according to this bug check and correcting code to read data execution error inspection and correction programs simultaneously.

Fig. 6 and Fig. 7 is the example schematic of the management entity block shown by the first exemplary embodiment.

Please refer to Fig. 6, entity erased cell 410 (0) ~ 410-(N) logically can be grouped into data field 504, free area 506, system region 502 and replace district 508 by memorizer control circuit unit 104 (or memory management circuitry 202).

Belonging to data field 504 in logic with the entity erased cell of free area 506 is in order to store the data coming from host computer system 1000.Specifically, the entity erased cell of data field 504 is the entity erased cell being regarded as storage data, and the entity erased cell of free area 506 is the entity erased cell in order to replacement data district 504.That is, when receiving the data that write instruction writes with wish from host computer system 1000, memory management circuitry 202 can extract entity erased cell from free area 506, and data is write in extracted entity erased cell, with the entity erased cell in replacement data district 504.

The entity erased cell belonging to system region 502 is in logic in order to register system data.Such as, system data comprises manufacturer about reproducible nonvolatile memorizer module and model, the entity erased cell number of reproducible nonvolatile memorizer module, the entity program unit number etc. of each entity erased cell.

Belonging to the entity erased cell replaced in district 508 is in logic replace program, with replacing damaged entity erased cell for damaging entity erased cell.Specifically, if replace in district 508 still have normal entity erased cell and data field 504 entity erased cell damages time, memory management circuitry 202 can extract normal entity erased cell to change the entity erased cell of damage from replacement district 508.

Particularly, data field 504, free area 506, system region 502 can be different according to different storer specifications from the quantity of entity erased cell replacing district 508.In addition, it must be appreciated, in the operation of memorizer memory devices 100, entity erased cell is associated to data field 504, free area 506, system region 502 can dynamically change with the grouping relation replacing district 508.Such as, when the entity erased cell in free area 506 damages and is substituted the entity erased cell replacement in district 508, then the entity erased cell originally replacing district 508 can be associated to free area 506.

Please refer to Fig. 7, memorizer control circuit unit 104 (or memory management circuitry 202) meeting configuration logic unit LBA (0) ~ LBA (H) is with the entity erased cell in mapping (enum) data district 504, and wherein each logical block has the entity program unit of the entity erased cell that multiple logical page (LPAGE) is answered with mapping pair.And, when host computer system 1000 to be stored in the data in logical block for write data to logical block or renewal, memorizer control circuit unit 104 (or memory management circuitry 202) can extract an entity erased cell and write data, with the entity erased cell in replacement data district 504 from free area 506.

Which entity erased cell is data in order to each logical block of identification data be stored in, in this exemplary embodiment, memorizer control circuit unit 104(or memory management circuitry 202) mapping between logical block and entity erased cell can be recorded.And, when host computer system 1000 is in logical page (LPAGE) during access data, memorizer control circuit unit 104 (or memory management circuitry 202) can confirm the logical block belonging to this logical page (LPAGE), and carrys out access data in the entity erased cell mapped in this logical block.Such as, in this exemplary embodiment, memorizer control circuit unit 104 (or memory management circuitry 202) stored logic can turn the entity erased cell that physical address mapping table maps to record each logical block in reproducible nonvolatile memorizer module 106, and logic is turned physical address mapping table and be loaded into memory buffer 208 when for memorizer control circuit unit 104 (or memory management circuitry 202) during access data and safeguard.

It is worth mentioning that, because the finite capacity of memory buffer 208 cannot the mapping table of mapping relations of all logical blocks of store recording, therefore, in this exemplary embodiment, memorizer control circuit unit 104(or memory management circuitry 202) logical block LBA (0) ~ LBA (H) can be grouped into multiple logic region LZ (0) ~ LZ (M), and turn physical address mapping table for each logic region configures a logic.Particularly, when memorizer control circuit unit 104 (or memory management circuitry 202) is for upgrading the mapping of certain logical block, the logic of corresponding logic region belonging to this logical block turns physical address mapping table and can be loaded on memory buffer 208 and be updated.

As mentioned above, in this exemplary embodiment, the reproducible nonvolatile memorizer module 106 of memorizer memory devices 100 manages based on the page, therefore, when performing write instruction, no matter current data are the logical page (LPAGE)s that will write to that logical block, memorizer control circuit unit 104(or memory management circuitry 202) all can connect the mode of an entity program unit to write data (hereinafter also referred to random writing mechanism) with an entity program unit.Specifically, memorizer control circuit unit 104(or memory management circuitry 202) an empty entity erased cell can be extracted from free area 506 and write data as the entity erased cell used at present.And, when the entity erased cell that this uses at present is fully written, memorizer control circuit unit 104 (or memory management circuitry 202) can extract the entity erased cell of another sky again as the entity erased cell used at present from free area 506, to continue to write the corresponding random data coming from the write instruction of host computer system 1000.Particularly, in order to avoid the entity erased cell of free area 506 is depleted, when the number of the entity erased cell of free area 506 drops to set garbage recovery threshold value, memorizer control circuit unit 104 (or memory management circuitry 202) can perform data consolidation procedure, to make the data at least one entity erased cell of data field 504 become invalid data, and the entity erased cell being all invalid data by data stored in data field 504 afterwards associates go back to free area 506.Such as, when performing data consolidation procedure, the entity erased cell that memorizer control circuit unit 104 (or memory management circuitry 202) at least needs use one empty, therefore, garbage recovery threshold value is set to I haven't seen you for ages and is greater than minimum threshold value (that is, 1).Particularly, in this exemplary embodiment, memorizer control circuit unit 104 (or memory management circuitry 202) can identify that the data of write are alphabetic data or random data, and carrys out dynamic conditioning garbage recovery threshold value according to the amount of write alphabetic data.Specifically, the behavior that host computer system 1000 writes data can be divided into the pattern of being sequentially written in (Sequential writing mode) and random writing pattern (random writing mode).Be sequentially written in pattern, host computer system 1000 can write many data in order in the multiple logical page (LPAGE) of continuous print.And in random writing pattern, host computer system 1000 writes data in discrete logical page (LPAGE), such as, first the first stroke random data is written into the 5th logical page (LPAGE), then second random data is write to the 3rd logical page (LPAGE).At this, host computer system 1000 is called alphabetic data with the data being sequentially written in pattern write, and the data that host computer system 1000 writes with random writing pattern are called random data.Particularly, as mentioned above, in this exemplary embodiment, the entity erased cell of the predetermined quantity in reproducible nonvolatile memorizer module can be maintained to be exclusively used in write sequence data, therefore, memorizer control circuit unit 104 (or memory management circuitry 202) can carry out dynamic conditioning garbage according to the amount of write alphabetic data and reclaim threshold value, is used to write random data to avoid the entity erased cell being preserved for write sequence data.

Fig. 8 ~ 20 are the examples writing random data with random writing mechanism shown by the present invention one exemplary embodiment.

Please refer to Fig. 8, for convenience of description, the entity erased cell of mapping logic unit is not initially had (namely in this tentation data district 504, memorizer memory devices 100 not yet write user's data after opening card), free area 506 has 8 entity erased cell, each entity erased cell has 3 entity program unit, must be written into for the data writing to each entity erased cell according to the order of entity program unit.In addition suppose that 3 entity erased cell can be retained and be exclusively used in write sequence data, 1 entity erased cell can be used as the use of replacing write data and 1 entity erased cell can be retained to carry out data consolidation procedure, therefore, garbage reclaims threshold value and initially can be set to 4 and the capacity that logical block maps can be set to the capacity of 3 entity erased cell.That is, for the memorizer memory devices 100 with 8 entity erased cell, be supplied to the capacity that capacity that host computer system 1000 accesses can be set to 6 entity erased cell originally, but after reservation is exclusively used in the entity erased cell of write sequence data, the capacity of 3 entity erased cell only can be provided to access to host computer system 1000, namely, the capacity of host computer system 1000 meeting recognition memory storage device 100 is the capacity (that is, logical block LBA (0) ~ LBA (2)) of 3 entity erased cell.It is worth mentioning that, although in this example, the number being retained the entity erased cell being exclusively used in write sequence data is identical with the capacity of configured logical block, but the present invention is not limited thereto, the number being retained the entity erased cell being exclusively used in write sequence data also can be less than the capacity of configured logical block.

Please refer to Fig. 9, when to suppose for sequencing random data RD1 and random data RD1 be the 1st logical page (LPAGE) belonging to logical block LBA (0), memorizer control circuit unit 104 (or memory management circuitry 202) can extract entity erased cell 410 (0) from free area 506, assigns programmed instructions this random data RD1 is write to the 0th entity program unit of entity erased cell 410 (0) and entity erased cell 410 (0) is associated to data field 504.

Please refer to Figure 10, hookup 9, when to suppose for reprogramming random data RD2 and random data RD2 be the 0th logical page (LPAGE) belonging to logical block LBA (1), memorizer control circuit unit 104 (or memory management circuitry 202) can assign programmed instructions this random data RD2 to be write to the 1st entity program unit of entity erased cell 410 (0).

Please refer to Figure 11, continue Figure 10, when to suppose for reprogramming random data RD3 and random data RD3 be the 1st logical page (LPAGE) belonging to logical block LBA (2), memorizer control circuit unit 104 (or memory management circuitry 202) can assign programmed instructions this random data RD3 to be write to the 2nd entity program unit of entity erased cell 410 (0).

Please refer to Figure 12, continue Figure 11, when to suppose for reprogramming random data RD4 and random data RD4 be the 0th logical page (LPAGE) belonging to logical block LBA (0), because entity erased cell 410 (0) is without storage area, therefore, memorizer control circuit unit 104 (or memory management circuitry 202) can extract entity erased cell 410 (1) from free area 506, assign programmed instructions this random data RD4 is write to the 0th entity program unit of entity erased cell 410 (1) and entity erased cell 410 (1) is associated to data field 504.

Please refer to Figure 13, continue Figure 12, when to suppose for reprogramming random data RD5 and random data RD5 be the 1st logical page (LPAGE) belonging to logical block LBA (1), memorizer control circuit unit 104 (or memory management circuitry 202) can assign programmed instructions this random data RD5 to be write to the 1st entity program unit of entity erased cell 410 (1).

Please refer to Figure 14, continue Figure 13, when to suppose for reprogramming random data RD6 and random data RD6 be the 2nd logical page (LPAGE) belonging to logical block LBA (0), memorizer control circuit unit 104 (or memory management circuitry 202) can assign programmed instructions this random data RD6 to be write to the 2nd entity program unit of entity erased cell 410 (1).

Please refer to Figure 15, continue Figure 14, when to suppose for reprogramming random data RD7 and random data RD4 be the 0th logical page (LPAGE) belonging to logical block LBA (2), because entity erased cell 410 (1) is without storage area, therefore, memorizer control circuit unit 104 (or memory management circuitry 202) can extract entity erased cell 410 (2) from free area 506, assign programmed instructions this random data RD7 is write to the 0th entity program unit of entity erased cell 410 (2) and entity erased cell 410 (2) is associated to data field 504.

Please refer to Figure 16, continue Figure 15, when to suppose for reprogramming random data RD8 and random data RD8 be the 2nd logical page (LPAGE) belonging to logical block LBA (1), memorizer control circuit unit 104 (or memory management circuitry 202) can assign programmed instructions this random data RD8 to be write to the 1st entity program unit of entity erased cell 410 (2).

Please refer to Figure 17, continue Figure 16, when to suppose for reprogramming random data RD9 and random data RD9 be the 2nd logical page (LPAGE) belonging to logical block LBA (2), memorizer control circuit unit 104 (or memory management circuitry 202) can assign programmed instructions this random data RD9 to be write to the 2nd entity program unit of entity erased cell 410 (2).

Please refer to Figure 18, continue Figure 17, when to suppose for reprogramming random data RD10 and random data RD10 be the 2nd logical page (LPAGE) belonging to logical block LBA (1), because entity erased cell 410 (2) is without storage area, therefore, memorizer control circuit unit 104 (or memory management circuitry 202) can extract entity erased cell 410 (3) from free area 506, assign programmed instructions this random data RD10 is write to the 0th entity program unit of entity erased cell 410 (3) and entity erased cell 410 (3) is associated to data field 504, wherein the 1st entity program unit of entity erased cell 410 (2) can be marked as invalid (shown in dotted line).

Please refer to Figure 19, continue Figure 18, when to suppose for reprogramming random data RD11 and random data RD11 be the 2nd logical page (LPAGE) belonging to logical block LBA (2), memorizer control circuit unit 104 (or memory management circuitry 202) can assign programmed instructions this random data RD11 to be write to the 1st entity program unit of entity erased cell 410 (3), and wherein the 2nd entity program unit of entity erased cell 410 (2) can be marked as invalid (shown in dotted line).

Please refer to Figure 20, continue Figure 19, when to suppose for reprogramming random data RD12 and random data RD12 be the 1st logical page (LPAGE) belonging to logical block LBA (1), memorizer control circuit unit 104 (or memory management circuitry 202) can assign programmed instructions this random data RD12 to be write to the 2nd entity program unit of entity erased cell 410 (3), and wherein the 1st entity program unit of entity erased cell 410 (1) can be marked as invalid (shown in dotted line).

By that analogy, though host computer system 1000 for by data storing in the logical page (LPAGE) of which logical block, in the entity erased cell that host computer system 1000 can use at present for the data write stored by memorizer control circuit unit 104 (or memory management circuitry 202) in order.Particularly, when the number of the entity erased cell of free area 506 is not more than garbage recovery threshold value, memorizer control circuit unit 104 (or memory management circuitry 202) can perform data consolidation procedure in the lump when performing write instruction, is exhausted to prevent the entity erased cell of free area.

Figure 21 illustrates to perform valid data consolidation procedure to complete the simplification example of follow-up write instruction.

Please refer to Figure 21, continue Figure 20, when to suppose for reprogramming random data RD13 and random data RD13 be the 0th logical page (LPAGE) belonging to logical block LBA (2), because entity erased cell 410 (3) is without storage area, therefore, memorizer control circuit unit 104 (or memory management circuitry 202) needs from free area 506, extract empty entity erased cell.But now, the number of the entity erased cell of free area 506 is not more than garbage to reclaim threshold value, and therefore, memorizer control circuit unit 104 (or memory management circuitry 202) must first perform data consolidation procedure.Such as, memorizer control circuit unit 104 (or memory management circuitry 202) extracts entity erased cell 410 (4) from free area 506, by the valid data in entity erased cell 410 (1) (namely, data RD4 and RD6) and entity erased cell 410 (2) in valid data (namely, data RD7) copy to entity erased cell 410 (4), entity erased cell 410 (4) is associated to data field 504, it is invalid 0th and 2 entity program unit of entity erased cell 410 (1) and the 0th entity program unit of entity erased cell 410 (2) to be labeled as, to only storing the entity erased cell of invalid data (namely, entity erased cell 410 (1) and entity erased cell 410 (2)) perform erase operation for use, and the entity erased cell after erasing is associated go back to free area 506.

Now, it was 5 (are greater than garbage and reclaim threshold value) that the number of the entity erased cell of free area 506 can be replied, base this, memorizer control circuit unit 104 (or memory management circuitry 202) can extract entity erased cell 410 (5) from free area 506, assign programmed instructions this random data RD13 is write to the 0th entity program unit of entity erased cell 410 (5) and entity erased cell 410 (5) is associated to data field 504, wherein the entity program unit of storage data RD7 (namely, 2nd entity program unit of entity erased cell 410 (4)) can be marked as invalid.

Figure 22 ~ 23 are the examples to be sequentially written in machine-processed write sequence data shown by the present invention one exemplary embodiment.

Please refer to Figure 22, continue Figure 21, when to suppose for reprogramming alphabetic data SD1 ~ SD6 and alphabetic data SD1 ~ SD6 be 0th ~ 2 logical page (LPAGE)s belonging to 0th ~ 2 logical page (LPAGE)s of logical block LBA (1) and logical block LBA (2), write sequence data are exclusively used in owing to remaining with 3 entity erased cell in free area 506, therefore, memorizer control circuit unit 104 (or memory management circuitry 202) can extract empty entity erased cell (such as from free area 506, entity erased cell 410 (6) and 410 (7)), assign programmed instructions sequentially to be write to by this alphabetic data SD1 ~ SD6 in entity erased cell 410 (6) and 410 (7) and entity erased cell 410 (6) is associated to data field 504 with 410 (7).In addition, memorizer control circuit unit 104 (or memory management circuitry 202) the 0th entity program unit of the 1st and 2 entity program unit of entity erased cell 410 (0), 0th ~ 2 entity program unit of entity erased cell 410 (3) and entity erased cell 410 (5) can be labeled as invalid.

Please refer to Figure 23, because entity erased cell 410 (3) only stores invalid data, therefore, memorizer control circuit unit 104 (or memory management circuitry 202) can perform erase operation for use to entity erased cell 410 (3) and be associated go back to free area.In addition, retain the entity erased cell being exclusively used in write sequence data and used, therefore, memorizer control circuit unit 104 (or memory management circuitry 202) can adjust garbage accordingly and reclaim threshold value.Specifically, current garbage can be reclaimed threshold value and deduct and perform the number that the entity erased cell being used for write sequence data is extracted in this time write instruction from free area 506 by memorizer control circuit unit 104 (or memory management circuitry 202), and judges that current garbage reclaims threshold value and deducts to perform and this time write the number that instruction extracts for the entity erased cell of write sequence data from free area 506 and whether be not more than minimum threshold value.If current garbage reclaims threshold value and deducts and perform this time write instruction when extracting from free area 506 that number for the entity erased cell of write sequence data is non-is less than minimum threshold value, memorizer control circuit unit 104 (or memory management circuitry 202) can reclaim threshold value using current garbage and deduct and perform the number that this time write instruction extracts for the entity erased cell of write sequence data from free area 506 and reclaim threshold value as new garbage.And if current garbage reclaims threshold value and deducts and perform this time write instruction number extracted from free area 506 for the entity erased cell of write sequence data when being less than minimum threshold value, then memorizer control circuit unit 104 (or memory management circuitry 202) can reclaim threshold value using minimum threshold value as new garbage.In the example of Figure 22 and Figure 23, new garbage reclaims threshold value can be set to 2.

In the example of Figure 22 and Figure 23, although the alphabetic data that host computer system 1000 indicates write-once a large amount of, but, because memorizer control circuit unit 104 (or memory management circuitry 202) carrys out vacating space without the need to performing data consolidation procedure, therefore, the time performing write instruction can effectively be shortened.

Figure 24 ~ 27 are another examples writing random data with random writing mechanism shown by the present invention one exemplary embodiment.

Please refer to Figure 24, continue Figure 23, when to suppose for reprogramming random data RD14 and random data RD14 be the 0th logical page (LPAGE) belonging to logical block LBA (1), memorizer control circuit unit 104 (or memory management circuitry 202) can assign programmed instructions this random data RD14 to be write to the 1st entity program unit of entity erased cell 410 (5), and it is invalid that the 0th entity program unit of the entity erased cell 410 (6) of wherein the 0th the former mapping of logical page (LPAGE) of logical block LBA (1) can be marked as.

Please refer to Figure 25, continue Figure 24, when to suppose for reprogramming random data RD15 and random data RD15 be the 2nd logical page (LPAGE) belonging to logical block LBA (1), memorizer control circuit unit 104 (or memory management circuitry 202) can assign programmed instructions this random data RD15 to be write to the 2nd entity program unit of entity erased cell 410 (5), and it is invalid that the 2nd entity program unit of the entity erased cell 410 (6) of wherein the 2nd the former mapping of logical page (LPAGE) of logical block LBA (1) can be marked as.

Please refer to Figure 26, continue Figure 25, when to suppose for reprogramming random data RD16 and random data RD16 be the 1st logical page (LPAGE) belonging to logical block LBA (1), due to entity erased cell 410 (5) without storage area and the number of the entity erased cell of free area 506 be greater than garbage reclaim threshold value, therefore, memorizer control circuit unit 104 (or memory management circuitry 202) directly can extract the 0th the entity program unit that this random data RD16 is write to entity erased cell 410 (1) by entity erased cell 410 (1) from free area 506, and without the need to performing data consolidation procedure.In this example, entity erased cell 410 (1) can be associated to data field 504 again.

Because entity erased cell 410 (6) only stores invalid data, therefore, memorizer control circuit unit 104 (or memory management circuitry 202) only can store invalid data, therefore, memorizer control circuit unit 104 (or memory management circuitry 202) can perform erase operation for use to entity erased cell 410 (6) and be associated go back to free area (see Figure 27).Particularly, because entity erased cell 410 (6) is be extracted with alphabetic data before, therefore, current garbage can be reclaimed threshold value and add 1 (that is, 3) as new garbage recovery threshold value by memorizer control circuit unit 104 (or memory management circuitry 202).

From the example of Fig. 8 ~ 27, can be well understood to, the memorizer control circuit unit 104 (or memory management circuitry 202) of this exemplary embodiment can reclaim threshold value by adjustment garbage and be exclusively used in write sequence data with the entity erased cell dynamically maintaining the predetermined quantity in reproducible nonvolatile memorizer module 106, to make the memorizer memory devices 100 carrying out managing based on the page, the writing speed of alphabetic data effectively can be promoted.

Please refer to Figure 28, in step S2801, the entity erased cell of reproducible nonvolatile memorizer module 106 is at least grouped into data field and free area by memorizer control circuit unit 104 (or memory management circuitry 202), configures multiple logical block and adds that with the entity erased cell in mapping (enum) data district 504 and by default minimum threshold value the value that predetermined quantity obtains reclaims threshold value to set garbage.As mentioned above, minimum threshold value is for performing the number of the entity erased cell needed for data union operations and to get predetermined quantity be for retaining the number being exclusively used in the entity erased cell of alphabetic data.At this, minimum threshold value and predetermined quantity can according to the demands of user, and suitable setting, is not limited to any number.

In step S2803, memorizer control circuit unit 104 (or memory management circuitry 202) receives write instruction from host computer system 1000, and wherein this write instruction instruction write data (hereinafter referred to as the first data) is at least one logical block (hereinafter referred to as the first logical block).

In step S2805, memorizer control circuit unit 104 (or memory management circuitry 202) can judge whether the number of the entity erased cell of free area 506 is not more than garbage and reclaims threshold value.

If when the number of the entity erased cell of free area 506 is not more than garbage recovery threshold value, in step S2807, memorizer control circuit unit 104 (or memory management circuitry 202) performs a data consolidation procedure so that at least one entity erased cell of data field 504 is associated to free area 506.Such as, memorizer control circuit unit 104 (or memory management circuitry 202) selects an entity erased cell (hereinafter referred to as the 3rd entity erased cell) from the entity erased cell of this data field, if and when the 3rd entity erased cell has at least one valid data, these at least one valid data are copied to another entity erased cell (hereinafter referred to as the 4th entity erased cell) data field 504 from the 3rd entity erased cell, the 3rd entity erased cell and the 3rd entity erased cell after erasing is associated to free area 506 of erasing.The detailed executive mode of data consolidation procedure has coordinated graphic description as above, is not repeated.

Afterwards, in step S2809, memorizer control circuit unit 104 (or memory management circuitry 202) judges that the first data belong to alphabetic data or random data.

If when these first data are alphabetic data, in step S2811, memorizer control circuit unit 104 (or memory management circuitry 202) can extract at least one entity erased cell (hereinafter referred to as first instance erased cell) from free area 506, by the first data write so far at least one first instance erased cell, this at least one first instance erased cell is associated to data field 504, adjusts garbage according to the number of this at least one first instance erased cell and minimum threshold value and reclaim threshold value.At this, when the value that the number that the garbage recovery threshold value before adjusting deducts this at least one first instance erased cell obtains is greater than minimum threshold value, the value that the number that the garbage recovery threshold value before this garbage recovery threshold value after adjustment can be set to adjustment deducts this at least one first instance erased cell obtains; And when the garbage before adjusting reclaims that value that the threshold value number that deducts this at least one first instance erased cell obtains is non-is greater than minimum threshold value, the garbage after adjustment reclaims threshold value can be set minimum threshold value for this reason.

If when the first data are random data, in step S2813, memorizer control circuit unit 104 (or memory management circuitry 202) can extract at least one entity erased cell (hereinafter referred to as at least one second instance erased cell) from the entity erased cell of free area 506, by the first data write so far at least one second instance erased cell and this at least one second instance erased cell is associated to data field 504.

Based on above-mentioned, the method for writing data of this exemplary embodiment, memorizer control circuit unit and memorizer memory devices can while effectively with random writing mechanism sequencing random data, also can write efficiently for a large amount of alphabetic data, shorten the time of the write instruction performing a large amount of alphabetic data of request write thus and avoid Missing data.

Last it is noted that above each embodiment is only in order to illustrate technical scheme of the present invention, be not intended to limit; Although with reference to foregoing embodiments to invention has been detailed description, those of ordinary skill in the art is to be understood that: it still can be modified to the technical scheme described in foregoing embodiments, or carries out equivalent replacement to wherein some or all of technical characteristic; And these amendments or replacement, do not make the essence of appropriate technical solution depart from the scope of various embodiments of the present invention technical scheme.

Claims

1. a method for writing data, for a reproducible nonvolatile memorizer module, is characterized in that, this reproducible nonvolatile memorizer module comprises multiple entity erased cell, and this method for writing data comprises:

Those entity erased cell are at least grouped into a data field and a free area;

Configure multiple logical block to map the entity erased cell of this data field; And

Dynamically maintain the entity erased cell of the predetermined quantity among those entity erased cell to be exclusively used in write one alphabetic data.

2. method for writing data according to claim 1, is characterized in that, the entity erased cell dynamically maintaining this predetermined quantity among those entity erased cell is exclusively used in the step writing this alphabetic data and comprises:

One minimum threshold value is added the value that this predetermined quantity obtains sets a garbage recovery threshold value;

A write instruction is received, at least one first logical block wherein among this write instruction instruction write one first data to those logical blocks from a host computer system;

Judge whether these first data are an alphabetic data or a random data; And

If when these first data are this alphabetic data, at least one first instance erased cell is extracted from those entity erased cell of this free area, these first data are write to this at least one first instance erased cell, this at least one first instance erased cell is associated to this data field, adjust this garbage according to the number of this at least one first instance erased cell and this minimum threshold value and reclaim threshold value

When the value that the number wherein deducting this at least one first instance erased cell when this garbage recovery threshold value before adjusting obtains is greater than this minimum threshold value, the value that the number that this garbage recovery threshold value before this garbage recovery threshold value after adjustment can be set to adjustment deducts this at least one first instance erased cell obtains

Wherein when this garbage before adjusting reclaims that value that the threshold value number that deducts this at least one first instance erased cell obtains is non-is greater than this minimum threshold value, this garbage after adjustment reclaims threshold value can be set to this minimum threshold value.

3. method for writing data according to claim 2, is characterized in that, the step dynamically keeping the entity erased cell of this predetermined quantity among those entity erased cell to be exclusively used in this alphabetic data of write also comprises:

If when these first data are this random data, from the entity erased cell of this free area, extract at least one second instance erased cell, these first data are write to this at least one second instance erased cell and this at least one second instance erased cell is associated to this data field.

4. method for writing data according to claim 3, is characterized in that, the step dynamically keeping the entity erased cell of this predetermined quantity among those entity erased cell to be exclusively used in this alphabetic data of write also comprises:

Judge whether the number of the entity erased cell of this free area is not more than this garbage and reclaims threshold value; And

If when the number of the entity erased cell of this free area is not more than this garbage recovery threshold value, perform a data consolidation procedure so that at least one entity erased cell of this data field is associated to this free area.

5. method for writing data according to claim 4, is characterized in that, performs this data consolidation procedure and comprises with the step that at least one entity erased cell of this data field is associated to this free area:

One the 3rd entity erased cell is selected from the entity erased cell of this data field;

If when the 3rd entity erased cell has at least one valid data, these at least one valid data are copied to 1 this data field the 4th entity erased cell from the 3rd entity erased cell; And

To erase the 3rd entity erased cell and the 3rd entity erased cell after erasing is associated to this free area.

6. method for writing data according to claim 1, is characterized in that, the capacity of this logical block equals the capacity of the entity erased cell of this data field, and the capacity of the entity erased cell of this predetermined quantity is less than or equal to the capacity of those logical blocks.

7. a memorizer control circuit unit, for controlling a reproducible nonvolatile memorizer module, is characterized in that, this memorizer control circuit unit comprises:

One host interface, in order to be electrically connected to a host computer system;

One memory interface, in order to be electrically connected to this reproducible nonvolatile memorizer module, wherein this reproducible nonvolatile memorizer module has multiple entity erased cell; And

One memory management circuitry, is electrically connected to this host interface and this memory interface, and in order to those entity erased cell are at least grouped into a data field and a free area,

Wherein this memory management circuitry is also in order to configure multiple logical block to map the entity erased cell of this data field,

Wherein this memory management circuitry is also in order to dynamically to maintain the entity erased cell of the predetermined quantity among those entity erased cell to be exclusively used in write one alphabetic data.

8. memorizer control circuit unit according to claim 7, is characterized in that, a minimum threshold value is added that the value that this predetermined quantity obtains sets a garbage recovery threshold value by this memory management circuitry,

Wherein this memory management circuitry receives a write instruction from this host computer system, at least one first logical block wherein among this write instruction instruction write one first data to those logical blocks,

Wherein this memory management circuitry judges whether these first data are an alphabetic data or a random data,

If when wherein these first data are this alphabetic data, this memory management circuitry extracts at least one first instance erased cell from those entity erased cell of this free area, these first data are write to this at least one first instance erased cell, this at least one first instance erased cell is associated to this data field, adjust this garbage according to the number of this at least one first instance erased cell and this minimum threshold value and reclaim threshold value

9. memorizer control circuit unit according to claim 8, it is characterized in that, if when these first data are this random data, this memory management circuitry extracts at least one second instance erased cell from the entity erased cell of this free area, these first data is write to this at least one second instance erased cell and this at least one second instance erased cell is associated to this data field.

10. memorizer control circuit unit according to claim 9, is characterized in that, this memory management circuitry judges whether the number of the entity erased cell of this free area is not more than this garbage and reclaims threshold value,

If when the number of the entity erased cell of this free area is not more than this garbage recovery threshold value, this memory management circuitry performs a data consolidation procedure so that at least one entity erased cell of this data field is associated to this free area.

11. memorizer control circuit unit according to claim 10, it is characterized in that, in this data consolidation procedure of execution so that at least one entity erased cell of this data field is associated in the operation of this free area, this memory management circuitry selects one the 3rd entity erased cell from the entity erased cell of this data field, and the 3rd entity erased cell and the 3rd entity erased cell after erasing is associated to this free area of erasing

If when wherein the 3rd entity erased cell has at least one valid data, these at least one valid data were first copied to 1 this data field the 4th entity erased cell from the 3rd entity erased cell by this memory management circuitry before the 3rd entity erased cell of erasing.

12. memorizer control circuit unit according to claim 7, it is characterized in that, the capacity of those logical blocks equals the capacity of the entity erased cell of this data field, and the capacity of the entity erased cell of this predetermined quantity is less than or equal to the capacity of those logical blocks.

13. 1 kinds of memorizer memory devices, is characterized in that, comprising:

One connecting interface unit, in order to be electrically connected to a host computer system;

One reproducible nonvolatile memorizer module, has multiple entity erased cell; And

One memorizer control circuit unit, is electrically connected to this connecting interface unit and this reproducible nonvolatile memorizer module, and in order to those entity erased cell are at least grouped into a data field and a free area,

Wherein this memorizer control circuit unit is also in order to configure multiple logical block to map the entity erased cell of this data field,

Wherein this memorizer control circuit unit is also in order to dynamically to maintain the entity erased cell of the predetermined quantity among those entity erased cell to be exclusively used in write one alphabetic data.

14. memorizer memory devices according to claim 13, is characterized in that, a minimum threshold value is added that the value that this predetermined quantity obtains sets a garbage recovery threshold value by this memorizer control circuit unit,

Wherein this memorizer control circuit unit receives a write instruction from this host computer system, at least one first logical block wherein among this write instruction instruction write one first data to those logical blocks,

Wherein whether these first data of this memorizer control circuit unit judges are an alphabetic data or a random data,

If when wherein these first data are this alphabetic data, this memorizer control circuit unit extracts at least one first instance erased cell from those entity erased cell of this free area, these first data are write to this at least one first instance erased cell, this at least one first instance erased cell is associated to this data field, adjust this garbage according to the number of this at least one first instance erased cell and this minimum threshold value and reclaim threshold value

15. memorizer memory devices according to claim 14, it is characterized in that, if when these first data are this random data, this memorizer control circuit unit extracts at least one second instance erased cell from the entity erased cell of this free area, these first data is write to this at least one second instance erased cell and this at least one second instance erased cell is associated to this data field.

16. memorizer memory devices according to claim 15, is characterized in that, whether the number of the entity erased cell of this this free area of memorizer control circuit unit judges is not more than this garbage is reclaimed threshold value,

If when the number of the entity erased cell of this free area is not more than this garbage recovery threshold value, this memorizer control circuit unit performs a data consolidation procedure so that at least one entity erased cell of this data field is associated to this free area.

17. memorizer memory devices according to claim 16, it is characterized in that, in this data consolidation procedure of execution so that at least one entity erased cell of this data field is associated in the operation of this free area, this memorizer control circuit unit selects one the 3rd entity erased cell from the entity erased cell of this data field, and the 3rd entity erased cell and the 3rd entity erased cell after erasing is associated to this free area of erasing

If when wherein the 3rd entity erased cell has at least one valid data, these at least one valid data were first copied to 1 this data field the 4th entity erased cell from the 3rd entity erased cell by this memorizer control circuit unit before the 3rd entity erased cell of erasing.

18. memorizer memory devices according to claim 13, it is characterized in that, the capacity of those logical blocks equals the capacity of the entity erased cell of this data field, and the capacity of the entity erased cell of this predetermined quantity is less than or equal to the capacity of those logical blocks.