CN111767005A - Memory control method, memory storage device and memory control circuit unit - Google Patents

Memory control method, memory storage device and memory control circuit unit Download PDF

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Publication number
CN111767005A
CN111767005A CN201910256261.2A CN201910256261A CN111767005A CN 111767005 A CN111767005 A CN 111767005A CN 201910256261 A CN201910256261 A CN 201910256261A CN 111767005 A CN111767005 A CN 111767005A
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management
unit
valid data
information
memory
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CN111767005B (en
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郭哲岳
陈鼎元
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Phison Electronics Corp
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Phison Electronics Corp
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0604—Improving or facilitating administration, e.g. storage management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0608—Saving storage space on storage systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0646—Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
    • G06F3/0652—Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

An exemplary embodiment of the invention provides a memory control method, a memory storage device and a memory control circuit unit. The method comprises the following steps: maintaining first management information in the rewritable nonvolatile memory module, wherein the first management information is used for identifying a first management unit; collecting first valid data from the first management unit according to first management information without reading the first mapping information from the rewritable non-volatile memory module in a data merging operation, wherein the first mapping information comprises logic-to-entity mapping information related to the first valid data; and storing the collected first valid data to a recovery unit.

Description

Memory control method, memory storage device and memory control circuit unit
Technical Field
The present invention relates to a memory control technology, and more particularly, to a memory control method, a memory storage device, and a memory control circuit unit.
Background
Digital cameras, mobile phones and MP3 players have grown rapidly over the years, resulting in a rapid increase in consumer demand for storage media. Since a rewritable non-volatile memory module (e.g., a flash memory) has the characteristics of non-volatility, power saving, small volume, and no mechanical structure, it is very suitable for being built in various portable multimedia devices.
When the memory storage device leaves a factory, a part of the management units in the memory storage device are configured as a plurality of idle management units, so as to store new data by using the idle management units. After a period of use, the number of idle management units in the memory storage device is gradually reduced. The memory storage device may copy valid data from a plurality of source units to a recovery unit (also referred to as a target unit) through a data merging procedure (or called a garbage collection procedure) and erase management units belonging to the source units to release new idle management units. However, in the data merging program, if the logical units mapped by the plurality of management units selected as the source units are more distributed, more tables for describing the management information (e.g., mapping information) of the logical units need to be accessed, thereby prolonging the time for executing the data merging program and/or reducing the execution efficiency of the data merging program.
Disclosure of Invention
The present invention provides a memory control method, a memory storage device and a memory control circuit unit, which can effectively improve the above problems and/or increase the system performance of the memory storage device.
An exemplary embodiment of the present invention provides a memory control method for a rewritable nonvolatile memory module. The rewritable nonvolatile memory module comprises a plurality of management units. The memory control method includes: maintaining first management information in the rewritable non-volatile memory module, the first management information identifying a first management unit of the plurality of management units; collecting first valid data from the first management unit according to first management information without reading the first mapping information from the rewritable non-volatile memory module in a data merging operation, wherein the first mapping information comprises logic-to-entity mapping information related to the first valid data; and storing the collected first valid data to a recovery unit.
In an exemplary embodiment of the invention, the collecting the first valid data from the first management unit according to the first management information without reading the first mapping information from the rewritable non-volatile memory module includes: reading second management information from the first management unit, wherein the second management information is used for identifying at least one first entity unit storing the first valid data in the first management unit; and collecting the first valid data from the at least one first entity unit according to the second management information.
In an exemplary embodiment of the invention, the memory control method further includes: updating third management information in response to the collection of the first valid data, wherein the third management information includes index information to read the logic-to-entity mapping information related to the first valid data.
In an exemplary embodiment of the invention, the memory control method further includes: reading second mapping information from the rewritable non-volatile memory module according to the updated third management information, wherein the second mapping information comprises logic-to-entity mapping information related to second valid data; collecting the second valid data from at least one second entity unit in the first management unit according to the second mapping information; and storing the collected second valid data to the recycle unit.
In an exemplary embodiment of the invention, the step of maintaining the first management information in the rewritable non-volatile memory module includes: in response to satisfaction of a first condition, including at least one of: the first management unit comprises a plurality of continuous physical nodes, and the plurality of continuous physical nodes are used for storing at least part of the first valid data; and the logical range to which the first valid data belongs is different from the logical range to which the remaining valid data in the first management unit belongs.
In an exemplary embodiment of the invention, the step of maintaining the first management information in the rewritable non-volatile memory module further includes: removing the identification information corresponding to the first management unit from the first management information in response to the first condition not being satisfied.
An exemplary embodiment of the present invention further provides a memory storage device, which includes a connection interface unit, a rewritable nonvolatile memory module and a memory control circuit unit. The connection interface unit is used for connecting to a host system. The rewritable nonvolatile memory module comprises a plurality of management units. The memory control circuit unit is connected to the connection interface unit and the rewritable nonvolatile memory module, wherein the memory control circuit unit is used for maintaining first management information in the rewritable non-volatile memory module, and the first management information is used for identifying a first management unit in the plurality of management units, the memory control circuit unit is also used for controlling the memory controller to operate in data merging operation, collecting first valid data from the first management unit according to the first management information without reading first mapping information from the rewritable non-volatile memory module, wherein the first mapping information comprises logic-to-entity mapping information related to the first valid data, and the memory control circuit unit is further configured to send a write instruction sequence to instruct to store the collected first valid data to a reclamation unit.
In an exemplary embodiment of the invention, the operation of the memory control circuit unit collecting the first valid data from the first management unit according to the first management information without reading the first mapping information from the rewritable non-volatile memory module includes: instructing reading of second management information from the first management unit, wherein the second management information is used for identifying at least one first entity unit storing the first valid data in the first management unit; and collecting the first valid data from the at least one first entity unit according to the second management information.
In an example embodiment of the present invention, the memory control circuit unit is further configured to update third management information in response to the collection of the first valid data, wherein the third management information includes index information for reading the logic-to-entity mapping information related to the first valid data.
In an example embodiment of the present invention, the memory control circuit unit is further configured to read second mapping information from the rewritable non-volatile memory module according to the updated third management information, wherein the second mapping information includes logic-to-entity mapping information related to second valid data; collecting the second valid data from at least one second entity unit in the first management unit according to the second mapping information; and instructing to store the collected second valid data to the recycle unit.
In an exemplary embodiment of the invention, the operation of the memory control circuit unit maintaining the first management information in the rewritable non-volatile memory module includes: in response to satisfaction of a first condition, including at least one of: the first management unit comprises a plurality of continuous physical nodes, and the plurality of continuous physical nodes are used for storing at least part of the first valid data; and the logical range to which the first valid data belongs is different from the logical range to which the remaining valid data in the first management unit belongs.
In an exemplary embodiment of the invention, the operation of the memory control circuit unit maintaining the first management information in the rewritable non-volatile memory module further includes: removing the identification information corresponding to the first management unit from the first management information in response to the first condition not being satisfied.
An exemplary embodiment of the present invention further provides a memory control circuit unit for controlling a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module includes a plurality of management units, and the memory control circuit unit includes a host interface, a memory interface, and a memory management circuit. The host interface is used for connecting to a host system. The memory interface is used for connecting to the rewritable nonvolatile memory module. The memory management circuit is connected to the host interface and the memory interface, wherein the memory management circuit is used for maintaining first management information in the rewritable non-volatile memory module, and the first management information is used to identify a first management unit of the plurality of management units, the memory management circuit is further used to, in a data union operation, collecting first valid data from the first management unit according to the first management information without reading first mapping information from the rewritable non-volatile memory module, wherein the first mapping information comprises logic-to-entity mapping information related to the first valid data, and the memory management circuitry is further to send a sequence of write instructions to instruct storage of the collected first valid data to a reclaim unit.
In an exemplary embodiment of the invention, the operation of the memory management circuit collecting the first valid data from the first management unit according to the first management information without reading the first mapping information from the rewritable non-volatile memory module includes: instructing reading of second management information from the first management unit, wherein the second management information is used for identifying at least one first entity unit storing the first valid data in the first management unit; and collecting the first valid data from the at least one first entity unit according to the second management information.
In an exemplary embodiment of the invention, each entity unit of the at least one first entity unit includes a plurality of consecutive entity nodes, and the plurality of consecutive entity nodes are configured to store at least a portion of the first valid data.
In an example embodiment of the present invention, the memory management circuit is further configured to update third management information in response to the collection of the first valid data, wherein the third management information includes index information for reading the logic-to-entity mapping information associated with the first valid data.
In an example embodiment of the present invention, the memory management circuit is further configured to read second mapping information from the rewritable non-volatile memory module according to the updated third management information, wherein the second mapping information includes logic-to-entity mapping information related to second valid data; collecting the second valid data from at least one second entity unit in the first management unit according to the second mapping information; and instructing to store the collected second valid data to the recycle unit.
In an exemplary embodiment of the invention, the operation of the memory management circuit to maintain the first management information in the rewritable non-volatile memory module includes: in response to satisfaction of a first condition, including at least one of: the first management unit comprises a plurality of continuous physical nodes, and the plurality of continuous physical nodes are used for storing at least part of the first valid data; and the logical range to which the first valid data belongs is different from the logical range to which the remaining valid data in the first management unit belongs.
In an example embodiment of the present invention, the operation of the memory management circuit maintaining the first management information in the rewritable non-volatile memory module further includes: removing the identification information corresponding to the first management unit from the first management information in response to the first condition not being satisfied.
Based on the above, the first management information for identifying the first management unit from the plurality of management units can be maintained in the rewritable non-volatile memory module. In the data merging operation, first valid data may be collected from the first management unit according to the first management information and stored to a recycling unit without reading first mapping information from the rewritable non-volatile memory module. The first mapping information includes logic-to-entity mapping information related to the first valid data. Therefore, the time for executing the data merging program can be effectively shortened and/or the execution efficiency of the data merging program can be improved, and the system efficiency of the memory storage device can be further improved.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
FIG. 1 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment of the present invention;
FIG. 2 is a diagram illustrating a host system, a memory storage device, and an I/O device according to another example embodiment of the present invention;
FIG. 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the invention;
FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention;
FIG. 5 is a schematic block diagram illustrating a memory control circuit unit according to an exemplary embodiment of the present invention;
FIG. 6 is a diagram illustrating management of a rewritable nonvolatile memory module according to an exemplary embodiment of the present invention;
FIG. 7 is a diagram illustrating a host write operation and a data merge operation according to an exemplary embodiment of the present invention;
FIG. 8 is a diagram illustrating management of a rewritable nonvolatile memory module according to an exemplary embodiment of the present invention;
FIG. 9 is a diagram illustrating a management unit according to an exemplary embodiment of the present invention;
fig. 10 is a diagram illustrating first management information according to an exemplary embodiment of the present invention;
FIG. 11 is a diagram illustrating a first management unit according to an exemplary embodiment of the present invention;
FIG. 12 is a diagram illustrating second management information according to an exemplary embodiment of the present invention;
fig. 13 is a diagram illustrating third management information according to an exemplary embodiment of the present invention;
FIG. 14 is a diagram illustrating a data merging operation according to an exemplary embodiment of the present invention;
FIG. 15 is a diagram illustrating a data merging operation according to an exemplary embodiment of the present invention;
FIG. 16 is a flowchart illustrating a memory control method according to an exemplary embodiment of the invention;
FIG. 17 is a flowchart illustrating a memory control method according to an exemplary embodiment of the invention.
Description of the reference numerals
10. 30: memory storage device
11. 31: host system
110: system bus
111: processor with a memory having a plurality of memory cells
112: random access memory
113: read-only memory
114: data transmission interface
12: input/output (I/O) device
20: main machine board
201: u disk
202: memory card
203: solid state disk
204: wireless memory storage device
205: global positioning system module
206: network interface card
207: wireless transmission device
208: keyboard with a keyboard body
209: screen
210: horn type loudspeaker
32: SD card
33: CF card
34: embedded memory device
341: embedded multimedia card
342: embedded multi-chip packaging storage device
402: connection interface unit
404: memory control circuit unit
406: rewritable nonvolatile memory module
502: memory management circuit
504: host interface
506: memory interface
508: error checking and correcting circuit
510: buffer memory
512: power management circuit
601: storage area
602: idle zone
603: system area
610(0) - (610 (C), P1-P42: entity node
612(0) to 612 (D): logic unit
701. 702: data of
710: host unit
720: source unit
730: recovery unit
80(1) to 80 (m): channel
81(1) -81 (n): management unit
CE (1), CE (2): chip enable
PL (1), PL (2): plane surface
1001. 1201 and 1301: form information
PU (1) to PU (16): entity unit
1501: logic to entity mapping table
S1601: step (maintaining first management information in a rewritable non-volatile memory module for identifying a first management unit of a plurality of management units)
S1602: step (in the data integration operation, on the premise of not reading the first mapping information from the rewritable nonvolatile memory module, collecting the first effective data from the first management unit according to the first management information, wherein the first mapping information comprises logic-to-entity mapping information related to the first effective data)
S1603: step (storing the collected first valid data to the recycle unit)
S1701: step (operation and integration of starting data)
S1702: step (selecting the first management unit based on the first management information)
S1703: step (fetching second management information from the first management unit, identifying at least one entity unit of the first management unit storing the first valid data)
S1704: a step of collecting first effective data from the at least one entity unit and storing the first effective data in a recovery unit based on the second management information
S1705: step (reading second mapping information from rewritable nonvolatile memory module)
S1706: step (collecting second effective data from the first management unit and storing the second effective data to the recycle unit according to the second mapping information)
S1707: step (Erase the first management unit)
Detailed Description
Generally, a memory storage device (also referred to as a memory storage system) includes a rewritable non-volatile memory module (rewritable non-volatile memory module) and a controller (also referred to as a control circuit). Typically, memory storage devices are used with a host system so that the host system can write data to or read data from the memory storage devices.
FIG. 1 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an exemplary embodiment of the invention. FIG. 2 is a diagram illustrating a host system, a memory storage device and an I/O device according to another example embodiment of the invention.
Referring to fig. 1 and 2, the host system 11 generally includes a processor 111, a Random Access Memory (RAM) 112, a Read Only Memory (ROM) 113, and a data transmission interface 114. The processor 111, the RAM 112, the ROM 113, and the data transmission interface 114 are all connected to a system bus (system bus) 110.
In the present exemplary embodiment, the host system 11 is connected to the memory storage device 10 through the data transmission interface 114. For example, host system 11 may store data to memory storage device 10 or read data from memory storage device 10 via data transfer interface 114. The host system 11 is connected to the I/O device 12 via a system bus 110. For example, the host system 11 may transmit output signals to the I/O device 12 or receive input signals from the I/O device 12 via the system bus 110.
In the present exemplary embodiment, the processor 111, the ram 112, the rom 113 and the data transmission interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. Through the data transmission interface 114, the motherboard 20 can be connected to the memory storage device 10 in a wired or wireless manner. The memory storage device 10 may be, for example, a usb disk 201, a memory card 202, a Solid State Drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 can be, for example, a Near Field Communication (NFC) memory storage device, a wireless facsimile (WiFi) memory storage device, a Bluetooth (Bluetooth) memory storage device, or a Bluetooth low energy (iBeacon) memory storage device based on various wireless communication technologies. In addition, the motherboard 20 may also be connected to various I/O devices such as a Global Positioning System (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, and a speaker 210 via the System bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 via the wireless transmission device 207.
In an exemplary embodiment, the host system referred to is substantially any system that can cooperate with a memory storage device to store data. Although the host system is described as a computer system in the above exemplary embodiment, fig. 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the invention. Referring to fig. 3, in another exemplary embodiment, the host system 31 may also be a digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer, and the memory storage device 30 may be various non-volatile memory storage devices such as a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded storage device 34. The embedded memory device 34 includes embedded Multi media card (eMMC) 341 and/or embedded Multi Chip Package (eMCP) memory device 342, which directly connects the memory module to the host system.
FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention.
Referring to fig. 4, the memory storage device 10 includes a connection interface unit 402, a memory control circuit unit 404 and a rewritable nonvolatile memory module 406.
The connection interface unit 402 is used to connect the memory storage device 10 to the host system 11. The memory storage device 10 may communicate with the host system 11 through the connection interface unit 402. In the exemplary embodiment, connection interface unit 402 is compatible with the Serial Advanced Technology Attachment (SATA) standard. However, it should be understood that the present invention is not limited thereto, and the connection interface unit 402 may also conform to the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronics Engineers (IEEE) 1394 standard, the High-Speed Peripheral Component connection interface (PCI) standard, the Universal Serial Bus (USB) standard, the SD interface standard, the Ultra High Speed (UHS-I) interface standard, the Ultra High Speed (UHS-II) interface standard, the memory stick (memory stick, MS) interface standard, the MCP interface standard, the MMC interface standard, the eMMC interface standard, the Universal Flash memory (Flash Storage, CF) interface standard, the CF interface standard, the Device interface (Electronic drive interface), IDE) standard or other suitable standard. The connection interface unit 402 may be packaged with the memory control circuit unit 404 in one chip, or the connection interface unit 402 may be disposed outside a chip including the memory control circuit unit 404.
The memory control circuit unit 404 is used for executing a plurality of logic gates or control commands implemented in a hardware type or a firmware type and performing operations such as writing, reading and erasing data in the rewritable nonvolatile memory module 406 according to commands of the host system 11.
The rewritable nonvolatile memory module 406 is connected to the memory control circuit unit 404 and is used for storing data written by the host system 11. The rewritable nonvolatile memory module 406 may be a Single Level Cell (SLC) NAND flash memory module (i.e., a flash memory module that can store 1 bit in one memory Cell), a Multi-Level Cell (MLC) NAND flash memory module (i.e., a flash memory module that can store 2 bits in one memory Cell), a Triple Level Cell (TLC) NAND flash memory module (i.e., a flash memory module that can store 3 bits in one memory Cell), a Quad Level Cell (TLC) NAND flash memory module (i.e., a flash memory module that can store 4 bits in one memory Cell), other flash memory modules, or other memory modules having the same characteristics.
Each memory cell in the rewritable nonvolatile memory module 406 stores one or more bits with a change in voltage (hereinafter also referred to as a threshold voltage). Specifically, each memory cell has a charge trapping layer between the control gate (control gate) and the channel. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be varied, thereby varying the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also referred to as "writing data to the memory cell" or "programming" the memory cell. As the threshold voltage changes, each memory cell in the rewritable nonvolatile memory module 406 has multiple memory states. The read voltage is applied to determine which memory state a memory cell belongs to, thereby obtaining one or more bits stored by the memory cell.
In the present exemplary embodiment, the memory cells of the rewritable nonvolatile memory module 406 may constitute a plurality of physical programming cells, and the physical programming cells may constitute a plurality of physical erasing cells. Specifically, memory cells on the same word line may constitute one or more physically programmed cells. If each memory cell can store more than 2 bits, the physical program cells on the same word line can be classified into at least a lower physical program cell and an upper physical program cell. For example, the Least Significant Bit (LSB) of a cell belongs to the lower physical program cell, and the Most Significant Bit (MSB) of a cell belongs to the upper physical program cell. Generally, in the MLC NAND flash memory, the writing speed of the lower physical program cell is faster than that of the upper physical program cell, and/or the reliability of the lower physical program cell is higher than that of the upper physical program cell.
In the present exemplary embodiment, the physical program cell is a programmed minimum cell. That is, the physical programming unit is the minimum unit for writing data. For example, the physical programming unit can be a physical page (page) or a physical fan (sector). If the physical programming units are physical pages, the physical programming units may include a data bit region and a redundancy (redundancy) bit region. The data bit region includes a plurality of physical sectors for storing user data, and the redundant bit region stores system data (e.g., management data such as error correction codes). In the present exemplary embodiment, the data bit area includes 32 physical fans, and the size of one physical fan is 512 bytes (B). However, in other example embodiments, the data bit region may also include 8, 16, or a greater or lesser number of physical fans, and the size of each physical fan may also be greater or lesser. On the other hand, the physically erased cell is the minimum unit of erase. That is, each physically erased cell contains one of the minimum number of memory cells that are erased. For example, the physical erase unit is a physical block (block).
FIG. 5 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention.
Referring to fig. 5, the memory control circuit unit 404 includes a memory management circuit 502, a host interface 504, and a memory interface 506.
The memory management circuit 502 is used to control the overall operation of the memory control circuit unit 404. Specifically, the memory management circuit 502 has a plurality of control commands, and the control commands are executed to perform data writing, reading, and erasing operations during the operation of the memory storage device 10. When the operation of the memory management circuit 502 is explained below, it is equivalent to the operation of the memory control circuit unit 404.
In the exemplary embodiment, the control instructions of the memory management circuit 502 are implemented in firmware. For example, the memory management circuit 502 has a microprocessor unit (not shown) and a read only memory (not shown), and the control instructions are burned into the read only memory. When the memory storage device 10 is in operation, the control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.
In another example embodiment, the control instructions of the memory management circuit 502 can also be stored in a program code type in a specific area of the rewritable nonvolatile memory module 406 (e.g., a system area dedicated to storing system data in the memory module). Further, the memory management circuit 502 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the ROM has a boot code (BOOT code), and when the memory control circuit 404 is enabled, the microprocessor unit first executes the boot code to load the control instructions stored in the rewritable nonvolatile memory module 406 into the RAM of the memory management circuit 502. Then, the microprocessor unit operates the control commands to perform data writing, reading, erasing, and the like.
In another exemplary embodiment, the control instructions of the memory management circuit 502 can also be implemented in a hardware form. For example, the memory management circuit 502 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory unit management circuit, the memory writing circuit, the memory reading circuit, the memory erasing circuit and the data processing circuit are connected to the microcontroller. The cell management circuit is used to manage the cells or cell groups of the rewritable nonvolatile memory module 406. The memory write circuit is configured to issue a write command sequence to the rewritable nonvolatile memory module 406 to write data into the rewritable nonvolatile memory module 406. The memory read circuit is configured to issue a read command sequence to the rewritable nonvolatile memory module 406 to read data from the rewritable nonvolatile memory module 406. The memory erasing circuit is used for issuing an erasing command sequence to the rewritable nonvolatile memory module 406 so as to erase data from the rewritable nonvolatile memory module 406. The data processing circuit is used for processing data to be written into the rewritable nonvolatile memory module 406 and data read from the rewritable nonvolatile memory module 406. The write command sequence, the read command sequence, and the erase command sequence may respectively include one or more program codes or command codes and instruct the rewritable nonvolatile memory module 406 to perform corresponding operations of writing, reading, and erasing. In an example embodiment, the memory management circuit 502 may issue other types of command sequences to the rewritable nonvolatile memory module 406 to instruct the corresponding operations to be performed.
The host interface 504 is connected to the memory management circuitry 502. The memory management circuitry 502 may communicate with the host system 11 via a host interface 504. The host interface 504 is used for receiving and recognizing commands and data transmitted from the host system 11. For example, commands and data transmitted by the host system 11 may be transmitted to the memory management circuit 502 through the host interface 504. In addition, the memory management circuitry 502 may transfer data to the host system 11 through the host interface 504. In the exemplary embodiment, host interface 504 is compatible with the SATA standard. However, it should be understood that the present invention is not limited thereto, and the host interface 504 may be compatible with the PATA standard, the IEEE 1394 standard, the PCI Express standard, the USB standard, the SD standard, the UHS-I standard, the UHS-II standard, the MS standard, the MMC standard, the eMMC standard, the UFS standard, the CF standard, the IDE standard or other suitable data transmission standards.
The memory interface 506 is connected to the memory management circuit 502 and is used for accessing the rewritable nonvolatile memory module 406. That is, the data to be written to the rewritable nonvolatile memory module 406 is converted into a format accepted by the rewritable nonvolatile memory module 406 through the memory interface 506. Specifically, if the memory management circuit 502 wants to access the rewritable nonvolatile memory module 406, the memory interface 506 transmits a corresponding instruction sequence. For example, the instruction sequences may include a write instruction sequence for indicating write data, a read instruction sequence for indicating read data, an erase instruction sequence for indicating erase data, and corresponding instruction sequences for indicating various memory operations (e.g., changing read voltage levels or performing garbage collection operations, etc.). The instruction sequences are generated by the memory management circuit 502 and transmitted to the rewritable nonvolatile memory module 406 through the memory interface 506, for example. The sequences of instructions may include one or more signals or data on a bus. These signals or data may include instruction code or program code. For example, the read command sequence includes read identification codes, memory addresses, and other information.
In an exemplary embodiment, the memory control circuitry 404 further includes error checking and correction circuitry 508, buffer memory 510, and power management circuitry 512.
The error checking and correcting circuit 508 is connected to the memory management circuit 502 and is used for performing error checking and correcting operations to ensure the correctness of data. Specifically, when the memory management circuit 502 receives a write command from the host system 11, the error checking and correcting circuit 508 generates an Error Correcting Code (ECC) and/or an Error Detecting Code (EDC) for data corresponding to the write command, and the memory management circuit 502 writes the data corresponding to the write command and the corresponding ECC and/or EDC into the rewritable nonvolatile memory module 406. Thereafter, when the memory management circuit 502 reads data from the rewritable nonvolatile memory module 406, the error correction code and/or the error check code corresponding to the data are simultaneously read, and the error checking and correcting circuit 508 performs an error checking and correcting operation on the read data according to the error correction code and/or the error check code.
The buffer memory 510 is connected to the memory management circuit 502 and is used for temporarily storing data and instructions from the host system 11 or data from the rewritable nonvolatile memory module 406. The power management circuit 512 is connected to the memory management circuit 502 and is used to control the power of the memory storage device 10.
In an example embodiment, the rewritable non-volatile memory module 406 of fig. 4 is also referred to as a flash (flash) memory module, the memory control circuit unit 404 is also referred to as a flash memory controller for controlling the flash memory module, and/or the memory management circuit 502 of fig. 5 is also referred to as a flash memory management circuit.
FIG. 6 is a diagram illustrating a management of a rewritable nonvolatile memory module according to an exemplary embodiment of the present invention.
Referring to FIG. 6, the memory management circuit 502 logically groups the physical nodes 610(0) -610 (C) of the rewritable nonvolatile memory module 406 into a storage area 601, an idle (spare) area 602, and a system area 603. The entity nodes 610(0) to 610(a) in the storage area 601 store data. For example, entity nodes 610(0) -610 (A) in storage area 601 may store valid (valid) data and invalid (invalid) data. The physical nodes 610(a +1) -610 (B) in the idle region 602 are not yet used to store data (e.g., valid data). The physical nodes 610(B +1) -610 (C) in the storage 603 are used to store system data, such as a logic-to-physical mapping table, a bad block management table, a device model, or other types of management data.
A physical node may include one or more physical addresses. A physical address may consist of multiple memory locations. When data is to be stored, the memory management circuit 502 may select at least one physical node from the physical nodes 610(a +1) to 610(B) of the idle region 602 and store the data from the host system 11 or from the at least one physical node in the storage region 601 into the selected physical node. At the same time, the selected physical node would be associated to the storage area 601. In addition, after erasing a physical node in the storage area 601, the erased physical node is re-associated with the idle area 602.
Memory management circuitry 502 may configure logic 612(0) - (612 (D) to map physical nodes 610(0) - (610 (A) in memory area 601. A logical unit may include one or more logical addresses. Each of logic units 612(0) -612 (D) may be mapped to one or more physical nodes. It should be noted that the memory management circuit 502 may not configure the logical units mapped to the system area 603, so as to prevent the system data stored in the system area 603 from being modified by the user.
The memory management circuit 502 may record the mapping relationship between the logical units and the physical nodes (also referred to as logical-to-physical mapping information or mapping information) in at least one logical-to-physical mapping table. The logical-to-physical mapping table is stored in the physical nodes 610(B +1) to 610(C) of the system area 603. When host system 11 is going to read data from memory storage device 10 or write data to memory storage device 10, memory management circuit 502 may perform data access operations with respect to memory storage device 10 according to the logical-to-physical mapping table.
The memory management circuit 502 can manage and access the physical nodes in the rewritable nonvolatile memory module 406 based on the management unit. One management unit is also called a Virtual Block (VB). A management unit may comprise a plurality of physical nodes. For example, a management unit may cover multiple physical nodes belonging to multiple planes (also referred to as memory planes) and/or multiple Chip Enables (CEs) in the rewritable nonvolatile memory module 406. Further, one management unit may be associated to the memory area 601, the idle area 602, or the system area 603. The management units belonging to the idle region 602 are also referred to as idle management units. The management units belonging to the storage area 601 are also called non-idle management units.
It should be noted that valid data is the latest data belonging to a logical unit, and invalid data is not the latest data belonging to any logical unit. For example, if the host system 11 stores a new data item in a logical unit to overwrite the old data originally stored in the logical unit (i.e. update the data belonging to the logical unit), the new data item stored in the storage area 601 is the latest data belonging to the logical unit and will be marked as valid, and the overwritten old data item may still be stored in the storage area 601 but marked as invalid.
In the exemplary embodiment, if the data belonging to a logical unit is updated, the mapping relationship between the logical unit and the entity node storing the old data belonging to the logical unit is removed, and the mapping relationship between the logical unit and the entity node storing the latest data belonging to the logical unit is established. However, in another exemplary embodiment, if the data belonging to a logical unit is updated, the mapping relationship between the logical unit and the physical node storing the old data belonging to the logical address can still be maintained.
When the memory storage device 10 is shipped from a factory, the total number of management units belonging to the idle area 602 is a preset number (e.g., 30). In the operation of the memory storage device 10, more and more management units are selected from the idle area 602 and associated with the storage area 601 to store data (e.g., user data from the host system 11). Therefore, the total number of management units belonging to the idle region 602 gradually decreases with the use of the memory storage device 10.
During the operation of the memory storage device 10, the memory management circuit 502 can continuously update the total number of management units belonging to the idle region 602. The memory management circuit 502 may perform the data union operation according to the number of the management units (i.e., the total number of idle management units) in the idle region 602. For example, the memory management circuit 502 can determine whether the total number of management units belonging to the idle region 602 is less than or equal to a threshold (also referred to as a first threshold). The first threshold value is, for example, a value of 2 or more (e.g., 10), but the invention is not limited thereto. If the total number of the management units belonging to the idle region 602 is less than or equal to the first threshold, the memory management circuit 502 may perform the data union operation. In an example embodiment, the data consolidation operation is also referred to as a garbage collection operation.
In a data merge operation, the memory management circuit 502 may select at least one management unit from the memory area 601 as a source unit and at least one management unit from the idle area 602 as a recycle unit. The memory management circuit 502 can send at least one instruction sequence to instruct the rewritable nonvolatile memory module 406 to copy valid data from the management unit as a source unit to the management unit as a recovery unit. A management unit that is full of valid data as a recycle unit may be associated to the storage area 601. If all valid data stored by a management unit has been copied to the recycle unit, the management unit may be erased and associated with the idle region 602. In an exemplary embodiment, the operation of re-associating a management unit from the storage area 601 back to the idle area 602 (or the operation of erasing a management unit) is also referred to as releasing an idle management unit. By performing the data consolidation operation, one or more idle management units are released and the total number of management units belonging to the idle region 602 is gradually increased.
After the completion operation is started, the completion operation may be stopped if the management units belonging to the idle region 602 meet a specific condition. For example, the memory management circuit 502 can determine whether the total number of management units belonging to the idle region 602 is greater than or equal to a threshold (hereinafter also referred to as a second threshold). For example, the second threshold value may be greater than or equal to the first threshold value. If the total number of the management units belonging to the idle region 602 is greater than or equal to the second threshold, the memory management circuit 502 may stop the data rounding operation. It should be noted that stopping the data merging operation refers to ending the currently executing data merging operation. After stopping a data consolidation operation, if the total number of the management units belonging to the idle region 602 is again less than or equal to the first threshold, the next data consolidation operation may be performed again to attempt to release a new idle management unit.
FIG. 7 is a diagram illustrating a host write operation and a data merge operation according to an exemplary embodiment of the invention. Referring to fig. 7, in a host write operation, the host system 11 may send at least one write command to instruct writing data 701 to one or more logical units (or logical addresses). According to this write instruction, the memory management circuit 502 may instruct to store the data 701 to the host unit 710 mapped to the logical unit (or logical address). For example, host unit 710 may include some management unit selected from idle region 602 of fig. 6.
Alternatively, the memory management circuit 502 may initiate a data union operation to free up new idle management units. For example, in a data union operation, data 702 may be collected from at least one management unit as a source unit 720 and written to at least one management unit as a recycle unit 730. The data 702 includes valid data stored in the source unit 720. If valid data stored in a management unit as the source unit 720 has been completely copied to the recycle unit 730, the management unit can be erased to become a new idle management unit. Thus, the number of idle management units in the idle region 602 of fig. 6 can be gradually increased.
FIG. 8 is a diagram illustrating a management of a rewritable nonvolatile memory module according to an exemplary embodiment of the present invention. Referring to FIG. 8, the rewritable nonvolatile memory module 406 includes management units 81(1) to 81 (n). Each of the management units 81(1) -81 (n) includes chip enable (also referred to as a chip enable group) CE (1) and CE (2). The chip enable CE (1) and CE (2) each include a plurality of physical nodes. The memory management circuit 502 can access the management units 81(1) to 81(n) through the channels 80(1) to 80 (m). For example, the memory management circuit 502 may access the management units 81(1) and 81(2) in parallel (or alternatively referred to as interleaved) through at least two of the channels 80(1) to 80 (m). In addition, chip enable CE (1) and CE (2) may include multiple planes (e.g., planes PL (1) and PL (2) of FIG. 9), respectively.
FIG. 9 is a diagram illustrating a management unit according to an exemplary embodiment of the invention. Referring to FIG. 9, taking the management units 81 and 1 as examples, the plane PL (1) in the chip enable CE (1) may include physical nodes P1-P7, P29-P35, etc., the plane PL (2) in the chip enable CE (1) may include physical nodes P8-P14, P36-42, etc., the plane PL (1) in the chip enable CE (2) may include physical nodes P15-P21, etc., and the plane PL (2) in the chip enable CE (2) may include physical nodes P22-P28, etc. The physical nodes P1-P28 can be accessed in parallel (or interleaved) to improve the access efficiency.
In an example embodiment, a plurality of consecutive entity nodes (e.g., entity nodes P1-P7) in a plane may be referred to as an entity unit. Alternatively, in an exemplary embodiment, a plurality of consecutive physical nodes (e.g., physical nodes P1-P14) in a chip enable may be referred to as a physical unit. Alternatively, in an example embodiment, a plurality of consecutive entity nodes (e.g., entity nodes P1-P28) in a plurality of planes may be referred to as one entity unit.
In an example embodiment, after the data consolidation operation is initiated, the memory management circuit 502 may read at least a portion of the logical-to-physical mapping table from the rewritable nonvolatile memory module 406 and analyze the data amount of the valid data and/or the storage location of the valid data stored in at least a portion of the management units according to the logical-to-physical mapping table. Then, the memory management circuit 502 may select at least one management unit as a source unit according to the analysis result and collect valid data therefrom. However, both the reading and analysis of the logical-to-physical mapping table require time. If the logical units to which the valid data stored in a certain management unit belong are distributed (i.e., the mapping information of these logical units is distributed in multiple logical-to-physical mapping tables), more time is often required to read multiple logical-to-physical mapping tables to obtain the required mapping information, thereby reducing the execution efficiency of the data merging operation.
In an example embodiment, the memory management circuit 502 may maintain specific management information (also referred to as first management information) in the rewritable non-volatile memory module 406. For example, the first management information may be stored in the system area 603 of fig. 6. The first management information can be used to identify a specific management unit (also referred to as a first management unit) in the rewritable nonvolatile memory module 406. In the data merge operation, the memory management circuit 502 can automatically select a first management unit from the plurality of management units as a source unit according to the first management information and collect valid data (also referred to as first valid data) from the first management unit without reading specific mapping information (also referred to as first mapping information) from the rewritable non-volatile memory module 406. It is noted that the first mapping information comprises logical-to-entity mapping information related to the first valid data. For example, the first mapping information may reflect a mapping relationship between at least one logical unit to which the first valid data belongs and at least one entity node in the first management unit. For example, the first mapping information may be recorded in at least one logic-to-entity mapping table and stored in the system area 603 of fig. 6. Then, the memory management circuitry 502 may instruct the storage of the collected first valid data to the reclaim unit.
In other words, in an example embodiment, the memory management circuit 502 may select the first management unit as the source unit and collect the first valid data from the first management unit without reading and analyzing the mapping information associated with the first valid data, thereby effectively improving the execution efficiency of the data merging operation. For example, the memory management circuit 502 may omit the time to read and analyze the first mapping information to quickly collect the first valid data from the first management unit.
Fig. 10 is a diagram illustrating first management information according to an exemplary embodiment of the invention. Referring to fig. 10, in an exemplary embodiment, the first management information includes table information 1001. The table information 1001 may be stored in the system area 603 of fig. 6. The table information 1001 may include identification information corresponding to the management units 81(1) to 81(n), respectively. In the present exemplary embodiment, it is assumed that the identification information corresponding to the management units 81(1) and 81(n) is bit "1" and the identification information corresponding to the management units 81(2) is bit "0". In the data merging operation, the memory management circuit 502 may select the management unit 81(1) (and the management unit 81(n)) corresponding to the identification information being the bit "1" as the source unit (i.e., the first management unit) according to the table information 1001. It is noted that in the exemplary embodiment of fig. 10, the selection of the management unit 81(1) as the source unit may be performed without considering the mapping information associated with the valid data stored in the management unit 81 (1).
In an example embodiment, the memory management circuit 502 may also maintain specific management information (also referred to as second management information) in the first management unit. The second management information may be used to identify at least one entity unit (also referred to as a first entity unit) of the first management unit storing the first valid data. For example, the second management information may be stored in a specific entity unit among the first management units. For example, the particular entity unit may be the last entity unit in the first management unit.
In an example embodiment, after selecting the first management unit as the source unit, the memory management circuit 502 may read the second management information from the first management unit. The memory management circuit 502 may identify a first entity unit of the first management units according to the second management information and collect the first valid data from the identified first entity unit. In an example embodiment, each of the first physical units may include a plurality of consecutive physical nodes, and the consecutive physical nodes are configured to store at least a portion of the first valid data. It should be noted that, in an exemplary embodiment, at least one entity unit (also referred to as a second entity unit) of the first management unit storing the remaining valid data (also referred to as second valid data) may not be identified by the second management information.
Fig. 11 is a diagram illustrating a first management unit according to an exemplary embodiment of the invention. Fig. 12 is a diagram illustrating second management information according to an exemplary embodiment of the invention.
Referring to fig. 11 and 12, it is assumed that the management unit 81(1) is selected as the source unit (i.e., the first management unit) and that the management unit 81(1) includes a plurality of physical units PU (1) -PU (8). Each of the physical units PU (1) to PU (8) contains K consecutive physical nodes. For example, K may be 14, as shown in fig. 9. However, in another exemplary embodiment, the value of K may be larger or smaller, and the invention is not limited thereto. In addition, in another exemplary embodiment, the management unit 81(1) may further include more or less physical units, and the invention is not limited thereto.
In the present exemplary embodiment, it is assumed that physical units PU (1), PU (4), PU (5), and PU (8) are the first physical unit and physical units PU (2) and PU (7) are the second physical unit. The physical units PU (3) and PU (6) do not store valid data. The second management information may include table information 1201. The table information 1201 may be stored in the management unit 81 (1). For example, the table information 1201 may be stored in the last entity unit (e.g., entity unit PU (8)) in the management unit 81 (1). Table information 1201 may be used to identify physical units PU (1), PU (4), PU (5), and PU (8). For example, in table information 1201, the identification information corresponding to physical units PU (1), PU (4), PU (5), and PU (8) may be bit "1" to reflect that physical units PU (1), PU (4), PU (5), and PU (8) are the first physical unit. Conversely, in table information 1201, the identification information corresponding to physical units PU (2), PU (3), PU (6), and PU (7) may be bit "0" to reflect that physical units PU (2), PU (3), PU (6), and PU (7) are not the first physical unit. Thus, after selecting the management unit 81(1) as the source unit, according to the table information 1201, the entity units PU (1), PU (4), PU (5) and PU (8) can be identified as the first entity unit and collect the first valid data therefrom.
In an example embodiment, the memory management circuit 502 may also maintain specific management information (also referred to as third management information) in the rewritable non-volatile memory module 406. The third management information may include index information for reading logical-to-entity mapping information related to the valid data stored by the first management unit.
Fig. 13 is a diagram illustrating third management information according to an exemplary embodiment of the invention. Referring to fig. 11 and fig. 13, in the present exemplary embodiment, it is assumed that the third management information includes table information 1301. In addition, in the present exemplary embodiment, it is assumed that mapping information of valid data (i.e., first valid data) stored in the physical units PU (1), PU (4), PU (5), and PU (8) is respectively recorded in the logic-to-entity mapping tables corresponding to the index information PTE (20), PTE (30), PTE (40), and PTE (50).
According to the table information 1301, PTE (i) in the PTE index (i.e. index information) corresponds to the logical to entity mapping table numbered i. The identification information of the index information PTE (1), PTE (2), PTE (20), PTE (30), PTE (40), and PTE (50) is a bit "1", and indicates that the mapping information of at least a part of the valid data stored in the management unit 81(1) is recorded in the corresponding logical-to-entity mapping table of the index information PTE (1), PTE (2), PTE (20), PTE (30), PTE (40), and PTE (50), respectively.
Fig. 14 is a diagram illustrating a data merging operation according to an exemplary embodiment of the present invention. Referring to fig. 14, after the physical units PU (1), PU (4), PU (5), and PU (8) are identified as the first physical unit, the first valid data can be read from the physical units PU (1), PU (4), PU (5), and PU (8) and sequentially written into the recycling unit. It should be noted that, in the exemplary embodiment, it is assumed that the management unit 81(2) is a recycling unit, and the collected first valid data can be written into the physical units PU (9) -PU (12) in the management unit 81 (2).
In an example embodiment, the memory management circuit 502 may update the third management information in response to the collection of the first valid data (or being written to the recycle unit). Taking fig. 14 as an example, after writing the first valid data into the physical units PU (9) to PU (12), the identification bits corresponding to the index information PTE (20), PTE (30), PTE (40), and PTE (50) in the table information 1301 may be updated to bit "0" to indicate that the management unit 81(1) does not store valid data corresponding to the index information PTE (20), PTE (30), PTE (40), and PTE (50). In addition, the memory management circuit 502 may update the mapping information of the first valid data in the logic-to-entity mapping table corresponding to the index information PTE (20), PTE (30), PTE (40), and PTE (50) to reflect that the first valid data has been moved to the entity units PU (9) -PU (12) for storage.
In an example embodiment, the memory management circuit 502 may read specific mapping information (also referred to as second mapping information) from the rewritable nonvolatile memory module 406 according to the updated third management information. The second mapping information may include mapping information related to the second valid data. The second valid data is at least one second entity unit stored in the first management unit. The memory management circuit 502 may collect the second valid data from the second entity unit according to the second mapping information and store the collected second valid data to the recycle unit.
Fig. 15 is a diagram illustrating a data merging operation according to an exemplary embodiment of the present invention. Referring to fig. 15, after the first valid data is stored in the management unit 81(2) and the table information 1301 is updated, the memory management circuit 502 may query the table information 1301 and read the logic-to-entity mapping table 1501 from the rewritable nonvolatile memory module 406 according to the query result of the table information 1301. For example, in the present exemplary embodiment, it is assumed that the identification information corresponding to the index information PTE (1) and PTE (2) in the updated table information 1301 is bit "1", so the read logic-to-entity mapping table 1501 may include the information recorded in the logic-to-entity mapping table corresponding to the index information PTE (1) and PTE (2).
The memory management circuit 502 may analyze whether the data stored by the entity units PU (2), PU (3), PU (6), and PU (7) is valid data according to the logic-to-entity mapping table 1501. In the present exemplary embodiment, it is assumed that the entity unit PU (2) stores valid data and invalid data at the same time, the entity unit PU (3) stores only invalid data, the entity unit PU (6) stores only invalid data, and the entity unit PU (7) stores valid data and invalid data at the same time. According to the analysis result, the memory management circuit 502 can automatically read the valid data (i.e., the second valid data) from the entity units PU (2) and PU (7) and write the second valid data to the management unit 81(2) (e.g., the entity unit PU (13)) as the recycling unit. After storing the first valid data and the second valid data in the management unit 81(2) (i.e. all valid data in the management unit 81(1) are collected), the memory management circuit 502 may instruct the erasure management unit 81 (1).
In the example embodiments of fig. 11-15, the collection of the first valid data (as shown in fig. 14) does not involve the reading and analysis of the logic-to-entity mapping table, and only a small portion of the collection of the second valid data (as shown in fig. 15) needs to go through the reading and analysis of the logic-to-entity mapping table. Therefore, compared to the conventional method in which the data stored in the entire management unit (or the physical block) is analyzed through the corresponding logical-to-physical mapping table, in the exemplary embodiment of the present invention, the valid data can be collected more quickly in the data merging operation, thereby improving the performance efficiency of the entire data merging operation and/or the system performance of the memory storage device.
It is noted that, in an example embodiment, in response to satisfaction of a particular condition (also referred to as a first condition), the memory management circuit 502 may add identification information corresponding to the first management unit to the first management information. For example, the first condition may include at least one of the following conditions. For example, the first management unit includes a plurality of consecutive physical nodes, and the consecutive physical nodes are used for storing at least a part of the first valid data. In other words, the first management unit includes at least one first entity unit. In addition, the logical range to which the first valid data in the first management unit belongs must be different from the logical range to which the remaining valid data (i.e., the second valid data) in the first management unit belongs. In other words, the logical ranges to which the first valid data and the second valid data belong must not overlap (or have the same index information pte (i)). Therefore, the first management unit selected according to the first management information can have the best data integration efficiency.
Taking fig. 11 as an example, the physical units PU (1), PU (4), PU (5) and PU (8) in the management unit 81(1) are all the first physical units, so the management unit 81(1) can satisfy the condition that the first management unit includes at least one first physical unit. In addition, the logical range to which the first valid data in the management unit 81(1) belongs corresponds to the logical ranges of the index information PTE (20), PTE (30), PTE (40), and PTE (50), and the logical range to which the second valid data in the management unit 81(1) belongs corresponds to the logical ranges of the index information PTE (1) and PTE (2), so the management unit 81(1) can also satisfy the condition that the logical ranges to which the first valid data and the second valid data belong do not overlap. In response to the management unit 81(1) satisfying at least one of the first conditions, the memory management circuit 502 may mark the identification information corresponding to the management unit 81(1) as bit "1" in the table information 1001. Therefore, the data merging operation performed on the management unit 81(1) according to the first management information and the second management information (and the third management information) can obtain the best performance.
In an example embodiment, in response to the first condition not being satisfied, the memory management circuit 502 may remove the identification information corresponding to the first management unit from the first management information. For example, in the example embodiments of fig. 10 and 11, if at least a portion of invalid data exists in each of the physical units PU (1), PU (4), PU (5) and PU (8) and/or the logical range of the first valid data in the management unit 81(1) overlaps with the logical range of the second valid data based on the data writing of the host system 11, the memory management circuit 502 may update the identification information corresponding to the management unit 81(1) to bit "0" in the table information 1001. Thus, according to the updated table information 1001, the management means 81(1) is not selected as the first management means in the data merging operation executed next time.
It should be noted that, in the exemplary embodiments of fig. 10 to fig. 15, the table information 1001, 1201 and 1301 are examples and are not intended to limit the present invention. In another example embodiment, the table information 1001, 1201 and 1301 may also have other data formats or describe other useful information. In addition, in another exemplary embodiment of fig. 10 to 15, if all the physical units PU (1) to PU (8) in the management unit 81(1) are the first physical unit, the management unit 81(1) may be erased after the first valid data is collected from the physical units PU (1) to PU (8), and the operation of collecting the second valid data in fig. 15 may not be performed.
FIG. 16 is a flowchart illustrating a memory control method according to an exemplary embodiment of the invention. Referring to fig. 16, in step S1601, first management information is maintained in the rewritable nonvolatile memory module. The first management information is used for identifying a first management unit in the plurality of management units. In step S1602, in the data merge operation, on the premise that the first mapping information is not read from the rewritable non-volatile memory module, first valid data is collected from the first management unit according to the first management information. The first mapping information includes logic-to-entity mapping information related to the first valid data. In step S1603, the collected first valid data is stored to the recycle unit.
FIG. 17 is a flowchart illustrating a memory control method according to an exemplary embodiment of the invention. Referring to fig. 17, in step S1701, a data merge operation is started. In step S1702, a first management unit is selected as a recovery unit according to the first management information. In step S1703, second management information is fetched from the first management unit. The second management information is used for identifying at least one entity unit storing the first valid data in the first management unit. In step S1704, first valid data is collected from the at least one entity unit according to the second management information and stored in the recycling unit. In step S1705, second mapping information is read from the rewritable non-volatile memory module. In step S1706, second valid data is collected from the first management unit according to the second mapping information and stored to the recycle unit. In step S1707, the first management unit is erased.
However, the steps in fig. 16 and 17 have been described in detail above, and are not repeated herein. It is to be noted that, the steps in fig. 16 and fig. 17 can be implemented as a plurality of program codes or circuits, and the invention is not limited thereto. In addition, the methods shown in fig. 16 and fig. 17 can be used with the above exemplary embodiments, or can be used alone, and the invention is not limited thereto.
In summary, the memory management circuit can automatically maintain the first management information in the rewritable nonvolatile memory module, which is used to identify the first management unit from the plurality of management units. In the data merging operation, on the premise that the first mapping information is not read from the rewritable non-volatile memory module, the memory management circuit can automatically collect the first valid data from the first management unit according to the first management information and store the first valid data in the recovery unit. In addition, the memory management circuit can automatically update the first management information to meet the current use condition of the memory storage device by determining whether a certain management unit meets a first condition (for example, whether the first entity unit is included and/or whether the valid data in the first entity unit and the rest of the valid data use the same logic range). Therefore, the time for executing the data merging program can be effectively shortened and/or the execution efficiency of the data merging program can be improved, and the overall system efficiency of the memory storage device can be further improved.
Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.

Claims (21)

1. A memory control method for a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module includes a plurality of management units, the memory control method comprising:
maintaining first management information in the rewritable non-volatile memory module, wherein the first management information is used for identifying a first management unit in the plurality of management units;
collecting first valid data from the first management unit according to first management information without reading the first mapping information from the rewritable non-volatile memory module in a data merging operation, wherein the first mapping information comprises logic-to-entity mapping information related to the first valid data; and
storing the collected first valid data to a recovery unit.
2. The memory control method according to claim 1, wherein the step of collecting the first valid data from the first management unit according to the first management information without reading the first mapping information from the rewritable non-volatile memory module includes:
reading second management information from the first management unit, wherein the second management information is used for identifying at least one first entity unit storing the first valid data in the first management unit; and
and collecting the first valid data from the at least one first entity unit according to the second management information.
3. The memory control method of claim 2, wherein each physical unit of the at least one first physical unit comprises a plurality of consecutive physical nodes, and the plurality of consecutive physical nodes are configured to store at least a portion of the first valid data.
4. The memory control method of claim 1, further comprising:
updating third management information in response to the collection of the first valid data, wherein the third management information includes index information to read the logic-to-entity mapping information related to the first valid data.
5. The memory control method of claim 4, further comprising:
reading second mapping information from the rewritable non-volatile memory module according to the updated third management information, wherein the second mapping information comprises logic-to-entity mapping information related to second valid data;
collecting the second valid data from at least one second entity unit in the first management unit according to the second mapping information; and
storing the collected second valid data to the recovery unit.
6. The memory control method according to claim 1, wherein the step of maintaining the first management information in the rewritable non-volatile memory module includes:
adding identification information corresponding to the first management unit to the first management information in response to satisfaction of a first condition,
wherein the first condition comprises at least one of the following conditions:
the first management unit comprises a plurality of continuous physical nodes, and the plurality of continuous physical nodes are used for storing at least part of the first valid data; and
the logical range to which the first valid data belongs is different from the logical range to which the remaining valid data in the first management unit belongs.
7. The memory control method of claim 6, wherein the step of maintaining the first management information in the rewritable non-volatile memory module further comprises:
removing the identification information corresponding to the first management unit from the first management information in response to the first condition not being satisfied.
8. A memory storage device, comprising:
a connection interface unit for connecting to a host system;
a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of management units; and
a memory control circuit unit connected to the connection interface unit and the rewritable nonvolatile memory module,
wherein the memory control circuit unit is configured to maintain first management information in the rewritable non-volatile memory module, and the first management information is configured to identify a first management unit of the plurality of management units,
the memory control circuit unit is further configured to collect first valid data from the first management unit according to first management information without reading the first mapping information from the rewritable non-volatile memory module in a data consolidation operation, wherein the first mapping information includes logic-to-entity mapping information related to the first valid data, and
the memory control circuit unit is also configured to send a write instruction sequence to instruct storing of the collected first valid data to a reclamation unit.
9. The memory storage device according to claim 8, wherein the operation of the memory control circuit unit collecting the first valid data from the first management unit according to the first management information without reading the first mapping information from the rewritable non-volatile memory module includes:
instructing reading of second management information from the first management unit, wherein the second management information is used for identifying at least one first entity unit storing the first valid data in the first management unit; and
and collecting the first valid data from the at least one first entity unit according to the second management information.
10. The memory storage device of claim 9, wherein each physical unit of the at least one first physical unit comprises a plurality of consecutive physical nodes, and the plurality of consecutive physical nodes are configured to store at least a portion of the first valid data.
11. The memory storage device of claim 8, wherein the memory control circuitry unit is further to update third management information in response to the collection of the first valid data, wherein the third management information includes index information to read the logic-to-entity mapping information related to the first valid data.
12. The memory storage device of claim 11, wherein the memory control circuitry unit is further configured to read second mapping information from the rewritable non-volatile memory module according to the updated third management information, wherein the second mapping information comprises logic-to-entity mapping information related to second valid data;
collecting the second valid data from at least one second entity unit in the first management unit according to the second mapping information; and
instructing to store the collected second valid data to the recycle unit.
13. The memory storage device of claim 8, wherein the operation of the memory control circuitry to maintain the first management information in the rewritable non-volatile memory module comprises:
adding identification information corresponding to the first management unit to the first management information in response to satisfaction of a first condition,
wherein the first condition comprises at least one of the following conditions:
the first management unit comprises a plurality of continuous physical nodes, and the plurality of continuous physical nodes are used for storing at least part of the first valid data; and
the logical range to which the first valid data belongs is different from the logical range to which the remaining valid data in the first management unit belongs.
14. The memory storage device of claim 13, wherein the operation of the memory control circuitry to maintain the first management information in the rewritable non-volatile memory module further comprises:
removing the identification information corresponding to the first management unit from the first management information in response to the first condition not being satisfied.
15. A memory control circuit unit for controlling a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module includes a plurality of management units, wherein the memory control circuit unit includes:
a host interface for connecting to a host system;
a memory interface for connecting to the rewritable nonvolatile memory module; and
a memory management circuit connected to the host interface and the memory interface,
wherein the memory management circuit is configured to maintain first management information in the rewritable non-volatile memory module, and the first management information is configured to identify a first management unit of the plurality of management units,
the memory management circuit is further configured to collect first valid data from the first management unit according to first management information without reading the first mapping information from the rewritable non-volatile memory module in a data merging operation, wherein the first mapping information includes logic-to-entity mapping information related to the first valid data, and
the memory management circuit is also to send a write instruction sequence to instruct storing of the collected first valid data to a reclaim unit.
16. The memory control circuit unit of claim 15, wherein the operation of the memory management circuit to collect the first valid data from the first management unit according to the first management information without reading the first mapping information from the rewritable non-volatile memory module comprises:
instructing reading of second management information from the first management unit, wherein the second management information is used for identifying at least one first entity unit storing the first valid data in the first management unit; and
and collecting the first valid data from the at least one first entity unit according to the second management information.
17. The memory control circuit unit of claim 16, wherein each physical unit of the at least one first physical unit comprises a plurality of consecutive physical nodes, and the plurality of consecutive physical nodes are configured to store at least a portion of the first valid data.
18. The memory control circuitry unit of claim 15, wherein the memory management circuitry is further to update third management information in response to the collection of the first valid data, wherein the third management information includes index information to read the logic-to-entity mapping information related to the first valid data.
19. The memory control circuit unit of claim 18, wherein the memory management circuit is further configured to read second mapping information from the rewritable non-volatile memory module according to the updated third management information, wherein the second mapping information comprises logic-to-entity mapping information related to second valid data;
collecting the second valid data from at least one second entity unit in the first management unit according to the second mapping information; and
instructing to store the collected second valid data to the recycle unit.
20. The memory control circuitry unit of claim 15, wherein the operation of the memory management circuitry to maintain the first management information in the rewritable non-volatile memory module comprises:
adding identification information corresponding to the first management unit to the first management information in response to satisfaction of a first condition,
wherein the first condition comprises at least one of the following conditions:
the first management unit comprises a plurality of continuous physical nodes, and the plurality of continuous physical nodes are used for storing at least part of the first valid data; and
the logical range to which the first valid data belongs is different from the logical range to which the remaining valid data in the first management unit belongs.
21. The memory control circuitry unit of claim 20, wherein the operation of the memory management circuitry to maintain the first management information in the rewritable non-volatile memory module further comprises:
removing the identification information corresponding to the first management unit from the first management information in response to the first condition not being satisfied.
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