CN104732153A - Data erasing method, storage control circuit unit and storage storing device - Google Patents
Data erasing method, storage control circuit unit and storage storing device Download PDFInfo
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Abstract
The invention provides a data erasing method, a storage control circuit unit and a storage storing device. The data erasing method includes: receiving a predefined instruction indicated and executed on the first logic sub-element from the host system; tabbing the first entity programming unit mapped by the first logic sub-element as the invalid data state, recording the tabbing of the first entity erasing unit mapped corresponds to the first logic sub-element unit and responding the predetermined instruction, wherein the first entity programming unit belongs to the first entity erasing unit; and selecting the first entity erasing unit according to the tabbing, moving the valid data in the first entity erasing unit to the second entity erasing unit extracted from the entity erasing unit of the idle zone and conducting the entity erasing on the first entity erasing unit.
Description
Technical field
The invention relates to a kind of data erasing method for reproducible nonvolatile memorizer module, memorizer control circuit unit and memory storage apparatus.
Background technology
Digital camera, mobile phone and MP3 are very rapid in growth over the years, and the demand of consumer to medium is also increased rapidly.There is due to type nonvolatile (rewritable non-volatilememory) characteristics such as data are non-volatile, power saving, volume is little, mechanical structure, read or write speed are fast, be most suitable for portable electronic product, such as notebook computer.Solid state hard disc is exactly a kind of memory storage apparatus using flash memory as medium.Therefore, flash memory industry becomes a ring quite popular in electronic industry in recent years.
Flash memory module has multiple entity erased cell and each entity erased cell has multiple entity program unit (physical page), must be sequentially written in data when wherein writing data in entity erased cell according to entity program unit.In addition, the entity program unit needing being written into data could again for writing data after first being erased.Particularly, entity erased cell is the least unit of erasing, and entity program unit is the minimum unit of sequencing (also claiming to write).Therefore, in the management of flash memory module, entity erased cell can be divided into data field and idle district.
The entity erased cell of data field is the data stored in order to host system.Specifically, the logic access address that host computer system can access by the memorizer control circuit unit in memory storage apparatus is converted to the logical subunit of logical block and the logical subunit of logical block is mapped to the entity program unit of the entity erased cell of data field.That is, in the management of flash memory module, the entity erased cell of data field is regarded as by the entity erased cell (such as, the data that write of host system) used.Such as, memorizer control circuit unit can use logic to turn physical address mapping table to record the mapping relations of the entity erased cell of logical block and data field, and the logical subunit wherein in logical block is the entity program unit of the corresponding entity erased cell mapped.
The entity erased cell in idle district is the entity erased cell of rotating in data field.Specifically, as mentioned above, the entity erased cell of written data just can again for writing data after must being erased, and therefore, the entity erased cell in idle district is designed to write data to replace the entity erased cell of mapping logic block.Base this, the entity erased cell in idle district is empty or spendable entity erased cell, i.e. no record data or be labeled as invalid data useless.
That is, the entity program unit of the entity erased cell in data field and idle district is the logical subunit that the mode of rotating carrys out mapping logic block, the data write with host system.Base this, when host computer system assigns delete instruction to ask to remove the data on logical subunit, the entity program unit that this logical subunit (hereinafter referred to as logical subunit data invalid logical subunit) maps can be labeled as invalid data state by memorizer control circuit unit, completes delete instruction thus.Although, in the management information of memorizer control circuit unit, the entity program unit of mapping logic subelement data invalid logical subunit has been marked as invalid data state, but the data on this entity program unit are not erased practically, therefore, these data still may have the risk be stolen.
Summary of the invention
The invention provides a kind of data erasing method, memorizer control circuit unit and memory storage apparatus, it can be avoided data deleted in type nonvolatile to be reduced and steal.
One embodiment of the invention provide a kind of data erasing method for reproducible nonvolatile memorizer module, this reproducible nonvolatile memorizer module comprises multiple entity erased cell, and each entity erased cell comprises multiple entity program unit.Notebook data erasing method comprises: this little entity erased cell is at least grouped into data field and idle district; And configure multiple logical block, wherein this little logical block comprises multiple logical subunit.Notebook data erasing method comprises: receive write instruction from host computer system and write the first data of instruction with corresponding this, and wherein this writes instruction request and writes in first logical subunit of the first data so far a bit among logical subunit.Notebook data erasing method also comprises: from the entity erased cell in idle district, extract first instance erased cell, write instruction by the first Data programming in the first instance programmed cell of first instance erased cell according to this, and the first logical subunit is mapped to first instance programmed cell.Notebook data erasing method also comprises: receive from host computer system the pre-defined instruction indicating and perform at the first logical subunit; The first instance programmed cell mapped by first logical subunit according to this pre-defined instruction is labeled as invalid data state, and in the specific region of corresponding first instance programmed cell recording mark, to respond this pre-defined instruction.Notebook data erasing method also comprises: confirm the first instance erased cell belonging to the first instance programmed cell that maps of corresponding first logical subunit according to this mark, to be moved by the valid data in first instance erased cell to the second instance erased cell extracted from those entity erased cell in idle district and performs entity to first instance erased cell and erase.
In one embodiment of this invention, above-mentioned data erasing method, also comprises: after first instance erased cell being performed to entity and erasing, delete the mark of corresponding first instance erased cell from garbage reclamation table.
In one embodiment of this invention, the pre-defined instruction that above-mentioned instruction performs on the first logical subunit is the deleted housekeeping instruction of the data be used to indicate on the first logical subunit or the pre-defined write instruction being used to indicate pre-defined aspect data to the first logical subunit of write.
In one embodiment of this invention, the above-mentioned first instance erased cell belonging to first instance programmed cell mapped according to corresponding first logical subunit of mark confirmation, the valid data in first instance erased cell being moved the operation of erasing to the second instance erased cell extracted from the entity erased cell in idle district and to first instance erased cell execution entity is be performed in the background execution pattern of memorizer control circuit unit.
In one embodiment of this invention, above-mentioned specific region is garbage reclamation table.
One embodiment of the invention provide a kind of memorizer control circuit unit for controlling reproducible nonvolatile memorizer module.This memorizer control circuit unit comprises host interface, memory interface and memory management circuitry.Host interface is in order to be electrically connected to host computer system.Memory interface is in order to be electrically connected to reproducible nonvolatile memorizer module, and wherein reproducible nonvolatile memorizer module has multiple entity erased cell and each entity erased cell comprises multiple entity program unit.Memory management circuitry is electrically connected to host interface and memory interface, and in order to this little entity erased cell is at least grouped into data field and idle district.At this, memory management circuitry is also in order to configure multiple logical block, and this little logical block comprises multiple logical subunit.Further, memory management circuitry also writes the first data of instruction in order to receive write instruction from host computer system with corresponding this, and wherein this writes instruction request and writes first logical subunit of the first data so far a bit among logical subunit.In addition, memory management circuitry also in order to extract first instance erased cell from the entity erased cell in idle district, according to this write instruction by the first Data programming to the first instance programmed cell of first instance erased cell, and the first logical subunit is mapped to first instance programmed cell.In addition, memory management circuitry is also in order to receive the pre-defined instruction indicating and perform at the first logical subunit from host computer system.The first instance programmed cell of memory management circuitry also in order to be mapped by the first logical subunit according to this pre-defined instruction is labeled as invalid data state, and recording mark in the specific region of corresponding first instance programmed cell, to respond this pre-defined instruction.Moreover, valid data in first instance erased cell, also in order to confirm the first instance erased cell belonging to the first instance programmed cell that maps of corresponding first logical subunit according to this mark, to be moved to the second instance erased cell extracted from those entity erased cell in idle district and are performed entity to first instance erased cell and erase by memory management circuitry.
In one embodiment of this invention, above-mentioned memory management circuitry also in order to after performing entity to first instance erased cell and erasing, deletes the mark of corresponding first instance erased cell from garbage reclamation table.
In one embodiment of this invention, above-mentioned memory management circuitry performs the above-mentioned first instance erased cell belonging to first instance programmed cell mapped according to corresponding first logical subunit of mark confirmation in background execution pattern, the valid data in first instance erased cell is moved the operation of erasing to the second instance erased cell extracted from the entity erased cell in idle district and to first instance erased cell execution entity.
One embodiment of the invention provide a kind of memory storage apparatus, and it comprises connecting interface unit, reproducible nonvolatile memorizer module and memorizer control circuit unit.Connecting interface unit is in order to be electrically connected to host computer system.Reproducible nonvolatile memorizer module has multiple entity erased cell, and each entity erased cell comprises multiple entity program unit.Memorizer control circuit unit is electrically connected to connecting interface unit and reproducible nonvolatile memorizer module, and in order to this little entity erased cell is at least grouped into data field and idle district.At this, memorizer control circuit unit is also in order to configure multiple logical block, and this little logical block comprises multiple logical subunit.Further, memorizer control circuit unit also writes the first data of instruction in order to receive write instruction from host computer system with corresponding this, and wherein this writes instruction request and writes first logical subunit of the first data so far a bit among logical subunit.In addition, memorizer control circuit unit also in order to extract first instance erased cell from the entity erased cell in idle district, according to this write instruction by the first Data programming to the first instance programmed cell of first instance erased cell, and the first logical subunit is mapped to first instance programmed cell.In addition, memorizer control circuit unit is also in order to receive the pre-defined instruction indicating and perform at the first logical subunit from host computer system.The first instance programmed cell of memorizer control circuit unit also in order to be mapped by the first logical subunit according to this pre-defined instruction is labeled as invalid data state, and recording mark in the specific region of corresponding first instance programmed cell, to respond this pre-defined instruction.Moreover, valid data in first instance erased cell, also in order to confirm the first instance erased cell belonging to the first instance programmed cell that maps of corresponding first logical subunit according to mark, to be moved to the second instance erased cell extracted from those entity erased cell in idle district and are performed entity to first instance erased cell and erase by memorizer control circuit unit.
In one embodiment of this invention, above-mentioned memorizer control circuit unit also in order to after performing entity to first instance erased cell and erasing, deletes the mark of corresponding first instance erased cell from garbage reclamation table.
In one embodiment of this invention, above-mentioned memorizer control circuit unit performs the above-mentioned first instance erased cell belonging to first instance programmed cell mapped according to corresponding first logical subunit of mark confirmation in background execution pattern, the valid data in first instance erased cell is moved the operation of erasing to the second instance erased cell extracted from the entity erased cell in idle district and to first instance erased cell execution entity.
Based on above-mentioned, data erasing method in the embodiment of the present invention, memorizer control circuit unit and memory storage apparatus are after receiving the pre-defined instruction from host computer system, can the entity erased cell that logical subunit data invalid logical subunit maps be marked in garbage reclamation table, and to be erased practically deleted data by data consolidation procedure, avoid deleted data to be reduced thus and steal.
For above-mentioned feature and advantage of the present invention can be become apparent, special embodiment below, and coordinate accompanying drawing to be described in detail below.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of host computer system shown by one embodiment of the invention and memory storage apparatus;
Fig. 2 is the schematic diagram of computer, input/output device and memory storage apparatus shown by the embodiment of the present invention;
Fig. 3 is the schematic diagram of host computer system shown by another embodiment of the present invention and memory storage apparatus;
Fig. 4 is the schematic block diagram that the memory storage apparatus shown in Fig. 1 is shown;
Fig. 5 is the schematic block diagram of the memorizer control circuit unit shown by an embodiment;
Fig. 6 and Fig. 7 is the schematic diagram of the management entity block shown by the first embodiment;
Fig. 8 ~ 20 are schematic diagram of the write data shown by one embodiment of the invention;
Figure 21 and 22 illustrates to perform valid data consolidation procedure to complete the rough schematic view of follow-up write instruction;
Figure 23 and 24 illustrates the operation chart after receiving housekeeping instruction according to one embodiment of the invention;
Figure 25 and Figure 26 is the process flow diagram of the data erasing method shown by one embodiment of the invention.
Description of reference numerals:
1000: host computer system;
1100: computer;
1102: microprocessor;
1104: random access memory;
1106: input/output device;
1108: system bus;
1110: data transmission interface;
1202: mouse;
1204: keyboard;
1206: display;
1208: printer;
1212:U dish;
1214: storage card;
1216: solid state hard disc;
1310: digital camera;
1312:SD card;
1314:MMC card;
1316: memory stick;
1318:CF card;
1320: embedded memory storage;
100: memory storage apparatus;
102: connecting interface unit;
104: memorizer control circuit unit;
106: reproducible nonvolatile memorizer module;
202: memory management circuitry;
204: host interface;
206: memory interface;
208: memory buffer;
212: electric power management circuit;
210: bug check and correcting circuit;
410 (0) ~ 410 (N): entity erased cell;
502: data field;
504: idle district; ;
506: system region
508: replace district;
LBA (0) ~ LBA (H): logical block;
LZ (0) ~ LZ (M): logic region;
UD1 ~ UD14: data;
S2501, S2503, S2505, S2601, S2603, S2605, S2607: the step of data erasing method.
Embodiment
Fig. 1 is the schematic diagram of host computer system shown by one embodiment of the invention and memory storage apparatus.
Please refer to Fig. 1, host computer system 1000 generally comprises computer 1100 and I/O (input/output is called for short I/O) device 1106.Computer 1100 comprises microprocessor 1102, random access memory (randomaccess memory is called for short RAM) 1104, system bus 1108 and data transmission interface 1110.Input/output device 1106 comprises as the mouse 1202 of Fig. 2, keyboard 1204, display 1206 and printer 1208.It must be appreciated, the unrestricted input/output device 1106 of the device shown in Fig. 2, input/output device 1106 can also comprise other devices.
In embodiments of the present invention, storage arrangement 100 is electrically connected by data transmission interface 1110 other elements with host computer system 1000.Data can be write to memory storage apparatus 100 by microprocessor 1102, random access memory 1104 with the operation of input/output device 1106 or read data from memory storage apparatus 100.Such as, memory storage apparatus 100 can be the type nonvolatile memory storage of USB flash disk 1212, storage card 1214 or solid state hard disc (Solid State Drive is called for short SSD) 1216 grades as shown in Figure 2.
Generally speaking, host computer system 1000 is any system that can coordinate to store data substantially with memory storage apparatus 100.Although in the present embodiment, host computer system 1000 explains with computer system, but host computer system 1000 can be the systems such as digital camera, video camera, communicator, audio player or video player in an alternative embodiment of the invention.Such as, when host computer system is digital camera (video camera) 1310, type nonvolatile memory storage is then its SD card 1312 used, mmc card 1314, memory stick (memory stick) 1316, CF card 1318 or embedded memory storage 1320 (as shown in Figure 3).Embedded memory storage 1320 comprises embedded multi-media card (EmbeddedMMC is called for short eMMC).It is worth mentioning that, embedded multi-media card is directly electrically connected on the substrate of host computer system.
Fig. 4 is the schematic block diagram that the memory storage apparatus shown in Fig. 1 is shown.
Please refer to Fig. 4, memory storage apparatus 100 comprises connecting interface unit 102, memorizer control circuit unit 104 and reproducible nonvolatile memorizer module 106.
In the present embodiment, connecting interface unit 102 is compatible to Serial Advanced Technology Attachment (SerialAdvanced Technology Attachment, abbreviate SAT A) standard.But, it must be appreciated, the present invention is not limited thereto, connecting interface unit 102 also can be meet parallel advanced technology annex (ParellelAdvanced Technology Attachment, be called for short PATA) standard, Institute of Electrical and Electric Engineers (Institute of Electrical and Electronic Engineers, IEEE) 1394 standards, high-speed peripheral interconnecting interface (Peripheral Component Interconnect Express, be called for short PCI Express) standard, USB (universal serial bus) (Universal Serial Bus, be called for short USB) standard, a hypervelocity generation (Ultra HighSpeed-I, be called for short UHS-I) interface standard, hypervelocity two generation (Ultra High Speed-II, be called for short UHS-II) interface standard, secure digital (Secure Digital, be called for short SD) interface standard, memory stick (Memory Stick, be called for short MS) interface standard, multimedia storage card (Multi Media Card, be called for short MMC) interface standard, compact flash (Compact Flash, be called for short CF) interface standard, integrated driving electrical interface (IntegratedDevice Electronics, be called for short IDE) standard or other be applicable to standard.In the present embodiment, connecting interface unit can with memorizer control circuit unit package in a chip, or is laid in one and comprises outside the chip of memorizer control circuit unit.
Memorizer control circuit unit 104 in order to perform in the form of hardware or multiple logic gate of form of firmware implementation or steering order, and according to the instruction of host computer system 1000 carry out in reproducible nonvolatile memorizer module 106 data write, read and the operation such as to erase.
Reproducible nonvolatile memorizer module 106 is electrically connected to memorizer control circuit unit 104, and in order to data that host system 1000 writes.Reproducible nonvolatile memorizer module 106 has entity erased cell 410 (0) ~ 410 (N).Such as, entity erased cell 410 (0) ~ 410 (N) can belong to same memory crystal grain (die) or belong to different memory crystal grain.Each entity erased cell has a plurality of entity program unit respectively, and the entity program unit wherein belonging to same entity erased cell can be written independently and side by side be erased.But it must be appreciated, the present invention is not limited thereto, each entity erased cell can be made up of 64 entity program unit, 256 entity program unit or other any entity program unit.
In more detail, entity erased cell is the least unit of erasing.Also namely, each entity erased cell contain minimal amount in the lump by the storage unit of erasing.Entity program unit is the minimum unit of sequencing.That is, entity program unit is the minimum unit of write data.Each entity program unit generally includes data bit district and redundancy ratio special zone.Data bit district comprises multiple entity access address in order to store the data of user, and redundancy ratio special zone is in order to the data (such as, control information and error correcting code) of storage system.In the present embodiment, 4 entity access addresses in the data bit district of each entity program unit, can be comprised, and the size of an entity access address is 512 bytes (byte).But in other embodiments, can comprise the more or less entity access address of number in data bit district, the present invention does not limit size and the number of entity access address yet.Such as, in one embodiment, entity erased cell is solid block, and entity program unit is physical page or entity sector, but the present invention is not as limit.
In the present embodiment, reproducible nonvolatile memorizer module 106 is multilayered memory unit (MultiLevel Cell is called for short MLC) NAND type flash memory module (that is, can store the flash memory module of 2 Bit datas in a storage unit).But, the present invention is not limited thereto, reproducible nonvolatile memorizer module 106 may also be individual layer storage unit (Single Level Cell, be called for short: SLC) NAND type flash memory module (namely, the flash memory module of 1 Bit data can be stored) in a storage unit, plural layer storage unit (Trinary Level Cell, being called for short TLC) NAND type flash memory module is (namely, the flash memory module of 3 Bit datas can be stored) in a storage unit, other flash memory module or other there is the memory module of identical characteristics.
Fig. 5 is the schematic block diagram of the memorizer control circuit unit shown by an embodiment.
Please refer to Fig. 5, memorizer control circuit unit 104 comprises memory management circuitry 202, host interface 204 and memory interface 206.
Memory management circuitry 202 is in order to the integrated operation of control store control circuit unit 104.Specifically, memory management circuitry 202 has multiple steering order, and when memory storage apparatus 100 operates, this little steering order can be performed to carry out data write, read and the operation such as to erase.
In the present embodiment, the steering order of memory management circuitry 202 carrys out implementation with form of firmware.Such as, memory management circuitry 202 has microprocessor unit (not shown) and ROM (read-only memory) (not shown), and this little steering order is burned onto in this ROM (read-only memory).When memory storage apparatus 100 operates, this little steering order can by microprocessor unit perform to carry out data write, read and the operation such as to erase.
In an alternative embodiment of the invention, the steering order of memory management circuitry 202 also can procedure code form be stored in the specific region (such as, being exclusively used in the system region of storage system data in memory module) of reproducible nonvolatile memorizer module 106.In addition, memory management circuitry 202 has microprocessor unit (not shown), ROM (read-only memory) (not shown) and random access memory (not shown).Particularly, this ROM (read-only memory) has driving code, and when memorizer control circuit unit 104 is enabled, microprocessor unit first can perform this and drive code section the steering order be stored in reproducible nonvolatile memorizer module 106 to be loaded in the random access memory of memory management circuitry 202.Afterwards, microprocessor unit can operate this little steering order with carry out data write, read and the operation such as to erase.
In addition, in an alternative embodiment of the invention, the steering order of memory management circuitry 202 also an example, in hardware can carry out implementation.Such as, memory management circuitry 202 comprises microcontroller, Storage Unit Management circuit, storer write circuit, memory reading circuitry, storer erase circuit and data processing circuit.Erase circuit and data processing circuit of Storage Unit Management circuit, storer write circuit, memory reading circuitry, storer is electrically connected to microcontroller.Wherein, Storage Unit Management circuit is in order to manage the entity erased cell of reproducible nonvolatile memorizer module 106; Storer write circuit is in order to assign write instruction data to be write in reproducible nonvolatile memorizer module 106 to reproducible nonvolatile memorizer module 106; Memory reading circuitry is in order to assign reading command to read data from reproducible nonvolatile memorizer module 106 to reproducible nonvolatile memorizer module 106; Storer erases circuit in order to assign instruction of erasing to reproducible nonvolatile memorizer module 106 data to be erased from reproducible nonvolatile memorizer module 106; And data processing circuit is in order to the data processed for writing to reproducible nonvolatile memorizer module 106 and the data read from reproducible nonvolatile memorizer module 106.
Host interface 204 is electrically connected to memory management circuitry 202 and in order to receive and to identify the instruction that transmits of host computer system 1000 and data.That is, the instruction that transmits of host computer system 1000 and data can be sent to memory management circuitry 202 by host interface 204.In the present embodiment, host interface 204 is compatible to SATA standard.But, it must be appreciated and the present invention is not limited thereto, host interface 204 also can be compatible to PATA standard, IEEE1394 standard, PCI Express standard, USB standard, UHS-I interface standard, UHS-II interface standard, SD standard, MS standard, MMC standard, CF standard, IDE standard or other data transmission standards be applicable to.
Memory interface 206 is electrically connected to memory management circuitry 202 and in order to access reproducible nonvolatile memorizer module 106.That is, the data for writing to reproducible nonvolatile memorizer module 106 can be converted to the receptible form of reproducible nonvolatile memorizer module 106 via memory interface 206.
In an embodiment of the present invention, memorizer control circuit unit 104 also comprises memory buffer 208, electric power management circuit 210 and bug check and correcting circuit 212.
Memory buffer 208 is electrically connected to memory management circuitry 202 and comes from the data and instruction of host computer system 1000 in order to temporary or come from the data of reproducible nonvolatile memorizer module 106.
Electric power management circuit 210 is electrically connected to memory management circuitry 202 and in order to the power supply of control store memory storage 100.
Bug check and correcting circuit 212 are electrically connected to memory management circuitry 202 and in order to execution error inspection and correction program to guarantee the correctness of data.Specifically, when memory management circuitry 202 receives write instruction from host computer system 1000, bug check and correcting circuit 212 can be that the corresponding data that this writes instruction produce corresponding bug check and correcting code (Error Checking andCorrecting Code, be called for short ECC Code), and the data of this write instruction corresponding can write in reproducible nonvolatile memorizer module 106 with corresponding bug check and correcting code by memory management circuitry 202.Afterwards, can read bug check corresponding to these data and correcting code when memory management circuitry 202 reads data from reproducible nonvolatile memorizer module 106, and bug check and correcting circuit 212 can according to this bug check and correcting code to read data execution error inspection and correction programs simultaneously.
Fig. 6 and Fig. 7 is the schematic diagram of the management entity block shown by the first embodiment.
Please refer to Fig. 6, entity erased cell 410 (0) ~ 410 (N) logically can be grouped into data field 502, idle district 504, system region 506 and replace district 508 by memorizer control circuit unit 104 (or memory management circuitry 202).
Belonging to data field 502 in logic with the entity erased cell in idle district 504 is in order to store the data coming from host computer system 1000.Specifically, the entity erased cell of data field 502 is the entity erased cell being regarded as storing data, and the entity erased cell in idle district 504 is the entity erased cell in order to replacement data district 502.That is, when receiving the data that write instruction writes with wish from host computer system 1000, memory management circuitry 202 can extract entity erased cell from idle district 504, and data is write in extracted entity erased cell, with the entity erased cell in replacement data district 502.
The entity erased cell belonging to system region 506 is in logic in order to register system data.Such as, system data comprises manufacturer about reproducible nonvolatile memorizer module and model, the entity erased cell number of reproducible nonvolatile memorizer module, the entity program unit number etc. of each entity erased cell.
Belonging to the entity erased cell replaced in district 508 is in logic replace program, with replacing damaged entity erased cell for bad entity erased cell.Specifically, if replace in district 508 still have normal entity erased cell and the entity erased cell of data field 502 damages time, memory management circuitry 202 can extract normal entity erased cell to change the entity erased cell of damage from replacement district 508.
Particularly, data field 502, idle district 504, system region 506 can be different according to different storer specifications with the quantity of the entity erased cell in replacement district 508.In addition, it must be appreciated, in the operation of memory storage apparatus 100, entity erased cell is associated to data field 502, idle district 504, system region 506 can dynamically change with the grouping relation replacing district 508.Such as, when the entity erased cell in idle district 504 damages and is substituted the entity erased cell replacement in district 508, then the entity erased cell originally replacing district 508 can be associated to idle district 504.
Please refer to Fig. 7, memorizer control circuit unit 104 (or memory management circuitry 202) meeting configuration logic unit LBA (0) ~ LBA (H) is with the entity erased cell in mapping (enum) data district 502, and wherein each logical block has the entity program unit of the entity erased cell that multiple logical subunit is answered with mapping pair.And, when host computer system 1000 for write data to logical block or when updating stored in logical block data, memorizer control circuit unit 104 (or memory management circuitry 202) can extract an entity erased cell and write data, with the entity erased cell of data field 502 of rotating from idle district 504.In the present embodiment, logical subunit can be logical page (LPAGE) or logic sector.
Which entity erased cell is data in order to each logical block of identification data be stored in, in the present embodiment, memorizer control circuit unit 104(or memory management circuitry 202) mapping between logical block and entity erased cell can be recorded.And, when host computer system 1000 is in logical subunit during access data, memorizer control circuit unit 104 (or memory management circuitry 202) can confirm the logical block belonging to this logical subunit, and carrys out access data in the entity erased cell mapped in this logical block.Such as, in the present embodiment, memorizer control circuit unit 104 (or memory management circuitry 202) stored logic can turn the entity erased cell that physical address mapping table maps to record each logical block in reproducible nonvolatile memorizer module 106, and logic is turned physical address mapping table and be loaded into memory buffer 208 when for memorizer control circuit unit 104 (or memory management circuitry 202) during access data and safeguard.
It is worth mentioning that, because the finite capacity of memory buffer 208 cannot the mapping table of mapping relations of all logical blocks of stored record, therefore, in the present embodiment, memorizer control circuit unit 104(or memory management circuitry 202) logical block LBA (0) ~ LBA (H) can be grouped into multiple logic region LZ (0) ~ LZ (M), and turn physical address mapping table for each logic region configures a logic.Particularly, when memorizer control circuit unit 104 (or memory management circuitry 202) is for upgrading the mapping of certain logical block, the logic of corresponding logic region belonging to this logical block turns physical address mapping table and can be loaded on memory buffer 208 and be updated.
As mentioned above, in the present embodiment, the reproducible nonvolatile memorizer module 106 of memory storage apparatus 100 manages based on the page, therefore, when performing write instruction, no matter current data are the logical subunit that will write to which logical block, memorizer control circuit unit 104(or memory management circuitry 202) all can continue the mode of an entity program unit to write data (hereinafter also referred to random writing mechanism) with an entity program unit.Specifically, memorizer control circuit unit 104(or memory management circuitry 202) an empty entity erased cell can be extracted from idle district 504 and write data as the entity erased cell used at present.And, when the entity erased cell that this uses at present is fully written, memorizer control circuit unit 104 (or memory management circuitry 202) can extract the entity erased cell of another sky again as the entity erased cell used at present from idle district 504, to continue to write the corresponding data coming from the write instruction of host computer system 1000.Particularly, in order to avoid the entity erased cell in idle district 504 is depleted, when memorizer control circuit unit 104 (or memory management circuitry 202) for from idle district 504, extract entity erased cell and the number of the entity erased cell in idle district 504 drops to set garbage reclamation threshold value time, memorizer control circuit unit 104 (or memory management circuitry 202) first can perform data consolidation procedure, the data at least one entity erased cell of data field 502 are made to become invalid data, and the entity erased cell data stored in data field 502 being all invalid data associates go back to idle district 504, so that the number of the entity erased cell in idle district 504 is greater than set garbage reclamation threshold value.Such as, when performing data consolidation procedure, the entity erased cell that memorizer control circuit unit 104 (or memory management circuitry 202) at least needs use one empty, therefore, garbage reclamation threshold value is set to be greater than the numerical value of 1 to I haven't seen you for ages.
Fig. 8 ~ 20 are schematic diagram of the write data shown by one embodiment of the invention.
Please refer to Fig. 8, for convenience of description, the entity erased cell of mapping logic unit is not initially had (namely in this tentation data district 502, memory storage apparatus 100 not yet write user's data after opening card), idle district 504 has 5 entity erased cell, each entity erased cell has 3 entity program unit, must be written into for the data writing to each entity erased cell according to the order of entity program unit.In addition suppose that memorizer control circuit unit 104 (or memory management circuitry 202) can configure 3 logical blocks and accesses for host computer system 1000, and set garbage reclamation threshold value be 1 wherein each logical block there are 3 logical subunit and the capacity of each logical subunit equals the capacity of 1 entity erased cell.
Please refer to Fig. 9, when to suppose for programming data UD1 and data UD1 be the 1st logical subunit belonging to logical block LBA (0), memorizer control circuit unit 104 (or memory management circuitry 202) can extract entity erased cell 410 (0) from idle district 504, assigns programmed instructions this data UD1 is write to the 0th entity program unit of entity erased cell 410 (0) and entity erased cell 410 (0) is associated to data field 502.
Please refer to Figure 10, hookup 9, when to suppose for reprogramming data UD2 and data UD2 be the 0th logical subunit belonging to logical block LBA (1), memorizer control circuit unit 104 (or memory management circuitry 202) can assign programmed instructions this data UD2 to be write to the 1st entity program unit of entity erased cell 410 (0).
Please refer to Figure 11, continue Figure 10, when to suppose for reprogramming data UD3 and data UD3 be the 1st logical subunit belonging to logical block LBA (2), memorizer control circuit unit 104 (or memory management circuitry 202) can assign programmed instructions this data UD3 to be write to the 2nd entity program unit of entity erased cell 410 (0).
Please refer to Figure 12, continue Figure 11, when to suppose for reprogramming data UD4 and data UD4 be the 0th logical subunit belonging to logical block LBA (0), because entity erased cell 410 (0) is without storage space, therefore, memorizer control circuit unit 104 (or memory management circuitry 202) can extract entity erased cell 410 (1) from idle district 504, assign programmed instructions this data UD4 is write to the 0th entity program unit of entity erased cell 410 (1) and entity erased cell 410 (1) is associated to data field 502.
Please refer to Figure 13, continue Figure 12, when to suppose for reprogramming data UD5 and data UD5 be the 1st logical subunit belonging to logical block LBA (1), memorizer control circuit unit 104 (or memory management circuitry 202) can assign programmed instructions this data UD5 to be write to the 1st entity program unit of entity erased cell 410 (1).
Please refer to Figure 14, continue Figure 13, when to suppose for reprogramming data UD6 and data UD6 be the 2nd logical subunit belonging to logical block LBA (0), memorizer control circuit unit 104 (or memory management circuitry 202) can assign programmed instructions this data UD6 to be write to the 2nd entity program unit of entity erased cell 410 (1).
Please refer to Figure 15, continue Figure 14, when to suppose for reprogramming data UD7 and data UD7 be the 0th logical subunit belonging to logical block LBA (2), because entity erased cell 410 (1) is without storage space, therefore, memorizer control circuit unit 104 (or memory management circuitry 202) can extract entity erased cell 410 (2) from idle district 504, assign programmed instructions this data UD7 is write to the 0th entity program unit of entity erased cell 410 (2) and entity erased cell 410 (2) is associated to data field 502.
Please refer to Figure 16, continue Figure 15, when to suppose for reprogramming data UD8 and data UD8 be the 2nd logical subunit belonging to logical block LBA (1), memorizer control circuit unit 104 (or memory management circuitry 202) can assign programmed instructions this data UD8 to be write to the 1st entity program unit of entity erased cell 410 (2).
Please refer to Figure 17, continue Figure 16, when to suppose for reprogramming data UD9 and data UD9 be the 2nd logical subunit belonging to logical block LBA (2), memorizer control circuit unit 104 (or memory management circuitry 202) can assign programmed instructions this data UD9 to be write to the 2nd entity program unit of entity erased cell 410 (2).
Please refer to Figure 18, continue Figure 17, when to suppose for reprogramming data UD10 and data UD10 be the 2nd logical subunit belonging to logical block LBA (1), because entity erased cell 410 (2) is without storage space, therefore, memorizer control circuit unit 104 (or memory management circuitry 202) can extract entity erased cell 410 (3) from idle district 504, assign programmed instructions this data UD10 is write to the 0th entity program unit of entity erased cell 410 (3) and entity erased cell 410 (3) is associated to data field 502, wherein the 1st entity program unit of entity erased cell 410 (2) can be marked as invalid data state (shown in dotted line).
Please refer to Figure 19, continue Figure 18, when to suppose for reprogramming data UD11 and data UD11 be the 2nd logical subunit belonging to logical block LBA (2), memorizer control circuit unit 104 (or memory management circuitry 202) can assign programmed instructions this data UD11 to be write to the 1st entity program unit of entity erased cell 410 (3), and wherein the 2nd entity program unit of entity erased cell 410 (2) can be marked as invalid data state (shown in dotted line).
Please refer to Figure 20, continue Figure 19, when to suppose for reprogramming data UD12 and data UD12 be the 1st logical subunit belonging to logical block LBA (1), memorizer control circuit unit 104 (or memory management circuitry 202) can assign programmed instructions this data UD12 to be write to the 2nd entity program unit of entity erased cell 410 (3), and wherein the 1st entity program unit of entity erased cell 410 (1) can be marked as invalid data state (shown in dotted line).
By that analogy, no matter host computer system 1000 is for being stored in the logical subunit of which logical block by data, host computer system 1000 can write in the entity erased cell used at present for the data stored by memorizer control circuit unit 104 (or memory management circuitry 202) in order.Particularly, when the number of the entity erased cell in idle district 504 is not more than garbage reclamation threshold value, memorizer control circuit unit 104 (or memory management circuitry 202) can perform data consolidation procedure in the lump when performing write instruction, is exhausted to prevent the entity erased cell in idle district.
Figure 21 and 22 illustrates to perform valid data consolidation procedure to complete the rough schematic view of follow-up write instruction.
Continue Figure 20, when to suppose for reprogramming data UD13 and UD14 and data UD13 and UD14 be the 0th and the 1st logical subunit belonging to logical block LBA (2), because entity erased cell 410 (3) is without storage space, therefore, memorizer control circuit unit 104 (or memory management circuitry 202) needs from idle district 504, extract empty entity erased cell.But now, the number of the entity erased cell in idle district 504 is not more than garbage reclamation threshold value, and therefore, memorizer control circuit unit 104 (or memory management circuitry 202) must first perform data consolidation procedure.
Please refer to Figure 21, such as, memorizer control circuit unit 104 (or memory management circuitry 202) extracts entity erased cell 410 (4) from idle district 504, by the valid data in entity erased cell 410 (1) (namely, data UD4 and UD6) and entity erased cell 410 (2) in valid data (namely, data UD7) copy to entity erased cell 410 (4), entity erased cell 410 (4) is associated to data field 502, it is invalid to be labeled as in the 0th of entity erased cell 410 (1) and the 0th entity program unit of 1 entity program unit and entity erased cell 410 (2), to only storing the entity erased cell of invalid data (namely, entity erased cell 410 (1) and entity erased cell 410 (2)) perform entity and erase, and the entity erased cell after erasing is associated go back to idle district 504.Now, the number of the entity erased cell in idle district 504 can be replied was 2 (being greater than garbage reclamation threshold value).
Please refer to Figure 22, afterwards, memorizer control circuit unit 104 (or memory management circuitry 202) can extract entity erased cell 410 (1) from idle district 504, assign programmed instructions data UD13 and data UD14 is write to the 0th and the 1st entity program unit of entity erased cell 410 (1) and entity erased cell 410 (1) is associated to data field 502, wherein the entity program unit that maps of the 0th and the 1st logical subunit of logical block LBA (2) (namely, 2nd entity program unit of entity erased cell 410 (0) and the 2nd entity program unit of entity erased cell 410 (4)) invalid data state can be marked as.
In this enforcement, memorizer control circuit unit 104 (or memory management circuitry 202) can judge whether to receive pre-defined instruction for performing at a logical subunit from host computer system 1000.Particularly, when judging to receive this pre-defined instruction, special area record one mark of the entity erased cell that memorizer control circuit unit 104 (or memory management circuitry 202) meeting this logical subunit corresponding maps, and according to this mark, above-mentioned data consolidation procedure is performed to the entity erased cell that this logical subunit maps afterwards, perform entity to this entity erased cell thus to erase, so that the data belonging to this logical subunit can fully be removed from memory storage apparatus 100.Such as, when judging to receive this pre-defined instruction, memorizer control circuit unit 104 (or memory management circuitry 202) can record the entity erased cell that this logical subunit maps in a garbage reclamation table, and performs above-mentioned data consolidation procedure according to this garbage reclamation table to the entity erased cell that this logical subunit maps afterwards.
Such as, in one embodiment, garbage reclamation table can be made up of multiple table, and one of them table first records the mapping relations between logical subunit and entity program unit, and the subordinate relation of another table record entity program unit and entity erased cell.Base this, memorizer control circuit unit 104 (or memory management circuitry 202) maps the entity erased cell belonging to entity program unit of a logical subunit by the identification of garbage reclamation table.
Such as, in an embodiment of the present invention, above-mentioned pre-defined instruction is for arranging (Trim) instruction in order to inform which data is no longer used.It must be appreciated, in another embodiment, pre-defined instruction also can be delete instruction (delete command), remove instruction (remove command), batch procedure quick copy instruction (robocopy command), write particular data instruction or other instructions do not re-used in order to indicate which data.Specifically, the housekeeping instruction that memorizer control circuit unit 104 (or memory management circuitry 202) can be assigned according to host computer system 1000 carrys out the data invalid logical subunit among recognition logic subelement and the entity program unit mapped by data invalid logical subunit is identified as sky.At this, data invalid logical subunit refer to storage its on data by host computer system 1000 by file allocation table (File Allocation Table) the logical subunit deleted and host computer system 1000 be no longer considered to use by the data that file system confirms on this logical subunit and this logical subunit can be written into new data.In the present embodiment, file system can be such as the Ext etc. of file allocation table (FileAllocation Table), the NTFS of Windows, HFS+, Linux of Macintosh operating system (OS X).In the present embodiment, when the operating system of host computer system 1000 is Microsft Windows 7, the data that host computer system 1000 can be informed on which logical subunit of memory storage apparatus 100 by housekeeping instruction have been invalid data.That is, data to be deleted and after informing memory storage apparatus 100 by housekeeping instruction, the entity erased cell that this logical subunit can map by memorizer control circuit unit 104 (or memory management circuitry 202) is recorded in garbage reclamation table in host computer system 1000.Afterwards, the data that memorizer control circuit unit 104 (or memory management circuitry 202) can be erased on it to the entity erased cell execution data consolidation procedure that this logical subunit maps practically according to garbage reclamation table, to avoid still being existed in reproducible nonvolatile memorizer module 106 by main frame cognition for deleted data, and have an opportunity to be stolen.
Figure 23 and 24 illustrates the operation chart after receiving housekeeping instruction according to one embodiment of the invention.
Please refer to Figure 23, suppose under the state of such as Figure 22, memory storage apparatus 100 receive housekeeping instruction and this housekeeping instruction inform the 0th logical subunit of logical block LBA (0) in file allocation table data for invalid data time, the entity program unit that 0th logical subunit of logical block LBA (0) can map by memorizer control circuit unit 104 (or memory management circuitry 202) (namely, 0th entity program unit of entity erased cell 410 (4)) be labeled as disarmed state, and in garbage reclamation table, record the mark of correspondent entity erased cell 410 (4), to respond the housekeeping instruction received.In addition, such as, in another embodiment, memorizer control circuit unit 104 (or memory management circuitry 202) also can turn in physical address mapping table the mapping relations of the 0th logical subunit deleting logical block LBA (0) in logic.
Please refer to Figure 24, after the 0th of entity erased cell 410 (4) the entity program unit is labeled as disarmed state, such as, memorizer control circuit unit 104 (or memory management circuitry 202) can leave unused and extract entity in district 504 and smear erased cell 410 (2), by the valid data in entity erased cell 410 (4) (namely, data UD6) and entity erased cell 410 (0) in valid data (namely, data UD1 and data UD2) copy to entity and smear erased cell 410 (2), entity is smeared erased cell 410 (2) and be associated to data field 502, it is invalid to be labeled as in the 0th of entity erased cell 410 (0) and the 1st entity program unit of 1 entity program unit and entity erased cell 410 (4), perform entity to the entity erased cell 410 (0) only storing invalid data with entity erased cell 410 (4) to erase, and the entity erased cell after erasing is associated go back to idle district 504.
It is worth mentioning that, the operation (operating as of fig. 24) of erasing practically to invalid data by performing data consolidation procedure can be perform immediately when receiving housekeeping instruction, or performs in a background execution pattern.Specifically, when memory storage apparatus 100 receives the instruction from host computer system 1000, memorizer control circuit unit 104 (or memory management circuitry 202) need perform immediately and respond host computer system 1000, to avoid time-out.At this, for responding the pattern of the program performed by host computer system 1000, be called prospect execution pattern.Relatively, memorizer control circuit unit 104 (or memory management circuitry 202) also (that is, not receiving the instruction that host computer system 1000 transmits) can operate under leaving unused, such as, and moving data etc.At this, the non-pattern for responding the program performed by host computer system 1000, is called background execution pattern.
Such as, in one embodiment, memorizer control circuit unit 104 (or memory management circuitry 202) can transmit confirmation to host computer system 1000, to represent the operation completing this housekeeping instruction corresponding.Base this, in one embodiment, memorizer control circuit unit 104 (or memory management circuitry 202) can before this confirmation of transmission, perform and operate as of fig. 24, that is, in prospect execution pattern, data consolidation procedure is performed host computer system 1000 to be erased practically for the data of deleting.Or, in another embodiment, memorizer control circuit unit 104 (or memory management circuitry 202) can after this confirmation of transmission, perform and operate as of fig. 24, that is, in background execution pattern, data consolidation procedure is performed host computer system 1000 to be erased practically for the data of deleting.
In addition, it is worth mentioning that, in the present embodiment, memorizer control circuit unit 104 (or memory management circuitry 202) is when identification receives housekeeping instruction, by performing data consolidation procedure host computer system 1000 to be erased practically for the data of deleting.But, the present invention is not limited thereto, in an alternative embodiment of the invention, memorizer control circuit unit 104 (or memory management circuitry 202) also can when the data receiving the pre-defined aspect of instruction write from host computer system 1000 be to write instruction (also referred to as the pre-defined write instruction) of logical subunit, by performing data consolidation procedure the data of this logical subunit to be erased practically.At this, the data of pre-defined aspect can according to the demand sets itself of user, and this is not restricted.
Such as, in an embodiment of the present invention, host computer system 1000 is provided with application program of erasing safely in advance, and when user uses this application program of erasing safely to delete data, safety erases the operating system transmission pre-defined instruction (such as, housekeeping instruction or instruction write the data write instruction to logical subunit of pre-defined aspect) of application program by host computer system 1000 to memory storage apparatus 100.
Figure 25 and Figure 26 is the process flow diagram of the data erasing method shown by one embodiment of the invention.
Please refer to Figure 25, in step S2501, the entity erased cell of reproducible nonvolatile memorizer module 106 can be at least grouped into data field 502 and idle district 504 by memorizer control circuit unit 104 (or memory management circuitry 202), and multiple logical blocks that configuration has multiple logical subunit access for host computer system 1000.
In step S2503, memorizer control circuit unit 104 (or memory management circuitry 202) receives write instruction from host computer system 1000 and writes the data (hereinafter referred to as the first data) of instruction with corresponding this, and wherein this writes instruction request and writes one of them logical subunit (hereinafter referred to as the first logical subunit) among these first data to logical subunit.
In step S2505, memorizer control circuit unit 104 (or memory management circuitry 202) extracts an entity erased cell (hereinafter referred to as first instance erased cell) from the entity erased cell in idle district 504, according to this write instruction by the first Data programming to the entity program unit (hereinafter referred to as first instance programmed cell) of first instance erased cell, and this first logical subunit is mapped to first instance programmed cell.
Please refer to Figure 26, in step S2601, memorizer control circuit unit 104 (or memory management circuitry 202) receives from host computer system 100 the pre-defined instruction indicating and perform at the first logical subunit.
In step S2603, the first instance programmed cell that first logical subunit maps by memorizer control circuit unit 104 (or memory management circuitry 202) is labeled as an invalid data state, and in garbage reclamation table, record a mark of the first instance erased cell belonging to first instance programmed cell that corresponding first logical subunit maps, to respond this pre-defined instruction.
Then, in step S2605, memorizer control circuit unit 104 (or memory management circuitry 202) selects first instance erased cell according to the record of garbage reclamation table, to be moved by the valid data in first instance erased cell in the second instance erased cell extracted to the entity erased cell from idle district 504 and performs entity to first instance erased cell and erase.
Finally, in step S2607, memorizer control circuit unit 104 (or memory management circuitry 202) deletes the mark of corresponding first instance erased cell from garbage reclamation table.
In sum, the data erasing method that the embodiment of the present invention provides, memorizer control circuit unit and memory storage apparatus can according to the requests of host computer system, erase practically in flash memory module for the data of deleting, avoid data to be reduced or to steal thus.
Last it is noted that above each embodiment is only in order to illustrate technical scheme of the present invention, be not intended to limit; Although with reference to foregoing embodiments to invention has been detailed description, those of ordinary skill in the art is to be understood that: it still can be modified to the technical scheme described in foregoing embodiments, or carries out equivalent replacement to wherein some or all of technical characteristic; And these amendments or replacement, do not make the essence of appropriate technical solution depart from the scope of various embodiments of the present invention technical scheme.
Claims (15)
1. a data erasing method, it is characterized in that, for a reproducible nonvolatile memorizer module, this reproducible nonvolatile memorizer module comprises multiple entity erased cell, each those entity erased cell comprises multiple entity program unit, and this data erasing method comprises:
Those entity erased cell are at least grouped into a data field and an idle district;
Configure multiple logical block, wherein those logical blocks comprise multiple logical subunit;
From one host computer system receive one write instruction with to one first data that should write instruction, wherein this write instruction request writes one first logical subunit among these first data to those logical subunit;
A first instance erased cell is extracted from those entity erased cell in this idle district, according to this write instruction by this first Data programming to a first instance programmed cell of this first instance erased cell, and this first logical subunit is mapped to this first instance programmed cell;
The pre-defined instruction indicating and perform at this first logical subunit is received from this host computer system;
This first instance programmed cell mapped by this first logical subunit according to this pre-defined instruction is labeled as an invalid data state, and to should record one mark in a specific region of first instance programmed cell, to respond this pre-defined instruction; And
Confirm should this first instance erased cell belonging to this first instance programmed cell of mapping of the first logical subunit according to this mark, the valid data in this first instance erased cell to be moved to the second instance erased cell extracted from those entity erased cell in this idle district and an entity is performed to this first instance erased cell and erase.
2. data erasing method according to claim 1, is characterized in that, also comprise:
After this first instance erased cell being performed to this entity and erasing, delete should this mark of first instance erased cell from this garbage reclamation table.
3. data erasing method according to claim 1, it is characterized in that, this pre-defined instruction that above-mentioned instruction performs on this first logical subunit is the deleted housekeeping instruction of the data be used to indicate on this first logical subunit or is used to indicate write one and pre-defines the pre-defined write instruction of aspect data to this first logical subunit.
4. data erasing method according to claim 1, it is characterized in that, above-mentionedly confirm should this first instance erased cell belonging to this first instance programmed cell of mapping of the first logical subunit according to this mark, being moved by the valid data in this first instance erased cell to this second instance erased cell extracted from those entity erased cell in this idle district and performing to this first instance erased cell the operation that this entity erases be performed in a background execution pattern of a memorizer control circuit unit.
5. data erasing method according to claim 1, is characterized in that, this specific region is a garbage reclamation table.
6. a memorizer control circuit unit, is characterized in that, for controlling a reproducible nonvolatile memorizer module, this memorizer control circuit unit comprises:
One host interface, in order to be electrically connected to a host computer system;
One memory interface, in order to be electrically connected to this reproducible nonvolatile memorizer module, wherein this reproducible nonvolatile memorizer module has multiple entity erased cell and each those entity erased cell comprises multiple entity program unit; And
One memory management circuitry, is electrically connected to this host interface and this memory interface, and in order to those entity erased cell to be at least grouped into a data field and an idle district;
Wherein this memory management circuitry is also in order to configure multiple logical block, and those logical blocks comprise multiple logical subunit,
Wherein this memory management circuitry also in order to from this host computer system receive one write instruction with to one first data that should write instruction, wherein this write instruction request writes one first logical subunit among these first data to those logical subunit,
Wherein this memory management circuitry also in order to extract a first instance erased cell from those entity erased cell in this idle district, according to this write instruction by this first Data programming to a first instance programmed cell of this first instance erased cell, and this first logical subunit is mapped to this first instance programmed cell
Wherein this memory management circuitry is also in order to receive the pre-defined instruction that instruction performs at this first logical subunit from this host computer system,
Wherein this memory management circuitry this first instance programmed cell also in order to be mapped by this first logical subunit according to this pre-defined instruction is labeled as an invalid data state, and to should record one mark in a specific region of first instance programmed cell, to respond this pre-defined instruction
Wherein this memory management circuitry is also in order to confirm should this first instance erased cell belonging to this first instance programmed cell of mapping of the first logical subunit according to this mark, to be moved by the valid data in this first instance erased cell to the second instance erased cell extracted from those entity erased cell in this idle district and performs an entity to this first instance erased cell and erase.
7. memorizer control circuit unit according to claim 6, it is characterized in that, this memory management circuitry, also in order to after performing this entity to this first instance erased cell and erasing, is deleted should this mark of first instance erased cell from this garbage reclamation table.
8. memorizer control circuit unit according to claim 6, it is characterized in that, this pre-defined instruction that above-mentioned instruction performs on this first logical subunit is the deleted housekeeping instruction of the data be used to indicate on this first logical subunit or is used to indicate write one and pre-defines the pre-defined write instruction of aspect data to this first logical subunit.
9. memorizer control circuit unit according to claim 6, it is characterized in that, this memory management circuitry performs and above-mentionedly confirms should this first instance erased cell belonging to this first instance programmed cell of mapping of the first logical subunit according to this mark in a background execution pattern, to be moved by the valid data in this first instance erased cell to this second instance erased cell extracted from those entity erased cell in this idle district and to perform to this first instance erased cell the operation that this entity erases.
10. memorizer control circuit unit according to claim 6, is characterized in that, this specific region is a garbage reclamation table.
11. 1 kinds of memory storage apparatus, is characterized in that, comprising:
One connecting interface unit, in order to be electrically connected to a host computer system;
One reproducible nonvolatile memorizer module, has multiple entity erased cell, and wherein each those entity erased cell comprises multiple entity program unit; And
One memorizer control circuit unit, is electrically connected to this connecting interface unit and this reproducible nonvolatile memorizer module, and in order to those entity erased cell to be at least grouped into a data field and an idle district;
Wherein this memorizer control circuit unit is also in order to configure multiple logical block, and those logical blocks comprise multiple logical subunit,
Wherein this memorizer control circuit unit also in order to from this host computer system receive one write instruction with to one first data that should write instruction, wherein this write instruction request writes one first logical subunit among these first data to those logical subunit,
Wherein this memorizer control circuit unit also in order to extract a first instance erased cell from those entity erased cell in this idle district, according to this write instruction by this first Data programming to a first instance programmed cell of this first instance erased cell, and this first logical subunit is mapped to this first instance programmed cell
Wherein this memorizer control circuit unit is also in order to receive the pre-defined instruction being instructed in this first logical subunit and performing from this host computer system,
Wherein this memorizer control circuit unit this first instance programmed cell also in order to be mapped by this first logical subunit according to this pre-defined instruction is labeled as an invalid data state, and to should record one mark in a specific region of first instance programmed cell, to respond this pre-defined instruction
Wherein this memorizer control circuit unit is also in order to confirm should this first instance erased cell belonging to this first instance programmed cell of mapping of the first logical subunit according to this mark, to be moved by the valid data in this first instance erased cell to the second instance erased cell extracted from those entity erased cell in this idle district and performs an entity to this first instance erased cell and erase.
12. memory storage apparatus according to claim 11, it is characterized in that, this memorizer control circuit unit, also in order to after performing this entity to this first instance erased cell and erasing, is deleted should this mark of first instance erased cell from this garbage reclamation table.
13. memory storage apparatus according to claim 11, it is characterized in that, this pre-defined instruction that above-mentioned instruction performs on this first logical subunit is the deleted housekeeping instruction of the data be used to indicate on this first logical subunit or is used to indicate write one and pre-defines the pre-defined write instruction of aspect data to this first logical subunit.
14. memory storage apparatus according to claim 11, it is characterized in that, this memorizer control circuit unit performs and above-mentionedly confirms should this first instance erased cell belonging to this first instance programmed cell of mapping of the first logical subunit according to this mark in a background execution pattern, to be moved by the valid data in this first instance erased cell to this second instance erased cell extracted from those entity erased cell in this idle district and to perform to this first instance erased cell the operation that this entity erases.
15. memory storage apparatus according to claim 11, is characterized in that, this specific region is a garbage reclamation table.
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