CN107103930B

CN107103930B - Data writing method, memory control circuit unit and memory storage device

Info

Publication number: CN107103930B
Application number: CN201610093439.2A
Authority: CN
Inventors: 黄嘉彦
Original assignee: Phison Electronics Corp
Current assignee: Phison Electronics Corp
Priority date: 2016-02-19
Filing date: 2016-02-19
Publication date: 2020-05-26
Anticipated expiration: 2036-02-19
Also published as: CN107103930A

Abstract

The invention provides a data writing method, a memory control circuit unit and a memory storage device. The method comprises the following steps: it is determined whether a default command is received from the host system. The method also comprises the following steps: when a default command is received from the host system, the temporary storage data in the buffer memory is written into a first entity erasing unit in the entity erasing units, a second entity erasing unit is selected from the entity erasing units, and effective data in the second entity erasing unit is written into the first entity erasing unit to respond to the default command. The invention can write the data of the buffer memory into the flash memory module and carry out the moving of the effective data when the host system issues the default instruction, thereby avoiding storing invalid data and prolonging the service life of the flash memory module.

Description

Data writing method, memory control circuit unit and memory storage device

Technical Field

The invention relates to a data writing method applied to a rewritable nonvolatile memory, a memory control circuit unit and a memory storage device.

Background

Digital cameras, cellular phones, and MP3 have grown rapidly over the years, resulting in a rapid increase in consumer demand for storage media. Since the rewritable non-volatile memory (rewritable non-volatile memory) has the characteristics of non-volatility, power saving, small volume, no mechanical structure, high read-write speed and the like, the rewritable non-volatile memory is most suitable for portable electronic products such as notebook computers. A solid state disk is a memory storage device using a flash memory module as a storage medium. Therefore, the flash memory industry has become a relatively popular segment of the electronics industry in recent years.

In a NAND-type flash memory module, a physical program unit is composed of a plurality of memory cells arranged on a same word line. The NAND-type flash memory module can be divided into a Single Level Cell (SLC) NAND-type flash memory module, a Multi-Level Cell (MLC) NAND-type flash memory module, and a Triple Level Cell (TLC) NAND-type flash memory module according to the number of bits that can be stored in each memory Cell, wherein each memory Cell of the SLC NAND-type flash memory module can store 1 bit of data (i.e., "1" and "0"), each memory Cell of the MLC NAND-type flash memory module can store 2 bits of data, and each memory Cell of the TLC NAND-type flash memory module can store 3 bits of data.

Since each memory cell of the SLC NAND flash memory module can store 1 bit of data, a plurality of memory cells arranged on a same word line in the SLC NAND flash memory module correspond to one physical program unit.

The floating gate storage layer of each cell of the MLC NAND-type flash memory module can store 2 bits of data, as opposed to the SLC NAND-type flash memory module, wherein each storage state (i.e., "11", "10", "01", and "00") includes a Least Significant Bit (LSB) and a Most Significant Bit (MSB). For example, the value of the 1 st bit from the left side in the storage state is LSB, and the value of the 2 nd bit from the left side is MSB. Therefore, the memory cells arranged on the same word line can constitute 2 physical programming units, wherein the physical programming unit composed of the LSBs of the memory cells is called a lower physical programming unit (low physical programming unit), and the physical programming unit composed of the MSBs of the memory cells is called an upper physical programming unit (upper physical programming unit). In particular, when an error occurs in the upper physical programming unit, the data stored in the lower physical programming unit may be lost.

Similarly, each memory cell in the TLC NAND type flash memory module may store 3 bits of data, wherein each storage state (i.e., "111", "110", "101", "100", "011", "010", "001", and "000") includes the LSB of the 1 st Bit from the left side, the middle Significant Bit (CSB) of the 2 nd Bit from the left side, and the MSB of the 3 rd Bit from the left side. Therefore, the memory cells arranged on the same word line can constitute 3 physical program units, wherein the physical program unit constituted by the LSBs of the memory cells is called a lower physical program unit, the physical program unit constituted by the CSBs of the memory cells is called a middle physical program unit, and the physical program unit constituted by the MSBs of the memory cells is called an upper physical program unit. In particular, in a TLC NAND type flash memory module, to ensure that data of a word line can be stably stored, three times of programming must be performed on the word line. For example, after the first programming of the memory cells of the first word line, the memory cells of the first word line are in the first state (first state). While programming the memory cells of the second word line, the memory cells of the first word line are programmed again. At this time, the memory cell of the first word line is in a foggy state. Then, the memory cells of the first word line and the second word line are programmed again while the memory cells of the third word line are programmed, and at this time, the memory cells of the first word line are in a good state (fine state). Furthermore, the memory cells of the second word line and the third word line are programmed again while the memory cells of the fourth word line are programmed. At this time, the memory cells of the second word line are in a good state, so that the data in the memory cells of the first word line can be stably stored.

In one situation, when the host system issues a suspend command to shut down the host system, a flush command is issued to write the temporary storage data temporarily stored in the buffer memory into the flash memory, so as to prevent the temporary storage data from being lost after power failure. Based on the hardware limitation of the TLC NAND type flash memory module, in order to ensure that the temporary data in the buffer memory is stably stored in the TLC NAND type flash memory module, the memory control circuit unit, after writing the temporary data in the buffer memory into an active physical erase unit of the TLC NAND type flash memory module, programs another three consecutive word lines with dummy data (dummy data) to ensure that the temporary data from the buffer memory is stably stored in the TLC NAND type flash memory module. However, the number of writing or erasing operations of the flash memory module is limited, and writing invalid data may shorten the lifespan of the TLC NAND type flash memory module.

Disclosure of Invention

The invention provides a data writing method, a memory control circuit unit and a memory storage device, which can write data of a buffer memory into a flash memory module and execute the moving of valid data when a host system issues a default instruction, avoid storing invalid data and prolong the service life of the flash memory module.

An exemplary embodiment of the present invention provides a data writing method for a rewritable nonvolatile memory module of a memory storage device, wherein the memory storage device has a buffer memory, the rewritable nonvolatile memory module has a plurality of physical erasing units, and each of the physical erasing units has a plurality of physical programming units. The method comprises the following steps: it is determined whether a default command is received from the host system. The method also comprises the following steps: when a default command is received from the host system, the temporary storage data in the buffer memory is written into a first entity erasing unit in the entity erasing units, and a second entity erasing unit is selected from the entity erasing units. The method also comprises the following steps: and writing the valid data in the second entity erasing unit into the first entity erasing unit.

In an embodiment of the present invention, the step of writing the valid data in the second physically erased cell to the first physically erased cell includes filling the available storage space of the first physically erased cell with the valid data.

In an embodiment of the present invention, the default instruction is a flush instruction or a terminate instruction.

In an embodiment of the invention, the data writing method further includes: judging whether the quantity of the temporary storage data is smaller than a default threshold value or not; writing the dummy data into the first entity erasing unit when the quantity of the temporary storage data is less than the default threshold value; and only when the amount of the temporary data is not less than the default threshold value, selecting the second entity erasing unit from the entity erasing units, and writing the effective data in the second entity erasing unit into the first entity erasing unit.

In an embodiment of the invention, the data writing method further includes performing an erase operation on the second physically erased cell.

In an embodiment of the present invention, the physical programming units include a plurality of lower physical programming units, a plurality of middle physical programming units, and a plurality of upper physical programming units.

An exemplary embodiment of the present invention provides a memory control circuit unit for controlling a rewritable nonvolatile memory module. The memory control circuit unit includes: a host interface for electrically connecting to a host system; the memory interface is electrically connected to the rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module is provided with a plurality of entity erasing units, and each entity erasing unit is provided with a plurality of entity programming units; the buffer memory is electrically connected to the host interface and the memory interface and used for storing temporary storage data; and a memory management circuit electrically connected to the host interface, the memory interface and the buffer memory. The memory management circuit is used for judging whether a default instruction is received from the host system. When the default command is received from the host system, the memory management circuit is further configured to issue a first command sequence to write the temporary data in the buffer memory into a first physical erase unit of the physical erase units, and select a second physical erase unit from the physical erase units. The memory management circuit is further configured to issue a second command sequence to write the valid data in the second physical erase unit into the first physical erase unit.

In one embodiment of the present invention, the operation of writing the valid data in the second physical erase unit into the first physical erase unit includes the memory management circuit filling the available storage space of the first physical erase unit with the valid data.

In an embodiment of the invention, the memory management circuit is further configured to determine whether the amount of the temporary data is smaller than a default threshold, when the amount of the temporary data is smaller than the default threshold, the memory management circuit is further configured to issue a third command sequence to write the dummy data into the first entity erasing unit, and only when the amount of the temporary data is not smaller than the default threshold, the memory management circuit is configured to select the second entity erasing unit from the entity erasing units and issue a second command sequence to write the valid data in the second entity erasing unit into the first entity erasing unit.

In an embodiment of the invention, the memory management circuit is further configured to issue a fourth command sequence to perform an erase operation on the second physically erased unit.

An exemplary embodiment of the present invention provides a memory storage device. It includes: the memory control circuit unit is electrically connected to the connection interface unit and the rewritable nonvolatile memory module. The rewritable nonvolatile memory comprises a plurality of entity erasing units, and each entity erasing unit comprises a plurality of entity programming units. The memory control circuit unit comprises a buffer memory used for storing temporary data. The memory control circuit unit is used for judging whether a default instruction is received from the host system. When the default command is received from the host system, the memory control circuit unit is further configured to issue a first command sequence to write the temporary data in the buffer memory into a first physical erase unit of the physical erase units, and select a second physical erase unit from the physical erase units. The memory control circuit unit is further used for issuing a second instruction sequence to write the valid data in the second entity erasing unit into the first entity erasing unit.

In an embodiment of the present invention, the operation of writing the valid data in the second physical erase unit into the first physical erase unit includes the memory control circuit unit filling the available storage space of the first physical erase unit with the valid data.

In an embodiment of the present invention, the default instruction is a flush instruction or a stop instruction

In an embodiment of the invention, the memory control circuit unit is further configured to determine whether the amount of the temporary data is smaller than a default threshold, when the amount of the temporary data is smaller than the default threshold, the memory control circuit unit is further configured to issue a third command sequence to write the dummy data into the first physical erase unit, and only when the amount of the temporary data is not smaller than the default threshold, the memory control circuit unit is configured to select the second physical erase unit from the physical erase units and issue a second command sequence to write the valid data in the second physical erase unit into the operation memory control circuit unit of the first physical erase unit.

In an embodiment of the invention, the memory control circuit unit is further configured to issue a fourth command sequence to perform an erase operation on the second physically erased cell.

Based on the above, the data writing method of the present invention can store the temporary data of the buffer memory into the entity erasing unit in the rewritable nonvolatile memory when receiving the default command issued by the host system, and write the valid data in other entity erasing units into the entity erasing unit, thereby effectively improving the utilization efficiency of the rewritable nonvolatile memory and prolonging the life of the rewritable nonvolatile memory.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device, according to an example embodiment;

FIG. 2 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device, according to another example embodiment;

FIG. 3 is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the invention;

FIG. 4 is a schematic block diagram illustrating a host system and a memory storage device according to an example embodiment;

FIGS. 5A and 5B are schematic diagrams of a memory cell storage architecture and physically erased cells according to an example embodiment;

FIG. 6 is a schematic block diagram of memory control circuitry shown in accordance with an example embodiment;

FIGS. 7 and 8 illustrate exemplary managing physical erase units according to one exemplary embodiment;

FIGS. 9A-9C illustrate exemplary data writes according to an exemplary embodiment;

FIG. 10 is a flowchart illustrating a data writing method according to an example embodiment.

Reference numerals:

10: memory storage device

11: host system

12: input/output (I/O) device

110: system bus

111: processor with a memory having a plurality of memory cells

112: random Access Memory (RAM)

113: read-only memory (ROM)

114: data transmission interface

20: main board

201: portable disc

202: memory card

203: 204 of solid state disk: wireless memory storage device

205: global positioning system module

206: network adapter

207: wireless transmission device

208: keyboard with a keyboard body

209: screen

210: horn type loudspeaker

30: memory storage device

31: host system

32: SD card

33: CF card

34: embedded memory device

341: embedded multimedia card

342: embedded multi-chip packaging storage device

402: connection interface unit

404: memory control circuit unit

406: rewritable nonvolatile memory module

410(0) to 410 (N): physical erase unit

502: memory management circuit

504: host interface

506: memory interface

508: buffer memory

510: power management circuit

512: error checking and correcting circuit

602: data area

604: idle zone

606: system area

608: substitution zone

LBA (0) to LBA (h): logical addresses

LZ (0) to LZ (M): logical area

D0(0) to D0(41), D1(0) to D1(41), D2(0) to D2 (85): valid data

BD (1), BD (2): temporary storage data

S1001: step for judging whether to receive default instruction from host computer system

S1003: writing the temporary data in the buffer memory into a first entity erasing unit in the entity erasing units when a default command is received from the host system

S1005: step for judging whether the quantity of the temporary storage data is less than the default threshold value

S1007: writing dummy data into first physically erased cells

S1009: selecting a second physically erased cell from the physically erased cells

S1011: writing the valid data in the second physically erased cell into the first physically erased cell

Detailed Description

Generally, a memory storage device (also referred to as a memory storage system) includes a rewritable nonvolatile memory module and a controller (also referred to as a control circuit unit). Typically, memory storage devices are used with a host system so that the host system can write data to or read data from the memory storage devices.

FIG. 1 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device, according to an example embodiment. And FIG. 2 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device, according to another example embodiment.

Referring to fig. 1 and 2, the host system 11 generally includes a processor 111, a Random Access Memory (RAM) 112, a Read Only Memory (ROM) 113, and a data transmission interface 114. The processor 111, the RAM 112, the ROM 113, and the data transmission interface 114 are all electrically connected to the system bus (system bus) 110.

In the present exemplary embodiment, the host system 11 is electrically connected to the memory storage device 10 through the data transmission interface 114. For example, host system 11 may write data to memory storage device 10 or read data from memory storage device 10 via data transfer interface 114. In addition, the host system 11 is electrically connected to the I/O device 12 via a system bus 110. For example, the host system 11 may transmit output signals to the I/O device 12 or receive input signals from the I/O device 12 via the system bus 110.

In the present exemplary embodiment, the processor 111, the random access memory 112, the read only memory 113 and the data transmission interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. Through the data transmission interface 114, the main board 20 can be electrically connected to the memory storage device 10 through a wired or wireless manner. The memory storage device 10 may be a flash Drive 201, a memory card 202, a Solid State Drive (SSD) 203, or a wireless memory storage device 204, for example. The wireless memory Storage device 204 can be a memory Storage device based on various wireless communication technologies, such as Near Field Communication (NFC) memory Storage device, wireless facsimile (WiFi) memory Storage device, Bluetooth (Bluetooth) memory Storage device, or Bluetooth low energy memory Storage device (e.g., iBeacon). In addition, the motherboard 20 may also be electrically connected to various I/O devices such as a Global Positioning System (GPS) module 205, a network adapter 206, a wireless transmission device 207, a keyboard 208, a screen 209, and a speaker 210 through the System bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 via the wireless transmission device 207.

In an exemplary embodiment, the host system is referred to as any system that can substantially cooperate with a memory storage device to store data. Although the host system is described as a computer system in the above exemplary embodiment, FIG. 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment. Referring to fig. 3, in another exemplary embodiment, the host system 31 may also be a digital camera, a video camera, a communication device, an audio player, a video player, a tablet computer, or the like, and the memory storage device 30 may be various non-volatile memory storage devices such as an SD card 32, a CF card 33, or an embedded storage device 34 used therein. The embedded memory device 34 includes various types of embedded Multi-media cards (eMMC) 341 and/or embedded Multi-chip package memory devices (eMCP) 342 to electrically connect the memory module directly to the embedded memory device on the substrate of the host system.

FIG. 4 is a schematic block diagram illustrating a host system and a memory storage device according to an example embodiment.

Referring to fig. 4, the memory storage device 10 includes a connection interface unit 402, a memory control circuit unit 404 and a rewritable nonvolatile memory module 406.

In the exemplary embodiment, connection interface unit 402 is compliant with the Serial Advanced Technology Attachment (SATA) standard. However, it should be understood that the present invention is not limited thereto, and the connection interface unit 402 may also conform to the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronic Engineers (IEEE) 1394 standard, the High-Speed Peripheral Component connection interface (PCI Express) standard, the Universal Serial Bus (USB) standard, the Ultra High Speed Specification-I (UHS-I) interface standard, the Ultra High Speed Specification-II (UHS-II) interface standard, the Secure Digital (SD) interface standard, the Memory Stick (Memory Stick, MS) interface standard, the Multi-Chip Package (Multi-P Package) interface standard, the Multi-Media storage Card (Multi-Media, Embedded Multimedia Card (MMC), eMMC) interface standard, Universal Flash Storage (UFS) interface standard, embedded Multi-Chip Package (eMCP) interface standard, Compact Flash (CF) interface standard, Integrated Device Electronics (IDE) standard, or other suitable standard. In the present exemplary embodiment, the connection interface unit 402 and the memory control circuit unit 404 may be packaged in one chip, or the connection interface unit 402 is disposed outside a chip including the memory control circuit unit.

The memory control circuit unit 404 is used for executing a plurality of logic gates or control commands implemented in a hardware type or a firmware type, and performing operations such as writing, reading and erasing data in the rewritable nonvolatile memory module 406 according to commands of the host system 11.

The rewritable nonvolatile memory module 406 is electrically connected to the memory control circuit unit 404 and is used for storing data written by the host system 11. The rewritable nonvolatile memory module 406 has physical erase units 410(0) -410 (N). For example, the physical erase units 410(0) -410 (N) may belong to the same memory die (die) or to different memory dies. Each entity erasing unit is respectively provided with a plurality of entity programming units, wherein the entity programming units belonging to the same entity erasing unit can be independently written and simultaneously erased. However, it should be understood that the invention is not limited thereto, and each of the plurality of physically erased cells may be composed of 64 physically programmed cells, 256 physically programmed cells, or any other number of physically programmed cells.

In more detail, the physically erased cell is the minimum unit of erase. That is, each physically erased cell contains one of the minimum number of memory cells that are erased. The physical programming unit is a minimum unit for programming. That is, the physical programming unit is the minimum unit for writing data. Each physical programming cell typically includes a data bit region and a redundancy bit region. The data bit region includes a plurality of physical access addresses for storing user data, and the redundant bit region is used for storing system data (e.g., control information and error correction codes). In the exemplary embodiment, each physical program unit includes 8 physical access addresses in the data bit region, and one physical access address has a size of 512 bytes (byte). However, in other exemplary embodiments, the data bit region may include a greater or lesser number of physical access addresses, and the size and number of the physical access addresses are not limited in the present invention. For example, in an exemplary embodiment, the physically erased cells are physical blocks, and the physically programmed cells are physical pages or physical sectors, but the invention is not limited thereto.

In the present exemplary embodiment, the rewritable nonvolatile memory module 406 is a multi-level Cell (TLC) NAND-type flash memory module (i.e., a flash memory module capable of storing 3 bits of data in one memory Cell). However, the invention is not limited thereto, and the rewritable nonvolatile memory module 406 may also be a Multi-level cell (MLC) NAND-type flash memory module (i.e., a flash memory module capable of storing 2 data bits in one memory cell) or other memory modules with the same characteristics.

FIGS. 5A and 5B are schematic diagrams illustrating an example memory cell storage architecture and physically erased cells according to an example embodiment.

Referring to fig. 5A, the storage status of each memory cell of the rewritable nonvolatile memory module 406 can be identified as "111", "110", "101", "100", "011", "010", "001", or "000" (as shown in fig. 5A), wherein the 1 st bit from the left side is LSB, the 2 nd bit from the left side is CSB, and the 3 rd bit from the left side is MSB. In addition, the memory cells arranged on the same word line may constitute 3 physical program units, wherein the physical program unit constituted by the LSBs of the memory cells is referred to as a lower physical program unit, the physical program unit constituted by the CSBs of the memory cells is referred to as a middle physical program unit, and the physical program unit constituted by the MSBs of the memory cells is referred to as an upper physical program unit.

Referring to FIG. 5B, a physical erase unit is composed of a plurality of physical program unit groups, wherein each physical program unit group includes a lower physical program unit, a middle physical program unit and an upper physical program unit composed of a plurality of memory cells arranged on the same word line. For example, in the solid erase cell, the 0 th solid program cell belonging to the lower solid program cell, the 1 st solid program cell belonging to the middle solid program cell, and the 2 nd solid program cell belonging to the upper solid program cell are regarded as one solid program cell group. Similarly, the 3 rd physical programming cell, the 4 th physical programming cell, and the 5 th physical programming cell are regarded as one physical programming cell group, and the other physical programming cells are divided into a plurality of physical programming cell groups according to the same manner. That is, in the exemplary embodiment of FIG. 5B, there are 258 physical program cells in total, and since the lower, middle and upper physical program cells, which are composed of the plurality of memory cells arranged on the same word line, constitute one physical program cell group, the physical erase cells of FIG. 5B can be divided into 86 physical program cell groups in total. It should be noted, however, that the present invention is not limited to the number of the physically programmed cells or the physically programmed cell groups in the physically erased cells.

FIG. 6 is a schematic block diagram of a memory control circuit unit shown in accordance with an example embodiment.

Referring to FIG. 6, the memory control circuit unit 404 includes a memory management circuit 502, a host interface 504, a memory interface 506, a buffer memory 508, a power management circuit 510, and an error checking and correcting circuit 512.

The memory management circuit 502 is used to control the overall operation of the memory control circuit unit 404. Specifically, the memory management circuit 502 has a plurality of control commands, and the control commands are executed to perform data writing, reading, and erasing operations during the operation of the memory storage device 10.

In the exemplary embodiment, the control instructions of the memory management circuit 502 are implemented in firmware. For example, the memory management circuit 502 has a microprocessor unit (not shown) and a read only memory (not shown), and the control commands are recorded in the read only memory. When the memory storage device 10 is in operation, the control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.

FIGS. 7 and 8 illustrate exemplary diagrams of managing physically erased cells, according to an exemplary embodiment.

It should be understood that, when describing the operation of the physically erased cells of the rewritable non-volatile memory module 406, it is a logical concept to operate the physically erased cells by the words "extract", "group", "partition", "associate", and the like. That is, the physical locations of the physical erase units of the rewritable nonvolatile memory module are not changed, but the physical erase units of the rewritable nonvolatile memory module are logically operated.

Referring to FIG. 7, the memory control circuit unit 404 (or the memory management circuit 502) logically groups the physical erase units 410(0) -410 (N) into a data area 602, an idle area 604, a system area 606, and a replacement area 608.

The physically erased cells logically belonging to the data area 602 and the idle area 604 are used for storing data from the host system 11. Specifically, the wear-leveling cells in the data area 602 are regarded as the wear-leveling cells storing data, and the wear-leveling cells in the idle area 604 are used to replace the wear-leveling cells in the data area 602. That is, when receiving a write command and data to be written from the host system 11, the memory management circuit 502 writes the data by extracting the physical erase unit from the idle region 604 to replace the physical erase unit in the data region 602.

The physically erased cells logically belonging to the system area 606 are used for recording system data. For example, the system data includes information about the manufacturer and model of the rewritable nonvolatile memory module, the number of physically erased cells of the rewritable nonvolatile memory module, the number of physically programmed cells per each physically erased cell, and the like.

The physically erased cells logically belonging to the replacement area 608 are used in the bad-physically-erased-cell replacement procedure to replace the damaged physically erased cells. Specifically, if there are normal physically erased cells in the replacement area 608 and the physically erased cells in the data area 602 are damaged, the memory management circuit 502 extracts the normal physically erased cells from the replacement area 608 to replace the damaged physically erased cells.

In particular, the number of physically erased cells in the data area 602, the idle area 604, the system area 606 and the replacement area 608 may vary according to different memory specifications. Moreover, it should be appreciated that during operation of memory storage device 10, the grouping of physically erased cells associated with data area 602, idle area 604, system area 606, and replacement area 608 may dynamically change. For example, when the physically erased cells in the idle area 604 are damaged and replaced by the physically erased cells in the replacement area 608, the physically erased cells in the replacement area 608 are associated with the idle area 604.

Referring to fig. 8, the memory control circuit unit 404 (or the memory management circuit 502) configures logical addresses LBA (0) to LBA (h) to map the physical erase units of the data area 602, where each logical address has a plurality of logical units to map the physical programming units of the corresponding physical erase units. Moreover, when the host system 11 is going to write data to the logical address or update the data stored in the logical address, the memory control circuit unit 404 (or the memory management circuit 502) will extract one physical erase unit from the idle area 604 as an active physical erase unit to write data, so as to replace the physical erase unit of the data area 602. Moreover, when the physical erase unit as the active physical erase unit is full, the memory control circuit unit 404 (or the memory management circuit 502) will extract the empty physical erase unit from the idle area 504 as the active physical erase unit to continue writing the update data corresponding to the write command from the host system 1000. In addition, when the number of available physical erase units in the idle area 604 is smaller than a predetermined value, the memory control circuit unit 404 (or the memory management circuit 502) performs a valid data merging procedure (also called a garbage collection procedure) to collate the valid data in the data area 602 so as to re-associate the physical erase units in the data area 602 that do not store the valid data with the idle area 604.

In order to identify the physical erase unit in which the data of each logical address is stored, in the present exemplary embodiment, the memory control circuit unit 404 (or the memory management circuit 502) records the mapping between the logical address and the physical erase unit. For example, in the present exemplary embodiment, the memory control circuit unit 404 (or the memory management circuit 502) stores a mapping table of logical addresses and physical addresses in the rewritable nonvolatile memory module 406 to record the physical erase unit mapped by each logical address. When data is to be accessed, the memory control circuit unit 404 (or the memory management circuit 502) loads the logical address-physical address mapping table into the buffer memory 508 for maintenance, and writes or reads data according to the logical address-physical address mapping table.

It should be noted that, since the buffer 508 has a limited capacity and cannot store a mapping table for recording mapping relationships of all logical addresses, in the exemplary embodiment, the memory control circuit unit 404 (or the memory management circuit 502) groups the logical addresses LBA (0) -LBA (h) into a plurality of logical zones LZ (0) -LZ (m), and configures a logical address-physical address mapping table for each logical zone. In particular, when the memory control circuit unit 404 (or the memory management circuit 502) wants to update the mapping of a logical address, the logical address-physical address mapping table corresponding to the logical area to which the logical address belongs is loaded into the buffer memory 508 for updating.

In another exemplary embodiment of the invention, the control instructions of the memory management circuit 502 can also be stored in a specific area of the rewritable nonvolatile memory module 406 (for example, a system area dedicated to storing system data in the memory module) by using a program code type. In addition, the memory management circuit 502 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the ROM has a driver, and when the memory control circuit 404 is enabled, the microprocessor first executes the driver to load the control command stored in the rewritable nonvolatile memory module 406 into the RAM of the memory management circuit 502. Then, the microprocessor unit operates the control commands to perform data writing, reading, erasing, and the like.

In another exemplary embodiment of the invention, the control instructions of the memory management circuit 502 can also be implemented in a hardware form. For example, the memory management circuit 502 includes a microcontroller, a cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory cell management circuit, the memory writing circuit, the memory reading circuit, the memory erasing circuit and the data processing circuit are electrically connected to the microcontroller. The memory cell management circuit is used for managing the entity erasing unit of the rewritable nonvolatile memory module 406; the memory writing circuit is used for issuing a writing instruction to the rewritable nonvolatile memory module 406 so as to write data into the rewritable nonvolatile memory module 406; the memory reading circuit is used for sending a reading instruction to the rewritable nonvolatile memory module 406 so as to read data from the rewritable nonvolatile memory module 406; the memory erasing circuit is used for issuing an erasing instruction to the rewritable nonvolatile memory module 406 so as to erase data from the rewritable nonvolatile memory module 406; the data processing circuit is used for processing data to be written into the rewritable nonvolatile memory module 406 and data read from the rewritable nonvolatile memory module 406.

Referring to fig. 6, the host interface 504 is electrically connected to the memory management circuit 502 and is electrically connected to the connection interface unit 402 for receiving and recognizing commands and data transmitted by the host system 11. That is, commands and data transmitted by the host system 11 are transmitted to the memory management circuit 502 through the host interface 504. In the exemplary embodiment, host interface 504 is compliant with the SATA standard. However, it should be understood that the present invention is not limited thereto, and the host interface 504 may also be compatible with the PATA standard, the IEEE 1394 standard, the PCI Express standard, the USB standard, the UHS-I interface standard, the UHS-II interface standard, the SD standard, the MS standard, the MMC standard, the CF standard, the IDE standard or other suitable data transmission standards.

The memory interface 506 is electrically connected to the memory management circuit 502 and is used for accessing the rewritable nonvolatile memory module 406. That is, the data to be written to the rewritable nonvolatile memory module 406 is converted into a format accepted by the rewritable nonvolatile memory module 406 through the memory interface 506.

The buffer memory 508 is electrically connected to the memory management circuit 502 and is used for temporarily storing temporary data and instructions from the host system 11 or data from the rewritable nonvolatile memory module 406.

The power management circuit 510 is electrically connected to the memory management circuit 502 and is used for controlling the power of the memory storage device 10.

The error checking and correcting circuit 512 is electrically connected to the memory management circuit 502 and is used for performing an error checking and correcting process to ensure the correctness of data. Specifically, when the memory management circuit 502 receives a write command from the host system 11, the Error Checking and Correcting circuit 512 generates an Error Checking and Correcting Code (ECC Code) corresponding to the data corresponding to the write command, and the memory management circuit 502 writes the data corresponding to the write command and the corresponding ECC Code into the rewritable nonvolatile memory module 406. Thereafter, when the memory management circuit 502 reads data from the rewritable nonvolatile memory module 406, the corresponding error checking and correcting codes are simultaneously read, and the error checking and correcting circuit 512 performs an error checking and correcting process on the read data according to the error checking and correcting codes.

In the exemplary embodiment, when the host system 11 issues a suspend command to shut down the host system 11, the host system 11 also issues a flush command to write the temporary storage data temporarily stored in the buffer memory into the rewritable non-volatile memory module 406, so as to prevent the temporary storage data from being lost after power failure. In another exemplary embodiment, when the host system 11 issues a termination command to shut down the host system 11, the memory control circuit unit 404 (or the memory management circuit 502) automatically performs a flush operation to write the temporary data temporarily stored in the buffer memory into the rewritable nonvolatile memory module 406. Next, the memory control circuit unit 404 (or the memory management circuit 502) determines whether a default command, such as the above-mentioned flush command or the termination command, is received from the host system 11. It is assumed that when the memory control circuit unit 404 (or the memory management circuit 502) receives the default command from the host system 11, the memory control circuit unit 404 (or the memory management circuit 502) executes the data writing method of the present invention. Specifically, when the memory control circuit unit 404 (or the memory management circuit 502) receives the default command from the host system 11, the memory control circuit unit 404 (or the memory management circuit 502) will issue a command sequence to write the temporary data in the buffer memory 508 into an active physical erase unit (hereinafter, referred to as a first physical erase unit) among the physical erase units 410(0) to 410(N) of the rewritable nonvolatile memory module 406, so as to prevent the temporary data from being lost after power-off. In the exemplary embodiment, the memory control circuit unit 404 (or the memory management circuit 502) selects the first physically erased cell from one of the physically erased cells 410(F) -410 (S-1) in the idle region 604.

It should be noted that, after the memory control circuit unit 404 (or the memory management circuit 502) writes the temporary data in the buffer memory 508 into the first physically erased unit, if the first physically erased unit still has available storage space (i.e., the first physically erased unit is not filled with the temporary data in the buffer memory 508), the memory control circuit unit 404 (or the memory management circuit 502) writes valid data into the first physically erased unit from other physically erased units of the rewritable nonvolatile memory module 406. For example, in the present exemplary embodiment, the memory control circuit unit 404 (or the memory management circuit 502) selects the physical erase unit (hereinafter referred to as the second physical erase unit) storing valid data from the physical erase units 410(0) -410 (F-1) of the data area 602. Thereafter, the memory control circuit unit 404 (or the memory management circuit 502) will execute a command sequence to write the valid data in the second physical erase units into the first physical erase units and fill the available storage space in the first physical erase units with the valid data. In particular, if the valid data in the second physically erased cell is written into the first physically erased cell, the data in the second physically erased cell becomes invalid data. In particular, when all the data in the second physically erased cells become invalid data, the memory control circuit unit 404 (or the memory management circuit 502) can erase the second physically erased cells and group the second physically erased cells into the idle area 602 to release the storage space available for the rewritable non-volatile memory module 406.

It should be noted that, in an exemplary embodiment of the invention, after the operation of the memory control circuit unit 404 (or the memory management circuit 502) writing the temporary data in the buffer memory 508 into the first physical erase unit and before the operation of the memory control circuit unit 404 (or the memory management circuit 502) selecting the second physical erase unit, the memory control circuit unit 404 (or the memory management circuit 502) may further determine whether the amount of the temporary data is smaller than a default threshold. When the amount of temporary data is smaller than the default threshold, the memory control circuit unit 404 (or the memory management circuit 502) will issue a command sequence to write at least one dummy data into the first physical erase unit. Only when the amount of the temporary data is not less than the default threshold, the memory control circuit unit 404 (or the memory management circuit 502) will execute the above-mentioned operation of selecting the second entity erasing unit from the entity erasing units 410(0) -410 (N), and issue the command sequence to write the valid data in the second entity erasing unit into the first entity erasing unit.

To more clearly understand the data writing method of the present invention, fig. 9A to 9C are exemplary diagrams illustrating data writing according to an exemplary embodiment.

For convenience of illustration, it is assumed that the data area 602 of the rewritable nonvolatile memory module 406 has 3 physically erased units, i.e., the physically erased units 410(0) to 410(2), and the idle area 604 has 2 physically erased units, i.e., the physically erased units 410(3) to 410 (4). In particular, in the exemplary embodiment of fig. 9A-9C, the rewritable nonvolatile memory module 406 is a TLC NAND type flash memory module, that is, each of the physical erase units 410(0) -410 (4) has a physical program unit including a plurality of lower physical program units, a plurality of middle physical program units, and a plurality of upper physical program units. Based on the characteristic that the cells of each word line in the TLC NAND type flash memory module must be programmed three times to ensure that the data of the cells is stably stored, it is assumed in the example of fig. 9A to 9C that the data is written in units of one "physical program cell group" and each physical erase cell has 86 physical program cell groups. The detailed description of the physical programming unit group of the TLC NAND-type flash memory module is described in the previous exemplary embodiments of fig. 5A and 5B, and thus, the detailed description thereof is omitted here. It should be noted that the present invention is not limited thereto, and in other exemplary embodiments, the data may be written in units of one physical programming unit or smaller.

Referring to fig. 9A, it is assumed that in the state of the memory storage device 10 in fig. 9A, the 0 th to 41 th physical programming unit groups of the physical erase unit 410(0) in the data area 602 store the valid data D0(0) to D0(41), the 0 th to 41 th physical programming unit groups of the physical erase unit 410(1) store the valid data D1(0) to D1(41), and the 0 th to 85 th physical programming unit groups of the physical erase unit 410(2) store the valid data D2(0) to D2(85), respectively. The data stored in the 42 th to 85 th physical programming unit groups of the physical erase unit 410(0) and the data stored in the 42 th to 85 th physical programming unit groups of the physical erase unit 410(1) are respectively identified as invalid data by the memory control circuit unit 404 (or the memory management circuit 502).

It is assumed that in the state of fig. 9A, the host system 11 issues a termination command to shut down the host system 11, and the host system 11 concurrently issues a flush command to write the temporary data temporarily stored in the buffer memory into the rewritable nonvolatile memory module 406. At this time, after the memory control circuit unit 404 (or the memory management circuit 502) receives the termination command or the flush command from the host system 11, the memory control circuit unit 404 (or the memory management circuit 502) selects, for example, the physical erase unit 410(3) (hereinafter, referred to as a first physical erase unit) from the idle area 604 for storing the temporary data in the buffer memory 508. In the present exemplary embodiment, assuming that the temporary data stored in the buffer memory 508 are temporary data BD (1) -BD (2), the memory control circuit unit 404 (or the memory management circuit 502) will issue a command sequence to write the temporary data BD (1) -BD (2) stored in the buffer memory 508 into the 1 st to 2 nd sets of physical programming cells of the physical erase unit 410(3), respectively.

It should be noted that, in an embodiment of the invention, after the memory control circuit unit 404 (or the memory management circuit 502) writes the temporary data BD (1) -BD (2) in the buffer memory 508 into the 1 st to 2 nd physical programming cell groups of the physical erase unit 410(3), respectively, the memory control circuit unit 404 (or the memory management circuit 502) may further determine whether the number of the temporary data BD (1) -BD (2) is smaller than a default threshold.

In an exemplary embodiment, the default threshold may be set to 43, for example. When the amount of the temporary data BD (1) -BD (2) is smaller than the default threshold, the memory control circuit unit 404 (or the memory management circuit 502) will issue a command sequence to fill the physical erasing unit 410(3) with at least one dummy data to fill the remaining storage space after storing the temporary data BD (1) -BD (2). In another exemplary embodiment, based on the characteristic that a word line of memory cells is programmed three times before the data in the word line of memory cells is stably stored, when the amount of the temporary data BD (1) -BD (2) is smaller than the default threshold value, the memory control circuit unit 404 (or the memory management circuit 502) may also write at least one dummy data into the "partial" available storage space after the temporary data BD (1) -BD (2) is stored, wherein the amount of the dummy data for writing into the physical erasing unit 410(3) is just enough to stably store the temporary data BD (1) -BD (2) in the physical erasing unit 410 (3). That is, in this exemplary embodiment, the dummy data written into the physical erase unit 410(3) may not need to fill up the remaining storage space of the physical erase unit 410(3) after storing the temporary data BD (1) -BD (2), and the memory control circuit unit 404 (or the memory management circuit 502) may only write a specific or unspecified amount of dummy data such that the temporary data BD (1) -BD (2) can be stably stored in the physical erase unit 410 (3).

It should be understood, however, that the invention is not limited to the values of the default threshold, and in other exemplary embodiments, the default threshold may be other suitable values. In addition, the present invention is not limited to the amount of dummy data for writing to the physical erase unit 410 (3).

In the present exemplary embodiment, as shown in fig. 9A to 9C, it is assumed that the default threshold is set to 1. Since the amount of the temporary data BD (1) -BD (2) is not less than the default threshold value, the memory control circuit unit 404 (or the memory management circuit 502) selects the second physical erase unit from the physical erase units 410(0) -410 (N), and issues a command sequence to write the valid data in the second physical erase unit into the first physical erase unit.

Specifically, since the available storage space of the physical erase units 410(3) is not filled up by the temporary data BD (1) -BD (2) of the buffer memory 508 (i.e., there are 2 nd to 85 th physical program cell groups in the physical erase units 410(3) that have not stored data), the memory control circuit unit 404 (or the memory management circuit 502) selects, for example, the physical erase unit 410(0) and the physical erase unit 410(1) (hereinafter, referred to as the second physical erase unit) from the physical erase units 410(0) -410 (2) of the data area 602 for performing the effective data merging procedure, and issues a command sequence to write the valid data of the entity erasing unit 410(0) and the entity erasing unit 410(1) into the entity erasing unit 410(3), respectively, and fill up the storage space of the entity erasing unit 410 (3). In the exemplary embodiment, the total data amount of the effective data of the physical erase units 410(0) and 410(1) selected by the memory control circuit unit 404 (or the memory management circuit 502) can just fill up the storage space left by the physical erase units 410(3) after the temporary storage data BD (1) -BD (2) are stored, i.e., the 2 nd to 85 th physical programming unit groups in the physical erase units 410 (3). However, it should be noted that, in other exemplary embodiments, the total data amount of the valid data of the second physical erase unit selected by the memory control circuit unit 404 (or the memory management circuit 502) may be more than the available storage space left by the first physical erase unit after storing the temporary data of the buffer memory. At this time, the memory control circuit unit 404 (or the memory management circuit 502) can write only part of the valid data from the second physically erased cell, so that the valid data can just fill up the available storage space of the first physically erased cell.

Referring to fig. 9A and 9B, the memory control circuit unit 404 (or the memory management circuit 502) writes the valid data D0(0) -D0 (41) of the erase unit 410(0) into the 2 nd to 43 th physical programming unit groups of the erase unit 410(3), and writes the valid data D1(0) -D1 (41) of the erase unit 410(1) into the 44 th to 85 th physical programming unit groups of the erase unit 410(3), respectively, so as to fill up the available storage space of the 2 nd to 85 th physical programming unit groups in the erase unit 410 (3).

Next, referring to fig. 9B and fig. 9C, in the present exemplary embodiment, since the valid data in the physical erase unit 410(0) and the physical erase unit 410(1) are both written into the physical erase unit 410(3), the memory control circuit unit 404 (or the memory management circuit 502) regards the data stored in the physical erase unit 410(0) and the physical erase unit 410(1) as invalid data, and the memory control circuit unit 404 (or the memory management circuit 502) will issue a command sequence to erase the physical erase unit 410(0) and the physical erase unit 410(1), and associating the physical erase unit 410(0) and the physical erase unit 410(1) to the idle region 604, thereby freeing up the storage space of the rewritable nonvolatile memory module 406 and increasing the number of the idle physical erase units in the idle region 604. In addition, the memory control circuit unit 404 (or the memory management circuit 502) associates the physical erase unit 410(3) with the data area 602.

FIG. 10 is a flowchart illustrating a data writing method according to another example embodiment.

Referring to fig. 10, in step S1001, the memory control circuit unit 404 (or the memory management circuit 502) determines whether a default command is received from the host system 11. When the memory control circuit unit 404 (or the memory management circuit 502) does not receive the default instruction from the host system 11, step S1001 is repeatedly executed. When the memory control circuit unit 404 (or the memory management circuit 502) receives the default command from the host system 11, in step S1003, the memory control circuit unit 404 (or the memory management circuit 502) will execute a command sequence to write the temporary data in the buffer memory 508 into the first physical erase unit of the physical erase units 410(0) -410 (N) of the rewritable nonvolatile memory module 406. Thereafter, in step S1005, the memory control circuit unit 404 (or the memory management circuit 502) determines whether the amount of the temporary data is smaller than the default threshold. When the memory control circuit unit 404 (or the memory management circuit 502) determines that the amount of the temporary data is smaller than the default threshold value, in step S1007, the memory control circuit unit 404 (or the memory management circuit 502) will issue a command sequence to write the dummy data into the first physical erase unit. When the memory control circuit unit 404 (or the memory management circuit 502) determines that the amount of the temporary data is not less than the default threshold value, in step S1009, the memory control circuit unit 404 (or the memory management circuit 502) selects a second physical erase unit from the physical erase units 410(0) -410 (N) of the rewritable nonvolatile memory module 406. And in step S1011, the memory control circuit unit 404 (or the memory management circuit 502) issues a command sequence to write the valid data in the second physically erased cell into the first physically erased cell.

In summary, the data writing method of the present invention can store the temporary data of the buffer memory into the first entity erasing unit of the rewritable nonvolatile memory and write the valid data of the second entity erasing unit into the first entity erasing unit when receiving the default command issued by the host system, thereby effectively improving the utilization efficiency of the rewritable nonvolatile memory, avoiding storing too much invalid data and prolonging the service life of the rewritable nonvolatile memory.

Although the present invention has been described with reference to the above embodiments, it should be understood that the invention is not limited to the embodiments, and various changes and modifications can be made by one skilled in the art without departing from the spirit and scope of the invention.

Claims

1. A data writing method is used for a rewritable nonvolatile memory module of a memory storage device, and is characterized in that the memory storage device is provided with a buffer memory, the rewritable nonvolatile memory module is provided with a plurality of entity erasing units, the entity erasing units are provided with a plurality of entity programming units, and the data writing method comprises the following steps:

judging whether a default instruction is received from a host system; and

when the default instruction is received from the host system,

writing at least one temporary data in the buffer memory into a first entity erasing unit in the entity erasing units;

judging whether the quantity of the at least one temporary storage data is smaller than a default threshold value or not;

writing at least one dummy data into the first entity erasing unit when the amount of the at least one temporary data is smaller than the default threshold value; and

and only when the quantity of the at least one temporary data is not less than the default threshold value, selecting at least one second entity erasing unit from the plurality of entity erasing units, and writing at least one valid data in the at least one second entity erasing unit into the first entity erasing unit.

2. The data writing method of claim 1, wherein the step of writing the at least one valid datum in the at least one second physically erased cell to the first physically erased cell includes filling an available storage space of the first physically erased cell with the at least one valid datum.

3. The data writing method according to claim 1, wherein the default command is a flush command or a terminate command.

4. The data writing method according to claim 1, further comprising:

and performing an erasing operation on the at least one second physically erased unit.

5. The method of claim 1, wherein the plurality of physical programming units comprise a plurality of lower physical programming units, a plurality of middle physical programming units, and a plurality of upper physical programming units.

6. A memory control circuit unit for controlling a rewritable nonvolatile memory module, the memory control circuit unit comprising:

a host interface for electrically connecting to a host system;

a memory interface electrically connected to the rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module has a plurality of entity erasing units, and the entity erasing units have a plurality of entity programming units;

the buffer memory is electrically connected to the host interface and the memory interface and used for storing at least one temporary storage data; and

a memory management circuit electrically connected to the host interface, the memory interface and the buffer memory, and used for determining whether a default command is received from the host system,

when the default command is received from the host system, the memory management circuit is further configured to issue a first command sequence to write the at least one temporary data in the buffer memory into a first physical erase unit of the plurality of physical erase units, wherein the memory management circuit is further configured to determine whether the amount of the at least one temporary data is less than a default threshold,

wherein when the amount of the at least one temporary data is smaller than the default threshold, the memory management circuit is further configured to issue a third command sequence to write at least one dummy data into the first physical erase unit,

the memory management circuit is configured to select the at least one second physical erase unit from the plurality of physical erase units only when the amount of the at least one temporary data is not less than the default threshold value, and issue a second command sequence to write at least one valid data in the at least one second physical erase unit into the first physical erase unit.

7. The memory control circuit unit of claim 6, wherein the operation of writing the at least one valid datum in the at least one second physically erased cell to the first physically erased cell includes the memory management circuit filling the available storage space of the first physically erased cell with the at least one valid datum.

8. The memory control circuit unit of claim 6, wherein the default command is a flush command or a terminate command.

9. The memory control circuit unit of claim 6, wherein the memory management circuit is further configured to issue a fourth command sequence to perform an erase operation on the at least one second physically erased cell.

10. The memory control circuit unit of claim 6, wherein the plurality of physical programming units comprises a plurality of lower physical programming units, a plurality of middle physical programming units and a plurality of upper physical programming units.

11. A memory storage device, comprising:

a connection interface unit for electrically connecting to a host system;

the rewritable nonvolatile memory module is provided with a plurality of entity erasing units, and the entity erasing units are provided with a plurality of entity programming units; and

a memory control circuit unit electrically connected to the connection interface unit and the rewritable nonvolatile memory module and including a buffer memory for storing at least one temporary data,

wherein the memory control circuit unit is used for judging whether a default instruction is received from the host system,

when the default command is received from the host system, the memory control circuit unit is further configured to issue a first command sequence to write the at least one temporary data in the buffer memory into a first physical erase unit of the plurality of physical erase units,

wherein the memory control circuit unit is further configured to determine whether the amount of the at least one temporary data is smaller than a default threshold,

wherein when the amount of the at least one temporary data is smaller than the default threshold, the memory control circuit unit is further configured to issue a third command sequence to write at least one dummy data into the first physical erase unit,

the memory control circuit unit is configured to select the at least one second physical erase unit from the plurality of physical erase units only when the amount of the at least one temporary data is not less than the default threshold value, and issue a second command sequence to write at least one valid data in the at least one second physical erase unit into the first physical erase unit.

12. The memory storage device of claim 11, wherein the operation of writing the at least one valid datum in the at least one second physically erased cell to the first physically erased cell includes the memory control circuitry unit filling available storage space of the first physically erased cell with the at least one valid datum.

13. The memory storage device of claim 11, wherein the default command is a flush command or a terminate command.

14. The memory storage device of claim 11, wherein the memory control circuit unit is further configured to issue a fourth command sequence to perform an erase operation on the at least one second physically erased cell.

15. The memory storage device of claim 11, wherein the plurality of physical programming cells comprises a plurality of lower physical programming cells, a plurality of middle physical programming cells, and a plurality of upper physical programming cells.