CN107346211B

CN107346211B - Mapping table loading method, memory control circuit unit and memory storage device

Info

Publication number: CN107346211B
Application number: CN201610300912.XA
Authority: CN
Inventors: 叶志刚
Original assignee: Hefei Core Storage Electronic Ltd
Current assignee: Hefei Core Storage Electronic Ltd
Priority date: 2016-05-06
Filing date: 2016-05-06
Publication date: 2020-03-31
Anticipated expiration: 2036-05-06
Also published as: CN107346211A

Abstract

The invention provides a mapping table loading method, a memory control circuit unit and a memory storage device. The method comprises the following steps: receiving a first instruction; when the operation mode of the rewritable nonvolatile memory module is a first operation mode, loading a first sub-logic address-entity address mapping table corresponding to a first instruction; and loading a first logical address-physical address mapping table corresponding to the first instruction when the operation mode of the rewritable non-volatile memory module is a second operation mode, wherein the first logical address-physical address mapping table comprises a first sub-logical address-physical address mapping table. The invention can effectively improve the use efficiency and the efficiency of the memory storage device.

Description

Mapping table loading method, memory control circuit unit and memory storage device

Technical Field

The invention relates to a mapping table loading method, a memory control circuit unit and a memory storage device.

Background

Digital cameras, cellular phones, and MP3 have grown rapidly over the years, resulting in a rapid increase in consumer demand for storage media. Since the rewritable non-volatile memory (rewritable non-volatile memory) has the characteristics of non-volatility, power saving, small volume, no mechanical structure, high read-write speed and the like, the rewritable non-volatile memory is most suitable for portable electronic products such as notebook computers. A solid state disk is a memory storage device using a flash memory module as a storage medium. Therefore, the flash memory industry has become a relatively popular segment of the electronics industry in recent years.

Generally, a rewritable nonvolatile memory module usually includes a plurality of physically erased cells, and each physically erased cell includes a plurality of physically programmed cells. A memory management circuit in the memory storage device configures logical addresses to map the entity erasing units, wherein each logical address has a plurality of logical units to map the entity programming units of the corresponding entity erasing unit.

In order to identify the physically erased cell in which the data of each logical address is stored, the memory management circuit records the mapping between the logical address and the physically erased cell. Specifically, the memory management circuit stores a plurality of logical address-physical address mapping tables in the rewritable nonvolatile memory module to record the physical erase unit mapped by each logical address. When data is to be accessed, the memory management circuit loads the corresponding logical address-physical address mapping table and writes or reads the data according to the logical address-physical address mapping table.

It should be noted that the memory management circuit is usually managed by a fixed size of the logical address-physical address mapping table. For example, when data is to be accessed, the memory management circuit loads a fixed-size logical address-physical address mapping table into the buffer memory, and writes or reads data according to the logical address-physical address mapping table.

In particular, in the case of a memory management circuit performing a random read operation, only part of the information of the loaded logical address-physical address mapping table is typically used. When the memory management circuit repeatedly performs the random read operation, the memory management circuit loads different logical address-physical address mapping tables for a plurality of times, and each logical address-physical address mapping table uses only part of the information, which results in inefficient use of the logical address-physical address mapping table. In addition, when the logical address-physical address mapping table is large, repeatedly loading different logical address-physical address mapping tables wastes the bandwidth of the memory storage device, thereby deteriorating the performance of the memory storage device.

Disclosure of Invention

The invention provides a mapping table loading method, a memory control circuit unit and a memory storage device, which can effectively improve the use efficiency and the efficiency of the memory storage device.

The invention provides a mapping table loading method, which is used for a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module stores a plurality of logical address-entity address mapping tables, each logical address-entity address mapping table is provided with a plurality of sub-logical address-entity address mapping tables, and the mapping table loading comprises the following steps: receiving a first instruction, wherein the first instruction corresponds to data stored at a first logical address; when the operation mode corresponding to the rewritable nonvolatile memory module is a first operation mode, loading a first sub-logical address-entity address mapping table in the sub-logical address-entity address mapping table into a buffer memory from the rewritable nonvolatile memory module, wherein the first sub-logical address-entity address mapping table records mapping information corresponding to a first logical address; and loading a first logical address-physical address mapping table in the logical address-physical address mapping tables from the rewritable non-volatile memory module to the buffer memory when the operation mode corresponding to the rewritable non-volatile memory module is a second operation mode, wherein the first logical address-physical address mapping table records mapping information corresponding to a first logical address, and the first logical address-physical address mapping table comprises a first sub-logical address-physical address mapping table.

In an exemplary embodiment of the invention, before the step of receiving the first instruction, the method further includes: executing a second instruction according to a second sub-logical address-physical address mapping table; when the second sub-logical address-physical address mapping table is different from the first sub-logical address-physical address mapping table, judging that the operation mode of the rewritable nonvolatile memory module is a first operation mode; and when the second sub-logical address-physical address mapping table is the same as the first sub-logical address-physical address mapping table, determining that the operation mode of the rewritable non-volatile memory module is the second operation mode.

In an exemplary embodiment of the present invention, when the second sub-logical address-to-physical address mapping table is different from the first sub-logical address-to-physical address mapping table, the method further includes: and when the first logical address-entity address mapping table comprises a second sub-logical address-entity address mapping table, judging the operation mode of the rewritable non-volatile memory module to be a second mode.

In an exemplary embodiment of the invention, before the step of receiving the first instruction, the method further includes: executing a third instruction according to a second logical address-physical address mapping table; and when the second logical address-physical address mapping table is different from the first logical address-physical address mapping table, judging that the operation mode of the rewritable nonvolatile memory module is the first operation mode.

In an exemplary embodiment of the invention, when the operation mode of the rewritable nonvolatile memory module is the first operation mode, the method further includes: executing a first instruction according to a first sub-logical address-physical address mapping table; erasing the first sub-logical address-physical address mapping table; and recording the use history of the first sub-logical address-physical address mapping table in the management table.

In an exemplary embodiment of the invention, an operation mode of the rewritable nonvolatile memory module after each power-on is a default first operation mode.

In an exemplary embodiment of the invention, the first operation mode includes a random read operation mode, a random write operation mode or an operation mode of selecting a recycling block in a garbage collection (garbage collection) procedure.

In an exemplary embodiment of the invention, the second operation mode includes a continuous read operation mode, a continuous write operation mode, a garbage collection (garbage collection) operation mode for writing to a destination block, or a flush operation mode.

An exemplary embodiment of the present invention provides a memory control circuit unit for controlling a rewritable nonvolatile memory module. The memory control circuit unit includes: a host interface for electrically connecting to a host system; a memory interface electrically connected to the rewritable non-volatile memory module, wherein the rewritable non-volatile memory module stores a plurality of logical address-physical address mapping tables and each logical address-physical address mapping table has a plurality of sub-logical address-physical address mapping tables; the memory management circuit is electrically connected to the host interface, the memory interface and the buffer memory. The memory management circuit is used for receiving a first instruction, wherein the first instruction corresponds to data stored in a first logic address; when the operation mode corresponding to the rewritable nonvolatile memory module is a first operation mode, loading a first sub-logical address-entity address mapping table in the sub-logical address-entity address mapping table into a buffer memory from the rewritable nonvolatile memory module, wherein the first sub-logical address-entity address mapping table records mapping information corresponding to a first logical address; and loading a first logical address-physical address mapping table in the logical address-physical address mapping tables from the rewritable non-volatile memory module to the buffer memory when the operation mode corresponding to the rewritable non-volatile memory module is a second operation mode, wherein the first logical address-physical address mapping table records mapping information corresponding to a first logical address, and the first logical address-physical address mapping table comprises a first sub-logical address-physical address mapping table.

In an exemplary embodiment of the invention, prior to the operation of receiving the first instruction, the memory management circuit is further configured to: executing a second instruction according to a second sub-logical address-physical address mapping table; when the second sub-logical address-physical address mapping table is different from the first sub-logical address-physical address mapping table, judging that the operation mode of the rewritable nonvolatile memory module is a first operation mode; and when the second sub-logical address-physical address mapping table is the same as the first sub-logical address-physical address mapping table, determining that the operation mode of the rewritable non-volatile memory module is the second operation mode.

In an exemplary embodiment of the invention, the memory management circuit is further configured to determine the operation mode of the rewritable non-volatile memory module to be the second mode when the second sub-logical address-to-physical address mapping table is different from the first sub-logical address-to-physical address mapping table and when the first logical address-to-physical address mapping table includes the second sub-logical address-to-physical address mapping table.

In an exemplary embodiment of the invention, prior to the operation of receiving the first instruction, the memory management circuit is further configured to: executing a third instruction according to a second logical address-physical address mapping table; and when the second logical address-physical address mapping table is different from the first logical address-physical address mapping table, judging that the operation mode of the rewritable nonvolatile memory module is the first operation mode.

In an exemplary embodiment of the invention, when the operation mode of the rewritable non-volatile memory module is the first operation mode, the memory management circuit is further configured to: executing a first instruction according to a first sub-logical address-physical address mapping table; erasing the first sub-logical address-physical address mapping table; and recording the use history of the first sub-logical address-physical address mapping table in the management table.

An exemplary embodiment of the present invention provides a memory storage device. It includes: the memory control circuit unit is electrically connected to the connection interface unit and the rewritable nonvolatile memory module. The memory control circuit unit comprises a buffer memory, and the rewritable nonvolatile memory stores a plurality of logical address-physical address mapping tables, and each logical address-physical address mapping table is provided with a plurality of sub-logical address-physical address mapping tables. The memory control circuit unit is used for receiving a first instruction, wherein the first instruction corresponds to data stored in a first logic address; when the operation mode corresponding to the rewritable nonvolatile memory module is a first operation mode, loading a first sub-logical address-entity address mapping table in the sub-logical address-entity address mapping table into a buffer memory from the rewritable nonvolatile memory module, wherein the first sub-logical address-entity address mapping table records mapping information corresponding to a first logical address; and loading a first logical address-physical address mapping table in the logical address-physical address mapping tables from the rewritable non-volatile memory module to the buffer memory when the operation mode corresponding to the rewritable non-volatile memory module is a second operation mode, wherein the first logical address-physical address mapping table records mapping information corresponding to a first logical address, and the first logical address-physical address mapping table comprises a first sub-logical address-physical address mapping table.

In an exemplary embodiment of the invention, prior to the operation of receiving the first instruction, the memory control circuit unit is further configured to: executing a second instruction according to a second sub-logical address-physical address mapping table; when the second sub-logical address-physical address mapping table is different from the first sub-logical address-physical address mapping table, judging that the operation mode of the rewritable nonvolatile memory module is a first operation mode; and when the second sub-logical address-physical address mapping table is the same as the first sub-logical address-physical address mapping table, determining that the operation mode of the rewritable non-volatile memory module is the second operation mode.

In an exemplary embodiment of the invention, the memory control circuit unit is further configured to determine that the operation mode of the rewritable non-volatile memory module is the second mode when the second sub-logical address-to-physical address mapping table is different from the first sub-logical address-to-physical address mapping table and when the first logical address-to-physical address mapping table includes the second sub-logical address-to-physical address mapping table.

In an exemplary embodiment of the invention, prior to the operation of receiving the first instruction, the memory control circuit unit is further configured to: executing a third instruction according to a second logical address-physical address mapping table; and when the second logical address-physical address mapping table is different from the first logical address-physical address mapping table, judging that the operation mode of the rewritable nonvolatile memory module is the first operation mode.

In an exemplary embodiment of the invention, when the operation mode of the rewritable non-volatile memory module is the first operation mode, the memory control circuit unit is further configured to: executing a first instruction according to a first sub-logical address-physical address mapping table; erasing the first sub-logical address-physical address mapping table; and recording the use history of the first sub-logical address-physical address mapping table in the management table.

Based on the above, the present invention avoids the waste of the bandwidth of the memory storage device caused by repeatedly loading a larger logical address-physical address mapping table when the host system performs the random read operation by loading the logical address-physical address mapping tables with different sizes, and can effectively improve the utilization efficiency and performance of the memory storage device.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

FIG. 1 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment;

FIG. 2 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to another example embodiment;

FIG. 3 is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the invention;

FIG. 4 is a schematic block diagram illustrating a host system and a memory storage device according to an example embodiment;

FIG. 5 is a schematic block diagram of memory control circuitry shown in accordance with an example embodiment;

FIGS. 6 and 7 illustrate exemplary managing physical erase units according to one exemplary embodiment;

FIGS. 8A and 8B are schematic diagrams illustrating exemplary logical address to physical address mapping tables and their corresponding sub-logical address to physical address mapping tables, according to an exemplary embodiment;

FIGS. 9A-9B are schematic diagrams illustrating a memory read method according to a first example;

FIGS. 10A-10B are schematic diagrams illustrating a memory read method according to a second example;

FIGS. 11A-11B are schematic diagrams illustrating a memory read method according to a third example;

FIGS. 12A-12B are schematic diagrams illustrating a memory read method according to a fourth example;

FIG. 13 is a flowchart illustrating a mapping table loading method according to an example embodiment;

reference numerals:

10: memory storage device

11: host system

12: input/output (I/O) device

110: system bus

111: processor with a memory having a plurality of memory cells

112: random Access Memory (RAM)

113: read-only memory (ROM)

114: data transmission interface

20: main board

204: wireless memory storage device

205: global positioning system module

206: network adapter

207: wireless transmission device

208: keyboard with a keyboard body

209: screen

210: horn type loudspeaker

30: memory storage device

31: host system

32: SD card

33: CF card

34: embedded storage device

341: embedded multimedia card

342: embedded multi-chip packaging storage device

402: connection interface unit

404: memory control circuit unit

406: rewritable nonvolatile memory module

410(0) -410 (N), 410(X +1), 410(X +11), 410 (Y): physical erase unit

502: memory management circuit

504: host interface

506: memory interface

508: buffer memory

510: power management circuit

512: error checking and correcting circuit

602: data area

604: idle zone

606: system area

608: substitution zone

LBA (0) to LBA (h): logical addresses

LZ (0) to LZ (M): logical area

810. 820: logical address-physical address mapping table

810a to 810n, 820a to 820 n: sub-logical address-physical address mapping table

508 a: first region

508 b: second region

S1301: receiving a first instruction corresponding to data stored at a first logical address

S1303: determining whether the operation mode corresponding to the rewritable non-volatile memory module is a first operation mode or a second operation mode

S1305: when the operation mode corresponding to the rewritable nonvolatile memory module is a first operation mode, loading a first sub-logical address-physical address mapping table in the sub-logical address-physical address mapping table into the buffer memory from the rewritable nonvolatile memory module, wherein the first sub-logical address-physical address mapping table records mapping information corresponding to the first logical address

S1307: loading a first logical address-physical address mapping table from a logical address-physical address mapping table to a buffer memory when an operation mode corresponding to the rewritable non-volatile memory module is a second operation mode, wherein the first logical address-physical address mapping table records mapping information corresponding to a first logical address, and the first logical address-physical address mapping table comprises a first sub-logical address-physical address mapping table

Detailed Description

Generally, a memory storage device (also referred to as a memory storage system) includes a rewritable nonvolatile memory module and a controller (also referred to as a control circuit unit). Memory storage devices are typically used with a host system so that the host system can write data to or read data from the memory storage device.

Fig. 1 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment, and fig. 2 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to another example embodiment.

Referring to fig. 1 and 2, the host system 11 generally includes a processor 111, a Random Access Memory (RAM) 112, a Read Only Memory (ROM) 113, and a data transmission interface 114. The processor 111, the RAM 112, the ROM 113, and the data transmission interface 114 are all electrically connected to the system bus (system bus) 110.

In the present exemplary embodiment, the host system 11 is electrically connected to the memory storage device 10 through the data transmission interface 114. For example, host system 11 may write data to memory storage device 10 or read data from memory storage device 10 via data transfer interface 114. In addition, the host system 11 is electrically connected to the I/O device 12 via a system bus 110. For example, the host system 11 may transmit output signals to the I/O device 12 or receive input signals from the I/O device 12 via the system bus 110.

In the present exemplary embodiment, the processor 111, the random access memory 112, the read only memory 113 and the data transmission interface 114 may be disposed on the motherboard 20 of the host system 11. The number of the data transmission interfaces 114 may be one or more. Through the data transmission interface 114, the main board 20 can be electrically connected to the memory storage device 10 in a wired or wireless manner. The memory storage device 10 can be, for example, a flash Drive 201, a memory card 202, a Solid State Drive (SSD) 203, or a wireless memory storage device 204. The wireless memory Storage device 204 can be a memory Storage device based on various wireless Communication technologies, such as a Near Field Communication (NFC) memory Storage device, a wireless facsimile (WiFi) memory Storage device, a Bluetooth (Bluetooth) memory Storage device, or a Bluetooth low energy memory Storage device (e.g., iBeacon). In addition, the motherboard 20 may also be electrically connected to various I/O devices such as a Global Positioning System (GPS) module 205, a network adapter 206, a wireless transmission device 207, a keyboard 208, a screen 209, and a speaker 210 through the System bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 via the wireless transmission device 207.

In an exemplary embodiment, the host system referred to is substantially any system that can cooperate with a memory storage device to store data. Although the host system is described as a computer system in the above exemplary embodiment, fig. 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment. Referring to fig. 3, in another exemplary embodiment, the host system 31 may also be a digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer, and the memory storage device 30 may be various non-volatile memory storage devices such as an SD card 32, a CF card 33, or an embedded storage device 34. The embedded storage device 34 includes various types of embedded Multi media cards (eMMC) 341 and/or embedded Multi Chip Package storage (eMCP) 342 to electrically connect the memory module directly to the embedded storage device on the substrate of the host system.

FIG. 4 is a schematic block diagram illustrating a host system and a memory storage device according to an example embodiment.

Referring to fig. 4, the memory storage device 10 includes a connection interface unit 402, a memory control circuit unit 404 and a rewritable nonvolatile memory module 406.

In the exemplary embodiment, connection interface unit 402 is compliant with the Serial Advanced Technology Attachment (SATA) standard. However, it should be understood that the present invention is not limited thereto, and the connection interface unit 402 may also conform to the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronic Engineers (IEEE) 1394 standard, the High-Speed Peripheral Component connection interface (PCI Express) standard, the Universal Serial Bus (USB) standard, the Ultra High Speed Specification-I (UHS-I) interface standard, the Ultra High Speed Specification-II (UHS-II) interface standard, the Secure Digital (SD) interface standard, the Memory Stick (Memory Stick, MS) interface standard, the Multi-Chip Package (Multi-P Package) interface standard, the Multi-Media storage Card (Multi-Media, Embedded Multimedia Card (MMC), eMMC) interface standard, Universal Flash Storage (UFS) interface standard, embedded Multi-Chip Package (eMCP) interface standard, Compact Flash (CF) interface standard, Integrated Device Electronics (IDE) standard, or other suitable standard. In the present exemplary embodiment, the connection interface unit 402 and the memory control circuit unit 404 may be packaged in one chip, or the connection interface unit 402 is disposed outside a chip including the memory control circuit unit.

The memory control circuit unit 404 is used for executing a plurality of logic gates or control commands implemented in a hardware type or a firmware type, and performing operations such as writing, reading and erasing data in the rewritable nonvolatile memory module 406 according to commands of the host system 11.

The rewritable nonvolatile memory module 406 is electrically connected to the memory control circuit unit 404 and is used for storing data written by the host system 11. The rewritable nonvolatile memory module 406 has physical erase units 410(0) -410 (N). For example, the physical erase units 410(0) -410 (N) may belong to the same memory die (die) or to different memory dies. Each entity erasing unit is respectively provided with a plurality of entity programming units, wherein the entity programming units belonging to the same entity erasing unit can be independently written and simultaneously erased. However, it should be understood that the invention is not limited thereto, and each of the plurality of physically erased cells may be composed of 64 physically programmed cells, 256 physically programmed cells, or any other number of physically programmed cells.

In more detail, the physically erased cell is the minimum unit of erase. That is, each physically erased cell contains one of the minimum number of memory cells that are erased. The physical programming unit is a minimum unit for programming. That is, the physical programming unit is the minimum unit for writing data. Each physical programming cell typically includes a data bit region and a redundancy bit region. The data bit region includes a plurality of physical access addresses for storing user data, and the redundant bit region is used for storing system data (e.g., control information and error correction codes). In the exemplary embodiment, each physical program unit includes 8 physical access addresses in the data bit region, and one physical access address has a size of 512bytes (byte). However, in other exemplary embodiments, the data bit region may include a greater or lesser number of physical access addresses, and the size and number of the physical access addresses are not limited in the present invention. For example, in an exemplary embodiment, the physically erased cells are physical blocks, and the physically programmed cells are physical pages or physical sectors, but the invention is not limited thereto.

In the present exemplary embodiment, the rewritable nonvolatile memory module 406 is a Triple Level Cell (TLC) NAND-type flash memory module (i.e., a flash memory module capable of storing 3 bits of data in one memory Cell). However, the invention is not limited thereto, and the rewritable nonvolatile memory module 406 may also be a Multi-level cell (MLC) NAND-type flash memory module (i.e., a flash memory module capable of storing 2 data bits in one memory cell) or other memory modules with the same characteristics.

FIG. 5 is a schematic block diagram of a memory control circuit unit shown in accordance with an example embodiment.

Referring to FIG. 5, the memory control circuit unit 404 includes a memory management circuit 502, a host interface 504, a memory interface 506, a buffer memory 508, a power management circuit 510, and an error checking and correcting circuit 512.

The memory management circuit 502 is used to control the overall operation of the memory control circuit unit 404. Specifically, the memory management circuit 502 has a plurality of control commands, and the control commands are executed to perform data writing, reading, and erasing operations when the memory storage device 10 is in operation.

In the exemplary embodiment, the control instructions of the memory management circuit 502 are implemented in firmware. For example, the memory management circuit 502 has a microprocessor unit (not shown) and a read only memory (not shown), and the control commands are recorded in the read only memory. When the memory storage device 10 is in operation, the control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.

FIGS. 6 and 7 illustrate exemplary embodiments of managing physically erased cells, according to an exemplary embodiment.

It should be understood that, when describing the operation of the physically erased cells of the rewritable non-volatile memory module 406, it is a logical concept to operate the physically erased cells by the words "extract", "group", "partition", "associate", and the like. That is, the physical locations of the physical erase units of the rewritable nonvolatile memory module are not changed, but the physical erase units of the rewritable nonvolatile memory module are logically operated.

Referring to FIG. 6, the memory control circuit unit 404 (or the memory management circuit 502) logically groups the physical erase units 410(0) -410 (N) into a data area 602, an idle area 604, a system area 606, and a replacement area 608.

The physically erased cells logically belonging to the data area 602 and the idle area 604 are used for storing data from the host system 11. Specifically, the wear-leveling cells in the data area 602 are regarded as the wear-leveling cells storing data, and the wear-leveling cells in the idle area 604 are used to replace the wear-leveling cells in the data area 602. That is, when receiving a write command and data to be written from the host system 11, the memory management circuit 502 writes the data by extracting the physical erase unit from the idle region 604 to replace the physical erase unit in the data region 602.

The physically erased cells logically belonging to the system area 606 are used for recording system data. For example, the system data includes information about the manufacturer and model of the rewritable nonvolatile memory module, the number of physically erased cells of the rewritable nonvolatile memory module, the number of physically programmed cells per physically erased cell, and the like.

The physically erased cells logically belonging to the replacement area 608 are used in the bad-physically-erased-cell replacement procedure to replace the damaged physically erased cells. Specifically, if there are normal physically erased cells in the replacement area 608 and the physically erased cells in the data area 602 are damaged, the memory management circuit 502 extracts the normal physically erased cells from the replacement area 608 to replace the damaged physically erased cells.

In particular, the number of physically erased cells in the data area 602, the idle area 604, the system area 606 and the replacement area 608 may vary according to different memory specifications. Moreover, it should be understood that during operation of the memory storage device 10, the grouping relationship of the physically erased cells associated with the data area 602, the idle area 604, the system area 606 and the replacement area 608 may dynamically change. For example, when the physically erased cells in the idle area 604 are damaged and replaced by the physically erased cells in the replacement area 608, the physically erased cells in the replacement area 608 are associated with the idle area 604.

Referring to fig. 7, the memory control circuit unit 404 (or the memory management circuit 502) configures logical addresses LBA (0) to LBA (h) to map the physical erase units of the data area 602, where each logical address has a plurality of logical units to map the physical program units of the corresponding physical erase units. Moreover, when the host system 11 is going to write data to the logical address or update the data stored in the logical address, the memory control circuit unit 404 (or the memory management circuit 502) will extract one physical erase unit from the idle area 604 as an active physical erase unit to write data, so as to replace the physical erase unit of the data area 602. Moreover, when the physical erase unit as the active physical erase unit is full, the memory control circuit unit 404 (or the memory management circuit 502) will extract the empty physical erase unit from the idle area 504 as the active physical erase unit to continue writing the update data corresponding to the write command from the host system 11. In addition, when the number of available physical erase units in the idle area 604 is smaller than a predetermined value, the memory control circuit unit 404 (or the memory management circuit 502) performs a valid data merging procedure (also called a garbage collection procedure) to merge the valid data in the data area 602, so as to re-associate the physical erase units in the data area 602 that do not store the valid data with the idle area 604.

In order to identify the physical erase unit in which the data of each logical address is stored, in the exemplary embodiment, the memory control circuit unit 404 (or the memory management circuit 502) records the mapping between the logical address and the physical erase unit. For example, in the present exemplary embodiment, the memory control circuit unit 404 (or the memory management circuit 502) stores a logical address-physical address mapping table in the rewritable nonvolatile memory module 406 to record the physical erase unit mapped by each logical address. When data is to be accessed, the memory control circuit unit 404 (or the memory management circuit 502) loads the logical address-physical address mapping table into the buffer memory 508 for maintenance, and writes or reads data according to the logical address-physical address mapping table.

It should be noted that, since the buffer 508 has a limited capacity and cannot store a mapping table for recording mapping relationships of all logical addresses, in the exemplary embodiment, the memory control circuit unit 404 (or the memory management circuit 502) groups the logical addresses LBA (0) to LBA (h) into a plurality of logical zones LZ (0) to LZ (m), and configures a logical address-physical address mapping table for each logical zone. In particular, when the memory control circuit unit 404 (or the memory management circuit 502) wants to update the mapping of a logical address, the logical address-physical address mapping table corresponding to the logical area to which the logical address belongs is loaded to the buffer memory 508 for updating.

In another exemplary embodiment of the invention, the control instructions of the memory management circuit 502 can also be stored in a specific area of the rewritable nonvolatile memory module 406 (for example, a system area dedicated to storing system data in the memory module) by using a program code type. In addition, the memory management circuit 502 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the rom has a driver code, and when the memory control circuit unit 404 is enabled, the microprocessor unit first executes the driver code segment to load the control command stored in the rewritable nonvolatile memory module 406 into the ram of the memory management circuit 502. Then, the microprocessor unit operates the control commands to perform data writing, reading, erasing, and the like.

In another exemplary embodiment of the invention, the control instructions of the memory management circuit 502 can also be implemented in a hardware form. For example, the memory management circuit 502 includes a microcontroller, a cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory cell management circuit, the memory writing circuit, the memory reading circuit, the memory erasing circuit and the data processing circuit are electrically connected to the microcontroller. The memory cell management circuit is used for managing the entity erasing unit of the rewritable nonvolatile memory module 406; the memory writing circuit is used for issuing a writing instruction to the rewritable nonvolatile memory module 406 so as to write data into the rewritable nonvolatile memory module 406; the memory reading circuit is used for sending a reading instruction to the rewritable nonvolatile memory module 406 so as to read data from the rewritable nonvolatile memory module 406; the memory erasing circuit is used for issuing an erasing instruction to the rewritable nonvolatile memory module 406 so as to erase data from the rewritable nonvolatile memory module 406; the data processing circuit is used for processing data to be written into the rewritable nonvolatile memory module 406 and data read from the rewritable nonvolatile memory module 406.

Referring to fig. 5 again, the host interface 504 is electrically connected to the memory management circuit 502 and is electrically connected to the connection interface unit 402 for receiving and recognizing the commands and data transmitted by the host system 11. That is, commands and data transmitted by the host system 11 are transmitted to the memory management circuit 502 through the host interface 504. In the exemplary embodiment, host interface 504 is compliant with the SATA standard. However, it should be understood that the present invention is not limited thereto, and the host interface 504 may also be compatible with the PATA standard, the IEEE 1394 standard, the PCI Express standard, the USB standard, the UHS-I interface standard, the UHS-II interface standard, the SD standard, the MS standard, the MMC standard, the CF standard, the IDE standard or other suitable data transmission standards.

The memory interface 506 is electrically connected to the memory management circuit 502 and is used for accessing the rewritable nonvolatile memory module 406. That is, the data to be written to the rewritable nonvolatile memory module 406 is converted into a format accepted by the rewritable nonvolatile memory module 406 through the memory interface 506.

The buffer memory 508 is electrically connected to the memory management circuit 502 and is used for temporarily storing temporary data and instructions from the host system 11 or data from the rewritable nonvolatile memory module 406.

The power management circuit 510 is electrically connected to the memory management circuit 502 and is used for controlling the power of the memory storage device 10.

The error checking and correcting circuit 512 is electrically connected to the memory management circuit 502 and is used for performing an error checking and correcting process to ensure the correctness of data. For example, when the memory management circuit 502 receives a write command from the host system 11, the Error Checking and Correcting circuit 512 generates an Error Checking and Correcting Code (ECC Code) corresponding to the data corresponding to the write command, and the memory management circuit 502 writes the data corresponding to the write command and the corresponding ECC Code into the rewritable nonvolatile memory module 406. Thereafter, when the memory management circuit 502 reads data from the rewritable nonvolatile memory module 406, the corresponding error checking and correcting codes are simultaneously read, and the error checking and correcting circuit 512 performs an error checking and correcting process on the read data according to the error checking and correcting codes.

It should be noted that, in the exemplary embodiment, the memory control circuit unit 404 (or the memory management circuit 502) groups the logical addresses LBA (0) -LBA (h) into a plurality of logical zones LZ (0) -LZ (m), and configures a logical address-physical address mapping table for each logical zone. In particular, the memory control circuit unit 404 (or the memory management circuit 502) further divides a logical address-physical address mapping table into a plurality of sub-logical address-physical address mapping tables.

Fig. 8A and 8B are exemplary diagrams illustrating a logical address-to-physical address mapping table and a plurality of sub-logical address-to-physical address mapping tables according to an exemplary embodiment.

Referring to fig. 8A, taking the logical address-physical address mapping table 810 corresponding to the logical zone LZ (0) as an example, the logical address-physical address mapping table 810 stores mapping information between each of the logical addresses LBA (0) -LBA (z) and a plurality of physical addresses. The memory control circuit unit 404 (or the memory management circuit 502) further divides the logical address-physical address mapping table 810 into a plurality of sub-logical address-physical address mapping tables 810 a-810 n.

In addition, referring to fig. 8B, taking the logical address-physical address mapping table 820 corresponding to the logical zone LZ (1) as an example, the logical address-physical address mapping table 820 stores mapping information between each of the logical addresses LBA (Z +1) -LBA (p) and a plurality of physical addresses. The memory control circuit unit 404 (or the memory management circuit 502) further divides the logical address-physical address mapping table 810 into a plurality of sub-logical address-physical address mapping tables 820 a-820 n. In the exemplary embodiment of fig. 8A and 8B, each sub-logical address-physical address mapping table has 11 mapping information of logical addresses and physical addresses. It should be noted, however, that the present invention is not limited to the number of mapping information that can be stored in each sub-logical address-physical address mapping table. Furthermore, in other example embodiments, a size of one sub-logical address-to-physical address mapping table in the same logical address-to-physical address mapping table may be different from a size of another sub-logical address-to-physical address mapping table located in the same logical address-to-physical address mapping table. That is, the size of a sub-logical address-to-physical address mapping table is smaller than the size of a logical address-to-physical address mapping table, but the size of the sub-logical address-to-physical address mapping tables may be different.

In addition, when the memory control circuit unit 404 (or the memory management circuit 502) needs mapping information of a certain logical address, the memory control circuit unit 404 (or the memory management circuit 502) can selectively load the sub-logical address-physical address mapping table corresponding to the logical address to the buffer memory 508 or load the logical address-physical address mapping table corresponding to the logical area to which the logical address belongs to the buffer memory 508 according to the current operation mode of the rewritable nonvolatile memory module 406 for reading. For example, when the current operation mode of the rewritable nonvolatile memory module 406 is the first operation mode, the memory control circuit unit 404 (or the memory management circuit 502) loads the sub-logical address-physical address mapping table corresponding to the logical address into the buffer memory 508. When the current operation mode of the rewritable nonvolatile memory module 406 is the second operation mode, the memory control circuit unit 404 (or the memory management circuit 502) loads the logical address-physical address mapping table corresponding to the logical area to which the logical address belongs to the buffer memory 508. It is noted that, in an exemplary embodiment of the invention, the operation mode of the rewritable non-volatile memory module 406 after each power-on is the first operation mode by default.

[ first exemplary embodiment ]

FIGS. 9A-9B are schematic diagrams illustrating a memory read method according to a first example. It should be noted that, in the exemplary embodiment of the present invention, the memory control circuit unit 404 (or the memory management circuit 502) establishes a management table (not shown) in the buffer memory 508. The management table is used to record the number of times (hereinafter, referred to as the number of times of use) that a certain sub-logical address-physical address mapping table is loaded into the buffer memory and used by the memory control circuit unit 404 (or the memory management circuit 502). In short, the management table is used to record the usage history of a sub-logical address-physical address mapping table.

Referring to fig. 9A, in the example embodiment of fig. 9A, the memory control circuit unit 404 (or the memory management circuit 502) divides the buffer memory 508 into a first mapping table register 508a and a second mapping table register 508b, wherein the first mapping table register 508a is used for temporarily storing the logical address-physical address mapping table loaded from the rewritable nonvolatile memory module 406, and the second mapping table register 508b is used for temporarily storing the sub-logical address-physical address mapping table loaded from the rewritable nonvolatile memory module 406.

Assume that the host system 11 issues a read command (hereinafter, referred to as a second command) to instruct reading of data stored in the logical address LBA (0). After the memory control circuit unit 404 (or the memory management circuit 502) receives the second command from the host system 11, the memory control circuit unit 404 (or the memory management circuit 502) determines that the current operation mode of the rewritable nonvolatile memory module 406 is the first operation mode or the second operation mode. For example, the memory control circuit unit 404 (or the memory management circuit 502) determines whether the current operation mode of the rewritable nonvolatile memory module 406 is the first operation mode or the second operation mode according to the management table determining whether the sub-logical address-physical address mapping table having the mapping information of the logical address LBA (0) is used.

Since the current rewritable nonvolatile memory module 406 is in a state of being powered on and the management table does not have a history of using the sub-logical address-physical address mapping table related to the logical address LBA (0), the memory control circuit unit 404 (or the memory management circuit 502) determines that the operation mode of the current rewritable nonvolatile memory module 406 is the first operation mode. The memory control circuit unit 404 (or the memory management circuit 502) loads the sub-logical address-to-physical address mapping table 810a (hereinafter, referred to as the second sub-logical address-to-physical address mapping table) corresponding to the second instruction from the rewritable nonvolatile memory module 406 into the second mapping table register 508b of the buffer memory 508. The sub-logical address-physical address mapping table 810a records mapping information corresponding to the logical address LBA (0). In particular, in the present example, the sub-logical address-physical address mapping table 810a only includes mapping information such as logical addresses LBA (0) to LBA (10). However, in another exemplary embodiment of the present invention, the size of the sub-logical address-to-physical address mapping table 810a may be 512Bytes or other sizes, and the present invention does not limit the size of the sub-logical address-to-physical address mapping table 810 a.

Thereafter, the memory control circuitry 404 (or the memory management circuitry 502) may execute the second instruction according to the sub-logical address-to-physical address mapping table 810 a. Specifically, the memory control circuit unit 404 (or the memory management circuit 502) can read data from the physical program unit mapping the logical address LBA (0) using the sub-logical address-physical address mapping table 810a loaded to the buffer memory 508. As shown in FIG. 9A, since the second instruction is used to read the data at the logical address LBA (0), the memory control circuit unit 404 (or the memory management circuit 502) will determine that the logical address LBA (0) is mapped to the physical erase unit 410(2) according to the sub-logical address-physical address mapping table 810 a. The memory control circuit unit 404 (or the memory management circuit 502) reads the data of the corresponding physical programming unit in the physical erase unit 410(2) according to the second instruction. It should be noted that the second instruction is exemplified by a fetch instruction, but the present invention is not limited to the type of the second instruction.

In addition, in the exemplary embodiment of the invention, the sub-logical address-to-physical address mapping table 810a of the second mapping table buffer 508b buffered in the buffer memory 508 is used only once. That is, after the memory control circuit unit 404 (or the memory management circuit 502) loads the sub-logical address-to-physical address mapping table 810a and reads the data corresponding to the second instruction according to the sub-logical address-to-physical address mapping table 810a, the memory control circuit unit 404 (or the memory management circuit 502) erases the sub-logical address-to-physical address mapping table 810a temporarily stored in the buffer memory 508.

In particular, after the memory control circuit unit 404 (or the memory management circuit 502) executes the second instruction according to the sub-logical address-to-physical address mapping table 810a, the memory control circuit unit 404 (or the memory management circuit 502) also updates the usage history of the corresponding sub-logical address-to-physical address mapping table 810a in the management table. For example, the memory control circuit unit 404 (or the memory management circuit 502) adds a new field in the management table to record that the sub-logical address-physical address mapping table 810a includes logical addresses LBA (0) to LBA (10), and records the number of times of using the sub-logical address-physical address mapping table 810a as 1.

Assume that fig. 9B is continued with fig. 9A. Then, referring to fig. 9B, it is assumed that the host system 11 issues a first command, wherein the first command corresponds to the data stored at the logical address LBA (Z +1) (hereinafter, referred to as a first logical address). Assume that the first instruction is a read instruction instructing to read data stored in the logical address LBA (Z + 1). After the memory control circuit unit 404 (or the memory management circuit 502) receives the first command from the host system 11, the memory control circuit unit 404 (or the memory management circuit 502) determines that the current operation mode of the rewritable nonvolatile memory module 406 is the first operation mode or the second operation mode. The memory control circuit unit 404 (or the memory management circuit 502) determines whether the sub-logical address-physical address mapping table 820a (hereinafter, referred to as the first sub-logical address-physical address mapping table) having the mapping information of the logical address LBA (Z +1) is used according to the management table to determine whether the current operation mode of the rewritable nonvolatile memory module 406 is the first operation mode or the second operation mode.

Since the management table currently stores only the usage history of the sub-logical address-to-physical address mapping table 810a, and the sub-logical address-to-physical address mapping table 810a is different from the sub-logical address-to-physical address mapping table 820a corresponding to the logical address LBA (Z +1), the memory control circuit unit 404 (or the memory management circuit 502) determines that the current operation mode of the rewritable nonvolatile memory module 406 is the first operation mode. When the operation mode corresponding to the rewritable nonvolatile memory module 406 is the first operation mode, the memory control circuit unit 404 (or the memory management circuit 502) loads the sub-logical address-physical address mapping table 820a corresponding to the first instruction from the rewritable nonvolatile memory module 406 into the second mapping table register 508b of the buffer memory 508. The sub-logical address-physical address mapping table 820a records mapping information corresponding to the logical address LBA (Z + 1). In this example, the sub-logical address-physical address mapping table 820a only includes mapping information such as logical addresses LBA (Z +1) to LBA (Z + 11). However, in another exemplary embodiment of the present invention, the size of the sub-logical address-to-physical address mapping table 810a may be 512Bytes or other sizes, and the present invention does not limit the size of the sub-logical address-to-physical address mapping table 810 a.

Thereafter, the memory control circuit unit 404 (or the memory management circuit 502) can read data from the physically programmed unit mapped with the logical address LBA (Z +1) using the sub logical address-physical address mapping table 820a loaded to the buffer memory 508. Specifically, as shown in FIG. 9B, since the first command is used to read the data at the logical address LBA (Z +1), the memory control circuit unit 404 (or the memory management circuit 502) determines that the logical address LBA (Z +1) is mapped to the physical erase unit 410(X) according to the sub-logical address-physical address mapping table 820 a. The memory control circuit unit 404 (or the memory management circuit 502) reads the data of the corresponding physical programming unit in the physical erase unit 410(X) according to the first command.

After the memory control circuit unit 404 (or the memory management circuit 502) loads the sub-logical address-to-physical address mapping table 820a and reads data corresponding to the first instruction according to the sub-logical address-to-physical address mapping table 820a, the memory control circuit unit 404 (or the memory management circuit 502) erases the sub-logical address-to-physical address mapping table 820a temporarily stored in the buffer memory 508.

In addition, after the memory control circuit unit 404 (or the memory management circuit 502) executes the first instruction according to the sub-logical address-to-physical address mapping table 820a, the memory control circuit unit 404 (or the memory management circuit 502) may further update the number of times of use of the corresponding sub-logical address-to-physical address mapping table 820a in the management table. For example, the memory control circuit unit 404 (or the memory management circuit 502) adds a new field in the management table to record that the sub-logical address-physical address mapping table 820a includes logical addresses LBA (Z +1) to LBA (Z +11), and records the number of times of use of the sub-logical address-physical address mapping table 820a as 1.

Based on the above, in the first exemplary embodiment of the invention, since the memory control circuit unit 404 (or the memory management circuit 502) determines that the memory control circuit unit 404 (or the memory management circuit 502) has not used the sub-logical address-physical address mapping table 820a with the mapping information of the logical address LBA (Z +1) according to the management table before loading the sub-logical address-physical address mapping table 820a, the memory control circuit unit 404 (or the memory management circuit 502) can reasonably determine that the mapping information in the logical address-physical address mapping table 820 corresponding to the sub-logical address-physical address mapping table 820a is likely to be used less frequently, so that the sub-logical address-physical address mapping table 820a with smaller loading capacity can be loaded in the first mode, thereby avoiding the situation that the host system 11 repeatedly loads a larger logical address-physical address mapping table to cause the random read operation The waste of bandwidth of the memory storage device.

[ second exemplary embodiment ]

FIGS. 10A-10B are schematic diagrams illustrating a memory read method according to a second example. In the exemplary embodiment of fig. 10A, after the rewritable nonvolatile memory module 406 in fig. 9A is powered on, the sub-logical address-physical address mapping table 810A is loaded according to the second instruction, and a process corresponding to the use history of the sub-logical address-physical address mapping table 810A is recorded in the management table, which is not described herein again. Referring to fig. 10B after fig. 10A, when the first command issued by the host system 11 corresponds to the data stored at the logical address LBA (1) (hereinafter, also referred to as the first logical address), the first command is a read command indicating to read the data stored at the logical address LBA (1). After the memory control circuit unit 404 (or the memory management circuit 502) receives the first command from the host system 11, the memory control circuit unit 404 (or the memory management circuit 502) determines that the current operation mode of the rewritable nonvolatile memory module 406 is the first operation mode or the second operation mode. The memory control circuit unit 404 (or the memory management circuit 502) determines whether the sub-logical address-physical address mapping table 810a (hereinafter, also referred to as the first sub-logical address-physical address mapping table) having the mapping information of the logical address LBA (1) is used according to the management table to determine whether the operation mode of the current rewritable nonvolatile memory module 406 is the first operation mode or the second operation mode.

Since the management table currently has a history of storing the sub-logical address-physical address mapping table 810a, and the sub-logical address-physical address mapping table 810a is the same as the sub-logical address-physical address mapping table 810a corresponding to the logical address LBA (1), the memory control circuit unit 404 (or the memory management circuit 502) determines that the current operation mode of the rewritable nonvolatile memory module 406 is the second operation mode. When the operation mode corresponding to the rewritable nonvolatile memory module 406 is the second operation mode, the memory control circuit unit 404 (or the memory management circuit 502) loads the logical address-physical address mapping table 810 corresponding to the first instruction from the rewritable nonvolatile memory module 406 into the first mapping table register 508a of the buffer memory 508. In particular, the logical address-physical address mapping table 810 includes mapping information such as logical addresses LBA (0) to LBA (z) (i.e., logical zone LZ (0)). That is, the logical address-to-physical address mapping table 810 contains mapping information of a sub-logical address-to-physical address mapping table 810a, and the sub-logical address-to-physical address mapping table 810a is a subset of the logical address-to-physical address mapping table 810. It is noted that, in an exemplary embodiment of the present invention, the size of the logical address-physical address mapping table 810 may be 16KBytes or other sizes, and the size of the logical address-physical address mapping table 810 is not limited by the present invention.

Thereafter, the memory control circuit unit 404 (or the memory management circuit 502) can read data from the physically programmed unit mapping the logical address LBA (1) using the logical address-physical address mapping table 810 loaded to the buffer memory 508. Specifically, since the first command is used to read the data at the logical address LBA (1), the memory control circuit unit 404 (or the memory management circuit 502) determines that the logical address LBA (1) is mapped to the physical erase unit 410(1) according to the logical address-physical address mapping table 810. The memory control circuit unit 404 (or the memory management circuit 502) reads the data in the corresponding physical programming unit of the physical erase unit 410(1) according to the first read command.

Based on the above, in the second exemplary embodiment of the present invention, since the memory control circuit unit 404 (or the memory management circuit 502) determines that the memory control circuit unit 404 (or the memory management circuit 502) has used the sub-logical address-physical address mapping table 810a with the mapping information of the logical address LBA (1) according to the management table, the memory control circuit unit 404 (or the memory management circuit 502) can reasonably determine that the mapping information in the logical address-physical address mapping table 810 corresponding to the sub-logical address-physical address mapping table 810a is likely to be reused in the future, so that the second operation mode is used to load the larger logical address-physical address mapping table 810, to facilitate subsequent access to the mapping information in the logical address to physical address mapping table 810.

[ third example embodiment ]

FIGS. 11A-11B are schematic diagrams illustrating a memory reading method according to a third example. The exemplary embodiment of fig. 11A is such that the sub-logical address-physical address mapping table 810a is loaded according to the second instruction in fig. 9A and the flow of the usage history corresponding to the sub-logical address-physical address mapping table 810a is recorded in the management table, which is not described herein again. It is assumed that after the exemplary embodiment of fig. 11A, the first command issued by the host system 11 corresponds to the data stored at the logical address lba (z) (hereinafter, also referred to as the first logical address), and the first command is a read command instructing to read the data stored at the logical address lba (z). After the memory control circuit unit 404 (or the memory management circuit 502) receives the first command from the host system 11, the memory control circuit unit 404 (or the memory management circuit 502) determines that the current operation mode of the rewritable nonvolatile memory module 406 is the first operation mode or the second operation mode. The memory control circuit unit 404 (or the memory management circuit 502) determines whether the sub-logical address-physical address mapping table 810n (hereinafter, also referred to as the first sub-logical address-physical address mapping table) having mapping information of the logical address lba (z) is used according to the management table, so as to determine whether the current operation mode of the rewritable non-volatile memory module 406 is the first operation mode or the second operation mode.

Since the management table currently stores only the usage history of the sub-logical address-to-physical address mapping table 810a, and the sub-logical address-to-physical address mapping table 810a is different from the sub-logical address-to-physical address mapping table 810n corresponding to the logical address lba (z), the memory control circuit unit 404 (or the memory management circuit 502) determines that the current operation mode of the rewritable nonvolatile memory module 406 is the first operation mode. It should be noted that at this time, the memory control circuit unit 404 (or the memory management circuit 502) determines that the logical address-physical address mapping table 810 (hereinafter, also referred to as the first logical address-physical address mapping table) of the logical zone LZ (0) corresponding to the sub-logical address-physical address mapping table 810a includes a sub-logical address-physical address mapping table 810n corresponding to the logical address (lba z), so that the memory control circuit unit 404 (or the memory management circuit 502) determines that the current operation mode of the rewritable nonvolatile memory module 406 is the second operation mode instead.

When the operation mode corresponding to the rewritable nonvolatile memory module 406 is the second operation mode, the memory control circuit unit 404 (or the memory management circuit 502) loads the logical address-physical address mapping table 810 corresponding to the first instruction from the rewritable nonvolatile memory module 406 into the first mapping table register 508a of the buffer memory 508. In particular, the logical address-physical address mapping table 810 includes mapping information such as logical addresses LBA (0) to LBA (z) (i.e., logical zone LZ (0)). That is, the logical address-to-physical address mapping table 810 contains mapping information of a sub-logical address-to-physical address mapping table 810n, and the sub-logical address-to-physical address mapping table 810n is a subset of the logical address-to-physical address mapping table 810. It is noted that, in an exemplary embodiment of the present invention, the size of the logical address-physical address mapping table 810 may be 16KBytes or other sizes, and the size of the logical address-physical address mapping table 810 is not limited by the present invention.

Based on the above, in the third exemplary embodiment of the invention, since the memory control circuit unit 404 (or the memory management circuit 502) determines that the logical address LBA (z) corresponding to the first instruction and the logical addresses LBA (0) -LBA (10) corresponding to the sub-logical address-physical address mapping table 810a belong to the same logical zone LZ (0), the memory control circuit unit 404 (or the memory management circuit 502) can reasonably determine that the mapping information in the logical address-physical address mapping table 810 corresponding to the logical zone LZ (0) is likely to be reused in the future, so that the second operation mode is used to load the logical address-physical address mapping table 810 with larger capacity, so as to facilitate the subsequent access to the mapping information in the logical address-physical address mapping table 810.

[ fourth exemplary embodiment ]

Fig. 12A to 12B are schematic diagrams illustrating a memory reading method according to a fourth example. Referring to fig. 12A, it is assumed that the memory control circuit unit 404 (or the memory management circuit 502) loads the logical address-physical address mapping table 810 (hereinafter, referred to as a second logical address-physical address mapping table) from the rewritable nonvolatile memory module 406 into the first mapping table register 508a of the buffer memory 508, and the memory control circuit unit 404 (or the memory management circuit 502) executes a third instruction according to the logical address-physical address mapping table 810. For example, the third instruction is an instruction to read data in the logical address LBA (0).

Next, referring to fig. 12B, it is assumed that after fig. 12A, a first command issued by the host system 10 corresponds to the data stored at the logical address LBA (Z +11) (hereinafter, also referred to as a first logical address), and the first command is a read command for reading the data stored at the logical address LBA (Z + 11). After the memory control circuit unit 404 (or the memory management circuit 502) receives the first command from the host system 11, the memory control circuit unit 404 (or the memory management circuit 502) determines that the current operation mode of the rewritable nonvolatile memory module 406 is the first operation mode or the second operation mode. In the present exemplary embodiment, the memory control circuit unit 404 (or the memory management circuit 502) determines whether the logical address-physical address mapping table 820 corresponding to the logical address LBA (Z +11) of the third instruction exists in the first mapping table buffer 508a of the buffer memory 508.

At this time, the memory control circuit unit 404 (or the memory management circuit 502) determines that only the logical address-physical address mapping table 810 currently exists in the first mapping table register 508a of the buffer memory 508, and the logical address-physical address mapping table 810 is different from the logical address-physical address mapping table 820 corresponding to the logical address LBA (Z +11) of the third instruction. At this time, the memory control circuit unit 404 (or the memory management circuit 502) determines that the current operation mode of the rewritable nonvolatile memory module 406 is the first operation mode, and loads the sub-logical address-physical address mapping table 820a corresponding to the logical address LBA (Z +11) of the third instruction.

In particular, if the host system 11 issues a fourth command later, wherein the mapping information of the fourth command can be found in the logical address-physical address mapping table 810 in the buffer 508, the memory control circuit unit 404 (or the memory management circuit 502) may not determine the first operation mode or the second operation mode of the current operation mode of the rewritable nonvolatile memory module 406, and the memory control circuit unit 404 (or the memory management circuit 502) may execute the fourth command directly according to the logical address-physical address mapping table 810 in the buffer 508.

Based on the above, in the fourth exemplary embodiment of the invention, when an instruction is executed, the memory control circuit unit 404 (or the memory management circuit 502) may also determine whether the operation mode of the current rewritable non-volatile memory module 406 is the first operation mode by determining whether the buffer memory 508 stores the logical address-physical address mapping table corresponding to the instruction, so as to determine whether to load the corresponding sub-logical address-physical address mapping table into the buffer memory 508.

It is noted that the first mode of operation is, for example, a random read mode of operation, a random write mode of operation, or a garbage collection mode of operation. The random read operation mode represents that the host system 11 is continuously issuing a plurality of read commands to the rewritable nonvolatile memory module 406 to respectively perform a plurality of read operations, wherein mapping information required for each read operation is stored in a plurality of different logical address-physical address mapping tables in a distributed manner. The memory control circuit unit 404 (or the memory management circuit 502) can determine that the mapping information of the logical addresses is stored in a plurality of different logical address-physical address mapping tables in a distributed manner according to the logical addresses corresponding to the read operations, respectively, so as to determine that the current operation mode of the rewritable nonvolatile memory module 406 is the random read operation mode. At this time, in order to avoid the waste of bandwidth caused by repeatedly loading a larger logical address-physical address mapping table into the buffer 508, in the random access operation mode, the memory control circuit unit 404 (or the memory management circuit 502) loads a smaller sub-logical address-physical address mapping table into the buffer 508 for reading.

The random write operation mode represents that the host system 11 is issuing a plurality of write commands to the rewritable nonvolatile memory module 406 to perform a plurality of write operations, respectively, wherein mapping information required for each write operation is stored in a plurality of different logical address-physical address mapping tables in a distributed manner. The memory control circuit unit 404 (or the memory management circuit 502) can determine that the mapping information of the logical addresses is stored in a plurality of different logical address-physical address mapping tables in a distributed manner according to the logical addresses corresponding to the plurality of write operations, respectively, so as to determine that the current operation mode of the rewritable nonvolatile memory module 406 is the random write operation mode. At this time, in order to avoid the waste of bandwidth caused by repeatedly loading a larger logical address-physical address mapping table into the buffer 508, the memory control circuit unit 404 (or the memory management circuit 502) loads a smaller sub-logical address-physical address mapping table into the buffer 508 in the random write operation mode.

The operation mode for selecting the recycle block in the garbage collection procedure represents that the memory control circuit unit 404 (or the memory management circuit 502) is executing a valid data merging procedure, and particularly, a process for loading the mapping information of the recycle block with valid data in the valid data merging procedure. In detail, in the valid data merging procedure, since the moving of the valid data requires loading and updating the mapping information of each valid data, the mapping information may be stored in a plurality of different logical address-physical address mapping tables, respectively. Therefore, when the memory control circuit unit 404 (or the memory management circuit 502) loads the mapping information of the valid data, the memory control circuit unit 404 (or the memory management circuit 502) determines that the mapping information of the valid data is stored in different logical address-physical address mapping tables in a scattered manner, and further determines that the current operation mode of the rewritable nonvolatile memory module 406 is the operation mode of selecting the recycling block in the garbage collection procedure. To avoid the waste of bandwidth caused by repeatedly loading a larger logical address-physical address mapping table into the buffer 508, the memory control circuit unit 404 (or the memory management circuit 502) loads a smaller sub-logical address-physical address mapping table into the buffer 508 under the operation mode of selecting the recycling block in the garbage collection procedure.

The second operation mode is, for example, a continuous read operation mode, a continuous write operation mode, an operation mode in which a destination block is written in a garbage collection procedure, or a bin cleaning operation mode.

The continuous read operation mode represents that the host system 11 is continuously issuing a plurality of read commands to the rewritable nonvolatile memory module 406 to respectively perform a plurality of read operations, wherein mapping information required by the read operations is continuously stored in the same logical address-physical address mapping table. The memory control circuit unit 404 (or the memory management circuit 502) can determine that the mapping information of the logical addresses is continuously stored in the same logical address-physical address mapping table according to the logical addresses respectively corresponding to the read operations, and further determine that the current operation mode of the rewritable nonvolatile memory module 406 is a continuous read operation mode. At this time, in the continuous read operation mode, the memory control circuit unit 404 (or the memory management circuit 502) loads the larger logical address-physical address mapping table into the buffer memory 508 for reading.

The continuous write operation represents that the host system 11 is continuously issuing a plurality of write commands to the rewritable nonvolatile memory module 406 to respectively execute a plurality of write operations, wherein mapping information required by the write operations is continuously stored in the same logical address-physical address mapping table. The memory control circuit unit 404 (or the memory management circuit 502) can determine that the mapping information of the logical addresses is continuously stored in the same logical address-physical address mapping table according to the logical addresses corresponding to the plurality of write operations, and further determine that the current operation mode of the rewritable nonvolatile memory module 406 is the continuous write operation mode. At this time, in the continuous write operation mode, the memory control circuit unit 404 (or the memory management circuit 502) loads the larger logical address-physical address mapping table into the buffer memory 508 for reading.

The operation mode of writing to the destination block in the garbage collection procedure represents that the memory control circuit unit 404 (or the memory management circuit 502) is writing the collected valid data to a destination block. The operation of writing the collected valid data to the destination block is similar to the above-described sequential write operation to the destination block. In the garbage collection procedure, since the mapping information of the valid data may be continuously stored in a logical address-physical address mapping table, the memory control circuit unit 404 (or the memory management circuit 502) may determine, for example, according to the logical addresses corresponding to the write operations performed on the destination block, that the mapping information of the logical addresses may be continuously stored in the same logical address-physical address mapping table, and further determine that the current operation mode of the rewritable nonvolatile memory module 406 is the operation mode of writing to the destination block in the garbage collection procedure. At this time, in the operation mode of writing to the destination block in the garbage collection procedure, the memory control circuit unit 404 (or the memory management circuit 502) loads the larger logical address-physical address mapping table into the buffer 508 for reading.

The flush operation mode represents that the memory control circuit unit 404 (or the memory management circuit 502) is writing a plurality of temporary data in the buffer memory 508 into the rewritable nonvolatile memory module 406. When performing the flush operation, the memory control circuit unit 404 (or the memory management circuit 502) may need to load the logical address-physical address mapping table to update multiple mapping information in the same logical address-physical address mapping table. Therefore, when the memory control circuit unit 404 (or the memory management circuit 502) is performing the flush operation, the memory control circuit unit 404 (or the memory management circuit 502) determines that the current operation mode of the rewritable nonvolatile memory module 406 is the flush operation mode. At this time, in the flush operation mode, the memory control circuit unit 404 (or the memory management circuit 502) loads the larger logical address-physical address mapping table into the buffer memory 508 for reading.

Based on the above, in the exemplary embodiment of the present invention, the memory control circuit unit 404 (or the memory management circuit 502) uses the smaller sub logical address-physical address mapping table to load into the buffer memory 508 in the first operation mode, and uses the larger sub logical address-physical address mapping table to load into the buffer memory 508 in the second operation mode. Therefore, the performance deterioration of the memory storage device caused by repeatedly loading too many logical address-physical address mapping tables with larger capacity in the first operation mode can be effectively avoided.

FIG. 13 is a flowchart illustrating a mapping table loading method according to an example embodiment.

Referring to fig. 13, in step S1301, the memory control circuit unit 404 (or the memory management circuit 502) receives a first command from the host system 11, wherein the first command corresponds to data stored at a first logical address. In step S1303, the memory control circuit unit 404 (or the memory management circuit 502) determines that the operation mode of the corresponding rewritable non-volatile memory module 406 is the first operation mode or the second operation mode. When the operation mode corresponding to the rewritable non-volatile memory module 406 is the first operation mode, in step S1305, the memory control circuit unit 404 (or the memory management circuit 502) loads a first sub-logical address-physical address mapping table in the sub-logical address-physical address mapping tables, which records mapping information corresponding to the first logical address, from the rewritable non-volatile memory module 406 into the buffer memory 508. When the operation mode corresponding to the rewritable non-volatile memory module 406 is the second operation mode, in step S1307, the memory control circuit unit 404 (or the memory management circuit 502) loads a first logical address-physical address mapping table in the logical address-physical address mapping tables, which records mapping information corresponding to a first logical address, into the buffer memory 508 from the rewritable non-volatile memory module 406, where the first logical address-physical address mapping table includes a first sub-logical address-physical address mapping table.

In summary, the present invention uses the smaller sub logical address-physical address mapping table to load into the buffer memory in the first operation mode, and uses the larger logical address-physical address mapping table to load into the buffer memory in the second operation mode. In particular, since only the sub logical address-physical address mapping table with smaller capacity is loaded in the first operation mode, the host system can be prevented from repeatedly loading a larger logical address-physical address mapping table in the first operation mode to cause the waste of the bandwidth of the memory storage device, and the utilization efficiency and the performance of the memory storage device can be effectively improved.

Although the present invention has been described with reference to the above embodiments, it should be understood that the invention is not limited to the embodiments, and various changes and modifications can be made by one skilled in the art without departing from the spirit and scope of the invention.

Claims

1. A mapping table loading method for a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module stores a plurality of logical address-physical address mapping tables, and each logical address-physical address mapping table has a plurality of sub-logical address-physical address mapping tables, the mapping table loading method comprising:

receiving a first instruction, wherein the first instruction corresponds to data stored at a first logical address;

when an operation mode corresponding to the rewritable non-volatile memory module is a first operation mode, loading a first sub-logical address-physical address mapping table in the multiple sub-logical address-physical address mapping tables from the rewritable non-volatile memory module into a buffer memory, wherein mapping information corresponding to the first logical address is recorded in the first sub-logical address-physical address mapping table; and

loading a first logical address-physical address mapping table of the plurality of logical address-physical address mapping tables from the rewritable non-volatile memory module into the buffer memory when the operation mode corresponding to the rewritable non-volatile memory module is a second operation mode, wherein the first logical address-physical address mapping table records mapping information corresponding to the first logical address,

wherein the first logical address-to-physical address mapping table comprises the first sub-logical address-to-physical address mapping table.

2. The mapping table loading method according to claim 1, before the step of receiving the first instruction, further comprising:

executing a second instruction according to a second sub-logical address-physical address mapping table;

when the second sub-logical address-to-physical address mapping table is different from the first sub-logical address-to-physical address mapping table, determining that the operation mode of the rewritable non-volatile memory module is the first operation mode; and

and when the second sub-logical address-physical address mapping table is the same as the first sub-logical address-physical address mapping table, determining that the operation mode of the rewritable non-volatile memory module is the second operation mode.

3. The mapping table loading method according to claim 2, wherein when the second sub-logical address-to-entity address mapping table is different from the first sub-logical address-to-entity address mapping table, further comprising:

and when the first logical address-physical address mapping table comprises the second sub-logical address-physical address mapping table, determining that the operation mode of the rewritable non-volatile memory module is a second mode.

4. The mapping table loading method according to claim 1, further comprising, before the step of receiving the first instruction:

executing a third instruction according to a second logical address-physical address mapping table;

when the second logical address-physical address mapping table is different from the first logical address-physical address mapping table, determining that the operation mode of the rewritable non-volatile memory module is the first operation mode.

5. The mapping table loading method according to claim 1, wherein when the operation mode of the rewritable non-volatile memory module is the first operation mode, the method further comprises:

executing the first instruction according to the first sub-logical address-to-physical address mapping table;

erasing the first sub-logical address-physical address mapping table; and

recording the use history of the first sub-logical address-physical address mapping table in a management table.

6. The mapping table loading method according to claim 1, wherein the operation mode of the rewritable nonvolatile memory module after each power-on is the first operation mode by default.

7. The mapping table loading method as claimed in claim 1, wherein the first operation mode comprises a random read operation mode, a random write operation mode or an operation mode for selecting a garbage collection block in a garbage collection procedure.

8. The method as claimed in claim 1, wherein the second operation mode comprises a continuous read operation mode, a continuous write operation mode, a write operation mode for writing to a destination block in a garbage collection procedure, or a flush operation mode.

9. A memory control circuit unit for controlling a rewritable nonvolatile memory module, the memory control circuit unit comprising:

a host interface for electrically connecting to a host system;

a memory interface electrically connected to the rewritable non-volatile memory module, wherein the rewritable non-volatile memory module stores a plurality of logical address-physical address mapping tables, and each logical address-physical address mapping table has a plurality of sub-logical address-physical address mapping tables;

a buffer memory; and

a memory management circuit electrically connected to the host interface, the memory interface and the buffer memory,

the memory management circuit is configured to receive a first instruction, wherein the first instruction corresponds to data stored at a first logical address,

when an operation mode corresponding to the rewritable non-volatile memory module is a first operation mode, the memory management circuit is further configured to load a first sub-logical address-physical address mapping table of the plurality of sub-logical address-physical address mapping tables from the rewritable non-volatile memory module into the buffer memory, wherein the first sub-logical address-physical address mapping table records mapping information corresponding to the first logical address,

when the operation mode corresponding to the rewritable non-volatile memory module is a second operation mode, the memory management circuit is further configured to load a first logical address-physical address mapping table of the plurality of logical address-physical address mapping tables from the rewritable non-volatile memory module into the buffer memory, wherein the first logical address-physical address mapping table records mapping information corresponding to the first logical address,

10. The memory control circuit unit of claim 9, wherein, prior to operation to receive the first instruction,

the memory management circuit is further configured to execute a second instruction according to a second sub-logical address-to-physical address mapping table,

when the second sub-logical address-to-physical address mapping table is different from the first sub-logical address-to-physical address mapping table, the memory management circuit is further configured to determine that the operation mode of the rewritable non-volatile memory module is the first operation mode, and

when the second sub-logical address-to-physical address mapping table is the same as the first sub-logical address-to-physical address mapping table, the memory management circuit is further configured to determine that the operation mode of the rewritable non-volatile memory module is the second operation mode.

11. The memory control circuit unit of claim 10, wherein when the second sub-logical address-to-physical address mapping table is different from the first sub-logical address-to-physical address mapping table,

when the first logical address-to-physical address mapping table includes the second sub-logical address-to-physical address mapping table, the memory management circuit is further configured to determine that the operation mode of the rewritable non-volatile memory module is a second mode.

12. The memory control circuit unit of claim 9, wherein, prior to operation to receive the first instruction,

the memory management circuit is further configured to execute a third instruction according to a second logical address to physical address mapping table,

when the second logical address-to-physical address mapping table is different from the first logical address-to-physical address mapping table, the memory management circuit is further configured to determine that the operation mode of the rewritable non-volatile memory module is the first operation mode.

13. The memory control circuit unit of claim 9, wherein when the operation mode of the rewritable non-volatile memory module is the first operation mode,

the memory management circuit is further configured to execute the first instruction according to the first sub-logical address-to-physical address mapping table,

the memory management circuit is further configured to erase the first sub-logical address-physical address mapping table, an

The memory management circuit is further configured to record a usage history of the first sub-logical address-physical address mapping table in a management table.

14. The memory control circuit unit of claim 9, wherein the operation mode of the rewritable non-volatile memory module after each power-up is the first operation mode by default.

15. The memory control circuit unit of claim 9, wherein the first operation mode comprises a random read operation mode, a random write operation mode, or an operation mode for selecting the garbage collection block in a garbage collection procedure.

16. The memory control circuit unit of claim 9, wherein the second operation mode comprises a continuous read operation mode, a continuous write operation mode, a write operation mode to a destination block in a garbage collection procedure, or a bin-clearing operation mode.

17. A memory storage device, comprising:

a connection interface unit for electrically connecting to a host system;

a rewritable non-volatile memory module for storing multiple logical address-physical address mapping tables, each having multiple sub-logical address-physical address mapping tables; and

a memory control circuit unit including a buffer memory, wherein the memory control circuit unit is electrically connected to the connection interface unit and the rewritable nonvolatile memory module,

wherein the memory control circuitry is configured to receive a first instruction, wherein the first instruction corresponds to data stored at a first logical address,

when an operation mode corresponding to the rewritable non-volatile memory module is a first operation mode, the memory control circuit unit is further configured to load a first sub-logical address-physical address mapping table of the plurality of sub-logical address-physical address mapping tables from the rewritable non-volatile memory module into the buffer memory, wherein the first sub-logical address-physical address mapping table records mapping information corresponding to the first logical address,

when the operation mode corresponding to the rewritable non-volatile memory module is a second operation mode, the memory control circuit unit is further configured to load a first logical address-physical address mapping table among the plurality of logical address-physical address mapping tables from the rewritable non-volatile memory module into the buffer memory, wherein the first logical address-physical address mapping table records mapping information corresponding to the first logical address,

18. The memory storage device of claim 17, wherein prior to operation to receive the first instruction,

the memory control circuit unit is further configured to execute a second instruction according to a second sub-logical address-to-physical address mapping table,

when the second sub-logical address-to-physical address mapping table is different from the first sub-logical address-to-physical address mapping table, the memory control circuit unit is further configured to determine that the operation mode of the rewritable non-volatile memory module is the first operation mode, and

when the second sub-logical address-to-physical address mapping table is the same as the first sub-logical address-to-physical address mapping table, the memory control circuit unit is further configured to determine that the operation mode of the rewritable non-volatile memory module is the second operation mode.

19. The memory storage device of claim 18, wherein the memory control circuitry unit is further configured to determine the operating mode of the rewritable non-volatile memory module as a second mode when the first logical address-to-physical address mapping table comprises the second sub-logical address-to-physical address mapping table when the second sub-logical address-to-physical address mapping table is different from the first sub-logical address-to-physical address mapping table.

20. The memory storage device of claim 17, wherein prior to operation to receive the first instruction,

the memory control circuit unit is further configured to execute a third instruction according to a second logical address-physical address mapping table;

when the second logical address-to-physical address mapping table is different from the first logical address-to-physical address mapping table, the memory control circuit unit is further configured to determine that the operation mode of the rewritable non-volatile memory module is the first operation mode.

21. The memory storage device of claim 17, wherein when the operating mode of the rewritable non-volatile memory module is the first operating mode,

the memory control circuitry is further configured to execute the first instruction according to the first sub-logical address-to-physical address mapping table,

the memory control circuit unit is further used for erasing the first sub-logical address-physical address mapping table, an

The memory control circuit unit is further configured to record a usage history of the first sub-logical address-physical address mapping table in a management table.

22. The memory storage device of claim 17, wherein the operating mode of the rewritable non-volatile memory module after each power-up is the first operating mode by default.

23. The memory storage device of claim 17, wherein the first operating mode comprises a random read operating mode, a random write operating mode, or a garbage collection operation mode for selecting the garbage collection block.

24. The memory storage device of claim 17, wherein the second mode of operation comprises a continuous read mode of operation, a continuous write mode of operation, a write to destination block mode of operation in a garbage collection procedure, or a flush mode of operation.