CN107402716B

CN107402716B - Data writing method, memory control circuit unit and memory storage device

Info

Publication number: CN107402716B
Application number: CN201610356300.2A
Authority: CN
Inventors: 柯伯政
Original assignee: Hefei Core Storage Electronic Ltd
Current assignee: Hefei Core Storage Electronic Ltd
Priority date: 2016-05-20
Filing date: 2016-05-20
Publication date: 2021-06-08
Anticipated expiration: 2036-05-20
Also published as: CN107402716A

Abstract

The invention provides a data writing method, a memory control circuit unit and a memory storage device. The method comprises the following steps: receiving a first write command, and writing data corresponding to the first write command into a buffer memory; and when the write cache function is closed and the data of the first write command is temporarily stored in the buffer memory, writing the data corresponding to the first write command from the buffer memory into a first physical programming unit of a first physical erasing unit by using a single page programming mode, wherein the first physical programming unit is composed of a plurality of first memory cells and each of the first memory cells composing the first physical programming unit only stores 1 bit of data in the single page programming mode. The invention can effectively avoid data loss caused by abnormal power failure of the host system and can effectively utilize the space of the rewritable nonvolatile memory.

Description

Data writing method, memory control circuit unit and memory storage device

Technical Field

The invention relates to a data writing method, a memory control circuit unit and a memory storage device.

Background

Digital cameras, cellular phones, and MP3 have grown rapidly over the years, resulting in a rapid increase in consumer demand for storage media. Since the rewritable non-volatile memory (rewritable non-volatile memory) has the characteristics of non-volatility, power saving, small volume, no mechanical structure, high read-write speed and the like, the rewritable non-volatile memory is most suitable for portable electronic products such as notebook computers. A solid state disk is a memory storage device using a flash memory as a storage medium. Therefore, the flash memory industry has become a relatively popular segment of the electronics industry in recent years.

The NAND-type flash memory is classified into a Single Level Cell (SLC) NAND-type flash memory, a Multi-Level Cell (MLC) NAND-type flash memory, and a Triple Level Cell (TLC) NAND-type flash memory according to the number of bits that can be stored in each memory Cell in the rewritable non-volatile memory, wherein each memory Cell of the SLC NAND-type flash memory can store 1 bit of data (i.e., "1" and "0"), each memory Cell of the MLC NAND-type flash memory can store 2 bits of data, and each memory Cell of the TLC NAND-type flash memory can store 3 bits of data.

In the NAND type flash memory, a physical program unit is composed of a plurality of memory cells arranged on a same word line. Since each cell of the SLC NAND flash can store 1 bit of data, several cells arranged on the same word line correspond to one physical program unit in the SLC NAND flash.

In contrast to SLC NAND-type flash memory, the floating gate storage layer of each cell of MLC NAND-type flash memory can store 2 bits of data, where each storage state (i.e., "11", "10", "01", and "00") includes the Least Significant Bit (LSB) and the Most Significant Bit (MSB). For example, the value of the 1 st bit from the left side in the storage state is LSB, and the value of the 2 nd bit from the left side is MSB. Therefore, the memory cells arranged on the same word line can constitute 2 physical programming units, wherein the physical programming unit constituted by the LSBs of the memory cells is called a lower physical programming unit (low physical programming unit), and the physical programming unit constituted by the MSBs of the memory cells is called an upper physical programming unit (upper physical programming unit). It should be noted that when an error or abnormal system power failure occurs while programming the upper physical programming unit, the data stored in the lower physical programming unit may be lost. In addition, when the lower physical programming unit is programmed and the upper physical programming unit corresponding to the lower physical programming unit is not yet programmed, the data stored in the lower physical programming unit may present an unstable state due to the characteristics of the mlc nand-type flash memory. In this state, the data stored in the lower physical program unit is also at risk of loss or damage.

Generally, when a memory controller of a rewritable nonvolatile memory receives a write command from a host system, data corresponding to the write command is usually temporarily stored in a buffer memory and write completion information corresponding to the write command is immediately returned to the host system in response to a write operation issued by the host system. Then, the memory controller writes the data in the buffer memory into the rewritable non-volatile memory at an appropriate time, for example, when the host system is idle for a certain period of time or the available space in the buffer memory is insufficient.

However, a typical buffer memory is a volatile memory. That is, when a piece of data is stored in the buffer memory but not written into the rewritable non-volatile memory, if the host system is powered off abnormally, the data stored in the buffer memory is lost.

Therefore, the host system can be generally prevented from abnormally powering down and causing the loss of the data stored in the buffer memory by using a write cache close (disable write cache) instruction. In detail, after the memory controller receives a write cache closing command from the host system, when the memory controller receives a write command from the host system, data corresponding to the write command is written into the buffer memory, and the memory controller immediately writes the data of the write command from the buffer memory into the rewritable non-volatile memory, so as to reduce the time for the data of the write command to stay in the buffer memory and reduce the risk of data loss.

However, it should be noted that the data of the write command may not fill the lower physical program cell and the upper physical program cell of one physical program cell at the same time. Therefore, if the data of the write command is only written into the lower physical programming unit and the upper physical programming unit corresponding to the lower physical programming unit does not store data, the data stored in the lower physical programming unit may be in an unstable state due to the characteristics of the MLC NAND-type flash memory, and may be lost.

In a conventional method, in order to avoid the loss of the data stored in the bottom-level physical programming unit caused by the above-mentioned situation, the memory controller may write redundant data (dummy data) into the top-level physical programming unit, so that the bottom-level physical programming unit is in a stable state, thereby ensuring that the data in the bottom-level physical programming unit is completely and stably stored. However, when the memory controller receives a write cache close command from the host system, it may write too much redundant data into the rewritable nonvolatile memory due to multiple write commands, which causes a problem of write amplification (write amplification), which is well known to those skilled in the art, and this problem causes a low storage efficiency of the rewritable nonvolatile memory.

Therefore, it is an objective of those skilled in the art to avoid the loss of data in the buffer memory due to abnormal power failure of the host system, and to ensure that the data of the write command before the abnormal power failure is stably stored in the rewritable non-volatile memory and the space of the rewritable non-volatile memory is effectively utilized.

Disclosure of Invention

The invention provides a data writing method, a memory control circuit unit and a memory storage device, which can effectively avoid data loss caused by abnormal power failure of a host system and effectively utilize the space of a rewritable nonvolatile memory.

The invention provides a data writing method for a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module is provided with a plurality of entity erasing units, each entity erasing unit in the entity erasing units is provided with a plurality of entity programming units, and the data writing method comprises the following steps: receiving a first write command from a host system, and temporarily storing data corresponding to the first write command into a buffer memory; and when the write cache function is closed and the data of the first write command is temporarily stored in the buffer memory, writing the data corresponding to the first write command from the buffer memory into a first physical programming unit of a first physical erasing unit among the physical erasing units by using a single page programming mode, wherein the first physical programming unit is composed of a plurality of first memory cells and each of the first memory cells composing the first physical programming unit only stores 1 bit of data in the single page programming mode.

In an embodiment of the present invention, the method further includes: a write cache close command is received from the host system, and the write cache function is closed in response to the write cache close command.

In an embodiment of the present invention, before the step of receiving the write cache close command from the host system, the method further includes: receiving a second write command from the host system and temporarily storing data corresponding to the second write command into the buffer memory; and writing the data temporarily stored in the buffer memory corresponding to the second write command to a second physical program unit of second physical erase units among the physical erase units using a multi-page program mode, wherein the second physical program unit is composed of a plurality of second memory cells and each of the second memory cells constituting the second physical program unit stores a plurality of bits of data in the multi-page program mode.

In an embodiment of the present invention, after the step of writing the data corresponding to the first write command from the buffer memory to the first physically programmed cell of the first physically erased cells among the physically erased cells using the single page programming mode, the method further includes: and replying the write completion information to the host system.

In an embodiment of the invention, the data writing method further includes: and when the write-in cache function is closed and the data of the first write-in command is temporarily stored in the buffer memory, issuing a flush command to execute the step of writing the data corresponding to the first write-in command into the first entity programming unit of the first entity erasing unit from the buffer memory by using the single-page programming mode.

In an embodiment of the invention, the data writing method further includes: in the background execution mode, an effective data merge operation is performed to copy a plurality of effective data in the first physically erased cell to a plurality of third physically programmed cells in a third physically erased cell of the physically erased cells using a multi-page program mode, wherein the third physically programmed cells are formed of a plurality of third memory cells and each of the third memory cells forming the third physically programmed cells stores a plurality of bits of data in the multi-page program mode.

In an embodiment of the invention, the data writing method further includes: a write cache open instruction is received, and the write cache function is opened in response to the write cache open instruction.

In an embodiment of the invention, the multi-page programming mode is a multi-level cell programming mode or a three-level cell programming mode, and the single-page programming mode is a single-level cell programming mode, a bottom-entity programming mode, a mixed programming mode, or a reduced-level cell programming mode.

An exemplary embodiment of the present invention provides a memory control circuit unit for controlling a rewritable nonvolatile memory module. The memory control circuit unit includes: a host interface for electrically connecting to a host system; the memory interface is electrically connected to the rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module is provided with a plurality of entity erasing units, and each entity erasing unit in the entity erasing units is provided with a plurality of entity programming units; a buffer memory electrically connected to the host interface and the memory interface; and a memory management circuit electrically connected to the host interface, the memory interface and the buffer memory. The memory management circuit is used for: receiving a first write command from a host system, and temporarily storing data corresponding to the first write command into a buffer memory; and when the write cache function is closed and the data of the first write command is temporarily stored in the buffer memory, issuing a first command sequence to write the data corresponding to the first write command from the buffer memory to a first physical programming unit of a first physical erasing unit among the physical erasing units by using a single page programming mode, wherein the first physical programming unit is composed of a plurality of first memory cells and each of the first memory cells composing the first physical programming unit stores only 1 bit of data in the single page programming mode.

In an exemplary embodiment of the present invention, the memory management circuit is further configured to: a write cache close command is received from the host system, and the write cache function is closed in response to the write cache close command.

In an exemplary embodiment of the invention, prior to the operation of receiving the write cache close instruction from the host system, the memory management circuit is further configured to: receiving a second write command from the host system and temporarily storing data corresponding to the second write command into the buffer memory; and issuing a second command sequence to write the data corresponding to the second write command temporarily stored in the buffer memory into a second physical programming unit of second physical erase units among the physical erase units using a multi-page programming mode, wherein the second physical programming unit is composed of a plurality of second memory cells and each of the second memory cells constituting the second physical programming unit stores a plurality of bits of data in the multi-page programming mode.

In an exemplary embodiment of the invention, after the operation of writing the data corresponding to the first write command from the buffer memory into the first physically programmed cell of the first one of the physically erased cells using the single page programming mode, the memory management circuit is further configured to: and replying the write completion information to the host system.

In an exemplary embodiment of the invention, wherein the first instruction sequence is a flush instruction, the memory management circuit is further configured to: when the write cache function is closed and the data of the first write command is temporarily stored in the buffer memory, the operation of writing the data corresponding to the first write command from the buffer memory to the first entity programming unit of the first entity erasing unit by using the single page programming mode is executed according to the flush command.

In an exemplary embodiment of the invention, the memory management circuit is further configured to: in the background execution mode, an effective data merge operation is performed to copy a plurality of effective data in the first physically erased cell to a plurality of third physically programmed cells in a third physically erased cell of the physically erased cells using a multi-page program mode, wherein the third physically programmed cells are formed of a plurality of third memory cells and each of the third memory cells forming the third physically programmed cells stores a plurality of bits of data in the multi-page program mode.

In an exemplary embodiment of the invention, the memory management circuit is further configured to: a write cache open instruction is received, and the write cache function is opened in response to the write cache open instruction.

In an exemplary embodiment of the invention, the multi-page programming mode is a multi-level cell programming mode or a three-level cell programming mode, and the single-page programming mode is a single-level cell programming mode, a bottom-entity programming mode, a mixed programming mode, or a reduced-level cell programming mode.

An exemplary embodiment of the present invention provides a memory storage device. It includes: the memory control circuit unit is electrically connected to the connection interface unit and the rewritable nonvolatile memory module. The memory control circuit unit comprises a buffer memory, the rewritable nonvolatile memory is provided with a plurality of entity erasing units, and each entity erasing unit in the entity erasing units is provided with a plurality of entity programming units. The memory control circuit unit is used for: receiving a first write command from a host system, and temporarily storing data corresponding to the first write command into a buffer memory; and when the write cache function is closed and the data of the first write command is temporarily stored in the buffer memory, issuing a first command sequence to write the data corresponding to the first write command from the buffer memory to a first physical programming unit of a first physical erasing unit among the physical erasing units by using a single page programming mode, wherein the first physical programming unit is composed of a plurality of first memory cells and each of the first memory cells composing the first physical programming unit stores only 1 bit of data in the single page programming mode.

In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to: a write cache close command is received from the host system, and the write cache function is closed in response to the write cache close command.

In an exemplary embodiment of the invention, prior to the operation of receiving the write cache close instruction from the host system, the memory control circuit unit is further configured to: receiving a second write command from the host system and temporarily storing data corresponding to the second write command into the buffer memory; and issuing a second command sequence to write the data corresponding to the second write command temporarily stored in the buffer memory into a second physical programming unit of second physical erase units among the physical erase units using a multi-page programming mode, wherein the second physical programming unit is composed of a plurality of second memory cells and each of the second memory cells constituting the second physical programming unit stores a plurality of bits of data in the multi-page programming mode.

In an exemplary embodiment of the invention, after the operation of writing the data corresponding to the first write command from the buffer memory into the first physically programmed cell of the first physically erased cell among the physically erased cells using the single page programming mode, the memory control circuit unit is further configured to: and replying the write completion information to the host system.

In an exemplary embodiment of the invention, wherein the first instruction sequence is a flush instruction, the memory control circuit unit is further configured to: when the write cache function is closed and the data of the first write command is temporarily stored in the buffer memory, the operation of writing the data corresponding to the first write command from the buffer memory to the first entity programming unit of the first entity erasing unit by using the single page programming mode is executed according to the flush command.

In an exemplary embodiment of the invention, the memory control circuit unit is further configured to: in the background execution mode, an effective data merge operation is performed to copy a plurality of effective data in the first physically erased cell to a plurality of third physically programmed cells in a third physically erased cell of the physically erased cells using a multi-page program mode, wherein the third physically programmed cells are formed of a plurality of third memory cells and each of the third memory cells forming the third physically programmed cells stores a plurality of bits of data in the multi-page program mode.

In an exemplary embodiment of the invention, the memory control circuit unit is further configured to: a write cache open instruction is received, and the write cache function is opened in response to the write cache open instruction.

Based on the above, the data writing method of the present invention can effectively avoid the loss of data in the buffer memory due to the abnormal power failure of the host system, and ensure that the data of the write command before the abnormal power failure is stably stored in the rewritable non-volatile memory and the space of the rewritable non-volatile memory is effectively utilized.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

FIG. 1 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment;

FIG. 2 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to another example embodiment;

FIG. 3 is a schematic diagram of a host system and a memory storage device according to another example embodiment;

FIG. 4 is a schematic block diagram illustrating a host system and a memory storage device according to an example embodiment;

FIGS. 5A and 5B are schematic diagrams illustrating an example memory cell storage architecture and physically erased cells according to an example embodiment;

FIG. 6 is a schematic block diagram of memory control circuitry shown in accordance with an example embodiment;

FIGS. 7 and 8 illustrate exemplary managing physical erase units according to one exemplary embodiment;

FIG. 9 is a diagram illustrating writing data to a rewritable nonvolatile memory module using a single page programming mode according to an example;

FIG. 10 is a schematic diagram showing an effective data merge operation using a multi-page program mode for data written in a single-page program mode, according to an example;

FIGS. 11 and 12 are flowcharts illustrating a data writing method according to an example embodiment.

Reference numerals:

10: memory storage device

11: host system

12: input/output (I/O) device

110: system bus

111: processor with a memory having a plurality of memory cells

112: random Access Memory (RAM)

113: read-only memory (ROM)

114: data transmission interface

20: main board

204: wireless memory storage device

205: global positioning system module

206: network adapter

207: wireless transmission device

208: keyboard with a keyboard body

209: screen

210: horn type loudspeaker

30: memory storage device

31: host system

32: SD card

33: CF card

34: embedded storage device

341: embedded multimedia card

342: embedded multi-chip packaging storage device

402: connection interface unit

404: memory control circuit unit

406: rewritable nonvolatile memory module

410(0) to 410 (N): physical erase unit

WL 0-WL 127: character line

502: memory management circuit

504: host interface

506: memory interface

508: buffer memory

510: power management circuit

512: error checking and correcting circuit

602: data area

604: idle zone

606: system area

608: substitution zone

LBA (0) to LBA (h): logical addresses

LZ (0) to LZ (M): logical area

S1101: step for judging whether receiving write cache closing command or write cache opening command from host system

S1103: closing the write cache function in response to a write cache close command if the write cache close command is received from the host system

S1105: if a write cache open command is received from the host system, opening the write cache function in response to the write cache open command

S1201: receiving a first write command from a host system and temporarily storing data corresponding to the first write command in a buffer memory

S1203: step for judging whether the write cache function is closed

S1205: writing data corresponding to the first write command from the buffer memory into a first one of the physically erased units using a single page program mode when the write cache function has been turned off

S1207: writing data corresponding to a first write command from the buffer memory into a first one of the physically erased units using a multiple page program mode when the write cache function is not turned off

Detailed Description

Generally, a memory storage device (also referred to as a memory storage system) includes a rewritable nonvolatile memory module and a controller (also referred to as a control circuit unit). Memory storage devices are typically used with a host system so that the host system can write data to or read data from the memory storage device.

Fig. 1 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment, and fig. 2 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to another example embodiment.

Referring to fig. 1 and 2, the host system 11 generally includes a processor 111, a Random Access Memory (RAM) 112, a Read Only Memory (ROM) 113, and a data transmission interface 114. The processor 111, the RAM 112, the ROM 113, and the data transmission interface 114 are all electrically connected to the system bus (system bus) 110.

In the present exemplary embodiment, the host system 11 is electrically connected to the memory storage device 10 through the data transmission interface 114. For example, host system 11 may write data to memory storage device 10 or read data from memory storage device 10 via data transfer interface 114. In addition, the host system 11 is electrically connected to the I/O device 12 via a system bus 110. For example, the host system 11 may transmit output signals to the I/O device 12 or receive input signals from the I/O device 12 via the system bus 110.

In the present exemplary embodiment, the processor 111, the random access memory 112, the read only memory 113 and the data transmission interface 114 may be disposed on the motherboard 20 of the host system 11. The number of the data transmission interfaces 114 may be one or more. Through the data transmission interface 114, the main board 20 can be electrically connected to the memory storage device 10 in a wired or wireless manner. The memory storage device 10 can be, for example, a flash Drive 201, a memory card 202, a Solid State Drive (SSD) 203, or a wireless memory storage device 204. The wireless memory Storage device 204 can be, for example, a Near Field Communication (NFC) memory Storage device, a wireless facsimile (WiFi) memory Storage device, a Bluetooth (Bluetooth) memory Storage device, or a low power Bluetooth memory Storage device (e.g., iBeacon) based on various wireless Communication technologies. In addition, the motherboard 20 may also be electrically connected to various I/O devices such as a Global Positioning System (GPS) module 205, a network adapter 206, a wireless transmission device 207, a keyboard 208, a screen 209, and a speaker 210 through the System bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 via the wireless transmission device 207.

In an exemplary embodiment, the host system referred to is substantially any system that can cooperate with a memory storage device to store data. Although the host system is described as a computer system in the above exemplary embodiment, fig. 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment. Referring to fig. 3, in another exemplary embodiment, the host system 31 may also be a digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer, and the memory storage device 30 may be various non-volatile memory storage devices such as an SD card 32, a CF card 33, or an embedded storage device 34. The embedded storage device 34 includes various types of embedded Multi-media cards (eMMC) 341 and/or embedded Multi-Chip Package storage devices (eMCP) 342 to electrically connect the memory module directly to the embedded storage device on the substrate of the host system.

FIG. 4 is a schematic block diagram illustrating a host system and a memory storage device according to an example embodiment.

Referring to fig. 4, the memory storage device 10 includes a connection interface unit 402, a memory control circuit unit 404 and a rewritable nonvolatile memory module 406.

In the exemplary embodiment, connection interface unit 402 is compliant with the Serial Advanced Technology Attachment (SATA) standard. However, it should be understood that the present invention is not limited thereto, and the connection interface unit 402 may also conform to the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronic Engineers (IEEE) 1394 standard, the High-Speed Peripheral Component connection interface (PCI Express) standard, the Universal Serial Bus (USB) standard, the Ultra High Speed Specification-I interface standard, the Ultra High Speed Specification-II (UHS-II) interface standard, the Secure Digital (SD) interface standard, the Memory Stick (Memory Stick, MS) interface standard, the Multi-Chip Package (Multi-Package) interface standard, the Multimedia storage Card (Multi, Embedded Multimedia Card, Multimedia storage Card (MMC) interface standard, eMMC) interface standard, Universal Flash Storage (UFS) interface standard, embedded Multi-Chip Package (eMCP) interface standard, Compact Flash (CF) interface standard, Integrated Device Electronics (IDE) standard, or other suitable standard. In the present exemplary embodiment, the connection interface unit 402 and the memory control circuit unit 404 may be packaged in one chip, or the connection interface unit 402 is disposed outside a chip including the memory control circuit unit.

The memory control circuit unit 404 is used for executing a plurality of logic gates or control commands implemented in a hardware type or a firmware type, and performing operations such as writing, reading and erasing data in the rewritable nonvolatile memory module 406 according to commands of the host system 11.

The rewritable nonvolatile memory module 406 is electrically connected to the memory control circuit unit 404 and is used for storing data written by the host system 11. The rewritable nonvolatile memory module 406 has physical erase units 410(0) -410 (N). For example, the physical erase units 410(0) -410 (N) may belong to the same memory die (die) or to different memory dies. Each of the plurality of physical erase units has a plurality of physical program units, wherein the physical program units belonging to the same physical erase unit can be independently written and simultaneously erased. However, it should be understood that the invention is not limited thereto, and each of the plurality of physically erased cells may be composed of 64 physically programmed cells, 256 physically programmed cells, or any other number of physically programmed cells.

In more detail, the physically erased cell is the minimum unit of erase. That is, each physically erased cell contains one of the minimum number of memory cells that are erased. The physical programming unit is a minimum unit for programming. That is, the physical programming unit is the minimum unit for writing data. Each physical programming cell typically includes a data bit region and a redundancy bit region. The data bit region includes a plurality of physical access addresses for storing user data, and the redundant bit region is used for storing system data (e.g., control information and error correction codes). In the exemplary embodiment, each physical program unit includes 8 physical access addresses in the data bit region, and one physical access address has a size of 512 bytes (byte). However, in other exemplary embodiments, the data bit region may include a greater or lesser number of physical access addresses, and the size and number of the physical access addresses are not limited in the present invention. For example, in an exemplary embodiment, the physically erased cells are physical blocks, and the physically programmed cells are physical pages or physical sectors, but the invention is not limited thereto.

In the present exemplary embodiment, the rewritable nonvolatile memory module 406 is a Multi-Level Cell (MLC) NAND-type flash memory module (i.e., a flash memory module capable of storing 2 bits of data in one memory Cell). However, the invention is not limited thereto, and the rewritable nonvolatile memory module 406 may also be a three-Level Cell (TLC) NAND-type flash memory module (i.e., a flash memory module capable of storing 3 bits of data in one memory Cell) or other memory modules with the same characteristics.

FIGS. 5A and 5B are schematic diagrams illustrating an example memory cell storage architecture and physically erased cells according to an example embodiment. In the present exemplary embodiment, an MLC NAND flash memory is exemplified.

Referring to FIG. 5A, each memory cell of the rewritable nonvolatile memory module 406 can store 2 bits of data, and the storage state of each memory cell can be identified as "11", "10", "01", or "00". Each of the storage states includes a Least Significant Bit (LSB) and a Most Significant Bit (MSB). For example, the value of the 1 st bit from the left side in the storage state is LSB, and the value of the 2 nd bit from the left side is MSB. Therefore, several memory cells connected to the same word line can be configured into 2 physical program units, wherein the physical program unit composed of the LSBs of the memory cells is referred to as a lower physical program unit, and the physical program unit composed of the MSBs of the memory cells is referred to as an upper physical program unit.

Referring to FIG. 5B, a physical erase unit is composed of a plurality of physical program unit groups, wherein each physical program unit group includes a lower physical program unit and an upper physical program unit composed of a plurality of memory cells arranged on the same word line. For example, in the physical erase cell, the 0 th physical page belonging to the lower physical program cell and the 1 st physical page belonging to the upper physical program cell are composed of memory cells arranged on the word line WL0, and thus are regarded as a physical program cell group. Similarly, the 2 nd physical program cell and the 3 rd physical program cell are composed of memory cells arranged on the word line WL1, and thus are considered as a physical program cell group, and so on, other physical program cells are divided into a plurality of physical program cell groups according to this manner.

FIG. 6 is a schematic block diagram of a memory control circuit unit shown in accordance with an example embodiment.

Referring to FIG. 6, the memory control circuit unit 404 includes a memory management circuit 502, a host interface 504, a memory interface 506, a buffer memory 508, a power management circuit 510, and an error checking and correcting circuit 512.

The memory management circuit 502 is used to control the overall operation of the memory control circuit unit 404. Specifically, the memory management circuit 502 has a plurality of control commands, and the control commands are executed to perform data writing, reading, and erasing operations when the memory storage device 10 is in operation.

In the exemplary embodiment, the control instructions of the memory management circuit 502 are implemented in firmware. For example, the memory management circuit 502 has a microprocessor unit (not shown) and a read only memory (not shown), and the control commands are recorded in the read only memory. When the memory storage device 10 is in operation, the control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.

FIGS. 7 and 8 illustrate exemplary embodiments of managing physically erased cells, according to an exemplary embodiment.

It should be understood that, when describing the operation of the physically erased cells of the rewritable non-volatile memory module 406, it is a logical concept to operate the physically erased cells by the words "extract", "group", "partition", "associate", and the like. That is, the physical locations of the physical erase units of the rewritable nonvolatile memory module are not changed, but the physical erase units of the rewritable nonvolatile memory module are logically operated.

Referring to FIG. 7, the memory control circuit unit 404 (or the memory management circuit 502) logically groups the physical erase units 410(0) -410 (N) into a data area 602, an idle area 604, a system area 606, and a replacement area 608.

The physically erased cells logically belonging to the data area 602 and the idle area 604 are used for storing data from the host system 11. Specifically, the wear-leveling cells in the data area 602 are regarded as the wear-leveling cells storing data, and the wear-leveling cells in the idle area 604 are used to replace the wear-leveling cells in the data area 602. That is, when receiving a write command and data to be written from the host system 11, the memory management circuit 502 writes the data by extracting the physical erase unit from the idle region 604 to replace the physical erase unit in the data region 602.

The physically erased cells logically belonging to the system area 606 are used for recording system data. For example, the system data includes information about the manufacturer and model of the rewritable nonvolatile memory module, the number of physically erased cells of the rewritable nonvolatile memory module, the number of physically programmed cells per each physically erased cell, and the like.

The physically erased cells logically belonging to the replacement area 608 are used in the bad-physically-erased-cell replacement procedure to replace the damaged physically erased cells. Specifically, if there are normal physically erased cells in the replacement area 608 and the physically erased cells in the data area 602 are damaged, the memory management circuit 502 extracts the normal physically erased cells from the replacement area 608 to replace the damaged physically erased cells.

In particular, the number of physically erased cells in the data area 602, the idle area 604, the system area 606 and the replacement area 608 may vary according to different memory specifications. Moreover, it should be understood that during operation of the memory storage device 10, the grouping relationship of the physically erased cells associated with the data area 602, the idle area 604, the system area 606 and the replacement area 608 may dynamically change. For example, when the physically erased cells in the idle area 604 are damaged and replaced by the physically erased cells in the replacement area 608, the physically erased cells in the replacement area 608 are associated with the idle area 604.

Referring to fig. 8, the memory control circuit unit 404 (or the memory management circuit 502) configures logical addresses LBA (0) to LBA (h) to map the physical erase units of the data area 602, where each logical address has a plurality of logical units to map the physical program units of the corresponding physical erase units. Moreover, when the host system 11 is going to write data to the logical address or update the data stored in the logical address, the memory control circuit unit 404 (or the memory management circuit 502) will extract one physical erase unit from the idle area 604 as an active physical erase unit to write data, so as to replace the physical erase unit of the data area 602. Moreover, when the physical erase unit as the active physical erase unit is full, the memory control circuit unit 404 (or the memory management circuit 502) will extract the empty physical erase unit from the idle area 604 as the active physical erase unit to continue writing the update data corresponding to the write command from the host system 11. In addition, when the number of available physical erase units in the idle area 604 is smaller than a predetermined value, the memory control circuit unit 404 (or the memory management circuit 502) performs a valid data merge operation (also referred to as a garbage collection (garbage collection) operation) to collate the valid data in the data area 602 so as to re-associate the physical erase units in the data area 602 that do not store the valid data with the idle area 604.

In order to identify the physical erase unit in which the data of each logical address is stored, in the exemplary embodiment, the memory control circuit unit 404 (or the memory management circuit 502) records the mapping between the logical address and the physical erase unit. For example, in the present exemplary embodiment, the memory control circuit unit 404 (or the memory management circuit 502) stores a logical-to-physical mapping table in the rewritable nonvolatile memory module 406 to record the physical erase unit mapped by each logical address. When data is to be accessed, the memory control circuit unit 404 (or the memory management circuit 502) loads the logical-to-physical mapping table into the buffer memory 508 for maintenance, and writes or reads data according to the logical-to-physical mapping table.

It should be noted that, since the buffer 508 has a limited capacity and cannot store a mapping table for recording mapping relationships of all logical addresses, in the exemplary embodiment, the memory control circuit unit 404 (or the memory management circuit 502) groups the logical addresses LBA (0) -LBA (h) into a plurality of logical zones LZ (0) -LZ (m), and configures a logical-physical mapping table for each logical zone. In particular, when the memory control circuit unit 404 (or the memory management circuit 502) wants to update the mapping of a logical address, the logical-to-physical mapping table corresponding to the logical area to which the logical address belongs is loaded to the buffer memory 508 for updating.

In another exemplary embodiment of the invention, the control instructions of the memory management circuit 502 can also be stored in a specific area of the rewritable nonvolatile memory module 406 (for example, a system area dedicated to storing system data in the memory module) by using a program code type. In addition, the memory management circuit 502 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the rom has a driver code, and when the memory control circuit unit 404 is enabled, the microprocessor unit first executes the driver code segment to load the control command stored in the rewritable nonvolatile memory module 406 into the ram of the memory management circuit 502. Then, the microprocessor unit operates the control commands to perform data writing, reading, erasing, and the like.

In another exemplary embodiment of the invention, the control instructions of the memory management circuit 502 can also be implemented in a hardware form. For example, the memory management circuit 502 includes a microcontroller, a cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory cell management circuit, the memory writing circuit, the memory reading circuit, the memory erasing circuit and the data processing circuit are electrically connected to the microcontroller. The memory cell management circuit is used for managing the entity erasing unit of the rewritable nonvolatile memory module 406; the memory writing circuit is used for issuing a writing instruction to the rewritable nonvolatile memory module 406 so as to write data into the rewritable nonvolatile memory module 406; the memory reading circuit is used for sending a reading instruction to the rewritable nonvolatile memory module 406 so as to read data from the rewritable nonvolatile memory module 406; the memory erasing circuit is used for issuing an erasing instruction to the rewritable nonvolatile memory module 406 so as to erase data from the rewritable nonvolatile memory module 406; the data processing circuit is used for processing data to be written into the rewritable nonvolatile memory module 406 and data read from the rewritable nonvolatile memory module 406.

Referring to fig. 6, the host interface 504 is electrically connected to the memory management circuit 502 and is electrically connected to the connection interface unit 402 for receiving and recognizing commands and data transmitted by the host system 11. That is, commands and data transmitted by the host system 11 are transmitted to the memory management circuit 502 through the host interface 504. In the exemplary embodiment, host interface 504 is compliant with the SATA standard. However, it should be understood that the present invention is not limited thereto, and the host interface 504 may also be compatible with the PATA standard, the IEEE 1394 standard, the PCI Express standard, the USB standard, the UHS-I interface standard, the UHS-II interface standard, the SD standard, the MS standard, the MMC standard, the CF standard, the IDE standard or other suitable data transmission standards.

The memory interface 506 is electrically connected to the memory management circuit 502 and is used for accessing the rewritable nonvolatile memory module 406. That is, the data to be written to the rewritable nonvolatile memory module 406 is converted into a format accepted by the rewritable nonvolatile memory module 406 through the memory interface 506.

The buffer memory 508 is electrically connected to the memory management circuit 502 and is used for temporarily storing temporary data and instructions from the host system 11 or data from the rewritable nonvolatile memory module 406.

The power management circuit 510 is electrically connected to the memory management circuit 502 and is used for controlling the power of the memory storage device 10.

The error checking and correcting circuit 512 is electrically connected to the memory management circuit 502 and is used for performing an error checking and correcting process to ensure the correctness of data. For example, when the memory management circuit 502 receives a write command from the host system 11, the Error Checking and Correcting circuit 512 generates an Error Checking and Correcting Code (ECC Code) corresponding to the data corresponding to the write command, and the memory management circuit 502 writes the data corresponding to the write command and the corresponding ECC Code into the rewritable nonvolatile memory module 406. Thereafter, when the memory management circuit 502 reads data from the rewritable nonvolatile memory module 406, the corresponding error checking and correcting codes are simultaneously read, and the error checking and correcting circuit 512 performs an error checking and correcting process on the read data according to the error checking and correcting codes.

It is worth noting that in the present exemplary embodiment, the memory control circuit unit 404 (the memory management circuit 502) uses different programming modes to program data to the rewritable nonvolatile memory module 406 in different states. For example, memory control circuitry 404 (memory management circuitry 502) may use a single page program mode or a multiple page program mode to program data to physically erased cells. Here, a programming speed of programming the memory cell based on the single page programming mode may be higher than a programming speed of programming the memory cell based on the multi-page programming mode (i.e., an operation time required to program data using the multi-page programming mode is longer than an operation time required to program data using the single page programming mode), and reliability of data stored based on the single page programming mode may be higher than that of data stored based on the multi-page programming mode. The single page programming mode is, for example, one of a single layer memory cell (SLC) programming mode, a lower physical programming (lower physical programming) mode, a mixed programming (mixture programming) mode, and a less layer memory cell (SLC) programming mode. More specifically, in the single-level cell mode, one memory cell stores only one bit of data. In the lower physical programming mode, only the lower physical programming unit is programmed, and the upper physical programming unit corresponding to the lower physical programming unit is not programmed. In the hybrid programming mode, valid data (or real data) is programmed in the lower physical program unit, and dummy data (dummy data) is programmed in the upper physical program unit corresponding to the lower physical program unit storing the valid data. In the reduced-level cell mode, one memory cell stores a first number of bits of data, e.g., the first number may be set to "1". The multi-page programming mode is, for example, a multi-level cell (MLC) programming mode, a three-level (TLC) cell programming mode, or the like. In the multi-page programming mode, a memory cell stores a second number of bits of data, wherein the second number is equal to or greater than "2". For example, this second number may be set to 2 or 3. In another exemplary embodiment, the first number in the single-page programming mode and the second number in the multi-page programming mode may be other numbers as long as the second number is greater than the first number. In other words, each of the memory cells constituting the first type of the physically-erased cells stores a smaller number of bits of data (i.e., the first number) after being programmed using the single-page program mode than each of the memory cells constituting the second type of the physically-erased cells stores a smaller number of bits of data (i.e., the second number) after being programmed using the multi-page program mode.

In the exemplary embodiment, when the host system 11 and the rewritable nonvolatile memory module 406 are in the state of being powered on, the memory control circuit unit 104 (or the memory management circuit 502) is default to use the multi-page programming mode to write data into the rewritable nonvolatile memory module 406. Specifically, assuming that the host system 11 and the rewritable nonvolatile memory module 406 are in a state of being powered on, when the memory control circuit unit 104 (or the memory management circuit 502) receives a write command (hereinafter, referred to as a second write command) from the host system 11, the memory control circuit unit 104 (or the memory management circuit 502) first temporarily stores data corresponding to the write command in the buffer 508 and immediately returns write completion information corresponding to the second write command to the host system 11. Then, at an appropriate time, for example, when the memory control circuit unit 104 (or the memory management circuit 502) receives a flush command from the host system 11, the amount of data in the buffer memory 508 reaches a threshold value, or the idle time of the host system 11 exceeds a threshold value, the second command sequence is reached to write the data corresponding to the second write command temporarily stored in the buffer memory 508 to at least one entity program unit (hereinafter, referred to as a second entity program unit) of the entity erase units (hereinafter, referred to as a second entity erase unit) in the rewritable non-volatile memory module 406 using the multi-page program mode. Here, since the second physically erased cell is programmed in the multi-page program mode, the memory cell of the physically programmed cell constituting the second physically erased cell is programmed to store a plurality of bit data, as described above. That is, in the multi-page programming mode, the lower physically programmed cell of the second physically erased cells and the upper physically programmed cell of the second physically erased cells are used to write data.

It should be noted, however, that in order to avoid the host system from being powered off abnormally and causing the data stored in the buffer memory to be lost, in the present exemplary embodiment, the user may issue a write cache disable (disable write cache) command to disable the write cache function of the memory storage device 10 through the host system 11. Closing the write cache reduces the time for the data of the write command to be temporarily stored in the buffer 508. In other words, after the memory control circuit unit 104 (or the memory management circuit 502) closes the write cache function according to the closing of the write cache, when the host system 11 issues a write command, the data of the write command is temporarily stored in the buffer 508 and then written into the rewritable nonvolatile memory module 406.

In addition, when the memory control circuit unit 104 (or the memory management circuit 502) receives a write cache close command from the host system 11, redundant data may be written due to a plurality of write commands, thereby causing a "write amplification" problem. To avoid the write amplification problem and efficiently utilize the storage space of the rewritable nonvolatile memory module 406, in the exemplary embodiment, after the memory control circuit unit 104 (or the memory management circuit 502) receives the write cache close command from the host system 11, the memory control circuit unit 104 (or the memory management circuit 502) changes to the single-page programming mode to write to the rewritable nonvolatile memory module 406.

Specifically, FIG. 9 illustrates writing data to a rewritable nonvolatile memory module using a single-page programming mode according to an example.

It is assumed that the memory control circuit unit 104 (or the memory management circuit 502) receives a write cache close instruction from the host system 11. After receiving the write cache close command, the memory control circuitry 104 (or the memory management circuitry 502) closes the write cache function in response to the write cache close command. Then, when the memory storage device 10 receives a write command (hereinafter, referred to as a first write command) from the host system 11 to store data to the 0 th to 255 th logical sub-units of the logical unit LBA (0), the memory control circuit unit 104 (or the memory management circuit 502) first temporarily stores the data of the first write command in the buffer memory 508. At this time, since the write cache function is disabled, the memory control circuit unit 104 (or the memory management circuit 502) issues the first command sequence accordingly. In the present exemplary embodiment, the first instruction sequence is a flush command, and the memory control circuit unit 104 (or the memory management circuit 502) can program the data corresponding to the first write instruction from the buffer memory 508 to the rewritable nonvolatile memory module 406 using a single-page programming mode according to the flush command.

For example, referring to fig. 9, the memory control circuit unit 104 (or the memory management circuit 502) can extract 2 physical erase units 510(F), 510(F +1) (hereinafter, referred to as a first physical erase unit) from the idle area 604 as a plurality of active physical erase units corresponding to the first write command, respectively. The memory control circuit unit 104 (or the memory management circuit 502) writes the data of the first write command from the buffer memory 508 to the physically erased cells 510(F) and the physically erased cells 510(F +1) (hereinafter, referred to as first physically programmed cells) using the single page programming mode according to the first command sequence. Here, since the physically erased cell 510(F) and the physically erased cell 510(F +1) are programmed in the single page programming mode, the memory cells constituting the physically programmed cells of the physically erased cell 510(F) and the physically erased cell 510(F +1) are programmed to store 1 bit of data, as described above. That is, in the single page programming mode, the lower physically programmed cells of the physically erased cells 510(F) and 510(F +1) are used to write data and the upper physically programmed cells of the physically erased cells 510(F) and 510(F +1) are not used to write data.

In detail, as shown in FIG. 9, the memory control circuit unit 104 (or the memory management circuit 502) sequentially writes the data of the 0 th to 127 th logical sub-units to be stored in the logical unit LBA (0) to the lower physical program unit of the physical erase unit 510(F) and sequentially writes the data of the 128 th to 255 th logical sub-units to be stored in the logical unit LBA (0) to the lower physical program unit of the physical erase unit 510(F + 1). That is, the memory control circuit unit 104 (or the memory management circuit 502) writes the data corresponding to the first write command from the buffer memory 508 to the lower physically programmed cell of the physically erased cells 510(F) and the lower physically programmed cell of the physically erased cells 510(F +1) in the rewritable non-volatile memory module 406 using the single page programming mode, and the upper physically programmed cell of the physically erased cells 510(F) and the upper physically programmed cell of the physically erased cells 510(F +1) are not used for writing the data.

After the data corresponding to the first write command is written from the buffer 508 to the lower entity programmed cell of the entity erased cell 510(F) and the lower entity programmed cell of the entity erased cell 510(F +1) in the rewritable non-volatile memory module 406 in the single page programming mode, the memory control circuit unit 104 (or the memory management circuit 502) associates the entity erased cell 510(F) and the entity erased cell 510(F +1) with the data area 602, and returns the write completion information to the host system 11 in response to the first write command issued by the host system 11. That is, in the exemplary embodiment, after the write cache function is closed, when the host system 11 issues a write command and receives a write completion message corresponding to the write command, the data representing the write command is stably stored in the rewritable nonvolatile memory module 406. Compared to a normal write operation (i.e., the memory control circuit unit 104 (or the memory management circuit 502) returns the write completion information to the host system 11 after the data is buffered in the buffer memory 508), the memory storage device 10 of the present example embodiment can further ensure that the data of the write command is written in the rewritable nonvolatile memory module 406 and reduce the loss of the data buffered in the buffer memory 508 due to the abnormal power-off of the host system 11.

It should be noted that, when the rewritable nonvolatile memory module 406 is written by using the single-page programming mode, the space into which the extracted active physical erase unit can be written is only half of the space of the original physical erase unit, because the upper physical program unit of the active physical erase unit extracted from the rewritable nonvolatile memory module 406 is not used for writing data. In order to not reduce the storage capacity of the rewritable nonvolatile memory module 406 in the single-page programming mode, in the exemplary embodiment, the memory control circuit unit 104 (or the memory management circuit 502) performs the effective data merging operation on the data written in the single-page programming mode by using the multi-page programming mode.

FIG. 10 is a diagram illustrating an example of an efficient data merge operation for data written in a single page program mode using a multiple page program mode.

Assuming that the physical erase unit 510(F) corresponding to the logical unit LBA (0), the physical erase unit 510(F +1) have stored valid data of all logical sub-units of the logical unit LBA (0) (as shown in fig. 9), and when the memory storage device 10 is in a background execution mode, for example, the memory storage device 10 is in an idle state for a period of time (for example, 30 seconds have not received an instruction (e.g., a write instruction, a read instruction, a flush instruction, a trim instruction (trim command)), or when the number of empty physical erase units in the idle area 504 is smaller than a predetermined threshold value, the memory control circuit unit 104 (or the memory management circuit 502) performs a valid data merge operation.

In detail, when the memory storage device 10 is idle and does not receive a command from the host system 11 for 30 seconds, or when the number of empty physical erase units in the idle area 504 is smaller than a predetermined threshold, the memory control circuit unit 104 (or the memory management circuit 502) performs a valid data merge operation. Referring to fig. 10, when the memory control circuit unit 104 (or the memory management circuit 502) performs the valid data merge operation, the memory control circuit unit 104 (or the memory management circuit 502) extracts a physical erase unit from the idle region 604 as a physical erase unit 510(F +2) (hereinafter, referred to as a third physical erase unit) for rotation. Specifically, the memory control circuit unit 104 (or the memory management circuit 502) selects an empty physical erase unit or a physical erase unit with invalid data stored therein from the idle region 604. In particular, if the extracted physical erase unit is a physical erase unit storing invalid data, the memory control circuit unit 104 (or the memory management circuit 502) performs an erase operation on the physical erase unit. That is, the invalid data on the physically erased cells must be erased first.

Thereafter, the memory control circuit unit 104 (or the memory management circuit 502) copies the plurality of valid data in the physically erased cells 510(F) and the physically erased cells 510(F +1) to the physically programmed cells in the physically erased cells 510(F +2) in the rewritable nonvolatile memory module 406 using the multi-page programming mode. Here, since the physically erased cell 510(F +2) is programmed in the multi-page program mode, the memory cell constituting the physically programmed cell of the physically erased cell 510(F +2) is programmed to store a plurality of bit data, as described above. That is, in the multi-page programming mode, the lower physically programmed cell of the physically erased cells 510(F +2) and the upper physically programmed cell of the physically erased cells 510(F +2) are used to write data.

In detail, the memory control circuit unit 104 (or the memory management circuit 502) writes (or copies) the valid data of the 0 th to 127 th logical sub-units belonging to the logical unit LBA (0) to the corresponding pages (e.g., 0 th to 127 th physical program units) of the physical erase unit 510(F +2) from the lower physical program unit of the physical erase unit 510 (F). Then, the memory control circuit unit 104 (or the memory management circuit 502) copies the valid data of the 128 th to 255 th logical sub-units belonging to the logical unit LBA (0) from the lower physical program unit of the temporary physical erase unit 510(F +1) to the corresponding page (e.g., 128 th to 255 th physical program units) of the physical erase unit 510(F + 2). That is, in the multi-page program mode, the 0 th to 255 th physical program cells (hereinafter, referred to as the third physical program cells) of the physical erase cell 510(F +2) are all used to write data.

That is, in performing the effective data merge operation, the physical erase cells to be associated with the data region 602 are operated in the multi-page programming mode, and thus, the writing to the physical erase cells 510(F +2) is simultaneously or stepwise programmed in units of the physical program cell group. Specifically, in an exemplary embodiment, the 0 th and 1 st physical program cells of the physical erase cell 510(F +2) are simultaneously programmed to write data belonging to the 0 th and 1 st logical sub-cells of the logical cell LBA (0); the 2 nd and 3 rd physical programming units of the physical erase unit 510(F +2) are simultaneously programmed to write data belonging to the 2 nd and 3 rd logical sub-units of the logical unit LBA (0); and so on, the data of other logical sub-cells are written into the physically erased cell 510(F +2) in units of the physically programmed cell group.

Finally, the memory control circuit unit 104 (or the memory management circuit 502) maps the logical unit LBA (0) to the physical unit 510(F +2) in the logical-to-physical mapping table, and performs an erase operation on the physical unit 510(F) -510 (F +1) and re-associates the physical unit 510(F) -510 (F +1) to the idle area 604. That is, in the following write command, the erased entity-erased units 510(F) -510 (F +1) can be selected as the active entity-erased units of the logic units to be written.

By the above-mentioned valid data merging operation, it can be ensured that the storage capacity of the rewritable nonvolatile memory module 406 is not reduced due to the previous writing using the single page programming mode.

It should be noted that a user of the memory storage device 10 may also issue an enable write cache command through the host system 11, and the memory control circuit unit 104 (or the memory management circuit 502) will enable the write cache function after receiving the enable write cache command to respond to the enable write cache command, so as to recover the function of the original rewritable nonvolatile memory module 406 that is default to write data in the multi-page programming mode.

In detail, the memory control circuit unit 104 (or the memory management circuit 502) may receive a write cache open command issued by a user from the host system 11. After the memory control circuit unit 104 (or the memory management circuit 502) receives the write cache open instruction, the memory control circuit unit 104 (or the memory management circuit 502) opens the write cache function in response to the write cache open instruction. Thereafter, when the memory control circuit unit 104 (or the memory management circuit 502) receives the write command from the host system 11 again, the memory control circuit unit 104 (or the memory management circuit 502) will temporarily store the data corresponding to the write command in the buffer memory 508 and immediately reply the write completion information corresponding to the third write command to the host system 11. Then, at an appropriate time, for example, when the memory control circuit unit 104 (or the memory management circuit 502) receives the flush command from the host system 11, the amount of data in the buffer memory 508 reaches a threshold value, or the idle time of the host system 11 exceeds a threshold value, the data temporarily stored in the buffer memory 508 is written into at least one physical program cell of the at least one physical erase cell in the rewritable non-volatile memory module 406 using the multi-page program mode. Similarly, in the multi-page program mode, the lower physical program cell and the upper physical program cell of the physical program cells used for writing data are used for writing data.

That is, a user of the memory storage device 10 can selectively use a write cache close instruction or a write cache open instruction to correspondingly close or open the write cache function.

Referring to fig. 11, in step S1101, the memory control circuit unit 104 (or the memory management circuit 502) determines whether a write cache close command or a write cache open command is received from the host system 11. If the memory control circuit unit 104 (or the memory management circuit 502) receives the write cache close command from the host system 11, in step S1103, the memory control circuit unit 104 (or the memory management circuit 502) closes the write cache function in response to the write cache close command. If the memory control circuit unit 104 (or the memory management circuit 502) receives the write cache open command from the host system 11, in step S1105, the memory control circuit unit 104 (or the memory management circuit 502) opens the write cache function in response to the write cache open command.

Referring to fig. 12, in step S1201, the memory control circuit unit 104 (or the memory management circuit 502) receives a first write command from the host system 11, and temporarily stores data corresponding to the first write command in the buffer memory 508. Next, in step S1203, the memory control circuit unit 104 (or the memory management circuit 502) determines whether the write caching function is turned off. When the write cache function is disabled, in step S1205, the memory control circuit unit 104 (or the memory management circuit 502) will issue the first command sequence to write the data corresponding to the first write command from the buffer memory 508 to the first physical program unit of the first one of the physical erase units using the single page program mode. For example, in an exemplary embodiment, the memory control circuit unit 104 (or the memory management circuit 502) immediately generates the flush command, and writes the data corresponding to the first write command from the buffer memory 508 to the first physical program cell of the first physical erase cell among the physical erase cells using the single page program mode according to the flush command.

In addition, when the write cache function is not turned off, in step S1207, the memory control circuit unit 104 (or the memory management circuit 502) issues a second command sequence to write data corresponding to the first write command from the buffer memory 508 to the first physical program unit of the first physical erase unit among the physical erase units in the multi-page program mode. It should be noted, however, that the memory control circuit 104 (or the memory management circuit 502) may not immediately perform the step 1207 when the write cache function is not turned off and the data of the first write command is buffered in the buffer. Specifically, the memory control circuit unit 104 (or the memory management circuit 502) may execute the step S1207 at an appropriate time, for example, when a flush command (flush command) is received from the host system 11 or the amount of data in the buffer memory 508 reaches a threshold value or enters the background execution mode.

In summary, the data writing method of the present invention can effectively avoid the loss of data in the buffer memory due to the abnormal power-off of the host system, and ensure that the data of the write command before the abnormal power-off is stably stored in the rewritable non-volatile memory. In addition, the data writing method of the invention can also avoid the problem of 'write amplification' and can effectively utilize the space of the rewritable nonvolatile memory.

Although the present invention has been described with reference to the above embodiments, it should be understood that the invention is not limited to the embodiments, and that various changes and modifications can be made by one skilled in the art without departing from the spirit and scope of the invention.

Claims

1. A data writing method is used for a rewritable nonvolatile memory module, and is characterized in that the rewritable nonvolatile memory module is provided with a plurality of entity erasing units, each entity erasing unit in the entity erasing units is provided with a plurality of entity programming units, and the data writing method comprises the following steps:

receiving a first write command from a host system, and temporarily storing data to be written corresponding to the first write command into a buffer memory;

when a write cache function is turned off and the data to be written of the first write command is temporarily stored in the buffer memory, writing the data to be written corresponding to the first write command from the buffer memory to at least one first physical program unit of a first physical erase unit of the plurality of physical erase units by using a single page program mode, and returning a write completion message to the host system,

wherein the at least one first physical program unit is composed of a plurality of first memory cells and each of the plurality of first memory cells constituting the at least one first physical program unit stores only 1 bit of data in the single page program mode, an

When the write cache function is turned on and the data to be written of the first write command is temporarily stored in the buffer memory, writing the data to be written corresponding to the first write command from the buffer memory into at least one first physical program unit of a first physical erase unit of the plurality of physical erase units in a multi-page program mode,

wherein the at least one first physical program unit is configured of a plurality of first memory cells and each of the plurality of first memory cells configuring the at least one first physical program unit stores a plurality of bits of data in the multi-page program mode,

when the write cache function is closed and the data to be written of the first write command is temporarily stored in the buffer memory, issuing a flush command to execute the step of writing the data to be written corresponding to the first write command from the buffer memory to the at least one first entity programming unit of the first entity erasing unit by using the single page programming mode.

2. The data writing method according to claim 1, further comprising:

a write cache close command is received from the host system, and the write cache function is closed in response to the write cache close command.

3. The data writing method of claim 2, wherein the step of receiving the write cache close command from the host system is preceded by the step of:

receiving a second write command from the host system and temporarily storing a second data to be written corresponding to the second write command in the buffer memory; and

writing the second data to be written corresponding to the second write command temporarily stored in the buffer memory into at least one second physical program cell of a second physical erase cell among the plurality of physical erase cells using a multi-page program mode,

wherein the at least one second physical program unit is configured of a plurality of second memory cells and each of the plurality of second memory cells configuring the at least one second physical program unit stores a plurality of bits of data in the multi-page program mode.

4. The data writing method according to claim 1, further comprising:

in a background execution mode, performing a valid data merge operation to copy the valid data in the first physically erased cell to a third physically erased cell of the plurality of physically erased cells using the multi-page programming mode,

wherein the plurality of third physical program units are configured by a plurality of third memory cells and each of the plurality of third memory cells configuring the plurality of third physical program units stores a plurality of bits of data in the multi-page program mode.

5. The data writing method according to claim 1, further comprising:

a write cache open instruction is received, and the write cache function is opened in response to the write cache open instruction.

6. The data writing method according to claim 1,

the multi-page programming mode is a multi-level cell programming mode or a three-level cell programming mode, and the single-page programming mode is a single-level cell programming mode, a lower physical programming mode, a hybrid programming mode, or a less-level cell programming mode.

7. A memory control circuit unit for controlling a rewritable nonvolatile memory module, the memory control circuit unit comprising:

a host interface for electrically connecting to a host system;

a memory interface electrically connected to the rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module has a plurality of entity erasing units, and each entity erasing unit in the plurality of entity erasing units has a plurality of entity programming units;

a buffer memory electrically connected to the host interface and the memory interface; and

a memory management circuit electrically connected to the host interface, the memory interface and the buffer memory,

the memory management circuit is used for receiving a first write command from the host system and temporarily storing data to be written corresponding to the first write command into the buffer memory,

when a write cache function is turned off and the data to be written of the first write command is temporarily stored in the buffer memory, the memory management circuit is further configured to issue a first command sequence to write the data to be written corresponding to the first write command from the buffer memory to at least one first entity programming unit of a first entity erasing unit among the plurality of entity erasing units using a single page programming mode, and to return a write completion message to the host system,

wherein the at least one first physical program unit is composed of a plurality of first memory cells and each of the plurality of first memory cells constituting the at least one first physical program unit stores only 1 bit of data in the single page program mode,

when the write cache function is turned on and the data to be written of the first write command is temporarily stored in the buffer memory, the memory management circuit is further configured to write the data to be written corresponding to the first write command from the buffer memory to at least one first physical program unit of a first physical erase unit among the plurality of physical erase units in a multi-page program mode,

wherein the first instruction sequence is a flush instruction,

when the write cache function is turned off and the data to be written of the first write command is temporarily stored in the buffer memory, the memory management circuit is further configured to perform the above-mentioned operation of writing the data to be written corresponding to the first write command from the buffer memory to the at least one first physical program unit of the first physical erase unit using the single-page program mode according to the flush command.

8. The memory control circuit unit of claim 7,

the memory management circuit is further configured to receive a write cache close command from the host system and close the write cache function in response to the write cache close command.

9. The memory control circuit unit of claim 8, wherein prior to the operation of receiving the write cache close command from the host system,

the memory management circuit is further configured to receive a second write command from the host system and temporarily store a second data to be written corresponding to the second write command in the buffer memory,

the memory management circuit is further configured to issue a second command sequence to write the second data to be written corresponding to the second write command temporarily stored in the buffer memory into at least one second physical program unit of a second physical erase unit among the plurality of physical erase units in a multi-page program mode,

10. The memory control circuit unit of claim 7,

in a background execution mode, the memory management circuit is further configured to perform a valid data merge operation to copy the valid data in the first physically-erased cell to third physically-erased cells of a third physically-erased cell among the plurality of physically-erased cells using the multi-page programming mode,

11. The memory control circuit unit of claim 7,

the memory management circuit is further configured to receive a write cache open instruction and open the write cache function in response to the write cache open instruction.

12. The memory control circuit unit of claim 7, wherein the multi-page programming mode is a multi-level cell programming mode or a three-level cell programming mode, and the single-page programming mode is a single-level cell programming mode, a lower physical programming mode, a hybrid programming mode, or a less-level cell programming mode.

13. A memory storage device, comprising:

a connection interface unit for electrically connecting to a host system;

the rewritable nonvolatile memory module is provided with a plurality of entity erasing units, and each entity erasing unit in the entity erasing units is provided with a plurality of entity programming units; and

a memory control circuit unit electrically connected to the connection interface unit and the rewritable nonvolatile memory module and including a buffer memory,

the memory control circuit unit is used for receiving a first write command from the host system and temporarily storing data to be written corresponding to the first write command into the buffer memory,

when a write cache function is turned off and the data to be written of the first write command is temporarily stored in the buffer memory, the memory control circuit unit is further configured to issue a first command sequence to write the data to be written corresponding to the first write command from the buffer memory to at least one first entity programming unit of a first entity erasing unit among the plurality of entity erasing units using a single page programming mode, and to reply a write completion message to the host system,

wherein the first instruction sequence is a flush instruction,

when the write cache function is turned off and the data to be written of the first write command is temporarily stored in the buffer memory, the memory control circuit unit is further configured to perform the above-mentioned operation of writing the data to be written corresponding to the first write command from the buffer memory to the at least one first physical program unit of the first physical erase unit using the single-page program mode according to the flush command,

when the write cache function is turned on and the data to be written of the first write command is temporarily stored in the buffer memory, the memory control circuit unit is further configured to write the data to be written corresponding to the first write command from the buffer memory to at least one first physical program unit of a first physical erase unit among the plurality of physical erase units in a multi-page program mode,

wherein the at least one first physical program unit is configured of a plurality of first memory cells and each of the plurality of first memory cells configuring the at least one first physical program unit stores a plurality of bits of data in the multi-page program mode.

14. The memory storage device of claim 13,

the memory control circuit unit is further configured to receive a write cache close command from the host system and close the write cache function in response to the write cache close command.

15. The memory storage device of claim 14, wherein prior to the operation of receiving the write cache close command from the host system,

the memory control circuit unit is further configured to receive a second write command from the host system and temporarily store a second data to be written corresponding to the second write command in the buffer memory,

the memory control circuit unit is further configured to issue a second command sequence to write the second data to be written corresponding to the second write command temporarily stored in the buffer memory into at least one second physical program unit of a second physical erase unit among the plurality of physical erase units using a multi-page program mode,

16. The memory storage device of claim 13,

in a background execution mode, the memory control circuit unit is further configured to perform a valid data merge operation to copy the valid data in the first physically-erased cell to third physically-erased cells of a third physically-erased cell among the plurality of physically-erased cells using the multi-page programming mode,

17. The memory storage device of claim 13,

the memory control circuit unit is further configured to receive a write cache open instruction and open the write cache function in response to the write cache open instruction.

18. The memory storage device of claim 13, wherein the multi-page programming mode is a multi-level cell programming mode or a three-level cell programming mode, and the single-page programming mode is a single-level cell programming mode, a lower physical programming mode, a hybrid programming mode, or a less-level cell programming mode.