CN103870214A - Method for enabling MLC (Multi Level Cell) to have function of SLC (Single Level Cell) - Google Patents
Method for enabling MLC (Multi Level Cell) to have function of SLC (Single Level Cell) Download PDFInfo
- Publication number
- CN103870214A CN103870214A CN201410065882.XA CN201410065882A CN103870214A CN 103870214 A CN103870214 A CN 103870214A CN 201410065882 A CN201410065882 A CN 201410065882A CN 103870214 A CN103870214 A CN 103870214A
- Authority
- CN
- China
- Prior art keywords
- slc
- mlc
- address
- individual layer
- storage block
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
The invention relates to a method for enabling an MLC (Multi Level Cell) to have a function of an SLC (Single Level Cell). The method comprises the steps of setting a '0' level and a '1' level on each storage unit; writing data into the MLC by simulating a writing method of the SLC. By adopting the technical scheme, the MLC can be enabled to have the writing performance of the SLC and also have the characteristics of high stability and long service life of the SLC.
Description
Technical field
The present invention relates to computer technology, particularly the improvement technology of computer memory device.
Background technology
The storage mode of computer memory device mainly contains three kinds at present: the SLC of individual layer, and speed is fast, durability good, but cost is high, capacity is little, and multiplex in enterprise-level product; The MLC of multilayer, cost is low, and capacity is large, but speed is slow, durability is general, is the main force of consumer level solid state hard disc; The TLC of three layers, cost is the cheapest, but durability is the poorest, is usually used in entry level product at a low price.
SLC(is as shown in Figure 1) full name single-layer type storage (Single Level Cell), refer to a Block(piece, the basic unit of storage of Flash, also can be described as Cell) only have two kinds of charge values, the different charge value of height shows 0 or 1, just can distinguish 0 or 1 signal because only need one group of high low-voltage, so the driving voltage of SLC maximum can be accomplished very low, SLC is because simple in structure, in the time of data writing, the interval of change in voltage is little, so the life-span is longer, traditional SLC Flash can stand the read-write of 100,000 times, therefore the probability that occurs bad Block is less, because storage organization is very simple, one group of voltage can drive, so its speed performance is better, all hypervelocity cards all adopt the Flash chip of SLC type at present.The pattern that but a this Block only stores one group of data cannot realize higher storage density on identical wafer area, so can only make great efforts progressively aspect manufacturing process, could meet the requirement of user aspect capacity.
MLC(is as shown in Figure 2) full name multiple field storage (Multi Leveled Cell), it is the technology of that Block of making full use of, it adopts higher voltage to drive, voltage by different stage records two groups of position information (00,01,11,10) in a Block, so just can promote one times by theoretical the recording density of script SLC, for this NAND Flash that runs into bottleneck for manufacturing process once, be extraordinary message.When but MLC is except same processing procedure, with wafer area theoretical twice record space, there are some inborn drawbacks, such as voltage range is less, Flash just needs more CRC check space, this can probably occupy in Block 10% space, therefore in actual use with processing procedure with the capacity of the MLC of wafer area one times less than SLC.Because change in voltage is more frequent, so the Flash of MLC technology aspect the life-span far inferior to SLC, the erasable number of times that official provides is only 10,000 times, that is to say the USB flash drive of a 512MB, you write the data 10,000 times (perfect condition) of 512MB, it is just dead, and this may be the shortcoming that MLC kills most.The Flash of MLC technology also has a shortcoming, its congenital SLC that is not so good as of read or write speed, and a Block stores two groups of bit data, the time that nature need to be longer, also has the factors such as Control of Voltage, CRC writing mode to need to consider here.Comprehensive, SLC has unique advantage in life-span and aspect of performance, but needs better manufacturing process just can have larger capacity.Although and MLC has inborn advantage aspect capacity, there is inborn deficiency aspect speed and life-span.
TLC full name (Trinary-Level Cell) is 3bit/cell, Ye You Flash producer is 8LC, the slow life-span of speed is short, low price, approximately 500 erasing and writing lifes, also do not have at present producer can accomplish 1000 times, the current more use of TLC, at less demanding USB storage card low-end product, has been introduced with regard to doing here.
MLC is low cost solution, and the expensive representative of SLC high-performance, all there is very big-difference in both performances (especially random writing aspect), reading-writing life-span, is 48GB TLC of 32GB MLC=of a 16GB SLC=.From the principle of work of above-mentioned various storage blocks with and relatively can the finding out of aspect of performance, various storage blocks all have oneself advantage and defect, if can make MLC have the high-performance of SLC, will be ideal storage mode.
Summary of the invention
The invention provides a kind of method that multilayered memory piece has individual layer storage block performance concurrently, adopt the hardware condition and the wiring method thereof that change traditional MLC, make its write performance that has SLC concurrently, solve the limited technical matters of SLC memory capacity in prior art.
The scheme of the present invention's design takes following methods to address the above problem: in each storage cell, only establish reset and " 1 " two current potentials; The writing mode of simulation individual layer storage block writes data in multilayered memory piece, simulation individual layer storage block writing mode is to adopt the form of independent built-in firmware to complete, and described built-in firmware adopts TurboMLC technology that per unit is stored to 2 bits to change per unit into and store 1 bit.
The present invention adopts above-mentioned technical scheme, can make MLC have the efficient write performance of SLC, and has SLC good stability and long feature of life-span.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of SLC storage mode.Fig. 2 is the schematic diagram of MLC storage mode.Fig. 3 is the schematic diagram of TurboMLC of the present invention.Fig. 4 is the principle of work schematic diagram of memory device of the present invention.
Embodiment
In conjunction with above-mentioned accompanying drawing 3 and accompanying drawing 4, specific embodiments of the invention are described.
The method that multilayered memory piece of the present invention has individual layer storage block performance concurrently comprises the following steps: A. only establishes reset and " 1 " two current potentials in each storage cell; The writing mode of B. simulating individual layer storage block writes data in multilayered memory piece, described simulation individual layer storage block writing mode is to adopt the form of independent built-in firmware to complete, and described built-in firmware adopts TurboMLC technology that per unit is stored to 2 bits and changes per unit into and store 1 bit.
Generalized case nand flash memory array is divided into a series of block (block), and these blocks are erasable entities minimum in NAND device.Wiping a block is exactly that all positions (bit) are set to " 1 " (and all bytes (byte) are set to FFh).Be necessary by programming, the position of having wiped is become to " 0 " from " 1 ".Minimum programming entity is byte (byte).The memory organizational form of the addressing mode of SLC NAND Flash and MLC NAND Flash is closely related, the data of NAND Flash are to be kept at memory cell in the mode of bit, in general, in cell of SLC NAND FLASH, can only store a bit.These cell are linked to be bit line as unit take 8 or 16, form so-called byte (x8)/word (x16), the bit wide of Here it is NAND Device.
These Line meeting recompositions Page, normally 528Byte/page or 264Word/page.Then, every 32 page form a Block, Sizeof (block)=16kByte, and Block is operating unit maximum in NAND Flash, wiping according to block is that unit completes, and is that unit completes and programme/read according to page.So, can form so-called three class addresses according to such organizational form :-Block Address-Page Address-Column Address
For NAND Flash, address and order can only be at I/O[7:0] upper transmission, data width can be 8 or 16, still, and for the NAND Device of x16, I/O[15:8] only for transmitting data.
The present invention is with MLC NAND FLASH-528Byte/page total volume, the NAND device of 512Mbit+512kbyte is example explanation: because 1 block=16kbyte, 512Mbit=64Mbyte, Numberof (block)=1024 1block=32page, 1page=528byte=512byte (Main Area)+16byte (Spare Area)
512byte needs 9bit to represent, for the NAND of 528byte series, this 512byte is divided into 1st half and 2nd half, and access is separately selected by so-called pointer operation order, has namely selected the height of bit8.Therefore A8 is exactly halfpage pointer, A[7:0] be exactly so-called column address.32 page need 5bit to represent, take A[13:9], i.e. the relative address of this page in piece.The address of Block is to be represented by bit more than A14, the for example NAND of MLC NAND FLASH 2GB, 4096block altogether, 2GB SLC NAND FLASL is 2096block altogether, therefore, need 24 bit to represent, be A[25:14], and the address table that page address is exactly blcok address|page address in block NAND Flash is shown: transmission order in Block Address|Page Address in block|halfpage pointer|Column Address address is Column Address, Page Address, Block Address.Because address can only be at I/O[7:0] upper transmission, therefore, adopt the mode of displacement to calculate (TurboMLC algorithm).For example, for the NAND flash of 512Mbit x8, address realm is 0 ~ 0x3FF_FFFF, as long as the address of the numeric representation within the scope of this is all effective.512byte needs 9bit to represent, for the NAND of 528byte series, this 512byte is divided into 1st half and 2nd half, and access is separately selected by so-called pointer operation order, has namely selected the height of bit8.Therefore A8 is exactly halfpage pointer, A[7:0] be exactly so-called column address.32 page need 5bit to represent, take A[13:9], i.e. the relative address of this page in piece.The address of Block is to be represented by bit more than A14, the NAND(4096block of MLC NAND FLASH 2GB), therefore, the page page is actual to be become as (4096bock). and order is Column Address, Page Address, Block Address.
Take the NAND(4096block of MLC NAND FLASH 2GB) as example:
The 1st step is to transmit column address, be exactly NAND_ADDR[7:0], not needing displacement can be delivered to I/O[7:0] to be bit8 determined by operational order for upper and halfpage pointer, be that instruction determines to read and write on which halfpage, and the value of real bit8 is don't care.
The 2nd step is exactly by the NAND(4096block of MLC NAND FLASH 2GB) NAND_ADDR moves to right 9, by MLC NAND FLASH NAND_ADDR[16:9] pass to I/O[7:0] on;
The 3rd step is put into [24:17] on I/O;
The 4th step need to be by NAND_ADDR[25] be put on I/O;
Therefore, whole address transmittance process needs 4 steps just can complete, i.e. 4-stepaddressing.
If the capacity of NAND Flash is below 256Mbit, so, block adress most significant digit only arrives bit24, and therefore addressing only needs 3 steps.
Therefore, whole address transmittance process needs 4 steps just can complete, and has both become 2-step addressing.Identical with the using method of SLC NAND FLASH, just become 1 page by 2 page, total capacity has become 2048Block.
Disc as hard disk is divided into magnetic track, and each magnetic track is divided into again some sectors, after MLC NAND FLASH is recompiled, is also divided into some block, and it is as follows in dry page allocation result that each block is divided into:
1block = 64page
1page=2048bytes (datafield)+32bytes (oob) is identical with the structure of SLC, and 4096bytes is divided into 1st half and 2sd half in theory, and each half respectively becomes 2048 bytes.06) begin to read this page by the controller algorithm of solid state hard disc, send command string realization 2 bit are realized to 1 bit.
column_addr=2096;
NF_CMD=0x01; From 2nd half R
NF_ADDR=column_addr&0xff; 1st Cycle
NF_ADDR=page_address&0xff; 2nd.Cycle
NF_ADDR=(page_address>>8)&0xff; 3rd.Cycle
NF_ADDR=(page_address>>16)&0xff; 4th.Cycle
Wherein NF_CMD and NF_ADDR are respectively the command register of NandFlash and the address dereference of address register,
#define rNFCMD (*(volatile unsigned char *)0x4e000004) //NADD Flash command
#define rNFADDR (*(volatile unsigned char *)0x4e000008) //NAND Flash address
In fact, in the time of NF_CMD=0x01, the 8th (A8) in address register will be set to 1, in the address that does not transmit at us A8 position, this position is exactly hardware management circuit according to improving high level or low level to 01h or these two orders of 00h set high position or set low position in fact), the value 256 that we transmit column_addr is like this with so because data from overflow becomes 1, but A8 position is set to 1 due to the relation of NF_CMD=0x01, so the value that we pass in address register has become
A0 A1 A2 A3 A4 A5 A6 A7 A8
1 0 0 0 0 0 0 0 1
The configuration mode that becomes SLC that these 8 positions are represented, read operation is by No. 0 byte of 2096byte(2nd half of page from then on like this) start reading out data.In nand_flash.c, comprise 3 functions
void nf_reset(void);
void nf_init(void);
void nf_read(unsigned int src_addr,unsigned char *desc_addr,int size);
Nf_reset () will be called by nf_init ().Nf_init () is the initialization function of nand_flash, and before nand flash is carried out to any operation, nf_init () must be called.
Nf_read (unsigned int src_addr, unsigned char * desc_addr, int size); For reading function, src_addr is the address on nand flash, and desc_addr is memory address, and size is the length of file reading.
In nf_reset and nf_read function, exist two grand
NF_nFCE_L();
NF_nFCE_H();
You can see ought be at every turn operate Nand Flash before NF_nFCE_L () must be called, NF_nFCE_H () must be called in EO.These two grand in starting and close the work (sheet selects/cancel sheet choosing) of Flash chip.As in nf_reset ()
rNFCONF=(1<<15)|(1<<14)|(1<<13)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0);
This line code is that the control register of MLC NAND NandFlash is carried out to initial configuration, and rNFCONF is the configuration FW instruction of Nand Flash.
According to
column_addr=src_addr%512;
page_address=(src_addr>>9);
column_addr=5000%512=392
page_address=(5000>>9)=9
Nf_read function will send order and parameter like this
column_addr=5000%512;
>page_address=(5000>>9);
NF_CMD=0x01; Start to read from 2nd half
NF_ADDR= column_addr &0xff;
1st Cycle
NF_ADDR=page_address&0xff;
2nd.Cycle
NF_ADDR=(page_address>>8)&0xff; 3rd.Cycle
NF_ADDR=(page_address>>16)&0xff; 4th.Cycle
After the command register of MLC Nand Flash and address register send above order and parameter, just can be from rNFDATA register (NandFlash data register has been modeled as SLC NADN FLASH) by a series of modifications, on solid state hard disc, MLC NAND FLASH can be modeled to SLC use, use MLC NAND FALSH to the object that reduces SLC NAND FLASH sky high cost thereby reach, flat and can significantly not reduce life of product.
The inventor develops the writing mode of independent FW firmware a piece of wood serving as a brake to halt a carriage n-body simulation n SLC, break through hardware constraints, significantly promote usefulness, the jumbo storage solution of very applicable needs, on each storage unit, only there is 0 and 1 storing state, put forward high-tension allowance, just as the firmware design of SLC, therefore, can reach degree of stability and the tolerance level of SLC.
Tool way of the present invention is on Controlle and FLASH basis, to add TurboMLC technology to make it break through hardware constraints and can support simulation, under hardware technology is supported, compiling firmware algorithm is 1bpc the 2bpc of MLC flash memory (two of every unit bit) reprogramming, to increase the susceptibility between every one deck, allow the working method of flash memory similarly be more SLC.The present invention is by evidence, this novel memory device on average can stand 30000 program/erase circulations (P/E), the life-span of contrast 3000 left and right of MLC has been improved an order of magnitude, and reach the half left and right of SLC of new generation, in performance, adopt the writing speed of the solid state hard disc of TurboMLC technology probably to have 70% of SLC NAND, compare MLC NAND and want fast a lot.TurboMLC principle is that 2bit is written as to 1bie again, and the MLC capacity of being write can reduce half, becomes 4GB such as capacity after 8GB employing TurboMLC can reduce half.Originally the life-span only has the MLC NAND of 3000 P/E adopting after TurboMLC technology, life-span will become 30000 P/E, also have one section of gap although compare the SLC NAND of 100000 P/E of conventional process SLC NAND and the 60000P/E of new processing procedure, comparing MLC NAND has been the once leap of how much levels.If do write operation on the 32GB solid state hard disc of an employing TurboMLC technology, calculate according to writing 320GB every day, also can write continuously 7.6 years, change MLC into and can only adhere to less than 1 year, the life-span obtains very large prolongation.
Above content is in conjunction with concrete preferred implementation further description made for the present invention, can not assert that specific embodiment of the invention is confined to these explanations.For general technical staff of the technical field of the invention, without departing from the inventive concept of the premise, can also make some simple deduction or replace, all should be considered as belonging to protection scope of the present invention.
Claims (5)
1. multilayered memory piece has a method for individual layer storage block performance concurrently, it is characterized in that: the method comprises the following steps: A. only establishes reset and " 1 " two current potentials in each storage cell; The writing mode of B. simulating individual layer storage block writes data in multilayered memory piece.
2. multilayered memory piece has the method for individual layer storage block performance concurrently according to claim 1, it is characterized in that: described in step B, simulating individual layer storage block writing mode is to adopt the form of independent built-in firmware to complete.
3. multilayered memory piece has the method for individual layer storage block performance concurrently according to claim 2, it is characterized in that: built-in firmware described in step B adopts TurboMLC technology that per unit is stored to 2 bits and changes per unit into and store 1 bit.
4. multilayered memory piece has the method for individual layer storage block performance concurrently according to claim 3, it is characterized in that: described in step B, built-in firmware compiles addressing mode.
5. multilayered memory piece has the method for individual layer storage block performance concurrently according to claim 3, it is characterized in that: built-in firmware described in step B is by the height of pointer operation command selection bit8 to the method for addressing mode compiling, thereby determine that A8 is halfpage pointer, determine A[7:0] be column address, determine the relative address of storage unit page in storage block.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410065882.XA CN103870214A (en) | 2014-02-26 | 2014-02-26 | Method for enabling MLC (Multi Level Cell) to have function of SLC (Single Level Cell) |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410065882.XA CN103870214A (en) | 2014-02-26 | 2014-02-26 | Method for enabling MLC (Multi Level Cell) to have function of SLC (Single Level Cell) |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103870214A true CN103870214A (en) | 2014-06-18 |
Family
ID=50908798
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410065882.XA Pending CN103870214A (en) | 2014-02-26 | 2014-02-26 | Method for enabling MLC (Multi Level Cell) to have function of SLC (Single Level Cell) |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103870214A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106293841A (en) * | 2016-08-11 | 2017-01-04 | 青岛海信移动通信技术股份有限公司 | A kind of method and apparatus of burning data |
| CN107402716A (en) * | 2016-05-20 | 2017-11-28 | 合肥兆芯电子有限公司 | Method for writing data, memory control circuit unit and internal storing memory |
| CN108572924A (en) * | 2018-04-20 | 2018-09-25 | 华中科技大学 | A kind of request processing method of 3D MLC flashes equipment |
| CN109002367A (en) * | 2017-06-07 | 2018-12-14 | 力晶科技股份有限公司 | Nonvolatile memory device, nonvolatile memory integrated circuit and operating method |
| CN109411000A (en) * | 2018-09-20 | 2019-03-01 | 联想(北京)有限公司 | A kind of control method of solid-state memory, solid-state memory and storage medium |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102346652A (en) * | 2010-07-21 | 2012-02-08 | 慧荣科技股份有限公司 | Flash storing device and method for managing flash storing device |
| CN103049217A (en) * | 2012-12-07 | 2013-04-17 | 记忆科技(深圳)有限公司 | Multi-level cell (MLC) NAND type solid-state hard disk, read-write control method and flash memory controller |
| US20130173857A1 (en) * | 2006-10-30 | 2013-07-04 | Won-Moon CHEON | Flash memory device with multi-level cells and method of writing data therein |
-
2014
- 2014-02-26 CN CN201410065882.XA patent/CN103870214A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20130173857A1 (en) * | 2006-10-30 | 2013-07-04 | Won-Moon CHEON | Flash memory device with multi-level cells and method of writing data therein |
| CN102346652A (en) * | 2010-07-21 | 2012-02-08 | 慧荣科技股份有限公司 | Flash storing device and method for managing flash storing device |
| CN103049217A (en) * | 2012-12-07 | 2013-04-17 | 记忆科技(深圳)有限公司 | Multi-level cell (MLC) NAND type solid-state hard disk, read-write control method and flash memory controller |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107402716A (en) * | 2016-05-20 | 2017-11-28 | 合肥兆芯电子有限公司 | Method for writing data, memory control circuit unit and internal storing memory |
| CN106293841A (en) * | 2016-08-11 | 2017-01-04 | 青岛海信移动通信技术股份有限公司 | A kind of method and apparatus of burning data |
| CN109002367A (en) * | 2017-06-07 | 2018-12-14 | 力晶科技股份有限公司 | Nonvolatile memory device, nonvolatile memory integrated circuit and operating method |
| CN108572924A (en) * | 2018-04-20 | 2018-09-25 | 华中科技大学 | A kind of request processing method of 3D MLC flashes equipment |
| CN108572924B (en) * | 2018-04-20 | 2021-10-08 | 华中科技大学 | Request processing method of 3D MLC flash memory device |
| CN109411000A (en) * | 2018-09-20 | 2019-03-01 | 联想(北京)有限公司 | A kind of control method of solid-state memory, solid-state memory and storage medium |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9317418B2 (en) | Non-volatile memory storage apparatus, memory controller and data storing method | |
| US8001317B2 (en) | Data writing method for non-volatile memory and controller using the same | |
| US8312554B2 (en) | Method of hiding file at data protecting mode for non-volatile memory module, memory controller and portable memory storage apparatus | |
| TWI425523B (en) | Hybrid flash memory storage device and method of controlling the same | |
| US9213629B2 (en) | Block management method, memory controller and memory stoarge apparatus | |
| US20090222643A1 (en) | Block management method for flash memory and controller and storage sysetm using the same | |
| US20090198875A1 (en) | Data writing method for flash memory, and controller and system using the same | |
| US9037814B2 (en) | Flash memory management method and flash memory controller and storage system using the same | |
| US9268688B2 (en) | Data management method, memory controller and memory storage apparatus | |
| TWI590051B (en) | Data storage device and data maintenance method thereof | |
| CN103514096B (en) | Data storage method, Memory Controller and memorizer memory devices | |
| CN107391389B (en) | Method for managing a memory device, memory device and controller | |
| US9141530B2 (en) | Data writing method, memory controller and memory storage device | |
| US9619380B2 (en) | Data writing method, memory control circuit unit and memory storage apparatus | |
| CN102214143A (en) | Method and device for managing multilayer unit flash memory, and storage equipment | |
| TWI606339B (en) | Data storage device and data maintenance method thereof | |
| CN106155582B (en) | Non-volatile memory device and controller | |
| CN103870214A (en) | Method for enabling MLC (Multi Level Cell) to have function of SLC (Single Level Cell) | |
| US9009442B2 (en) | Data writing method, memory controller and memory storage apparatus | |
| CN101266828B (en) | Mixed flash memory device and its operation method | |
| US8417909B2 (en) | Block management and data writing method, and flash memory storage system and controller using the same | |
| CN103389941A (en) | Memorizer formatting method, memorizer controller and memorizer memory device | |
| US10824340B2 (en) | Method for managing association relationship of physical units between storage area and temporary area, memory control circuit unit, and memory storage apparatus | |
| CN110442299B (en) | Data writing method, memory control circuit unit and memory storage device | |
| US20090182932A1 (en) | Method for managing flash memory blocks and controller using the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20140618 |
|
| RJ01 | Rejection of invention patent application after publication |