CN102346652A - Flash storing device and method for managing flash storing device - Google Patents
Flash storing device and method for managing flash storing device Download PDFInfo
- Publication number
- CN102346652A CN102346652A CN2011101521021A CN201110152102A CN102346652A CN 102346652 A CN102346652 A CN 102346652A CN 2011101521021 A CN2011101521021 A CN 2011101521021A CN 201110152102 A CN201110152102 A CN 201110152102A CN 102346652 A CN102346652 A CN 102346652A
- Authority
- CN
- China
- Prior art keywords
- data
- flash memory
- memory module
- order
- cell
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Read Only Memory (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
Provided is a flash storing device, comprising a flash memory and a controller, wherein the flash memory comprises a single-layer memory module and a multi-layer memory module; the single-layer memory module comprises a first data bus and at least one single-layer unit flash memory, with the single storing unit of each single-layer unit flash memory capable of storing one-digit data; the multi-layer memory module comprises a second data bus and at least one multi-layer unit flash memory, with the single storing unit of each multi-layer unit flash memory capable of storing data more than one digits; and the first data bus is coupled to the second data bus. When the write-in operation is carried out, the controller writes in the data on the single-layer memory module; and the single-layer memory module, via the mutually coupled first data bus and second data bus, transmits the data to the multi-layer memory module, without through the controller.
Description
Technical field
The present invention is about a kind of flash memory control and flash memory access method, especially in regard to a kind of flash memory control and flash memory access method that promotes the read-write speed of flash memory and reduce error rate.
Background technology
The NAND flash memory is a non-volatility memorizer, does not therefore need electric power to keep the storage of data.In addition, the NAND flash memory has the programming (program) faster and (erase) time of removing.In the NAND flash memory, the shared chip area of each storage unit (cell) is less, therefore has higher storage density.
Traditional NAND flash memory is broadly divided into single layer cell (Single Level Cell; SLC) and multilevel-cell (Multi Level Cell; MLC); Wherein the single memory cell of single layer cell (SLC) flash memory only can store the one digit number certificate, and the single memory cell of multilevel-cell (MLC) flash memory can store the data of two (or more than).Evolution along with technology; In order further to promote the storage density of memory cell; More develop now and three-layer unit (Triple level cell; TLC) and four layers of unit (Quad level cell; QLC) NAND flash memory; Wherein the single memory cell of three-layer unit (TLC) flash memory can store three bit data, and the single memory cell of four layers of unit (QLC) flash memory can store the four figures certificate.
Flash memory is usually with page or leaf (page; Or title Physical Page; Physical page) writes or read for unit carries out data; With the three-layer unit flash memory is example; A Physical Page is made up of one group of flash memory cells; Each storage unit can store three data respectively in this group storer; Comprise highest significant position (Most SignificantBit; MSB); Significance bit (the Central Significant Bit of central authorities; CSB), and least significant bit (LSB) (LeastSignificant Bit, LSB); And each three position corresponds respectively to three different logical pages or leaves (Logical page), promptly has the different logical address to supply main frame (Host) addressing.In other words, a Physical Page corresponds to three logical page (LPAGE)s.Therefore; With the three-layer unit flash memory is example; Each Physical Page also can be considered and more comprises three pagings (sub-page), and each paging is respectively to the highest significant position (MSB) that should organize each storage unit in the storage unit, central significance bit (CSB), and least significant bit (LSB) (LSB).Note that each paging that each Physical Page comprised can be notion in logic, flash memory cells not necessarily will have this paging physically to exist.
Yet, along with the storage density of each storage unit is raised, flash memory read with the write time also with increase, on the other hand, data error rate also can be along with the storable bit quantity of storage unit increases and improve.Therefore, need a kind of brand-new flash memory access method and flash memory control, can effectively promote the read-write speed of flash memory, and further reduce error rate.
Summary of the invention
According to one embodiment of the invention, a kind of flash memory devices is coupled to a main frame, in order to storage data, comprises a flash memory and a controller.Flash memory comprises a single layer of memory module and a multilayer memory module.The single layer of memory module comprises one first data bus and at least one single layer cell flash memory, and the single memory cell of each single layer cell flash memory can store one data.The multilayer memory module comprises one second data bus and at least one multilevel-cell flash memory, and the single memory cell of each multilevel-cell flash memory can store the data more than, and this first data bus is coupled to this second data bus.Controller is in order to manage the data access of this flash memory; Wherein when a write operation; This controller is from this host receiving data; Again these data are write this flash memory this single layer of memory module should (etc.) the single layer cell flash memory, and wherein this single layer of memory module through this first data bus of coupling each other and this second data bus will be stored in this (etc.) these data of single layer cell flash memory are sent to this multilayer memory module and need pass through controller.
According to another embodiment of the present invention, A flash memory device management method for managing a host coupled to a flash memory device, wherein the flash memory device comprises means for storing data and a flash memory The flash memory is used to manage a data access controller, the method comprising: in a write operation, to receive data from the host computer and the data is written to the flash memory, a single memory module, wherein the single memory module includes a first data bus and at least one single-cell flash memory, a flash memory cell of the single memory cell can store a single bit of data, and wherein the flash memory further comprises more than one layer memory module including the first data bus coupled to a second data bus and at least one multi-level cell flash memory, a flash memory of the multi-unit memory cell can store more than one bit of data; and coupled to each other through the first data bus and the second data bus will be stored in the (s) of the single unit of the flash memory of the controller and data is not written directly through the multi-layered memory module for the The data is stored in the (other) multi-level cell flash memory.
Description of drawings
Fig. 1 is the calcspar according to the described flash memory devices of one embodiment of the invention.
Fig. 2 shows the distribution schematic diagram of the critical voltage when the three-layer unit flash memory is programmed.
Fig. 3 shows a kind of anti-tampering order embodiment.
Fig. 4 shows according to the described flash memory device calcspar of one embodiment of the invention.
Fig. 5 demonstration writes and reads order according to the described data of one embodiment of the invention.
Fig. 6 shows the flow direction of flash memory device control signal and data when generally writing with read operation.
Fig. 7 shows the flow direction of flash memory device control signal and data when background operation.
Fig. 8 shows that the invader because of adjacent according to the present invention causes storage unit to produce the variation synoptic diagram.
Fig. 9 shows according to the described flash memory devices management method of one embodiment of the invention process flow diagram.
Figure 10 shows described according to another embodiment of the present invention flash memory devices management method process flow diagram.
The primary clustering symbol description:
102～main frame;
104～flash memory devices;
106～controller;
108～flash memory;
110～bug patch code coder/decoder;
412～single layer of memory;
414～multilayer storer;
416～data gate
EV, PV1, PV2, PV3, PV4, PV5, PV6, PV7, Vth～voltage;
RE, WE～signal.
Embodiment
For making manufacturing of the present invention, method of operating, target and the advantage can be more obviously understandable, hereinafter specially lift several preferred embodiments, and cooperate appended graphicly, describe in detail as follows:
Embodiment:
Fig. 1 is the calcspar according to the described flash memory devices 104 of one embodiment of the invention.Flash memory devices 104 is coupled to main frame 102, uses for main frame 102 access datas.In an embodiment, flash memory devices 104 comprises a controller 106 and a flash memory 108.The data access of controller 106 management flash memories 108.When main frame 102 was desired storage data to flash memory devices 104, the controller 106 that is coupled to main frame 102 received data from main frame 102, data is write flash memory 108 again.Desire when flash memory devices 104 extracts data when main frame 102, controller 106 is from flash memory 108 reading of data, again with data transfer to main frame 102.
Fig. 2 shows critical voltage (Threshold voltage, the V when the three-layer unit flash memory is programmed
Th) distribution schematic diagram.Note that the present invention is not exceeded with the three-layer unit flash memory, present embodiment only is the usefulness of explanation.As shown in the figure; From corresponding to the voltage of erasing (Erase Voltage; EV), (ProgramVoltage 1 for program voltage 1; PV 1, program voltage 2 (PV 2) ... the stored bit data of eight states to program voltage 7 (PV 7) etc. can be represented respectively; For example, logic state 111 ', ' 110 ', ' 100 ', ' 101 ', ' 001 ', ' 000 ', ' 010 ' and ' 011 '.
Generally speaking, for fear of once applying excessive voltage to storage unit, in writing the process of data, controller 106 can write data in the storage unit of desire programming with progressive mode usually.For example, be example with the three-layer unit flash memory, controller 106 can write the least significant bit (LSB) (LSB) of data earlier, writes central significance bit (CSB) again, writes highest significant position (MSB) at last.Thus, the accuracy that can improve programming also can increase the speed of programming.
Yet; Because when the programming multi-layer cell flash memory; Above-mentioned progressive writing mode can't avoid still applying a voltage to repeatedly that (value is noted that on the same memory cell; In this manual; Therefore the multilevel-cell flash memory of the following stated can store the general name more than the flash memory of a metadata for the representative single memory cell, and described multilevel-cell flash memory can comprise above-mentioned MLC, TLC, QLC or other).For example, when writing TLC, can apply 3 times voltage at least, in order to write LSB, CSB and MSB respectively.Therefore, in writing the process of data, the programming operation that puts on repeatedly on the same memory cell possibly cause adjacent memory cell to produce coupling effect, and then causes variation.Therefore; In fact when data are write the multilevel-cell flash memory; Can't write one by one according to the order of each paging of each Physical Page, but need be according to a kind of specific paging order (below be called anti-tampering order (anti-disturbance order)) program memory cells
Fig. 3 shows a kind of anti-tampering order embodiment.Be example with programming three-layer unit flash memory in this embodiment, the numbering among the figure is represented the programmed order of each paging.As shown in the figure, in this embodiment, the LSB that Physical Page is the 0th page at first is programmed; Then the programme LSB of the 1st page of Physical Page then returns the 0th page of programming of Physical Page CSB, then continues the LSB of the 2nd page of programming Physical Page; Return the 1st page of programming of Physical Page CSB ... by that analogy.Because according to described anti-tampering order embodiment; Each paging of same Physical Page can not be programmed continuously; But with each paging interleaved program of adjacent Physical Page; So interleaved program can produce the effect of correction, the variation that neighbor memory cell is produced in order to the programming operation of avoiding putting on continuously on the same memory cell.
Yet because reading of flash memory is in proper order preferably identical with write sequence, otherwise controller need be done extra rearrangement (reorder) action, and therefore such interleaved program can increase the time for reading of flash memory.In particular, when data are fashionable according to as shown in Figure 3 anti-tampering sequential write, controller can't be obtained all the elements of three pagings of same Physical Page in continuous 3 times logical page (LPAGE) read operation.For example; Controller must be waited until the content that just can collect the 0th page LSB, CSB and MSB when the 6th logical page (LPAGE) reads; That is; Controller must be controlled flash memory and read several Physical Page; Just can obtain the stored data of each paging of single one physical page or leaf, cause time for reading significantly to increase.Therefore, the present invention proposes a kind of new hybrid flash memory architecture, in conjunction with new flash memory access method and the flash memory control of carrying out this method, in order to significantly to promote the read-write speed of flash memory.
Fig. 4 shows according to the described flash memory device calcspar of one embodiment of the invention.As shown in the figure; Flash memory 108 can be a mixed type quick flash memory; Comprise single layer of memory module 412 and multilayer memory module 414; Wherein single layer of memory module 412 can comprise several or at least one single layer cell flash memory, and multilayer memory module 414 can comprise several or at least one multilevel-cell flash memory.The single memory cell of each single layer cell flash memory can store the data of single position; Therefore in an embodiment of the present invention; The single layer cell flash memory can be above-mentioned SLC; And each multilevel-cell flash memory can comprise several Physical Page; Each Physical Page comprises several pagings respectively, and each paging is in order to store one data.In an embodiment of the present invention; Because the single memory cell of multilevel-cell flash memory can store the data more than, so these multilevel-cell flash memories can be that above-mentioned MLC, TLC, QLC or other can store the flash memory of the data more than two.According to one embodiment of the invention, the data bus D of single layer of memory module 412
0[0]～D
0The data bus D of [n] and multilayer memory module 414
1[0]～D
1[n] couples mutually, in order to directly in transmitting data (following more detailed introduction will be arranged) between the two.
According to one embodiment of the invention, when a write operation, controller 106 can receive data from main frame 102, and at first these data is write the single layer of memory module 412 of flash memory 108.Because single layer of memory module 412 comprises several SLC flash memories, it has fast writing speed, so controller 106 can write data flash memory 108 apace, in order to promote writing speed.When treating that single layer of memory module 412 receives a set quantity data position, single layer of memory module 412 can begin the data bus D through coupling each other
0[0]～D
0[n] and D
1[0]～D
1[n] directly is sent to multilayer memory module 414 with the data that are stored in these single layer cell flash memories in background.That is, can be under the control that need not controller 106, in directly being sent to multilayer memory module 414, thus, the calculation resources of controller 106 will can be not occupied with the data that are stored in these single layer cell flash memories.
Fig. 5 demonstration writes and reads order according to the described data of one embodiment of the invention.In conjunction with anti-tampering order embodiment shown in Figure 3, below will do detailed introduction to spirit of the present invention.It should be noted that; For clear elaboration notion of the present invention; Fig. 3 and Fig. 5 with three-layer unit (TLC) flash memory be each paging of showing of example write and read order; Yet the present invention is not limited to be applied in TLC when can be applicable to the flash memory that any single memory cell can store bits of data.
As stated, disturb in order to lower in programming process adjacent Physical Page produced, each paging of same Physical Page to be being programmed discontinuously, but is preferable according to as shown in Figure 3 anti-tampering order with each paging interleaved program of adjacent Physical Page.Yet, if controller 106 according to this anti-tampering order from the flash memory reading of data, can be because of can't in continuous read operation, obtaining all the elements of each paging of same Physical Page, and significantly reduce reading rate.
Therefore; According to one embodiment of the invention; As shown in Figure 5; When write operation; Controller 106 writes single layer of memory module 412 in proper order with data based one first data; And single layer of memory module 412 is sent to multilayer memory module 414 with data in background according to one second data orders, and when a read operation, controller 106 again according to first data order from multilayer memory module 414 reading of data.
With reference to Fig. 5, the data A1 among the figure, A3 and A6 correspond respectively to the 0th page paging LSB, CSB and MSB among Fig. 3, and wherein English alphabet A represents the 0th Physical Page.Likewise, the data B2 among the figure, B5 and B9 correspond respectively to the 1st page paging LSB, CSB and MSB among Fig. 3, and wherein English alphabet B represents the 1st Physical Page, and the rest may be inferred.Shown in first row of Fig. 5, controller 106 writes single layer of memory module 412 with data based first data orders (A1, A3, A6, B2, B5, B9, C4, C8, C12...).According to first data orders, the data of each paging that are about to be stored in the same Physical Page of TLC can be write SLC earlier continuously.Then, shown in second row of Fig. 5, single layer of memory module 412 is sent to multilayer memory module 414 with data in background according to second data orders (A1, B2, A3, C4, B5, A6, D7, C8, B9...).In this embodiment; Multilayer memory module 414 receives data with described second data order from single layer of memory module 412; And those data are deposited in the multilayer memory module 414 according to anti-tampering order shown in Figure 3, be programmed with the order of interlocking in order to several pagings that will adjacent Physical Page.So the programming of interleaved order can produce the effect of correction, in order to lower the variation that the programming operation that puts on continuously on the same memory cell produces neighbor memory cell.
It should be noted that Fig. 3 in order to show wherein a kind of example of several anti interference order, is not in order to limiting scope of the present invention, and notion of the present invention is when can be applicable to other different anti-tampering order.As above-mentioned, because the SLC flash memory has fast writing speed, so controller 106 can write data in the flash memory 108 apace.When treating that single layer of memory module 412 receives a set quantity data position; For example in this embodiment; When treating that single layer of memory module 412 receives the data of paging B2, single layer of memory module 412 can begin according to second order, through the data bus D that couples each other
0[0]～D
0[n] and D
1[0]～D
1[n]; The data that are stored in these single layer cell flash memories directly are sent to multilayer memory module 414 in background; Wherein said background write operation be data without controller 106, but directly be sent to multilayer memory module 414 by single layer of memory module 412.
Because for controller 106, data based first data are written in the flash memory 108 in proper order.Therefore when reading of data, shown in the third line of Fig. 5, controller 106 equally according to these first data orders (A1, A3, A6, B2, B5, B9, C4, C8, C12...) from multilayer memory module 414 reading of data.What can notice is; According to first order; The data that are stored in each paging of same Physical Page can be read continuously; That is; Controller is only controlled multilayer memory module 414 and is read the single one physical page or leaf; The stored data of each paging of this Physical Page can be obtained, thus, reading speed can be significantly accelerated.Therefore; In conjunction with above-mentioned hybrid framework and read and wiring method; Flash memory device proposed by the invention not only can provide very fast writing and reading speed, simultaneously also because with data storing in the multilevel-cell flash memory, and then very high storage volume can be provided.
According to one embodiment of the invention, controller 106 can transmit and control signal to single layer of memory module 412 and multilayer memory module 414, in order to the data access of management flash memory.Fig. 6 shows the flow direction of flash memory device control signal and data when generally writing with read operation.As shown in Figure 6, when write operation, controller 106 transmits one and writes enable signal WE and frequency signal (scheming not show) to single layer of memory module 412, in order to data are write single layer of memory module 412.And when read operation, controller 106 transmits one and reads enable signal RE and frequency signal (scheming not show) to multilayer memory module 414, in order to data are read out from multilayer memory module 414.It should be noted that general controller 106 can control data bus D when writing with read operation
0[0]～D
0[n] and D
1[0]～D
1Data gate 416 between [n] (a for example impact damper) makes its anergy, avoids multilayer memory module 414 to be interfered.
Fig. 7 shows the flow direction of flash memory device control signal and data when background operation.Controller 106 can control data bus D
0[0]～D
0[n] and D
1[0]～D
1Data gate 416 between [n] makes its unlatching; As shown in Figure 7; Controller 106 transmits one and reads enable signal RE and frequency signal (scheming not show) to single layer of memory module 412; And transmit one simultaneously and write enable signal WE and frequency signal (figure does not show) to multilayer memory module 414; Do not pass through controller 106 in order to cause data, and directly pass through data bus D from the single layer of memory module
0[0]～D
0[n] and D
1[0]～D
1[n] is sent to the multilayer memory module.Thus, can significantly promote the speed of data transmission, reduce the computing and the transmission resource consumption of controller.
In addition, as shown in Figure 1, controller 106 can more comprise a bug patch code coder/decoder 110, writes the data of flash memory 108 in order to coding, and deciphers the data that read from flash memory 108.According to another embodiment of the present invention; When the data of adjacent Physical Page in regular turn after the multilayer memory module 414 of flash memory 108 is read; Bug patch code coder/decoder 110 can be deciphered these data that read; Whether the detecting data content is wrong; And when the wrong figure place that detects too much can't be revised according to bug patch code; Further infer the position of making a mistake, and carry out error correction, with reduction proper data content according to the stored content of neighbor memory cell.
Generally speaking, controller can define an amendable wrong figure place, and when in a paging, detecting the bit quantity that makes a mistake less than amendable wrong figure place, traditional bug patch code coder/decoder just can be carried out error correction.Otherwise traditional bug patch code coder/decoder can be considered as and can't revise, and abandons this paging.
Yet; According to one embodiment of the invention; Because the content of adjacent Physical Page can be read in multilayer memory module 414 in regular turn apace; Therefore when detecting the bit quantity that makes a mistake greater than amendable wrong figure place; Bug patch code coder/decoder 110 of the present invention can further be found out the memory cell that possibly make a mistake according to the stored content of consecutive storage unit; And infer according to the stored content of consecutive storage unit and the stored initial data of this memory cell; Again carry out bug patch code decoding according to the initial data of this supposition; In order to the initial data of attempt reduction memory cell, and the position that corrects mistakes.
According to one embodiment of the invention, controller 106 can define the logic state that easily other logic state that is stored is exerted an influence earlier, below is referred to as invader (aggressor).With the three-layer unit flash memory is example, and Fig. 8 shows that the invader because of adjacent according to the present invention causes storage unit to produce the variation synoptic diagram.As shown in the figure; Because the programming state of certain storage unit of Physical Page i page or leaf is PV7; It has the highest voltage; In other words; When being programmed into this state; Need apply maximum voltage to storage unit; Cause in the process of programming; The influence that the big voltage that applies produces variation to the storage unit of the Physical Page i+1 page or leaf of adjacent (or contiguous) (or i-1 page or leaf, the i+2 page or leaf, i-2 page or leaf etc. of a Physical Page) at interval; For example; Cause its programming state to be displaced near PV1, and then produce mistake by EV.Therefore, the storage unit that is programmed into state PV7 can be defined as the invader.
In an embodiment of the present invention; When bug patch code coder/decoder 110 detects bit quantity that a logical page (LPAGE) (corresponding to a paging) makes a mistake greater than amendable wrong figure place; Can find out earlier the corresponding paging of this logical page (LPAGE) the content of adjacent Physical Page whether have the invader; If have, can infer that then error bit betides the storage unit of adjacent with the invader (for example adjacent on the physical location).Then; Bug patch code coder/decoder 110 is inferred the original contents that with invader's adjacent memory unit according to the stored content of invader; Again carry out bug patch code decoding revise the information that reads of this paging according to the original contents of this supposition after; In order to the original contents of attempt reduction memory cell, and the position that corrects mistakes.In one embodiment, bug patch code coder/decoder 110 is found out each storage unit that is programmed to ceiling voltage state (for example PV7) in this adjacent Physical Page earlier, for example a paging (for example MSB) the correcting code decoding error that makes a mistake in the Physical Page K page or leaf.And bug patch code coder/decoder 110 finds the 1st, 3,5 storage unit to be programmed to the ceiling voltage state in Physical Page K+1 page or leaf, and in Physical Page K-1 page or leaf, finds the 7th, 9 storage unit to be programmed to the ceiling voltage state.Bug patch code coder/decoder 110 is considered as the invader with the above-mentioned storage unit that is programmed to the ceiling voltage state; And because those invaders are programmed to the storage unit of ceiling voltage state, so bug patch code coder/decoder 110 is according to the reading of content of the 1st, 3,5,7,9 storage unit of the stored content modification Physical Page K page or leaf of invader.For example, before modification, the voltage status that controller 106 reads the 1st, 3,5,7,9 storage unit of K page or leaf is respectively PV1, PV2, PV1, PV1, PV1.Bug patch code coder/decoder 110 infers that according to the invader those storage unit receive invader's influence and cause upwards skew of voltage; And the virgin state of inferring those storage unit is respectively PV0, PV1, PV0, PV0, PV0; And the information that reads of corresponding modification MSB; Again carry out bug patch code decoding again, whether correct to confirm its supposition (correction).
In another embodiment; To a paging controller 106 defined amendable wrong figure places is 68; And bug patch code coder/decoder 110 is when certain MSB paging of decoding; Detect 100 error bits; Because the error bit that takes place is greater than amendable wrong figure place; Bug patch code coder/decoder 110 can't be revised according to bug patch code, whether has the invader so bug patch code coder/decoder 110 begins to seek the content of adjacent Physical Page.If bug patch code coder/decoder 110 can find out more than 32 with invader's adjacent memory unit; Then can be according to notion as shown in Figure 8; Infer the original contents that with invader's adjacent memory unit according to the stored content of invader, carry out bug patch code decoding after revising according to the original contents of this supposition again.When these and invader's storage unit during really for the position of making a mistake; Revised wrong figure place can be less than controller 106 defined amendable wrong figure places; Thus; Bug patch code coder/decoder 110 can be carried out bug patch code decoding again according to revised content; Revising all error bits, and correctly restore the raw data of this Physical Page.If bug patch code coder/decoder 110 can't find out more than 32 with invader's adjacent memory unit; Then can relax invader's definition; For example each storage unit that is programmed to time high-voltage state (for example PV6) in the adjacent Physical Page also is defined as the invader; Seek once more and invader's adjacent memory unit of relaxing after the definition, revise again and confirm.If after relaxing invader's definition; Bug patch code coder/decoder 110 still can't find out more than 32 with invader's adjacent memory unit; Then can relax invader's definition once again; For example will be close to each storage unit that is programmed for the ceiling voltage state in the Physical Page (for example with this paging under the Physical Page Physical Page of a Physical Page at interval) and also be defined as the invader, and revise again and confirm.Perhaps increase invader's coverage, also include those adjacent in same Physical Page storage unit institute adjacent memory unit in extent of amendment, revise once more and confirm with the invader.Revise invader's definition and invader's coverage repeatedly, in the hope of correctly restoring the raw data of this Physical Page.Note that do not need according to certain order make amendment invader definition and coverage, the user carries out when can under instruction of the present invention, arranging in pairs or groups arbitrarily.
In sum, Fig. 9 shows according to the described flash memory devices management method of one embodiment of the invention process flow diagram.At first, when a write operation, from host receiving data and according to first data orders data are write in the single layer of memory module of flash memory (step S901).Then; Transmit one and read enable signal to single layer of memory module; And transmit one and write enable signal to multilayer memory module; And through data based second data that the data bus that couples each other will be stored in the single layer cell flash memory multilayer memory module (step S902) of writing direct in proper order, in order under not through the situation of controller with this data storing in these multilevel-cell flash memories.At last, when a read operation, according to first data orders from multilayer memory module reading of data, again with data transfer to main frame (step S903).
Figure 10 shows described according to another embodiment of the present invention flash memory devices management method process flow diagram.According to embodiments of the invention; When in the process of flash memory devices reading of data and decoding, detecting bit quantity that a paging makes a mistake greater than an amendable wrong figure place, at first according to the Physical Page under this paging the stored content of several storage unit of adjacent Physical Page infer one or more storage unit (step S1001) that possibly make a mistake in this paging.Then, according to the stored content of these adjacent storage unit infer should (etc.) original contents (step S1002) of the storage unit that possibly make a mistake.At last, according to this (etc.) original contents inferred carries out bug patch code decoding (step S1003) again.
Though the present invention discloses as above with preferred embodiment; Right its is not in order to limiting scope of the present invention, anyly has the knack of this art, do not breaking away from the spirit and scope of the present invention; When can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking claims person of defining.
Claims (15)
1. a flash memory devices is coupled to a main frame, in order to storage data, comprising:
One flash memory comprises:
One single layer of memory module comprises one first data bus and at least one single layer cell flash memory, and the single memory cell of each single layer cell flash memory can store one data; And
One multilayer memory module comprises one second data bus and at least one multilevel-cell flash memory, and the single memory cell of each multilevel-cell flash memory can store the data more than, and this first data bus is coupled to this second data bus; And
One controller, in order to manage the data access of this flash memory, wherein when a write operation, this controller writes these data this single layer cell flash memory of this single layer of memory module of this flash memory again from this host receiving data,
And wherein this single layer of memory module is sent to this multilayer memory module and need pass through this controller through these data that this first data bus of coupling each other and this second data bus will be stored in this single layer cell flash memory.
2. flash memory devices as claimed in claim 1; Wherein this controller transmits one and reads enable signal to this single layer of memory module; And transmit one and write enable signal to this multilayer memory module; In order to causing these data, and directly be sent to this multilayer memory module from this single layer of memory module through this controller.
3. flash memory devices as claimed in claim 1, wherein when a read operation, this controller is from this multilayer memory module reading of data, again with this data transfer to this main frame.
4. flash memory devices as claimed in claim 1; Wherein this controller writes this single layer cell flash memory according to one first data order with these data; This single layer of memory module is sent to this multilayer memory module according to one second data order with these data; And when a read operation; This controller reads this data according to this first data order from this multilayer memory module, and wherein these first data are not equal to this second data order in proper order.
5. flash memory devices as claimed in claim 4; Wherein this multilevel-cell flash memory respectively comprises several Physical Page; Each Physical Page comprises several pagings respectively, and according to this first data order, these data that are stored in these pagings of same Physical Page are read continuously.
6. flash memory devices as claimed in claim 5, wherein according to this second data order, these pagings of these adjacent Physical Page are programmed with staggered order, in order to avoid programming same Physical Page continuously adjacent Physical Page are produced interference.
7. flash memory devices as claimed in claim 1; Wherein this controller more comprises a bug patch code coder/decoder; Write these data of this flash memory in order to coding; And these data of reading from this flash memory of decoding; Wherein in the process that this bug patch code coder/decoder is being deciphered; When detecting bit quantity that the paging under the Physical Page makes a mistake greater than an amendable wrong figure place; This bug patch code coder/decoder further basis is inferred one or more memory cell that possibly make a mistake in this Physical Page with the stored content of several memory cell of the Physical Page of this Physical Page vicinity; Infer the original contents of this memory cell that possibly make a mistake according to the stored content of this contiguous memory cell, and carry out bug patch code again according to the original contents of this supposition and decipher.
8. flash memory devices management method; Be coupled to a flash memory devices of a main frame in order to management; Wherein this flash memory devices comprises that this method comprises in order to a flash memory of storage data and in order to a controller of the data access of managing this flash memory:
In the write operation, the master receives data from and write data to the flash memory that a single memory module, wherein the single memory module includes a first data bus and at least one single unit flash memory, a flash memory cell of the single memory cell can store a single bit of data, and wherein the flash memory further comprises a multi-layer memory module including the first data bus coupled to a second data bus at least one multi-level cell flash memory, the multi-level cell flash memory can store more than a single storage unit data; and
These data that will be stored in this single layer cell flash memory through this first data bus of coupling each other and this second data bus do not write this multilayer memory module through this controller, in order to this data storing in this multilevel-cell flash memory.
9. method as claimed in claim 8 more comprises:
Transmit one and read enable signal to this single layer of memory module;
Transmit one and write enable signal to this multilayer memory module; And
Reading enable signal and this according to this writes enable signal these data directly is sent to this multilayer memory module from this single layer of memory module.
10. method as claimed in claim 8 more comprises:
When a read operation, this multilayer memory module reading of data certainly, again with this data transfer to this main frame.
11. method as claimed in claim 8, the step that wherein these data is write this single layer of memory module more comprises:
According to one first data order these data are write this single layer cell flash memory;
And the step that directly these data is write this multilayer memory module more comprises:
According to one second data order these data are write this multilayer memory module, wherein these first data are not equal to this second data order in proper order.
12. method as claimed in claim 11 more comprises:
When a read operation, read this data from this multilayer memory module according to this first data order.
13. method as claimed in claim 11, wherein according to this first data order, the data of several pagings that are stored in the same Physical Page of this multilevel-cell flash memory are read continuously.
14. method as claimed in claim 11, wherein according to this second data order, several pagings of the adjacent Physical Page of this multilevel-cell flash memory are programmed with staggered order.
15. method as claimed in claim 10, the step that wherein these data is write this single layer of memory module more comprises:
Write these data of this flash memory according to bug patch code coding;
And the step of this multilayer memory module reading of data more comprises certainly:
These data that are read according to this bug patch code coding and decoding;
When in the process of decoding, detecting bit quantity that the paging under the Physical Page makes a mistake, according to inferring one or more storage unit that possibly make a mistake in this Physical Page with the stored content of several storage unit of the contiguous Physical Page of this Physical Page greater than an amendable wrong figure place;
Infer the original contents of this storage unit that possibly make a mistake according to the stored content of this contiguous storage unit; And
Again carry out bug patch code decoding according to the original contents of this supposition.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US36620110P | 2010-07-21 | 2010-07-21 | |
| US61/366,201 | 2010-07-21 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102346652A true CN102346652A (en) | 2012-02-08 |
Family
ID=45545363
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011101521021A Pending CN102346652A (en) | 2010-07-21 | 2011-05-27 | Flash storing device and method for managing flash storing device |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN102346652A (en) |
| TW (1) | TWI442222B (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103678159A (en) * | 2013-12-27 | 2014-03-26 | 威盛电子股份有限公司 | Data storage device and data write-in method thereof |
| CN103870214A (en) * | 2014-02-26 | 2014-06-18 | 深圳市安信达存储技术有限公司 | Method for enabling MLC (Multi Level Cell) to have function of SLC (Single Level Cell) |
| CN105786412A (en) * | 2013-11-05 | 2016-07-20 | 威盛电子股份有限公司 | Method of operating a non-volatile memory device |
| CN110175088A (en) * | 2013-08-23 | 2019-08-27 | 慧荣科技股份有限公司 | Access the method for storage element and the device using this method in flash memory |
| CN110197689A (en) * | 2018-02-27 | 2019-09-03 | 东芝存储器株式会社 | Semiconductor storage and storage system |
| CN110277129A (en) * | 2018-03-16 | 2019-09-24 | 爱思开海力士有限公司 | Coding method and system for the memory device including QLC unit |
| CN111399752A (en) * | 2019-01-03 | 2020-07-10 | 慧荣科技股份有限公司 | Control device and method for different types of storage units |
| US11748022B2 (en) | 2019-01-03 | 2023-09-05 | Silicon Motion, Inc. | Method and apparatus for controlling different types of storage units |
| US11762569B2 (en) | 2019-10-29 | 2023-09-19 | International Business Machines Corporation | Workload based relief valve activation for hybrid controller architectures |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2019149220A (en) * | 2018-02-27 | 2019-09-05 | 東芝メモリ株式会社 | Semiconductor memory device and memory system |
| TWI698749B (en) * | 2019-03-13 | 2020-07-11 | 慧榮科技股份有限公司 | A data storage device and a data processing method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030031053A1 (en) * | 2000-11-21 | 2003-02-13 | Cheng-Chung Tsao | Integrated circuit memory device having interleaved read and program capabilities and methods of operating same |
| US20080104309A1 (en) * | 2006-10-30 | 2008-05-01 | Cheon Won-Moon | Flash memory device with multi-level cells and method of writing data therein |
| US20080253188A1 (en) * | 2006-02-16 | 2008-10-16 | Micron Technology, Inc. | Programming method to reduce gate coupling interference for non-volatile memory |
| US20080316816A1 (en) * | 2007-06-25 | 2008-12-25 | Lin Jason T | Systems for programming multilevel cell nonvolatile memory |
-
2011
- 2011-02-01 TW TW100103848A patent/TWI442222B/en active
- 2011-05-27 CN CN2011101521021A patent/CN102346652A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030031053A1 (en) * | 2000-11-21 | 2003-02-13 | Cheng-Chung Tsao | Integrated circuit memory device having interleaved read and program capabilities and methods of operating same |
| US20080253188A1 (en) * | 2006-02-16 | 2008-10-16 | Micron Technology, Inc. | Programming method to reduce gate coupling interference for non-volatile memory |
| US20080104309A1 (en) * | 2006-10-30 | 2008-05-01 | Cheon Won-Moon | Flash memory device with multi-level cells and method of writing data therein |
| US20080316816A1 (en) * | 2007-06-25 | 2008-12-25 | Lin Jason T | Systems for programming multilevel cell nonvolatile memory |
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110175088A (en) * | 2013-08-23 | 2019-08-27 | 慧荣科技股份有限公司 | Access the method for storage element and the device using this method in flash memory |
| CN110175088B (en) * | 2013-08-23 | 2022-11-11 | 慧荣科技股份有限公司 | Method for accessing storage unit in flash memory and device using the same |
| CN105786412A (en) * | 2013-11-05 | 2016-07-20 | 威盛电子股份有限公司 | Method of operating a non-volatile memory device |
| CN105786412B (en) * | 2013-11-05 | 2019-04-19 | 威盛电子股份有限公司 | Method of operating a non-volatile memory device |
| CN106959822B (en) * | 2013-12-27 | 2020-02-07 | 威盛电子股份有限公司 | Data storage device and data writing method thereof |
| CN106959822A (en) * | 2013-12-27 | 2017-07-18 | 威盛电子股份有限公司 | Data memory device and its method for writing data |
| CN103678159A (en) * | 2013-12-27 | 2014-03-26 | 威盛电子股份有限公司 | Data storage device and data write-in method thereof |
| CN103870214A (en) * | 2014-02-26 | 2014-06-18 | 深圳市安信达存储技术有限公司 | Method for enabling MLC (Multi Level Cell) to have function of SLC (Single Level Cell) |
| CN110197689A (en) * | 2018-02-27 | 2019-09-03 | 东芝存储器株式会社 | Semiconductor storage and storage system |
| CN110197689B (en) * | 2018-02-27 | 2023-03-10 | 铠侠股份有限公司 | Semiconductor memory device and memory system |
| CN110277129A (en) * | 2018-03-16 | 2019-09-24 | 爱思开海力士有限公司 | Coding method and system for the memory device including QLC unit |
| CN111399752A (en) * | 2019-01-03 | 2020-07-10 | 慧荣科技股份有限公司 | Control device and method for different types of storage units |
| US11748022B2 (en) | 2019-01-03 | 2023-09-05 | Silicon Motion, Inc. | Method and apparatus for controlling different types of storage units |
| CN111399752B (en) * | 2019-01-03 | 2023-11-28 | 慧荣科技股份有限公司 | Control device and method for different types of storage units |
| US11762569B2 (en) | 2019-10-29 | 2023-09-19 | International Business Machines Corporation | Workload based relief valve activation for hybrid controller architectures |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201205277A (en) | 2012-02-01 |
| TWI442222B (en) | 2014-06-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102346652A (en) | Flash storing device and method for managing flash storing device | |
| US8732538B2 (en) | Programmable data storage management | |
| US11573742B2 (en) | Dynamic data placement for collision avoidance among concurrent write streams | |
| US11709632B2 (en) | Input/output size control between a host system and a memory sub-system | |
| US11676679B2 (en) | Two-layer code with low parity cost for memory sub-systems | |
| US11269552B2 (en) | Multi-pass data programming in a memory sub-system having multiple dies and planes | |
| US11294820B2 (en) | Management of programming mode transitions to accommodate a constant size of data transfer between a host system and a memory sub-system | |
| US9122583B2 (en) | Memory controller and memory storage device and data writing method | |
| US11249896B2 (en) | Logical-to-physical mapping of data groups with data locality | |
| US8301850B2 (en) | Memory system which writes data to multi-level flash memory by zigzag interleave operation | |
| US20220075690A1 (en) | Error handling optimization in memory sub-system mapping | |
| CN113377279A (en) | Data storage device and data processing method | |
| US11726669B2 (en) | Coherency locking schemes | |
| CN113094293B (en) | Memory system and related method and computer readable storage medium | |
| US20220375522A1 (en) | Copy redundancy in a key-value data storage system using content addressable memory | |
| CN117612589A (en) | Partial block processing in a non-volatile memory device | |
| CN117882043A (en) | Eliminating write disturbance of system metadata in a memory subsystem |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20120208 |