CN107346211A - Mapping table loading method, memory control circuit unit and internal storing memory - Google Patents

Mapping table loading method, memory control circuit unit and internal storing memory Download PDF

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Publication number
CN107346211A
CN107346211A CN201610300912.XA CN201610300912A CN107346211A CN 107346211 A CN107346211 A CN 107346211A CN 201610300912 A CN201610300912 A CN 201610300912A CN 107346211 A CN107346211 A CN 107346211A
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Prior art keywords
mapping table
logical address
physical address
operator scheme
sub
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CN107346211B (en
Inventor
叶志刚
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Hefei Core Electronics Co Ltd
Hefei Core Storage Electronic Ltd
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Hefei Core Electronics Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0604—Improving or facilitating administration, e.g. storage management
    • G06F3/0607—Improving or facilitating administration, e.g. storage management by facilitating the process of upgrading existing storage systems, e.g. for improving compatibility between host and storage device
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1009—Address translation using page tables, e.g. page table structures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Memory System (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

The present invention proposes a kind of mapping table loading method, memory control circuit unit and internal storing memory.This method includes：Receive the first instruction；When the operator scheme of duplicative Nonvolatile memory module is first operator scheme, the first sub- logical address physical address mapping table of corresponding first instruction of loading；And when the operator scheme of duplicative Nonvolatile memory module is second operator scheme, first logical address physical address mapping table of corresponding first instruction of loading, wherein the first logical address physical address mapping table includes the first sub- logical address physical address mapping table.The present invention can effectively improve the service efficiency and efficiency of internal storing memory.

Description

Mapping table loading method, memory control circuit unit and internal storing memory
Technical field
The present invention relates to a kind of mapping table loading method, memory control circuit unit and internal storing memory.
Background technology
Digital camera, mobile phone and MP3 are very rapid in growth over the years so that consumer is also anxious to the demand of store media Speed increase.Due to duplicative Nonvolatile memory (rewritable non-volatile memory) have data non-volatile, power saving, Small volume, without the characteristic such as mechanical structure, read or write speed be fast, be most suitable for portable electronic product, such as notebook computer.Solid-state Hard disk is exactly a kind of internal storing memory using flash memory module as store media.Therefore, flash memory industry turns into electronic industry in recent years In a quite popular ring.
In general, duplicative Nonvolatile memory module generally includes multiple entity erased cells, and each entity is smeared Except unit can include multiple entity program units.Memory management circuit in internal storing memory can configure logical address to map Entity erased cell, each of which logical address have multiple logic units to map the entity program of corresponding entity erased cell Change unit.
In order to identify which entity erased cell is the data of each logical address be stored in, memory management circuit can record logically Mapping between location and entity erased cell.Specifically, memory management circuit can be in duplicative Nonvolatile memory module Multiple logical addresses-physical address mapping table is stored to record the entity erased cell that each logical address is mapped.When number to be accessed According to when, memory management circuit can load corresponding logical address-physical address mapping table, and be reflected according to logical address-physical address Firing table writes or read data.
It is noted that memory management circuit is typically to be managed with the logical address of fixed size-physical address mapping table. For example, when data to be accessed, in logical address-physical address mapping table to the buffering note of memory management circuit loading fixed size Deposit, and write or read data according to logical address-physical address mapping table.
Particularly, in the case where memory management circuit performs random read take (random read) operation, it generally can only use and be loaded Logical address-physical address mapping table partial information.When random read operation is repeatedly carried out in memory management circuit, internal memory Management circuit can load different logical addresses-physical address mapping table, and each logical address-physical address mapping table in multiple times It can only use and arrive partial information, this situation can cause the service efficiency of logical address-physical address mapping table low.Patrolled in addition, working as When volume address-physical address mapping table is larger, memory storage can also be wasted by repeatedly loading different logical addresses-physical address mapping table The bandwidth of cryopreservation device, in turn result in the performance deterioration of internal storing memory.
The content of the invention
The present invention provides a kind of mapping table loading method, memory control circuit unit and internal storing memory, can effectively improve interior Store the service efficiency and efficiency of cryopreservation device.
The present invention proposes a kind of mapping table loading method, non-easily for duplicative Nonvolatile memory module, wherein duplicative Multiple logical address-physical address the mapping tables of the property lost memory modules storage and each logical address-physical address mapping table have multiple Sub- logical address-physical address mapping table, the loading of this mapping table include：The first instruction is received, wherein the first instruction corresponds to storage In the data of the first logical address；When the operator scheme of corresponding duplicative Nonvolatile memory module is first operator scheme, From the first sub- logical address among the sub- logical address of duplicative Nonvolatile memory module loading-physical address mapping table-physically Location mapping table is into buffer storage, wherein the first sub- logical address-physical address mapping table record has corresponding first logical address Map information；And when the operator scheme of corresponding duplicative Nonvolatile memory module is second operator scheme, from can make carbon copies The first logical address-physical address mapping table among formula Nonvolatile memory module loading logical address-physical address mapping table is extremely In buffer storage, wherein the first logical address-physical address mapping table record has the map information of corresponding first logical address, its In the first logical address-physical address mapping table include the first sub- logical address-physical address mapping table.
In one example of the present invention embodiment, wherein before the step of receiving the first instruction, in addition to：Patrolled according to the second son Collect address-physical address mapping table and perform the second instruction；When the second sub- logical address-physical address mapping table is different from the first sub- logic During address-physical address mapping table, judge the operator scheme of duplicative Nonvolatile memory module for first operator scheme；And When the second sub- logical address-physical address mapping table is same as the first sub- logical address-physical address mapping table, duplicative is judged The operator scheme of Nonvolatile memory module is second operator scheme.
In one example of the present invention embodiment, when the second sub- logical address-physical address mapping table be different from the first sub- logical address- During physical address mapping table, in addition to：When the first logical address-physical address mapping table includes second sub- logical address-physical address During mapping table, judge the operator scheme of duplicative Nonvolatile memory module for second mode.
In one example of the present invention embodiment, before the step of receiving the first instruction, in addition to：According to the second logical address- Physical address mapping table performs the 3rd instruction；When the second logical address-physical address mapping table is different from the first logical address-physically During the mapping table of location, judge the operator scheme of duplicative Nonvolatile memory module for first operator scheme.
In one example of the present invention embodiment, wherein when the operator scheme of duplicative Nonvolatile memory module is the first operation During pattern, in addition to：First instruction is performed according to the first sub- logical address-physical address mapping table；Erase the first sub- logical address- Physical address mapping table；And in the use course for managing record the first sub- logical address-physical address mapping table in table.
In one example of the present invention embodiment, wherein operator scheme of the duplicative Nonvolatile memory module after upper electricity every time It is to be defaulted as first operator scheme.
In one example of the present invention embodiment, wherein first operator scheme includes random read operation pattern, random writing operates The operator scheme of selection recovery block in pattern or collecting garbage (garbage collection) program.
In one example of the present invention embodiment, wherein second operator scheme includes continuous read mode, is continuously written into operation The operator scheme that is write in pattern, collecting garbage (garbage collection) program to purpose block brings down stocks (flush) operation mould Formula.
An exemplary embodiment of the invention provides a kind of memory control circuit list for being used to control duplicative Nonvolatile memory module Member.This memory control circuit unit includes：It is electrically connected to the HPI of host computer system；It is electrically connected to answer The memory interface of formula Nonvolatile memory module is write, wherein duplicative Nonvolatile memory module stores multiple logical address-entities Address mapping table and each logical address-physical address mapping table have more sub- logical address-physical address mapping tables；Buffer-stored Device and the memory management circuit for being electrically connected to HPI, memory interface and buffer storage.Memory management circuit is connecing The first instruction is received, wherein the first instruction corresponds to the data for being stored in the first logical address；In corresponding duplicative is non-volatile When the operator scheme of storing module is first operator scheme, from the sub- logical address of duplicative Nonvolatile memory module loading-physically The first sub- logical address-physical address mapping table is into buffer storage among the mapping table of location, wherein the first sub- logical address-physically Location mapping table record has the map information of corresponding first logical address；And the behaviour when corresponding duplicative Nonvolatile memory module When operation mode is second operator scheme, among duplicative Nonvolatile memory module loading logical address-physical address mapping table The first logical address-physical address mapping table into buffer storage, wherein the first logical address-physical address mapping table record has The map information of corresponding first logical address, wherein the first logical address-physical address mapping table includes first sub- logical address-entity Address mapping table.
In one example of the present invention embodiment, wherein in receive first instruction running before, memory management circuit more to： Second instruction is performed according to the second sub- logical address-physical address mapping table；When the second sub- logical address-physical address mapping table is different When the first sub- logical address-physical address mapping table, judge the operator scheme of duplicative Nonvolatile memory module for the first behaviour Operation mode；And when the second sub- logical address-physical address mapping table is same as the first sub- logical address-physical address mapping table, Judge the operator scheme of duplicative Nonvolatile memory module for second operator scheme.
In one example of the present invention embodiment, when the second sub- logical address-physical address mapping table be different from the first sub- logical address- During physical address mapping table and when the first logical address-physical address mapping table includes the second sub- logical address-physical address mapping table When, memory management circuit is more judging the operator scheme of duplicative Nonvolatile memory module for second mode.
In one example of the present invention embodiment, in receive first instruction running before, memory management circuit more to：According to Second logical address-physical address mapping table performs the 3rd instruction；When the second logical address-physical address mapping table is patrolled different from first When collecting address-physical address mapping table, judge the operator scheme of duplicative Nonvolatile memory module for first operator scheme.
In one example of the present invention embodiment, wherein when the operator scheme of duplicative Nonvolatile memory module is the first operation During pattern, memory management circuit more to：First instruction is performed according to the first sub- logical address-physical address mapping table；Erase One sub- logical address-physical address mapping table；And in the use for managing record the first sub- logical address-physical address mapping table in table Course.
In one example of the present invention embodiment, wherein operator scheme of the duplicative Nonvolatile memory module after upper electricity every time It is to be defaulted as first operator scheme.
In one example of the present invention embodiment, wherein first operator scheme includes random read operation pattern, random writing operates The operator scheme of selection recovery block in pattern or collecting garbage (garbage collection) program.
In one example of the present invention embodiment, wherein second operator scheme includes continuous read mode, is continuously written into operation The operator scheme that is write in pattern, collecting garbage (garbage collection) program to purpose block brings down stocks (flush) operation mould Formula.
An exemplary embodiment of the invention provides a kind of internal storing memory.It includes：It is electrically connected to the connection of host computer system Interface unit, duplicative Nonvolatile memory module and be electrically connected to connecting interface unit and duplicative it is non-volatile in The memory control circuit unit of storing module.Wherein memory control circuit unit includes buffer storage, and duplicative is non-volatile The multiple logical addresses of memory storage-physical address mapping table and each logical address-physical address mapping table has more height logically Location-physical address mapping table.Memory control circuit unit is to receive the first instruction, wherein the first instruction, which corresponds to, is stored in first The data of logical address；When the operator scheme of corresponding duplicative Nonvolatile memory module is first operator scheme, from can answer The first sub- logical address-physical address maps among writing the sub- logical address of formula Nonvolatile memory module loading-physical address mapping table Table is into buffer storage, wherein the first sub- logical address-physical address mapping table record has the mapping letter of corresponding first logical address Breath；And when the operator scheme of corresponding duplicative Nonvolatile memory module is second operator scheme, it is non-easily from duplicative The first logical address-physical address mapping table to buffering among the property lost memory modules load logic address-physical address mapping table is deposited In reservoir, wherein the first logical address-physical address mapping table record has the map information of corresponding first logical address, wherein first Logical address-physical address mapping table includes the first sub- logical address-physical address mapping table.
In one example of the present invention embodiment, wherein before the running of the first instruction is received, memory control circuit unit is more used With：Second instruction is performed according to the second sub- logical address-physical address mapping table；When the second sub- logical address-physical address mapping table During different from the first sub- logical address-physical address mapping table, judge the operator scheme of duplicative Nonvolatile memory module for One operator scheme；And when the second sub- logical address-physical address mapping table is same as the first sub- logical address-physical address mapping table When, judge the operator scheme of duplicative Nonvolatile memory module for second operator scheme.
In one example of the present invention embodiment, when the second sub- logical address-physical address mapping table be different from the first sub- logical address- During physical address mapping table and when the first logical address-physical address mapping table includes the second sub- logical address-physical address mapping table When, memory control circuit unit is more judging the operator scheme of duplicative Nonvolatile memory module for second mode.
In one example of the present invention embodiment, in receive first instruction running before, memory control circuit unit more to： 3rd instruction is performed according to the second logical address-physical address mapping table；When the second logical address-physical address mapping table is different from the During one logical address-physical address mapping table, judge the operator scheme of duplicative Nonvolatile memory module for first operator scheme.
In one example of the present invention embodiment, wherein when the operator scheme of duplicative Nonvolatile memory module is the first operation During pattern, memory control circuit unit more to：First instruction is performed according to the first sub- logical address-physical address mapping table；Smear Except the first sub- logical address-physical address mapping table；And the first sub- logical address-physical address mapping table is recorded in table in managing Use course.
In one example of the present invention embodiment, wherein operator scheme of the duplicative Nonvolatile memory module after upper electricity every time It is to be defaulted as first operator scheme.
In one example of the present invention embodiment, wherein first operator scheme includes random read operation pattern, random writing operates The operator scheme of selection recovery block in pattern or collecting garbage (garbage collection) program.
In one example of the present invention embodiment, wherein second operator scheme includes continuous read mode, is continuously written into operation The operator scheme that is write in pattern, collecting garbage (garbage collection) program to purpose block brings down stocks (flush) operation mould Formula.
Based on above-mentioned, the present invention uses by different size of logical address-physical address mapping table is loaded and avoids host computer system from holding The bandwidth that larger logical address-physical address mapping table is repeatedly loaded during row random read operation and causes internal storing memory Waste, and the service efficiency and efficiency of internal storing memory can be effectively improved.
For features described above of the invention and advantage can be become apparent, special embodiment below, and coordinate accompanying drawing to elaborate It is as follows.
Brief description of the drawings
Fig. 1 is the signal of host computer system according to an exemplary embodiment, internal storing memory and input/output (I/O) device Figure；
Fig. 2 is showing for host computer system according to another exemplary embodiment, internal storing memory and input/output (I/O) device It is intended to；
Fig. 3 is the schematic diagram of the host computer system and internal storing memory according to exemplary embodiment of the present invention；
Fig. 4 is the summary block diagram of the host computer system and internal storing memory according to an exemplary embodiment；
Fig. 5 is the summary block diagram of the memory control circuit unit according to an exemplary embodiment；
Fig. 6 and Fig. 7 is the example schematic of the management entity erased cell according to an exemplary embodiment；
Fig. 8 A and Fig. 8 B are the corresponding more height of logical address-physical address mapping table according to an exemplary embodiment The example schematic of logical address-physical address mapping table；
Fig. 9 A~Fig. 9 B are the schematic diagrames of the internal memory read method according to the first example；
Figure 10 A~Figure 10 B are the schematic diagrames of the internal memory read method according to the second example；
Figure 11 A~Figure 11 B are the schematic diagrames of the internal memory read method according to the 3rd example；
Figure 12 A~Figure 12 B are the schematic diagrames of the internal memory read method according to the 4th example；
Figure 13 is the flow chart of the mapping table loading method according to an exemplary embodiment；
Reference：
10：Internal storing memory
11：Host computer system
12：Input/output (I/O) device
110：System bus
111：Processor
112：Random access memory (RAM)
113：Read-only storage (ROM)
114：Data transmission interface
20：Mainboard
204：Wireless internal storing memory
205：GPS module
206：Network adapter
207：Radio transmitting device
208：Keyboard
209：Screen
210：Loudspeaker
30：Internal storing memory
31：Host computer system
32：SD card
33：CF cards
34：Embedded storage device
341：Embedded multi-media card
342：Embedded type multi-core piece encapsulates storage device
402：Connecting interface unit
404：Memory control circuit unit
406：Duplicative Nonvolatile memory module
410 (0)~410 (N), 410 (X), 410 (X+1), 410 (X+11), 410 (Y)：Entity erased cell
502：Memory management circuit
504：HPI
506：Memory interface
508：Buffer storage
510：Electric power management circuit
512：Error checking and correcting circuit
602：Information data area
604：Idle area
606：System area
608：Substitute area
LBA (0)~LBA (H)：Logical address
LZ (0)~LZ (M)：Logic region
810、820：Logical address-physical address mapping table
810a~810n, 820a~820n：Sub- logical address-physical address mapping table
508a：First area
508b：Second area
S1301：The first instruction is received, wherein the step of the first instruction corresponds to the data for being stored in the first logical address
S1303：Judge the operator scheme of corresponding duplicative Nonvolatile memory module for first operator scheme or second operator scheme The step of
S1305：It is non-from duplicative when the operator scheme of corresponding duplicative Nonvolatile memory module is first operator scheme The first sub- logical address-physical address mapping table is to slow among the sub- logical address of volatile ram module loading-physical address mapping table Rush in memory, wherein the first sub- logical address-physical address mapping table record has the step of the map information of corresponding first logical address Suddenly
S1307：It is non-from duplicative when the operator scheme of corresponding duplicative Nonvolatile memory module is second operator scheme The first logical address-physical address mapping table among volatile ram module loading logical address-physical address mapping table extremely buffers In memory, wherein the first logical address-physical address mapping table record has the map information of corresponding first logical address, wherein the One logical address-physical address mapping table includes the step of the first sub- logical address-physical address mapping table
Embodiment
In general, internal storing memory (also known as, memory storage system) includes duplicative Nonvolatile memory module and controller (also known as, control circuit unit).Usual internal storing memory is used together with host computer system, so that host computer system can write data Enter to internal storing memory or data are read from internal storing memory.
Fig. 1 is showing for host computer system according to an exemplary embodiment, internal storing memory and input/output (I/O) device It is intended to, and Fig. 2 is host computer system, internal storing memory and the input/output (I/O) according to another exemplary embodiment The schematic diagram of device.
Refer to Fig. 1 and Fig. 2, host computer system 11 generally comprise processor 111, random access memory (random access memory, RAM) 112, read-only storage (read only memory, ROM) 113 and data transmission interface 114.Processor 111, Random access memory 112, read-only storage 113 and data transmission interface 114 are all electrically connected to system bus (system bus) 110。
In this exemplary embodiment, host computer system 11 is electrically connected with by data transmission interface 114 and internal storing memory 10. For example, host computer system 11 can write data into internal storing memory 10 via data transmission interface 114 or be filled from memory storage Data are read in putting 10.In addition, host computer system 11 is electrically connected with by system bus 110 and I/O devices 12.For example, Output signal can be sent to I/O devices 12 via system bus 110 or receive input letter from I/O devices 12 by host computer system 11 Number.
In this exemplary embodiment, processor 111, random access memory 112, read-only storage 113 and data transmission interface 114 It is on the mainboard 20 for may be provided at host computer system 11.The number of data transmission interface 114 can be one or more.Pass through number According to coffret 114, mainboard 20 can be electrically connected to internal storing memory 10 via wired or wireless way.Memory storage fills Put 10 and can be for example Portable disk 201, memory card 202, solid state hard disc (Solid State Drive, SSD) 203 or wireless internal memories Storage device 204.Wireless internal storing memory 204 can be for example wireless near field communication (Near Field Communication Storage, NFC) internal storing memory, radio facsimile (WiFi) internal storing memory, bluetooth (Bluetooth) memory storage The memory storage based on various wireless communication technology such as device or low-power consumption bluetooth internal storing memory (for example, iBeacon) Device.In addition, mainboard 20 can also be electrically connected to global positioning system (Global Positioning by system bus 110 System, GPS) module 205, network adapter 206, radio transmitting device 207, keyboard 208, screen 209, loudspeaker 210 Etc. various I/O devices.For example, in an exemplary embodiment, mainboard 20 can pass through the access wireless internal memory of radio transmitting device 207 Storage device 204.
In an exemplary embodiment, mentioned host computer system is that substantially can coordinate with internal storing memory to store appointing for data Meaning system.Although in above-mentioned exemplary embodiment, host computer system is explained with computer system, however, Fig. 3 is basis The schematic diagram of host computer system and internal storing memory shown by another exemplary embodiment.Fig. 3 is refer to, in another exemplary embodiment In, host computer system 31 can also be digital camera, video camera, communicator, audio player, video player or flat board electricity The systems such as brain, and internal storing memory 30 can be its used SD card 32, CF cards 33 or embedded storage device 34 etc. Various nonvolatile memory storage device.Embedded storage device 34 include embedded multi-media card (embedded MMC, EMMC) 341 and/or embedded type multi-core piece encapsulation storage device (embedded Multi Chip Package, eMCP) 342 etc. The all types of embedded storage devices being directly electrically connected at memory modules on the substrate of host computer system.
Fig. 4 is the summary block diagram of the host computer system and internal storing memory according to an exemplary embodiment.
Fig. 4 is refer to, internal storing memory 10 includes connecting interface unit 402, memory control circuit unit 404 with that can make carbon copies Formula Nonvolatile memory module 406.
In this exemplary embodiment, connecting interface unit 402 is compatible with the advanced annex of sequence (Serial Advanced Technology Attachment, SATA) standard.However, it is necessary to be appreciated that, the invention is not restricted to this, connecting interface unit 402 can also It is to meet advanced annex (Parallel Advanced Technology Attachment, PATA) standard, Electrical and Electronic work arranged side by side SCTE (Institute of Electrical and Electronic Engineers, IEEE) 1394 standards, the connection of high-speed peripheral part Interface (Peripheral Component Interconnect Express, PCI Express) standard, USB (Universal Serial Bus, USB) standard, a ultrahigh speed generation (Ultra High Speed-I, UHS-I) interface standard, ultrahigh speed two generations (Ultra High Speed-II, UHS-II) interface standard, secure digital (Secure Digital, SD) interface standard, memory stick (Memory Stick, MS) interface standard, multi-chip package (Multi-Chip Package) interface standard, Multi Media Card (Multi Media Card, MMC) interface standard, built-in multimedia memory card (Embedded Multimedia Card, eMMC) interface standard, Common Flash Memory (Universal Flash Storage, UFS) interface standard, embedded type multi-core piece encapsulation (embedded Multi Chip Package, eMCP) interface standard, compact flash (Compact Flash, CF) interface standard, integrated driving electrical interface (Integrated Device Electronics, IDE) standard or other suitable standards.In this exemplary embodiment, connecting interface Unit 402 can be encapsulated in a chip with memory control circuit unit 404, or connecting interface unit 402 is to be laid in one Outside chip comprising memory control circuit unit.
Memory control circuit unit 404 to perform the multiple gates or control instruction with hardware pattern or firmware pattern implementation, And the write-in of data is carried out in duplicative Nonvolatile memory module 406 according to the instruction of host computer system 11, reads and smears Operated except waiting.
Duplicative Nonvolatile memory module 406 is electrically connected to memory control circuit unit 404, and to store main frame The data that system 11 is write.Duplicative Nonvolatile memory module 406 has entity erased cell 410 (0)~410 (N). For example, entity erased cell 410 (0)~410 (N) can belong to same internal memory crystal grain (die) or belong to different internal memory crystal grain. Each entity erased cell has multiple entity program units respectively, wherein belonging to the entity program of same entity erased cell Changing unit can be written independently and simultaneously be erased.However, it is necessary to be appreciated that, the invention is not restricted to this, each entity Erased cell is can be by 64 entity program units, 256 entity program units or other any entity program unit Formed.
In more detail, entity erased cell is the least unit erased.That is, each entity erased cell contain minimal amount it The memory cell being erased in the lump.Entity program unit is the minimum unit of sequencing.That is, entity program unit is write-in number According to minimum unit.Each entity program unit generally includes data bit area and redundant digit area.Data bit area includes multiple entities Access address to store the data of user, and redundant digit area to stocking system data (for example, control information with mistake more Code).In this exemplary embodiment, 8 entity access addresses can be included in the data bit area of each entity program unit, And the size of an entity access address is 512 bytes (byte).However, in other exemplary embodiments, in data bit area The more or less entity access addresses of number can be included, the present invention is not intended to limit the size and number of entity access address.Example Such as, in an exemplary embodiment, entity erased cell is physical blocks, and entity program unit is physical page or entity Sector, but the present invention is not limited.
In this exemplary embodiment, duplicative Nonvolatile memory module 406 be three rank memory cells (Trinary Level Cell, TLC) NAND-type flash memory module (that is, the flash memory module that 3 data bit can be stored in a memory cell).However, this hair Bright not limited to this, duplicative Nonvolatile memory module 406 also can be multistage memory cell (Multi Level Cell, MLC) NAND-type flash memory module (that is, the flash memory module that 2 data bit can be stored in a memory cell) or other there is identical characteristic Memory modules.
Fig. 5 is the summary block diagram of the memory control circuit unit according to an exemplary embodiment.
Refer to Fig. 5, memory control circuit unit 404 include memory management circuit 502, HPI 504 and memory interface 506, Buffer storage 508, electric power management circuit 510 and error checking and correcting circuit 512.
Memory management circuit 502 is controlling the overall operation of memory control circuit unit 404.Specifically, memory management electricity Road 502 has multiple control instructions, and when internal storing memory 10 operates, this little control instruction can be performed to enter line number According to write-in, read and the running such as erase.
In this exemplary embodiment, the control instruction of memory management circuit 502 is to carry out implementation with firmware pattern.For example, internal memory pipe Managing circuit 502 has microprocessor unit (not shown) and a read-only storage (not shown), and this little control instruction be by Imprinting is so far in read-only storage.When internal storing memory 10 operates, this little control instruction can be performed by microprocessor unit To carry out the write-in of data, read and the running such as erase.
Fig. 6 and Fig. 7 is the example schematic of the management entity erased cell according to an exemplary embodiment.
It will be appreciated that when being described herein the running of the entity erased cell of duplicative Nonvolatile memory module 406, " to carry Take ", " packet ", " division ", the word such as " association " carrys out application entity erased cell is concept in logic.That is, it can make carbon copies The physical location of the entity erased cell of formula Nonvolatile memory module is not changed, but non-volatile to duplicative in logic The entity erased cell of memory modules is operated.
Fig. 6 is refer to, memory control circuit unit 404 (or memory management circuit 502) can be by entity erased cell 410 (0)~410 (N) Logically it is grouped into data field 602, idle area 604, system area 606 and substitution area 608.
The entity erased cell for logically belonging to data field 602 and idle area 604 is to store the number for coming from host computer system 11 According to.Specifically, the entity erased cell of data field 602 is regarded as having stored the entity erased cell of data, and idle area 604 entity erased cell is the entity erased cell to replacement data area 602.Connect that is, working as from host computer system 11 When receiving write instruction and the data to be write, memory management circuit 502, which can use, to be extracted entity from idle area 604 and erases list Member writes data, with the entity erased cell in replacement data area 602.
The entity erased cell for logically belonging to system area 606 is to record system data.For example, system data report include on The manufacturer of duplicative Nonvolatile memory module and model, duplicative Nonvolatile memory module entity erased cell number, Entity program unit number of each entity erased cell etc..
It is to be used for bad entity erased cell substitution program to logically belong to substitute the entity erased cell in area 608, with replacing damaged Entity erased cell.Specifically, if still having normal entity erased cell and data field 602 in substitution area 608 The damage of entity erased cell when, memory management circuit 502 can extract normal entity erased cell and comes more from substitution area 608 Change the entity erased cell of damage.
Particularly, the quantity of data field 602, idle area 604, system area 606 and the entity erased cell in substitution area 608 can root It is different according to different memory standards.Further, it is necessary to be appreciated that, in the running of internal storing memory 10, entity is smeared Except unit is associated to data field 602, idle area 604, system area 606 with substituting the packet relation in area 608 dynamically to change. For example, when the entity erased cell damage in idle area 604 is substituted the entity erased cell substitution in area 608, then originally The entity erased cell in substitution area 608 can be associated to idle area 604.
Fig. 7 is refer to, memory control circuit unit 404 (or memory management circuit 502) can configure logical address LBA (0)~LBA (H) To map the entity erased cell of data field 602, each of which logical address has multiple logic units to map corresponding entity The entity program unit of erased cell.Also, when 11 logical address to be write data to of host computer system or renewal are stored in logic During data in address, memory control circuit unit 404 (or memory management circuit 502) can extract one from idle area 604 Entity erased cell writes data as start entity erased cell, with the entity erased cell for data field 602 of rotating.Also, When this is fully written as the entity erased cell of start entity erased cell, memory control circuit unit 404 (or memory management electricity Road 502) empty entity erased cell can be extracted from idle area 504 again as start entity erased cell, to continue to write to correspondingly Come from updating the data for the write instruction of host computer system 11.In addition, when the number of available entity erased cell in idle area 604 When mesh is less than default value, memory control circuit unit 404 (or memory management circuit 502) can perform valid data consolidation procedure (also known as For collecting garbage (garbage collecting) program) valid data in data field 602 are arranged, by nothing in data field 602 The entity erased cell of storage valid data associates to idle area 604 again.
In order to identify the data of each logical address are stored in which entity erased cell, in this exemplary embodiment, internal memory control Circuit unit 404 (or memory management circuit 502) processed can record the mapping between logical address and entity erased cell.For example, In this exemplary embodiment, memory control circuit unit 404 (or memory management circuit 502) can be in duplicative be non-volatile Stored logic address-physical address mapping table records the entity erased cell that each logical address is mapped in storing module 406.When Memory control circuit unit 404 (or memory management circuit 502) can add logical address-physical address mapping table during data to be accessed Buffer storage 508 is loaded onto to safeguard, and write or read data according to logical address-physical address mapping table.
It is noted that record the mapping relations of all logical addresses because the finite capacity of buffer storage 508 can not store Mapping table, therefore, in this exemplary embodiment, memory control circuit unit 404 (or memory management circuit 502) will can patrol Collect address LBA (0)~LBA (H) and be grouped into multiple logic region LZ (0)~LZ (M), and configure one for each logic region and patrol Collect address-physical address mapping table.Particularly, when memory control circuit unit 404 (or memory management circuit 502) is intended to update certain During the mapping of individual logical address, corresponding to logical address-physical address mapping table of the logic region belonging to this logical address can be loaded It is updated to buffer storage 508.
In another exemplary embodiment of the present invention, the control instruction of memory management circuit 502 can also program code pattern be stored in The specific region of duplicative Nonvolatile memory module 406 is (for example, be exclusively used in the system of storage system data in memory modules Area) in.In addition, memory management circuit 502 have microprocessor unit (not shown), read-only storage (not shown) and Random access memory (not shown).Particularly, this read-only storage has driving code, and works as memory control circuit unit 404 When being enabled, microprocessor unit can first carry out this driving code section and will be stored in duplicative Nonvolatile memory module 406 Control instruction be loaded onto in the random access memory of memory management circuit 502.Afterwards, microprocessor unit can operate this little control System instruction is to carry out the write-in of data, read and the running such as erase.
In addition, in another exemplary embodiment of the present invention, the control instruction of memory management circuit 502 can also a hardware pattern Implementation.Read for example, memory management circuit 502 includes microcontroller, memory cell management circuit, internal memory write circuit, internal memory Circuit, internal memory are erased circuit and data processing circuit.It is memory cell management circuit, internal memory write circuit, internal memory reading circuit, interior Deposit circuit of erasing and be electrically connected to microcontroller with data processing circuit.Wherein, memory cell management circuit can be made carbon copies to manage The entity erased cell of formula Nonvolatile memory module 406；Internal memory write circuit is to duplicative Nonvolatile memory module 406 assign write instruction to write data into duplicative Nonvolatile memory module 406；Internal memory reading circuit is to pair can Manifolding formula Nonvolatile memory module 406 assigns reading instruction to read data from duplicative Nonvolatile memory module 406； Internal memory erases circuit to assign instruction of erasing to duplicative Nonvolatile memory module 406 so that data are non-easily from duplicative Erased in the property lost memory modules 406；And data processing circuit is intended to write to duplicative Nonvolatile memory module 406 to handle Data and the data that are read from duplicative Nonvolatile memory module 406.
Referring again to Fig. 5, HPI 504 is electrically connected to memory management circuit 502 and is electrically connected to connection to connect Mouthful unit 402, to receive and identify instruction and data that host computer system 11 transmitted.That is, host computer system 11 is transmitted Instruction and data memory management circuit 502 can be sent to by HPI 504.In this exemplary embodiment, HPI 504 are compatible with SATA standard.However, it is necessary to be appreciated that the invention is not restricted to this, HPI 504 can also be compatible Connect in PATA standards, the standards of IEEE 1394, PCI Express standards, USB standard, UHS-I interface standards, UHS-II Mouth standard, SD standards, MS standards, MMC standards, CF standards, IDE standards or other suitable data transmission standards.
Memory interface 506 is electrically connected to memory management circuit 502 and to access duplicative Nonvolatile memory module 406.It can be converted to that is, being intended to write to the data of duplicative Nonvolatile memory module 406 via memory interface 506 The receptible form of the institute of duplicative Nonvolatile memory module 406.
Buffer storage 508 is electrically connected to memory management circuit 502 and is configured to temporarily store come from the temporary of host computer system 11 Data and the data for instructing or coming from duplicative Nonvolatile memory module 406.
Electric power management circuit 510 is electrically connected to memory management circuit 502 and to control the power supply of internal storing memory 10.
Error checking is electrically connected to memory management circuit 502 and to perform error checking and correction with correcting circuit 512 Program is to ensure the correctness of data.For example, when memory management circuit 502 receives write instruction from host computer system 11, Error checking can be error checking and correcting code (Error corresponding to the data generation of this corresponding write instruction with correcting circuit 512 Checking and Correcting Code, ECC Code), and memory management circuit 502 can be by the number of this corresponding write instruction Write according to corresponding error checking and correcting code into duplicative Nonvolatile memory module 406.Afterwards, memory management is worked as Circuit 502 can read error checking corresponding to this data simultaneously when data are read from duplicative Nonvolatile memory module 406 With correcting code, and error checking and correcting circuit 512 can perform mistake according to this error checking and correcting code to the data read Flase drop is looked into and correction program.
It is noted that in this exemplary embodiment, memory control circuit unit 404 (or memory management circuit 502) can incite somebody to action Logical address LBA (0)~LBA (H) is grouped into multiple logic region LZ (0)~LZ (M), and configures one for each logic region Logical address-physical address mapping table.Particularly, memory control circuit unit 404 (or memory management circuit 502) can also be by one Individual logical address-physical address mapping table is divided into more sub- logical address-physical address mapping tables.
Fig. 8 A and Fig. 8 B are the corresponding more height of logical address-physical address mapping table according to an exemplary embodiment The example schematic of logical address-physical address mapping table.
Fig. 8 A are refer to, exemplified by corresponding to logic region LZ (0) logical address-physical address mapping table 810, logical address Each logical address LBA (0)~mapping between LBA (Z) and multiple physical address is stored in-physical address mapping table 810 to believe Breath.Wherein, memory control circuit unit 404 (or memory management circuit 502) can also be by logical address-physical address mapping table 810 are divided into more sub- logical address-physical address mapping table 810a~810n.
In addition, refer to Fig. 8 B, exemplified by corresponding to logic region LZ (1) logical address-physical address mapping table 820, patrol Each logical address LBA (Z+1)~between LBA (P) and multiple physical address is stored in volume address-physical address mapping table 820 Map information.Wherein, memory control circuit unit 404 (or memory management circuit 502) can also be by logical address-physical address Mapping table 810 is divided into more sub- logical address-physical address mapping table 820a~820n.Implement in Fig. 8 A and Fig. 8 B example In example, each sub- logical address-physical address mapping table has the map information of 11 logical addresses and physical address respectively.So And it is noted that the present invention is not used to limit the map information that each sub- logical address-physical address mapping table can store Number.In addition, in other exemplary embodiments, a sub- logical address in same logical address-physical address mapping table- The size of physical address mapping table can be differently configured from another sub- logical address in same logical address-physical address mapping table The size of-physical address mapping table.That is, the size of a sub- logical address-physical address mapping table is less than a logic The size of address-physical address mapping table, but the size of sub- logical address-physical address mapping table can be different.
In addition, when memory control circuit unit 404 (or memory management circuit 502) needs the map information of some logical address, Memory control circuit unit 404 (or memory management circuit 502) can be current according to duplicative Nonvolatile memory module 406 Operator scheme, selectively load sub- logical address-physical address mapping table to buffer storage belonging to this corresponding logical address 508, or the logic region belonging to this corresponding logical address of loading logical address-physical address mapping table to buffer storage 508 To be read out.For example, when the current operator scheme of duplicative Nonvolatile memory module 406 is first operator scheme, Memory control circuit unit 404 (or memory management circuit 502) can load sub- logical address-entity belonging to this corresponding logical address Address mapping table is to buffer storage 508.When the current operator scheme of duplicative Nonvolatile memory module 406 is the second operation During pattern, memory control circuit unit 404 (or memory management circuit 502) can load the logic area belonging to this corresponding logical address The logical address in domain-physical address mapping table is to buffer storage 508.It is noted that in one example of the present invention embodiment, Operator scheme of the duplicative Nonvolatile memory module 406 after upper electricity every time is to be defaulted as first operator scheme.
[the first exemplary embodiment]
Fig. 9 A~Fig. 9 B are the schematic diagrames of the internal memory read method according to the first example.Herein it should be noted that, in this hair In bright exemplary embodiment, memory control circuit unit 404 (or memory management circuit 502) can 508 foundation in buffer storage One management table (not shown).Wherein, management table is loaded on buffering and deposited for recording a certain sub- logical address-physical address mapping table Reservoir and the number (hereinafter referred to as, access times) used in memory control circuit unit 404 (or memory management circuit 502).Letter Yan Zhi, management table are used for the use course for recording a certain sub- logical address-physical address mapping table.
Fig. 9 A are refer to, in Fig. 9 A exemplary embodiment, memory control circuit unit 404 (or memory management circuit 502) meeting Buffer storage 508 is divided into the first mapping table working area 508a and the second mapping table working area 508b, wherein the first mapping Table working area 508a is used for the temporary logical address-physical address mapping loaded from duplicative Nonvolatile memory module 406 Table, and the second mapping table working area 508b is used for the temporary son loaded from duplicative Nonvolatile memory module 406 logically Location-physical address mapping table.
Assuming that host computer system 11 assigns reading instruction (below with reference to for second instructs) to indicate that reading is stored in logical address Data in LBA (0).Memory control circuit unit 404 (or memory management circuit 502) from host computer system 11 receive second instruction after, Memory control circuit unit 404 (or memory management circuit 502) can judge the behaviour of current duplicative Nonvolatile memory module 406 Operation mode is first operator scheme or second operator scheme.For example, memory control circuit unit 404 (or memory management circuit 502) It can be judged whether once to use sub- logical address-physical address of the map information with logical address LBA (0) to reflect according to management table Firing table, to judge the operator scheme of current duplicative Nonvolatile memory module 406 for first operator scheme or the second operation mould Formula.
Because current duplicative Nonvolatile memory module 406 is in the state of just upper electricity, and there is not pass in management table yet In the use course of logical address LBA (0) sub- logical address-physical address mapping table, therefore memory control circuit unit 404 (or it is interior Deposit management circuit 502) operator scheme of current duplicative Nonvolatile memory module 406 can be judged for first operator scheme.It is interior The can be corresponded to from the loading of duplicative Nonvolatile memory module 406 by depositing control circuit unit 404 (or memory management circuit 502) Sub- logical address-physical address mapping table 810a (below with reference to for the second sub- logical address-physical address mapping table) of two instructions are extremely In second mapping table working area 508b of buffer storage 508.Wherein, sub- logical address-physical address mapping table 810a records There is counterlogic address LBA (0) map information.Particularly, in this example, sub- logical address-physical address mapping table 810a Only include such as logical address LBA (0)~LBA (10) map information.However, in another example of the present invention embodiment, son Logical address-physical address mapping table 810a size can be 512Bytes or other sizes, and the present invention is not to sub- logic Address-physical address mapping table 810a size is limited.
Afterwards, memory control circuit unit 404 (or memory management circuit 502) can be according to sub- logical address-physical address mapping table 810a performs the second instruction.Specifically, memory control circuit unit 404 (or memory management circuit 502) can use be loaded onto The sub- logical address of buffer storage 508-physical address mapping table 810a, from mapping logic address LBA (0) entity program Data are read in unit.As shown in Figure 9 A, because the second instruction is to read the data in logical address LBA (0), Memory control circuit unit 404 (or memory management circuit 502) can judge to patrol according to sub- logical address-physical address mapping table 810a It is to map to entity erased cell 410 (2) to collect address LBA (0).Memory control circuit unit 404 (or memory management circuit 502) meeting The data of corresponding entity program unit in entity erased cell 410 (2) are read according to the second instruction.It is noted that above-mentioned Two instructions are to be instructed with reading as example, but the present invention is not restricted to the instruction type of the second instruction.
In addition, in the exemplary embodiment of invention, the son for being temporarily stored into the second mapping table working area 508b of buffer storage 508 is patrolled Collecting address-physical address mapping table 810a can only be only used once.That is, when (or the internal memory pipe of memory control circuit unit 404 Manage circuit 502) load sub- logical address-physical address mapping table 810a and according to sub- logical address-physical address mapping table 810a After the data for reading corresponding second instruction, memory control circuit unit 404 (or memory management circuit 502), which can erase, is temporarily stored into buffering The sub- logical address of memory 508-physical address mapping table 810a.
Particularly, mapped in memory control circuit unit 404 (or memory management circuit 502) according to sub- logical address-physical address After table 810a performs the second instruction, memory control circuit unit 404 (or memory management circuit 502) can also correspond in more new management table Sub- logical address-physical address mapping table 810a use course.For example, memory control circuit unit 404 (or memory management circuit 502) field can be increased newly in table is managed, include logical address to record sub- logical address-physical address mapping table 810a LBA (0)~LBA (10), and sub- logical address-physical address mapping table 810a access times are recorded as 1.
Assuming that Fig. 9 B are hookup 9A.Afterwards, Fig. 9 B be refer to, it is assumed that host computer system 11 assigns the first instruction afterwards, its In this first instruction correspond to the data for being stored in logical address LBA (Z+1) (below with reference to for the first logical address).Assuming that the One instruction is stored in the reading instruction of the data in logical address LBA (Z+1) for instruction reading.Memory control circuit unit 404 (or Memory management circuit 502) after host computer system 11 receives the first instruction, memory control circuit unit 404 (or memory management circuit 502) The operator scheme of current duplicative Nonvolatile memory module 406 can be judged for first operator scheme or second operator scheme.It is interior Depositing control circuit unit 404 (or memory management circuit 502) can judge whether once to use and have logical address according to management table The sub- logical address of LBA (Z+1) map information-physical address mapping table 820a is (below with reference to for first sub- logical address-entity Address mapping table), to judge the operator scheme of current duplicative Nonvolatile memory module 406 for first operator scheme or second Operator scheme.
Due to only storing sub- logical address-physical address mapping table 810a use course in management table at present, and sub- logical address- Physical address mapping table 810a is distinct from sub- logical address-physical address mapping table corresponding to logical address LBA (Z+1) 820a, therefore memory control circuit unit 404 (or memory management circuit 502) can judge current duplicative Nonvolatile memory module 406 operator scheme is first operator scheme.When the operator scheme of corresponding duplicative Nonvolatile memory module 406 is the first behaviour During operation mode, memory control circuit unit 404 (or memory management circuit 502) can be from duplicative Nonvolatile memory module 406 Loading is kept in corresponding to the first sub- logical address-physical address mapping table 820a instructed to the second mapping table of buffer storage 508 In area 508b.Wherein, the mapping that sub- logical address-physical address mapping table 820a records have counterlogic address LBA (Z+1) is believed Breath.In this example, sub- logical address-physical address mapping table 820a only includes such as logical address LBA (Z+1)~LBA (Z+11) Map information.However, in another example of the present invention embodiment, sub- logical address-physical address mapping table 810a size Can be 512Bytes or other sizes, the present invention is not limited sub- logical address-physical address mapping table 810a size System.
Afterwards, memory control circuit unit 404 (or memory management circuit 502) can use the son for being loaded onto buffer storage 508 Logical address-physical address mapping table 820a, data are read from mapping logic address LBA (Z+1) entity program unit. Specifically, as shown in Figure 9 B, because the first instruction is to read the data in logical address LBA (Z+1), internal memory Control circuit unit 404 (or memory management circuit 502) can according to sub- logical address-physical address mapping table 820a decision logics Location LBA (Z+1) is to map to entity erased cell 410 (X).Memory control circuit unit 404 (or memory management circuit 502) can root The data of corresponding entity program unit in entity erased cell 410 (X) are read according to the first instruction.
When memory control circuit unit 404 (or memory management circuit 502) loads sub- logical address-physical address mapping table 820a simultaneously After the data that corresponding first instruction is read according to sub- logical address-physical address mapping table 820a, memory control circuit unit 404 (or Memory management circuit 502) can erase is temporarily stored into sub- logical address-physical address mapping table 820a of buffer storage 508.
In addition, in memory control circuit unit 404 (or memory management circuit 502) according to sub- logical address-physical address mapping table After 820a performs the first instruction, memory control circuit unit 404 (or memory management circuit 502) can also correspond to son in more new management table Logical address-physical address mapping table 820a access times.For example, memory control circuit unit 404 (or memory management circuit 502) field can be increased newly in table is managed, include logical address to record sub- logical address-physical address mapping table 820a LBA (Z+1)~LBA (Z+11), and sub- logical address-physical address mapping table 820a access times are recorded as 1.
Based on above-mentioned, in the first exemplary embodiment of the present invention, due to (or the memory management circuit of memory control circuit unit 404 502) judge that memory control circuit unit 404 is (or interior according to management table before sub- logical address-physical address mapping table 820a is loaded Deposit management circuit 502) do not used sub- logical address-physical address of the map information with logical address LBA (Z+1) to map Table 820a, memory control circuit unit 404 (or memory management circuit 502) can reasonably judge that sub- logical address-physical address reflects The map information in logical address-physical address mapping table 820 corresponding to firing table 820a may be less often used, therefore can be made With the less sub- logical address of first mode load capacity-physical address mapping table 820a, use avoid host computer system 11 perform with The wave for the bandwidth that larger logical address-physical address mapping table is repeatedly loaded during machine-readable extract operation and causes internal storing memory Take.
[the second exemplary embodiment]
Figure 10 A~Figure 10 B are the schematic diagrames of the internal memory read method according to the second example.Wherein Figure 10 A example is implemented Such as duplicative Nonvolatile memory module 406 loads sub- logical address-reality according to the second instruction after the power-up in above-mentioned Fig. 9 A Body address mapping table 810a, and record is gone through corresponding to sub- logical address-physical address mapping table 810a use in management table The flow of journey, therefore do not repeat herein.Assuming that after Figure 10 A, Figure 10 B are refer to, when the first finger that host computer system 11 is assigned Order corresponds to be stored in the data of logical address LBA (1) (being also referenced as below, the first logical address), and the first instruction is finger Show the reading instruction for the data that reading is stored in logical address LBA (1).Memory control circuit unit 404 (or memory management circuit 502) after host computer system 11 receives the first instruction, memory control circuit unit 404 (or memory management circuit 502) can judge at present The operator scheme of duplicative Nonvolatile memory module 406 is first operator scheme or second operator scheme.Wherein, internal memory control Circuit unit 404 (or memory management circuit 502) processed can judge whether once to use with logical address LBA (1) according to management table The sub- logical address of map information-physical address mapping table 810a (is also referenced as, the first sub- logical address-physical address mapping below Table), to judge the operator scheme of current duplicative Nonvolatile memory module 406 for first operator scheme or second operator scheme.
Due to there is the use course for storing sub- logical address-physical address mapping table 810a in management table at present, and sub- logical address- Physical address mapping table 810a is the same as sub- logical address-physical address mapping table 810a corresponding to logical address LBA (1), Therefore memory control circuit unit 404 (or memory management circuit 502) can judge current duplicative Nonvolatile memory module 406 Operator scheme is second operator scheme.When the operator scheme of corresponding duplicative Nonvolatile memory module 406 is the second operation mould During formula, memory control circuit unit 404 (or memory management circuit 502) can load from duplicative Nonvolatile memory module 406 Corresponding to the first mapping table working area 508a of the first logical address-physical address mapping table 810 instructed to buffer storage 508 In.Particularly, logical address-physical address mapping table 810 includes such as logical address LBA (0)~LBA (Z) (that is, logic region LZ (0)) map information.That is, logical address-physical address mapping table 810 includes sub- logical address-physical address mapping Table 810a map information, sub- logical address-physical address mapping table 810a are the sons of logical address-physical address mapping table 810 Set.It is noted that in one example of the present invention embodiment, the size of logical address-physical address mapping table 810 can be with It is 16KBytes or other sizes, the present invention is not limited to the size of logical address-physical address mapping table 810.
Afterwards, memory control circuit unit 404 (or memory management circuit 502) can use and be loaded onto patrolling for buffer storage 508 Address-physical address mapping table 810 is collected, data are read from mapping logic address LBA (1) entity program unit.It is specific next Say, because the first instruction is to read the data in logical address LBA (1), memory control circuit unit 404 (or internal memory Management circuit 502) can be to map to entity to erase list according to the decision logic address LBA (1) of logical address-physical address mapping table 810 First 410 (1).Memory control circuit unit 404 (or memory management circuit 502), which can read instruction according to first and read entity, erase list Data in first 410 (1) in corresponding entity program unit.
Based on above-mentioned, in the second exemplary embodiment of the present invention, due to (or the memory management circuit of memory control circuit unit 404 502) judge that memory control circuit unit 404 (or memory management circuit 502) once used and has logical address according to management table The sub- logical address of LBA (1) map information-physical address mapping table 810a, memory control circuit unit 404 (or memory management electricity Road 502) it can reasonably judge logical address-physical address mapping table corresponding to sub- logical address-physical address mapping table 810a Map information future in 810 has an opportunity to be used again very much, therefore can use the larger logical address of second operator scheme load capacity - physical address mapping table 810, in favor of the access for the map information in logical address-physical address mapping table 810 afterwards.
[the 3rd exemplary embodiment]
Figure 11 A~Figure 11 B are the schematic diagrames of the internal memory read method according to the 3rd example.Wherein Figure 11 A example is implemented Such as sub- logical address-physical address mapping table 810a and the record pair in table is managed are loaded according to the second instruction in above-mentioned Fig. 9 A Ying Yuzi logical addresses-physical address mapping table 810a the flow using course, therefore do not repeat herein.Assuming that in Figure 11 A Exemplary embodiment after, the first instruction that host computer system 11 is assigned corresponds to be stored in logical address LBA (Z) (also to be referred to below For the first logical address) data, and the first instruction refers to for the reading of data that instruction reading is stored in logical address LBA (Z) Order.Memory control circuit unit 404 (or memory management circuit 502) is after host computer system 11 receives the first instruction, Memory control electricity Road unit 404 (or memory management circuit 502) can judge the operator scheme of current duplicative Nonvolatile memory module 406 for One operator scheme or second operator scheme.Memory control circuit unit 404 (or memory management circuit 502) can judge according to management table Sub- logical address-physical address mapping table 810n of the map information with logical address LBA (Z) whether was once used (also to join below Examine as the first sub- logical address-physical address mapping table), to judge the operation of current duplicative Nonvolatile memory module 406 Pattern is first operator scheme or second operator scheme.
Due to only storing sub- logical address-physical address mapping table 810a use course in management table at present, and sub- logical address - physical address mapping table 810a is to be different from sub- logical address-physical address mapping table 810n corresponding to logical address LBA (Z), Therefore memory control circuit unit 404 (or memory management circuit 502) can judge current duplicative Nonvolatile memory module 406 Operator scheme is first operator scheme.It is to be noted that now memory control circuit unit 404 (or memory management circuit 502) Logical address-physical address mapping table of the logic region LZ (0) corresponding to sub- logical address-physical address mapping table 810a can be judged The sub- logic corresponding to logical address LBA (Z) is included in 810 (being also referenced as below, the first logical address-physical address mapping table) Address-physical address mapping table 810n, so when memory control circuit unit 404 (or memory management circuit 502) can be changed to judge mesh The operator scheme of preceding duplicative Nonvolatile memory module 406 is second operator scheme.
When the operator scheme of corresponding duplicative Nonvolatile memory module 406 is second operator scheme, memory control circuit unit 404 (or memory management circuits 502) can correspond to the first instruction from the loading of duplicative Nonvolatile memory module 406 logically Location-physical address mapping table 810 is into the first mapping table working area 508a of buffer storage 508.Particularly, logical address- Physical address mapping table 810 includes such as logical address LBA (0)~LBA (Z) (that is, logic region LZ (0)) map information. That is logical address-physical address mapping table 810 includes sub- logical address-physical address mapping table 810n map information, Sub- logical address-physical address mapping table 810n is the subclass of logical address-physical address mapping table 810.It is noted that In one example of the present invention embodiment, the size of logical address-physical address mapping table 810 can be 16KBytes or others Size, the present invention are not limited to the size of logical address-physical address mapping table 810.
Based on above-mentioned, in the 3rd exemplary embodiment of the present invention, due to (or the memory management circuit of memory control circuit unit 404 502) can judge the logical address LBA (Z) corresponding to the first instruction be with sub- logical address-physical address mapping table 810a corresponding to Logical address LBA (0)~LBA (10) belong to same logic region LZ (0), (or the memory management of memory control circuit unit 404 Circuit 502) it can reasonably judge map information in counterlogic region LZ (0) logical address-physical address mapping table 810 Future has an opportunity to be used again very much, therefore can use the larger logical address-physical address mapping table of second operator scheme load capacity 810, in favor of the access for the map information in logical address-physical address mapping table 810 afterwards.
[the 4th exemplary embodiment]
Figure 12 A~Figure 12 B are the schematic diagrames of the internal memory read method according to the 4th example.It refer to Figure 12 A, it is assumed that interior Control circuit unit 404 (or memory management circuit 502) is deposited from the load logic address of duplicative Nonvolatile memory module 406-reality Body address mapping table 810 (below with reference to for the second logical address-physical address mapping table) to buffer storage 508 the first mapping In the 508a of table working area, and memory control circuit unit 404 (or memory management circuit 502) is according to logical address-physical address Mapping table 810 performs one the 3rd instruction.For example, the 3rd instruction is the data in instruction reading logical address LBA (0).
Then, Figure 12 B be refer to, it is assumed that patrolled after Figure 12 A when the first instruction that host computer system 10 is assigned corresponds to be stored in Address LBA (Z+11) (being also referenced as below, the first logical address) data are collected, and the first instruction is stored in for instruction reading and patrolled Collect the reading instruction of the data in address LBA (Z+11).Memory control circuit unit 404 (or memory management circuit 502) is from main frame After system 11 receives the first instruction, memory control circuit unit 404 (or memory management circuit 502) can judge that current duplicative is non- The operator scheme of volatile ram module 406 is first operator scheme or second operator scheme.In this exemplary embodiment, internal memory Control circuit unit 404 (or memory management circuit 502) can judge the logical address LBA (Z+11) of corresponding 3rd instruction logically Location-physical address mapping table 820 whether there is in the first mapping table working area 508a of buffer storage 508.
Now, memory control circuit unit 404 (or memory management circuit 502) can judge the first mapping table of buffer storage 508 Only there are logical address-physical address mapping table 810, and logical address-physical address mapping table 810 at present in the 508a of working area It is distinct from the logical address LBA (Z+11) of corresponding 3rd instruction logical address-physical address mapping table 820.Now, internal memory Control circuit unit 404 (or memory management circuit 502) can judge the operation mould of current duplicative Nonvolatile memory module 406 Formula is first operator scheme, and the sub- logical address-physical address for loading the logical address LBA (Z+11) of corresponding 3rd instruction reflects Firing table 820a.
Particularly, it is assumed that one the 4th instruction is assigned after host computer system 11, the map information of wherein this 4th instruction can buffer When being found in logical address-physical address mapping table 810 in memory 508, then (or the internal memory pipe of memory control circuit unit 404 Reason circuit 502) the operator scheme first operator scheme or that judges current duplicative Nonvolatile memory module 406 can not had to Two operator schemes, memory control circuit unit 404 (or memory management circuit 502) can be directly according in buffer storage 508 Logical address-physical address mapping table 810 performs the 4th instruction.
Based on above-mentioned, in the 4th exemplary embodiment of the present invention, when performing an instruction, memory control circuit unit 404 (or Memory management circuit 502) can also be by judging whether to have in buffer storage 508 logical address of this corresponding instruction-physically Whether location mapping table is first operator scheme to judge the operator scheme of current duplicative Nonvolatile memory module 406, with certainly It is fixed whether to load corresponding sub- logical address-physical address mapping table into buffer storage 508.
It is noted that first operator scheme is, for example, random read operation pattern, random writing operator scheme or collecting garbage behaviour Operation mode.Random read operation pattern represents host computer system 11 and duplicative Nonvolatile memory module 406 is continuously assigned It is multiple to read instruction to perform multiple read operations respectively, divided wherein corresponding to the map information used needed for each read operation It is stored in scatteredly in multiple different logical addresses-physical address mapping tables.Memory control circuit unit 404 (or memory management electricity Road 502) for example can according to corresponding to being distinguished above-mentioned multiple read operations logical address, judge the mapping of this little logical address Information is dispersedly stored in multiple different logical addresses-physical address mapping tables, and then judges that duplicative is non-volatile interior The current operator scheme of storing module 406 is random read operation pattern.Now, in order to avoid repeatedly load it is larger logically Location-physical address mapping table causes the waste of bandwidth into buffer storage 508, under random read operation pattern, internal memory control Circuit unit 404 (or memory management circuit 502) processed can load the less sub- logical address-physical address mapping table of size to buffering Memory 508 is read out.
Random writing operator scheme represents host computer system 11 and assigns multiple write-ins to duplicative Nonvolatile memory module 406 Instruction is dispersedly stored with performing multiple write operations respectively wherein corresponding to the map information used needed for each write operation In multiple different logical addresses-physical address mapping tables.Memory control circuit unit 404 (or memory management circuit 502) example As can according to corresponding to being distinguished above-mentioned multiple write operations logical address, judge that the map information of this little logical address is divided It is stored in scatteredly in multiple different logical addresses-physical address mapping tables, and then judges duplicative Nonvolatile memory module 406 current operator schemes are random writing operator scheme.Now, in order to avoid repeatedly loading larger logical address-entity Address mapping table causes the waste of bandwidth into buffer storage 508, under random writing operator scheme, memory control circuit Unit 404 (or memory management circuit 502) can load the less sub- logical address-physical address mapping table to buffer storage of size 508。
The operator scheme of selection recovery block represents (or the memory management circuit of memory control circuit unit 404 in collecting garbage program 502) it is carrying out being loaded with the recovery block of valid data in valid data consolidation procedure, particularly valid data consolidation procedure The process of map information.Specifically, in valid data consolidation procedure, because moving for valid data must load and update respectively The map information of individual valid data, and this little map information also may respectively be stored in multiple different logical addresses-physically In the mapping table of location.Therefore, when the map information of memory control circuit unit 404 (or memory management circuit 502) loading valid data When, memory control circuit unit 404 (or memory management circuit 502) can judge that the map information of valid data is stored in by scattered In different logical addresses-physical address mapping table, and then judge the current operation mould of duplicative Nonvolatile memory module 406 Formula is the operator scheme of selection recovery block in collecting garbage program.In order to avoid repeatedly loading larger logical address-physically Location mapping table causes the waste of bandwidth into buffer storage 508, the operation mould of selection recovery block in collecting garbage program Under formula, memory control circuit unit 404 (or memory management circuit 502) can load the less sub- logical address-physical address of size Mapping table is to buffer storage 508.
In addition, second operator scheme is, for example, continuous read mode, is continuously written into operator scheme, is right in collecting garbage program The operator scheme or bring down stocks operator scheme that purpose block is write.
Continuous read mode represent host computer system 11 duplicative Nonvolatile memory module 406 is continuously being assigned it is multiple Instruction is read to perform multiple read operations respectively, the map information wherein used needed for this little read operation is stored successively In same logical address-physical address mapping table.Memory control circuit unit 404 (or memory management circuit 502) for example can be with The logical address according to corresponding to being distinguished above-mentioned multiple read operations, judge that the map information of this little logical address is continuously stored up Exist in identical logical address-physical address mapping table, and then judge the current behaviour of duplicative Nonvolatile memory module 406 Operation mode is continuous read mode.Now, under continuous read mode, memory control circuit unit 404 (or internal memory Management circuit 502) the larger logical address of size-physical address mapping table can be loaded it is read out to buffer storage 508.
It is continuously written into operation and represents host computer system 11 and multiple write-ins is continuously assigned to duplicative Nonvolatile memory module 406 To perform multiple write operations respectively, the map information wherein used needed for this little write operation is stored successively same for instruction In individual logical address-physical address mapping table.Memory control circuit unit 404 (or memory management circuit 502) for example can basis Above-mentioned multiple write operations distinguish corresponding to logical address, judge that the map information of this little logical address is stored successively In identical logical address-physical address mapping table, and then judge the current operation mould of duplicative Nonvolatile memory module 406 Formula is to be continuously written into operator scheme.Now, in the case where being continuously written into operator scheme, memory control circuit unit 404 (or memory management Circuit 502) the larger logical address of size-physical address mapping table can be loaded it is read out to buffer storage 508.
The operator scheme write in collecting garbage program to purpose block represents (or the memory management of memory control circuit unit 404 Circuit 502) just the valid data collected are being write into the block of a mesh.Write by the valid data collected to purpose area The running of block is similar to be carried out above-mentioned being continuously written into operation to purpose block.In collecting garbage program, due to multiple significant figures According to map information may be stored successively in one logical address-physical address mapping table, therefore memory control circuit unit 404 (or memory management circuits 502) for example can be according to corresponding to being distinguished the multiple write operations carried out to purpose block logically Location, judging the map information of this little logical address may be stored successively in identical logical address-physical address mapping table, And then purpose block is carried out in judging the current operator scheme of duplicative Nonvolatile memory module 406 for collecting garbage program The operator scheme of write-in.Now, under the operator scheme write in collecting garbage program to purpose block, Memory control electricity Road unit 404 (or memory management circuit 502) can load the larger logical address of size-physical address mapping table to buffer storage 508 are read out.
Bring down stocks operator scheme and represent memory control circuit unit 404 (or memory management circuit 502) by buffer storage 508 Multiple temporal datas write into duplicative Nonvolatile memory module 406.When operation is brought down stocks in execution, due to internal memory control Circuit unit 404 (or memory management circuit 502) processed may need load logic address-physical address mapping table update it is same logically Multiple map informations in location-physical address mapping table.Therefore, when memory control circuit unit 404 (or memory management circuit 502) When being carrying out bringing down stocks operation, memory control circuit unit 404 (or memory management circuit 502) can judge that duplicative is non-volatile The current operator scheme of memory modules 406 is to bring down stocks operator scheme.Now, in the case where bringing down stocks operator scheme, memory control circuit list First 404 (or memory management circuits 502) can load the larger logical address of size-physical address mapping table to buffer storage 508 To be read out.
Based on above-mentioned, in the exemplary embodiment of the present invention, memory control circuit unit 404 (or memory management circuit 502) is the Buffer storage 508 is loaded onto using the less sub- logical address-physical address mapping table of capacity under one operator scheme, and Under two operator schemes buffer storage 508 is loaded onto using the larger logical address of capacity-physical address mapping table.Can thereby have Effect avoid in the first mode of operation because repeatedly load the larger logical address of excessive capacity-physical address mapping table and caused by Store the performance deterioration of cryopreservation device.
Figure 13 is the flow chart of the mapping table loading method according to an exemplary embodiment.
Figure 13 is refer to, in step S1301, memory control circuit unit 404 (or memory management circuit 502) is from main frame system System 11 receives the first instruction, wherein the first instruction corresponds to the data being stored in the first logical address.In step S1303, Memory control circuit unit 404 (or memory management circuit 502) judges the operation of corresponding duplicative Nonvolatile memory module 406 Pattern is first operator scheme or second operator scheme.When the operator scheme of corresponding duplicative Nonvolatile memory module 406 is During first operator scheme, in step S1305, memory control circuit unit 404 (or memory management circuit 502) is from duplicative Nonvolatile memory module 406 loads the first sub- logical address-physical address mapping table among sub- logical address-physical address mapping table Into buffer storage 508, wherein the first sub- logical address-physical address mapping table record has the mapping of corresponding first logical address Information.When the operator scheme of corresponding duplicative Nonvolatile memory module 406 is second operator scheme, in step S1307 In, memory control circuit unit 404 (or memory management circuit 502) is from the load logic of duplicative Nonvolatile memory module 406 The first logical address-physical address mapping table among address-physical address mapping table is into buffer storage 508, wherein first patrols Collecting address-physical address mapping table record has the map information of corresponding first logical address, wherein the first logical address-physical address reflects Firing table includes the first sub- logical address-physical address mapping table.
In summary, the present invention can use the less sub- logical address of capacity-physical address mapping table to load in the first mode of operation To buffer storage, and it is loaded onto buffering using the larger logical address of capacity-physical address mapping table in the second mode of operation Memory.Especially since in first operator scheme only can the less sub- logical address-physical address mapping table of load capacity, Host computer system can be avoided repeatedly to load larger logical address-physical address mapping table in the first mode of operation and cause internal memory The bandwidth waste of storage device, and the service efficiency and efficiency of internal storing memory can be effectively improved.
Although the present invention is disclosed as above with embodiment, so it is not limited to the present invention, common in any art Technical staff, without departing from the spirit and scope of the present invention, when can make a little change and retouching, therefore the protection model of the present invention Enclose to work as and be defined depending on appended claims confining spectrum.

Claims (24)

  1. A kind of 1. mapping table loading method, for a duplicative Nonvolatile memory module, it is characterised in that described to make carbon copies Formula Nonvolatile memory module stores multiple logical address-physical address mapping tables and each logical address-physical address mapping table tool There are more sub- logical address-physical address mapping tables, the mapping table loading method includes：
    One first instruction is received, wherein first instruction corresponds to the data for being stored in one first logical address；
    When an operator scheme of the corresponding duplicative Nonvolatile memory module is a first operator scheme, answered from described Write one first sub- logical address-reality among the multiple sub- logical address-physical address mapping table of formula Nonvolatile memory module loading Body address mapping table is into a buffer storage, wherein the first sub- logical address-physical address mapping table record has described in correspondence The map information of first logical address；And
    When the operator scheme of the corresponding duplicative Nonvolatile memory module is a second operator scheme, from it is described can One first logical address-reality among the multiple logical address of manifolding formula Nonvolatile memory module loading-physical address mapping table Body address mapping table is into the buffer storage, wherein first logical address-physical address mapping table record has described in correspondence The map information of first logical address,
    Wherein described first logical address-physical address mapping table includes the described first sub- logical address-physical address mapping table.
  2. 2. mapping table loading method according to claim 1, before the step of receiving first instruction, its feature exists In, in addition to：
    One second instruction is performed according to one second sub- logical address-physical address mapping table；
    When the described second sub- logical address-physical address mapping table is different from the described first sub- logical address-physical address mapping table When, judge the operator scheme of the duplicative Nonvolatile memory module for the first operator scheme；And
    When the described second sub- logical address-physical address mapping table is same as the described first sub- logical address-physical address mapping table When, judge the operator scheme of the duplicative Nonvolatile memory module for the second operator scheme.
  3. 3. mapping table loading method according to claim 2, it is characterised in that when the described second sub- logical address-physically When location mapping table is different from the described first sub- logical address-physical address mapping table, in addition to：
    When first logical address-physical address mapping table includes the described second sub- logical address-physical address mapping table, sentence The operator scheme for the duplicative Nonvolatile memory module of breaking is the second mode.
  4. 4. mapping table loading method according to claim 1, it is characterised in that in receive it is described first instruction the step of it Before, in addition to：
    One the 3rd instruction is performed according to second logical address-physical address mapping table；
    When second logical address-physical address mapping table is different from first logical address-physical address mapping table, sentence The operator scheme for the duplicative Nonvolatile memory module of breaking is the first operator scheme.
  5. 5. mapping table loading method according to claim 1, it is characterised in that when the duplicative Nonvolatile memory When the operator scheme of module is the first operator scheme, in addition to：
    First instruction is performed according to the described first sub- logical address-physical address mapping table；
    Erase the described first sub- logical address-physical address mapping table；And
    The use course of the described first sub- logical address-physical address mapping table is recorded in a management table.
  6. 6. mapping table loading method according to claim 1, it is characterised in that the duplicative Nonvolatile memory mould The operator scheme of the block after upper electricity every time is to be defaulted as the first operator scheme.
  7. 7. mapping table loading method according to claim 1, it is characterised in that it is random that the first operator scheme includes one The operator scheme of selection recovery block in read mode, a random writing operator scheme or a collecting garbage program.
  8. 8. mapping table loading method according to claim 1, it is characterised in that it is continuous that the second operator scheme includes one Read mode, one be continuously written into the operator scheme that is write in operator scheme, a collecting garbage program to purpose block or One brings down stocks (flush) operator scheme.
  9. A kind of 9. memory control circuit unit, for controlling a duplicative Nonvolatile memory module, it is characterised in that described Memory control circuit unit includes：
    One HPI, it is electrically connected to a host computer system；
    One memory interface, the duplicative Nonvolatile memory module is electrically connected to, wherein the duplicative is non-easily Multiple logical address-physical address the mapping tables of the property lost memory modules storage and each logical address-physical address mapping table have multiple Sub- logical address-physical address mapping table；
    One buffer storage；And
    One memory management circuit, the HPI, the memory interface and the buffer storage are electrically connected to,
    The memory management circuit is to receive one first instruction, wherein first instruction, which corresponds to, is stored in one first logically Data on location,
    When an operator scheme of the corresponding duplicative Nonvolatile memory module is a first operator scheme, the internal memory pipe Circuit is managed more among a little logical address-physical address mapping table described in the duplicative Nonvolatile memory module loading One first sub- logical address-physical address mapping table is into the buffer storage, wherein the first sub- logical address-physical address Mapping table record has the map information of corresponding first logical address,
    When the operator scheme of the corresponding duplicative Nonvolatile memory module is a second operator scheme, the internal memory Manage circuit more to from the multiple logical address of the duplicative Nonvolatile memory module loading-physical address mapping table it In first logical address-physical address mapping table into the buffer storage, wherein first logical address-physical address Mapping table record has the map information of corresponding first logical address,
    Wherein described first logical address-physical address mapping table includes the described first sub- logical address-physical address mapping table.
  10. 10. memory control circuit unit according to claim 9, it is characterised in that in the running for receiving first instruction Before,
    The memory management circuit more instructs to perform one second according to one second sub- logical address-physical address mapping table,
    When the described second sub- logical address-physical address mapping table is different from the described first sub- logical address-physical address mapping table When, the memory management circuit is more judging the operator scheme of the duplicative Nonvolatile memory module for described One operator scheme, and
    When the described second sub- logical address-physical address mapping table is same as the described first sub- logical address-physical address mapping table When, the memory management circuit is more judging the operator scheme of the duplicative Nonvolatile memory module for described Two operator schemes.
  11. 11. memory control circuit unit according to claim 10, it is characterised in that when described second sub- logical address-reality When body address mapping table is different from the described first sub- logical address-physical address mapping table,
    When first logical address-physical address mapping table includes the described second sub- logical address-physical address mapping table, institute Memory management circuit is stated more judging the operator scheme of the duplicative Nonvolatile memory module for second mould Formula.
  12. 12. memory control circuit unit according to claim 9, it is characterised in that in the running for receiving first instruction Before,
    The memory management circuit more instructs to perform one the 3rd according to second logical address-physical address mapping table,
    When second logical address-physical address mapping table is different from first logical address-physical address mapping table, institute State memory management circuit more to judge the operator scheme of the duplicative Nonvolatile memory module for described first operation Pattern.
  13. 13. memory control circuit unit according to claim 9, it is characterised in that in the duplicative is non-volatile When the operator scheme of storing module is the first operator scheme,
    The memory management circuit more instructs to perform described first according to the described first sub- logical address-physical address mapping table,
    The memory management circuit more to the described first sub- logical address-physical address mapping table of erasing, and
    The memory management circuit in a management table more recording the use of the described first sub- logical address-physical address mapping table Course.
  14. 14. memory control circuit unit according to claim 9, it is characterised in that the duplicative Nonvolatile memory The operator scheme of the module after upper electricity every time is to be defaulted as the first operator scheme.
  15. 15. memory control circuit unit according to claim 9, it is characterised in that the first operator scheme include one with The operator scheme of selection recovery block in machine read mode, a random writing operator scheme or a collecting garbage program.
  16. 16. memory control circuit unit according to claim 9, it is characterised in that the second operator scheme includes one and connected Continuous read mode, one are continuously written into the operator scheme write in operator scheme, a collecting garbage program to purpose block Or one bring down stocks operator scheme.
  17. A kind of 17. internal storing memory, it is characterised in that including：
    One connecting interface unit, is electrically connected to a host computer system；
    One duplicative Nonvolatile memory module, to store multiple logical addresses-physical address mapping table and each logical address - physical address mapping table has more sub- logical address-physical address mapping tables；And
    One memory control circuit unit, including a buffer storage, wherein the memory control circuit unit be electrically connected to it is described Connecting interface unit and the duplicative Nonvolatile memory module,
    Wherein described memory control circuit unit is to receive one first instruction, wherein first instruction, which corresponds to, is stored in one the Data in one logical address,
    When an operator scheme of the corresponding duplicative Nonvolatile memory module is a first operator scheme, the internal memory control Circuit unit processed is more to from the mapping of the multiple sub- logical address of the duplicative Nonvolatile memory module loading-physical address One first sub- logical address-physical address mapping table is into the buffer storage among table, wherein the first sub- logical address- Physical address mapping table record has the map information of corresponding first logical address,
    When the operator scheme of the corresponding duplicative Nonvolatile memory module is a second operator scheme, the internal memory Control circuit unit is more to from the mapping of the multiple logical address of the duplicative Nonvolatile memory module loading-physical address First logical address-physical address mapping table among table is into the buffer storage, wherein first logical address-entity Address mapping table record has the map information of corresponding first logical address,
    Wherein described first logical address-physical address mapping table includes the described first sub- logical address-physical address mapping table.
  18. 18. internal storing memory according to claim 17, it is characterised in that in receive it is described first instruction running it Before,
    The memory control circuit unit more instructs to perform one second according to one second sub- logical address-physical address mapping table,
    When the described second sub- logical address-physical address mapping table is different from the described first sub- logical address-physical address mapping table When, the memory control circuit unit is more judging the operator scheme of the duplicative Nonvolatile memory module for institute First operator scheme is stated, and
    When the described second sub- logical address-physical address mapping table is same as the described first sub- logical address-physical address mapping table When, the memory control circuit unit is more judging the operator scheme of the duplicative Nonvolatile memory module for institute State second operator scheme.
  19. 19. internal storing memory according to claim 18, it is characterised in that when the described second sub- logical address-physically When location mapping table is different from the described first sub- logical address-physical address mapping table, when first logical address-physical address reflects When firing table includes the described second sub- logical address-physical address mapping table, the memory control circuit unit more to judge it is described can The operator scheme of manifolding formula Nonvolatile memory module is the second mode.
  20. 20. internal storing memory according to claim 17, it is characterised in that in receive it is described first instruction running it Before,
    The memory control circuit unit more instructs to perform one the 3rd according to second logical address-physical address mapping table；
    When second logical address-physical address mapping table is different from first logical address-physical address mapping table, institute Memory control circuit unit is stated more judging the operator scheme of the duplicative Nonvolatile memory module for described first Operator scheme.
  21. 21. internal storing memory according to claim 17, it is characterised in that when the duplicative Nonvolatile memory When the operator scheme of module is the first operator scheme,
    The memory control circuit unit more refers to perform described first according to the described first sub- logical address-physical address mapping table Order,
    The memory control circuit unit more to the described first sub- logical address-physical address mapping table of erasing, and
    The memory control circuit unit in a management table more recording the described first sub- logical address-physical address mapping table Use course.
  22. 22. internal storing memory according to claim 17, it is characterised in that the duplicative Nonvolatile memory mould The operator scheme of the block after upper electricity every time is to be defaulted as the first operator scheme.
  23. 23. internal storing memory according to claim 17, it is characterised in that it is random that the first operator scheme includes one The operator scheme of selection recovery block in read mode, a random writing operator scheme or a collecting garbage program.
  24. 24. internal storing memory according to claim 17, it is characterised in that it is continuous that the second operator scheme includes one Read mode, one be continuously written into the operator scheme that is write in operator scheme, a collecting garbage program to purpose block or One brings down stocks operator scheme.
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