CN103544115A

CN103544115A - Data writing method, memorizer controller and memorizer storage device

Info

Publication number: CN103544115A
Application number: CN201210236689.9A
Authority: CN
Inventors: 叶志刚
Original assignee: Phison Electronics Corp
Current assignee: Phison Electronics Corp
Priority date: 2012-07-10
Filing date: 2012-07-10
Publication date: 2014-01-29
Anticipated expiration: 2032-07-10
Also published as: CN103544115B

Abstract

The invention provides a data writing method, a memorizer controller and a memorizer storage device. The data writing method, the memorizer controller and the memorizer storage device are used for controlling a rewritable nonvolatile memory module provided with a plurality of entity erasure units. The method comprises the steps of receiving a writing instruction instructing the operation of writing data into a first logic address, wherein the first logic address is mapped to a second entity erasure unit; judging whether the second entity erasure unit is in a continuous writing state or not, wherein the continuous writing state represents that entity programmatic units which excess the preset proportion in the second entity erasure unit are continuously programmed in preset time; the data are written into a third entity erasure unit through a first programmatic pattern if the second entity erasure unit is in the continuous writing state, wherein the first programmatic pattern represents that the entity programmatic units cannot be programmed. Therefore, the writing speed of the data can be improved.

Description

Method for writing data, Memory Controller and memory storage apparatus

Technical field

The present invention relates to a kind of method for writing data for duplicative non-volatile memory module, relate in particular to a kind of Memory Controller and memory storage apparatus that uses the method.

Background technology

Digital camera, mobile phone and MP3 player are very rapid in growth over the years, and consumer is also increased rapidly to the demand of medium.For example, because duplicative non-volatile memory module (, flash memory) has that data are non-volatile, power saving, volume be little, and the characteristic such as machinery-free structure, so be built in above-mentioned given an example various portable multimedia devices in being applicable to very much.

In general, duplicative non-volatile memory module can be used with a host computer system collocation.Host computer system can be assigned the instruction of access logical address and read or data writing to duplicative non-volatile memory module.Yet host computer system may mark off ，Ci region, a specific region from logical address can be used to backup or dump (dump) data.When this region of host computer system access, may assign a plurality ofly writing instruction and carry out a plurality of continuous logical addresses of access.If the data volume of to back up or dump is very large, the speed writing significantly affects the usefulness of host computer system.Therefore, how writing rapidly the data of continuous logic address to duplicative non-volatile memory module, is the subject under discussion that this area research personnel are concerned about.

Summary of the invention

Embodiments of the invention provide a kind of method for writing data, and Memory Controller and memory storage apparatus can increase the speed of data writing.

One embodiment of the invention provides a kind of method for writing data, for controlling duplicative non-volatile memory module.Duplicative non-volatile memory module comprises a plurality of entity erase units, and each entity erase unit comprises a plurality of entity sequencing unit group, and each entity sequencing unit group comprises a plurality of entity sequencing unit.The entity sequencing unit of each entity sequencing unit group comprises a lower entity sequencing unit and a upper entity sequencing unit.A plurality of logical addresses are a plurality of first instance erase units that map in entity erase unit.This method for writing data comprises: receive one first and write instruction, this first writes instruction indication and data is write to at least one first logical address of logical address, and wherein the first logical address is the second instance erase unit mapping in first instance erase unit.The method also comprises: judge whether second instance erase unit is continuous write state, the entity sequencing unit that continuously write state represents to surpass in second instance erase unit preset ratio in Preset Time once by sequencing continuously; And if second instance erase unit is continuous write state, data are write to the 3rd entity erase unit with the first sequencing pattern, wherein on the first sequencing modal representation, entity sequencing unit is non-program.

In one embodiment, above-mentioned before judging whether second instance erase unit is the step of continuous write state, this method for writing data also comprises: judge that whether first write instruction for writing continuously instruction.Write continuously instruction and represent that the first logical address is to write after instruction indication wants the logical address of access second, and second write instruction be received in first write instruction before.

In one embodiment, above-mentioned method for writing data also comprises: if first write instruction not for writing continuously instruction, data are write to the 4th entity erase unit; And set the 4th entity erase unit for continuous write state.

In one embodiment, above-mentioned before judging whether second instance erase unit is the step of continuous write state, this method for writing data also comprises: judge that whether second instance erase unit was for not being written into; And if second instance erase unit was not written into, data are write to second instance erase unit with the second sequencing pattern, wherein all entity sequencing unit of the second sequencing modal representation can be by sequencing.

In one embodiment, if above-mentioned second instance erase unit is continuous write state, the step that data are write to the 3rd entity erase unit with the first sequencing pattern comprises: judge whether second instance erase unit is to write with the first sequencing pattern; If second instance erase unit is the first sequencing pattern, judge whether the number of the idle entity erase unit in entity erase unit is not less than the first preset number; And if the number of idle entity erase unit is not less than the first preset number, data are write to the 3rd entity erase unit with the first sequencing pattern; And to set the 3rd entity erase unit be continuous write state.

In one embodiment, if above-mentioned second instance erase unit is continuous write state, the step that data are write to the 3rd entity erase unit with the first sequencing pattern comprises: judge whether second instance erase unit is to write with the first sequencing pattern; If second instance erase unit is not to write with the first sequencing pattern, judge whether the number of the idle entity erase unit of one in entity erase unit is not less than the second preset number; And if the number of idle entity erase unit is not less than the second preset number, data are write to the 3rd entity erase unit with the first sequencing pattern, and to set the 3rd entity erase unit be continuous write state.

In one embodiment, above-mentioned method for writing data also comprises: if the number of idle entity erase unit is less than the second preset number, whether the number of the idle entity erase unit of judgement is not less than the first preset number, and wherein the second preset number is greater than the first preset number; If the number of idle entity erase unit is not less than the first preset number, data are write to the 5th entity erase unit in entity erase unit with the second sequencing pattern; And to set the 5th entity erase unit be continuous write state.

In one embodiment, above-mentioned method for writing data also comprises: if second instance erase unit is not continuous write state, judge whether the number of idle entity erase unit in entity erase unit is not less than the first preset number; If the number of idle entity erase unit is not less than the first preset number, data are write to the 6th entity erase unit in entity erase unit with the second sequencing pattern; And to set the 6th entity erase unit be continuous write state.

With another one angle, one embodiment of the invention provides a kind of memory storage apparatus, comprises connector, duplicative non-volatile memory module and Memory Controller.Connector is to be electrically connected to host computer system.Duplicative non-volatile memory module comprises a plurality of entity erase units, wherein each entity erase unit comprises a plurality of entity sequencing unit group, each entity sequencing unit group comprises a plurality of entity sequencing unit, and these entity sequencing unit of each entity sequencing unit group comprise a lower entity sequencing unit and a upper entity sequencing unit.A plurality of logical addresses are to map to a plurality of first instance erase units.Memory Controller is to be electrically connected to connector and duplicative non-volatile memory module, in order to receive one first, writes instruction.This first writes instruction indication data is write to few first logical address, and the first logical address is the second instance erase unit mapping in described first instance erase unit.Memory Controller is also in order to judge whether second instance erase unit is a continuous write state, the entity sequencing unit that this continuous write state represents to surpass in second instance erase unit a preset ratio in a Preset Time once by sequencing continuously.If second instance erase unit is continuous write state, Memory Controller is also in order to write to a 3rd entity erase unit by data with the first sequencing pattern, and wherein on the first sequencing modal representation, entity sequencing unit is non-program.

In one embodiment, above-mentioned Memory Controller is also in order to judge that whether first write instruction for writing continuously instruction.Write continuously instruction and represent that the first logical address is to write after instruction indication wants the logical address of access second, and second write instruction be stored device controller be received in first write instruction before.

In one embodiment, if first write instruction not for writing continuously instruction, Memory Controller is also in order to data are write to the 4th entity erase unit in entity erase unit, and to set the 4th entity erase unit be not continuous write state.

In one embodiment, above-mentioned Memory Controller is also in order to judge whether second instance erase unit was not written into.If second instance erase unit was not written into, Memory Controller is also in order to write to second instance erase unit by data with the second sequencing pattern, and wherein the second sequencing modal representation entity sequencing unit can be by sequencing.

In one embodiment, above-mentioned Memory Controller is also in order to judge whether second instance erase unit is to write with the first sequencing pattern.If second instance erase unit is to write with the first sequencing pattern, Memory Controller is also in order to judge whether the number of idle entity erase unit in entity erase unit is not less than the first preset number.If the number of idle entity erase unit is not less than the first preset number, Memory Controller is also in order to data are write to the 3rd entity erase unit with the first sequencing pattern, and to set the 3rd entity erase unit be continuous write state.

In one embodiment, above-mentioned Memory Controller is also in order to judge whether second instance erase unit is to write with the first sequencing pattern.If second instance erase unit is not to write with the first sequencing pattern, Memory Controller is also in order to judge whether the number of idle entity erase unit in entity erase unit is not less than the second preset number.If the number of idle entity erase unit is not less than the second preset number, Memory Controller is also in order to data are write to the 3rd entity erase unit with the first sequencing pattern, and to set the 3rd entity erase unit be continuous write state.

In one embodiment, if the number of idle entity erase unit is less than the second preset number, Memory Controller is also in order to judge whether the number of idle entity erase unit is not less than the first preset number, and wherein the second preset number is greater than the first preset number.If the number of idle entity erase unit is not less than the first preset number, Memory Controller is also in order to write to data the second sequencing pattern the 5th entity erase unit of entity erase unit.Memory Controller is also continuous write state in order to set the 5th entity erase unit.

In one embodiment, if second instance erase unit is not continuous write state, Memory Controller is also in order to judge whether the number of idle entity erase unit is not less than the first preset number.If the number of idle entity erase unit is not less than the first preset number, Memory Controller is also in order to data are write to the 6th entity erase unit with the first sequencing pattern, and to set the 6th entity erase unit be continuous write state.

With another one angle, one embodiment of the invention provides a kind of Memory Controller, comprises host interface, memory interface and memory management circuitry.Host interface is to be electrically connected to host computer system.Memory interface is to be electrically connected to a duplicative non-volatile memory module.This duplicative non-volatile memory module comprises a plurality of entity erase units, wherein each entity erase unit comprises a plurality of entity sequencing unit group, each entity sequencing unit group comprises a plurality of entity sequencing unit, and these entity sequencing unit of each entity sequencing unit group comprise a lower entity sequencing unit and a upper entity sequencing unit.A plurality of logical addresses are to map to a plurality of first instance erase units.Memory management circuitry is to be electrically connected to connector and duplicative non-volatile memory module, in order to receive one first, writes instruction.This first writes instruction indication data is write to few first logical address, and the first logical address is the second instance erase unit mapping in described first instance erase unit.Memory management circuitry is also in order to judge whether second instance erase unit is a continuous write state, the entity sequencing unit that this continuous write state represents to surpass in second instance erase unit a preset ratio in a Preset Time once by sequencing continuously.If second instance erase unit is continuous write state, memory management circuitry is also in order to write to a 3rd entity erase unit by data with the first sequencing pattern.On the first sequencing modal representation, entity sequencing unit is non-program.

In one embodiment, above-mentioned memory management circuitry is also in order to judge that whether first write instruction for writing continuously instruction.Write continuously instruction and represent that the first logical address is to write after instruction indication wants the logical address of access second, and second write instruction be stored management circuit be received in first write instruction before.

In one embodiment, if first write instruction not for writing continuously instruction, memory management circuitry is also in order to data are write to the 4th entity erase unit in entity erase unit, and to set the 4th entity erase unit be not continuous write state.

In one embodiment, above-mentioned memory management circuitry is also in order to judge whether second instance erase unit was not written into.If second instance erase unit was not written into, memory management circuitry is also in order to write to second instance erase unit by data with the second sequencing pattern, and wherein the second sequencing modal representation entity sequencing unit can be by sequencing.

In one embodiment, above-mentioned memory management circuitry is also in order to judge whether second instance erase unit is to write with the first sequencing pattern.If second instance erase unit is to write with the first sequencing pattern, memory management circuitry is also in order to judge whether the number of idle entity erase unit in entity erase unit is not less than the first preset number.If the number of idle entity erase unit is not less than the first preset number, memory management circuitry is also in order to data are write to the 3rd entity erase unit with the first sequencing pattern, and to set the 3rd entity erase unit be continuous write state.

In one embodiment, above-mentioned memory management circuitry is also in order to judge whether second instance erase unit is to write with the first sequencing pattern.If second instance erase unit is not to write with the first sequencing pattern, memory management circuitry is also in order to judge whether the number of idle entity erase unit in entity erase unit is not less than the second preset number.If the number of idle entity erase unit is not less than the second preset number, memory management circuitry is also in order to data are write to the 3rd entity erase unit with the first sequencing pattern, and to set the 3rd entity erase unit be continuous write state.

In one embodiment, if the number of idle entity erase unit is less than the second preset number, memory management circuitry is also in order to judge whether the number of idle entity erase unit is not less than the first preset number, and wherein the second preset number is greater than the first preset number.If the number of idle entity erase unit is not less than the first preset number, memory management circuitry is also in order to write to data the second sequencing pattern the 5th entity erase unit of entity erase unit.Memory management circuitry is also continuous write state in order to set the 5th entity erase unit.

In one embodiment, if second instance erase unit is not continuous write state, memory management circuitry is also in order to judge whether the number of idle entity erase unit is not less than the first preset number.If the number of idle entity erase unit is not less than the first preset number, memory management circuitry is also in order to data are write to the 6th entity erase unit with the first sequencing pattern, and to set the 6th entity erase unit be continuous write state.

Based on above-mentioned, the method for writing data that the embodiment of the present invention provides, Memory Controller and memory storage apparatus, can when will to write logical address be continuous data, increase the speed that data write in host computer system.

For above-mentioned feature and advantage of the present invention can be become apparent, special embodiment below, and coordinate accompanying drawing to be described in detail below.

Accompanying drawing explanation

Figure 1A is according to the structural representation of the shown host computer system of an embodiment and memory storage apparatus;

Figure 1B is according to the schematic diagram of the shown computing machine of an embodiment, input/output device and memory storage apparatus;

Fig. 1 C is according to the schematic diagram of the shown host computer system of an embodiment and memory storage apparatus;

Fig. 2 A is the summary calcspar that the memory storage apparatus shown in Figure 1A is shown;

Fig. 2 B illustrates the schematic diagram of the first sequencing pattern and the second sequencing pattern according to an embodiment;

Fig. 3 is according to the summary calcspar of the shown Memory Controller of an embodiment;

Fig. 4 and Fig. 5 are according to the schematic diagram of the shown management duplicative of embodiment non-volatile memory module;

Fig. 6 illustrates that according to an embodiment second instance erase unit is with the first sequencing pattern, to write the schematic diagram of fashionable write operation;

Fig. 7 illustrates that according to an embodiment second instance erase unit is not with the first sequencing pattern, to write the schematic diagram of fashionable write operation;

Fig. 8 illustrates that according to an embodiment second instance erase unit is not to write with the first sequencing pattern, and the schematic diagram of the write operation of the number of idle entity erase unit while being less than the second preset number;

Fig. 9 A～Fig. 9 C illustrates the process flow diagram of method for writing data according to an embodiment;

Figure 10 illustrates the process flow diagram of method for writing data according to another embodiment.

Description of reference numerals:

1000: host computer system;

1100: computing machine;

1102: microprocessor;

1104: random access memory;

1106: input/output device;

1108: system bus;

1110: data transmission interface;

1202: mouse;

1204: keyboard;

1206: display;

1208: printer;

1212:U dish;

1214: memory card;

1216: solid state hard disc;

1310: digital camera;

1312:SD card;

1314:MMC card;

1316: memory stick;

1318:CF card;

1320: embedded memory storage;

100: memory storage apparatus;

102: connector;

104: Memory Controller;

106: duplicative non-volatile memory module;

304 (0)～304 (R): entity erase unit;

220 (0)～220 (127): entity sequencing unit group;

202: memory management circuitry;

204: host interface;

206: memory interface;

252: memory buffer;

254: electric power management circuit;

256: bug check and correcting circuit;

402: data field;

404: idle district;

406: system region;

408: replace district;

504: data;

502 (0)～502 (A): logical address;

S602, S604, S606, S608, S610, S612, S614, S616, S618, S620, S622, S624, S626, S628, S630, S632, S634, S636, S1002, S1004, S1006, S1008: the step of method for writing data.

Embodiment

Generally speaking, memory storage apparatus (also claiming storage system) comprises duplicative non-volatile memory module and controller (also claiming control circuit).Conventionally memory storage apparatus is to use together with host computer system, so that host computer system can write to data memory storage apparatus or reading out data from memory storage apparatus.

Figure 1A is according to the structural representation of the shown host computer system of an embodiment and memory storage apparatus.

Please refer to Figure 1A, host computer system 1000 generally comprises computing machine 1100 and installs 1106 with I/O (input/output, I/O).Computing machine 1100 comprises microprocessor 1102, random access memory (random access memory, RAM) 1104, system bus 1108 and data transmission interface 1110.Input/output device 1106 comprises mouse 1202, keyboard 1204, display 1206 and printer 1208 as shown in Figure 1B.It must be appreciated, the unrestricted input/output device 1106 of the device shown in Figure 1B, input/output device 1106 can also comprise other devices.

In embodiments of the present invention, memory storage apparatus 100 is to be electrically connected by data transmission interface 1110 and other elements of host computer system 1000.By microprocessor 1102, random access memory 1104, data can be write to memory storage apparatus 100 or reading out data from memory storage apparatus 100 with the operation of input/output device 1106.For example, memory storage apparatus 100 can be the duplicative non-volatile memory device of USB flash disk 1212, memory card 1214 or solid state hard disc (Solid State Drive, SSD) 1216 as shown in Figure 1B etc.

Generally speaking, host computer system 1000 is for can coordinate to store substantially any system of data with memory storage apparatus 100.Although in the present embodiment, host computer system 1000 is to explain with computer system, yet host computer system 1000 can be the systems such as digital camera, video camera, communicator, audio player or video player in another embodiment of the present invention.For example, as shown in Figure 1 C, in host computer system, be digital camera (video camera) 1310 o'clock, duplicative non-volatile memory device is its SD card 1312 using, mmc card 1314, memory stick (memory stick) 1316, CF card 1318 or embedded memory storage 1320.Embedded memory storage 1320 comprises embedded multi-media card (Embedded MMC, eMMC).It is worth mentioning that, embedded multi-media card is to be directly electrically connected on the substrate of host computer system.

Fig. 2 A is the summary calcspar that the memory storage apparatus shown in Figure 1A is shown.

Please refer to Figure 1A and Fig. 2, memory storage apparatus 100 comprises connector 102, Memory Controller 104 and duplicative non-volatile memory module 106.

In the present embodiment, connector 102 is to be compatible with Serial Advanced Technology Attachment (Serial Advanced Technology Attachment, SATA) standard.Yet, it must be appreciated, the invention is not restricted to this, connector 102 can be also compatible parallel Advanced Technology Attachment (ParallelAdvanced Technology Attachment, PATA) standard, Institute of Electrical and Electronics Engineers (Institute of Electrical and Electronic Engineers, IEEE) 1394 standards, high-speed peripheral assembly interconnect (Peripheral Component Interconnect Express, PCI Express) standard, USB (universal serial bus) (Universal Serial Bus, USB) standard, safe digital (SecureDigital, SD) interface standard, a hypervelocity generation (Ultra High Speed-I, UHS-I) interface standard, hypervelocity two generations (Ultra High Speed-II, UHS-II) interface standard, memory stick (Memory Stick, MS) interface standard, multimedia storage card (Multi Media Card, MMC) interface standard, built-in multimedia storage card (Embedded Multimedia Card, eMMC) interface standard, general flash memory (Universal Flash Storage, UFS) interface standard, compact flash (CompactFlash, CF) interface standard, ide (Integrated Device Electronics, IDE) standard or other applicable standards.

A plurality of logic gates or steering order that Memory Controller 104 is realized with hardware pattern or firmware pattern in order to execution, and according to the instruction of host computer system 1000, in duplicative non-volatile memory module 106, carry out the operations such as writing, read and wipe of data.

Duplicative non-volatile memory module 106 is to be electrically connected to Memory Controller 104, and the data that write in order to host system 1000.Duplicative non-volatile memory module 106 has entity erase unit 304 (0)～304 (R).For example, entity erase unit 304 (0)～304 (R) can belong to same memory crystal grain (die) or belong to different memory crystal grain.Each entity erase unit has respectively a plurality of entity sequencing unit, and the entity sequencing unit that belongs to same entity erase unit can be write independently and side by side be wiped.For example, each entity erase unit is comprised of 128 entity sequencing unit.Yet, it must be appreciated, the invention is not restricted to this, each entity erase unit can be comprised of 64 entity sequencing unit, 256 entity sequencing unit or other arbitrarily individual entity sequencing unit.

In more detail, entity erase unit is the least unit of wiping.Also the memory cell being wiped free of in the lump that, each entity erase unit contains minimal amount.The minimum unit that entity sequencing unit is sequencing.That is the minimum unit that, entity sequencing unit is data writing.Each entity sequencing unit generally includes data byte district and redundancy bytes district.Data byte district comprises a plurality of entities access address in order to for example to store user's data ，Er redundancy bytes district, in order to the data (, control information and error correcting code) of storage system.In the present embodiment, in the data byte district of each entity sequencing unit, can comprise 4 entity access addresses, and the size of an entity access address is 512 bytes (byte, B).Yet, in other embodiments, in data byte district, also can comprise 8,16 or the more or less entity access address of number, the present invention does not limit size and the number of entity access address.For example, entity erase unit is physical blocks, and entity sequencing unit is physical page or entity fan.

In the present embodiment, duplicative non-volatile memory module 106 is multistage memory cell (Multi Level Cell, MLC) nand flash memory memory module, in a memory cell, can store at least 2 byte datas.Also, each entity erase unit can comprise a plurality of entity sequencing unit group, and each entity sequencing unit group can comprise lower entity sequencing unit and upper entity sequencing unit.Wherein descend the sequencing speed of entity sequencing unit can be greater than the sequencing speed of entity sequencing unit.Yet, the invention is not restricted to this, duplicative non-volatile memory module 106 is single-order memory cell (Single Level Cell also, SLC) nand flash memory memory module, Complex Order memory cell (Trinary Level Cell, TLC) NAND type flash memories module, other flash memories modules or other have the memory module of identical characteristics.

Fig. 2 B illustrates the schematic diagram of the first sequencing pattern and the second sequencing pattern according to an embodiment.

In the present embodiment, the sequencing pattern of an entity erase unit at least can comprise two kinds, i.e. the first sequencing pattern and the second sequencing pattern.And entity sequencing unit can not be by sequencing on the first sequencing modal representation.In each entity sequencing unit group of the second sequencing modal representation, all entity sequencing unit can be by sequencing.For instance, please refer to Fig. 2 B, entity erase unit 304 (0) operates in the second sequencing pattern, and entity erase unit 304 (1) operates in the first sequencing pattern.Entity erase unit 304 (0) has comprised entity sequencing unit group 220 (0)～220 (127), and wherein all entity sequencing unit (that is, the entity sequencing unit of physical address 0～255) all can be by sequencing.On the other hand, the inner upper entity sequencing unit of entity erase unit 304 (1) is can not be by sequencing, in other words, only descends the entity sequencing unit (that is, the entity sequencing unit of physical address 0～127) can be by sequencing.When an entity erase unit operates in the first sequencing pattern, in its erasing times, be limited to the first critical value.When an entity erase unit operates in the second sequencing pattern, in its erasing times, be limited to the second critical value.And the second critical value can be greater than the first critical value.In the present embodiment, each entity erase unit 304 (0)～304 (R) can carry out data writing by the first sequencing pattern or the second sequencing pattern.

Fig. 3 is according to the summary calcspar of the shown Memory Controller of an embodiment.

Please refer to Fig. 2 A and Fig. 3, Memory Controller 104 comprises memory management circuitry 202, host interface 204 and memory interface 206.

Memory management circuitry 202 is in order to the integrated operation of control store controller 104.Specifically, memory management circuitry 202 has a plurality of steering orders, and when memory storage apparatus 100 operation, these a little steering orders can be performed to carry out the operations such as writing, read and wipe of data.

In the present embodiment, the steering order of memory management circuitry 202 is to carry out implementation with firmware pattern.For example, memory management circuitry 202 has microprocessor unit (not shown) and ROM (read-only memory) (not shown), and these a little steering orders are to be burned onto in this ROM (read-only memory).When memory storage apparatus 100 operation, these a little steering orders can be carried out to carry out by microprocessor unit the operations such as writing, read and wipe of data.

In another embodiment of the present invention, the steering order of memory management circuitry 202 also can procedure code pattern for example be stored in, in the specific region (, being exclusively used in the system region of storage system data in memory module) of duplicative non-volatile memory module 106.In addition, memory management circuitry 202 has microprocessor unit (not shown), ROM (read-only memory) (not shown) and random access memory (not shown).Particularly, this ROM (read-only memory) has the code of driving, and when Memory Controller 104 is enabled, microprocessor unit can first be carried out this and drive code section that the steering order being stored in duplicative non-volatile memory module 106 is loaded in the random access memory of memory management circuitry 202.Afterwards, microprocessor unit can be carried out these a little steering orders to carry out the operations such as writing, read and wipe of data.

In addition,, in another embodiment of the present invention, the steering order of memory management circuitry 202 also can a hardware pattern operate.For example, memory management circuitry 202 comprises microcontroller, Memory Management Unit, storer writing unit, storer reading unit, memory erase unit and data processing unit.Memory Management Unit, storer writing unit, storer reading unit, memory erase unit and data processing unit are to be electrically connected to microcontroller.Wherein, Memory Management Unit is in order to manage the entity erase unit of duplicative non-volatile memory module 106; Storer writing unit writes instruction data are write in duplicative non-volatile memory module 106 in order to duplicative non-volatile memory module 106 is assigned; Storer reading unit is in order to assign reading command with reading out data from duplicative non-volatile memory module 106 to duplicative non-volatile memory module 106; Memory erase unit is in order to assign erasing instruction so that data are wiped from duplicative non-volatile memory module 106 to duplicative non-volatile memory module 106; And data processing unit wants to write to the data of duplicative non-volatile memory module 106 and the data that read from duplicative non-volatile memory module 106 in order to process.

Host interface 204 is instruction and the data that are electrically connected to memory management circuitry 202 and transmit in order to reception and identification host computer system 1000 as shown in Figure 1A.That is to say, the instruction that host computer system 1000 transmits and data can be sent to memory management circuitry 202 by host interface 204.In the present embodiment, host interface 204 is to be compatible with SATA standard.Yet, it must be appreciated and the invention is not restricted to this, host interface 204 can be to be also compatible with PATA standard, IEEE 1394 standards, PCI Express standard, USB standard, SD standard, MS standard, MMC standard, CF standard, IDE standard or other applicable data transmission standards.

Memory interface 206 is to be electrically connected to memory management circuitry 202 and in order to access duplicative non-volatile memory module 106.That is to say, the data of wanting to write to duplicative non-volatile memory module 106 can be converted to 106 receptible forms of duplicative non-volatile memory module via memory interface 206.

In an embodiment of the present invention, Memory Controller 104 also comprises memory buffer 252, electric power management circuit 254 and bug check and correcting circuit 256.

Please refer to Figure 1A, Fig. 2 A and Fig. 3, memory buffer 252 is to be electrically connected to memory management circuitry 202 and in order to deposit the data and instruction that comes from host computer system 1000 or the data that come from duplicative non-volatile memory module 106.

Electric power management circuit 254 is to be electrically connected to memory management circuitry 202 and in order to the power supply of control store memory storage 100.

Bug check and correcting circuit 256 be electrically connected to memory management circuitry 202 and in order to execution error inspection and correction program to guarantee the correctness of data.Specifically, when memory management circuitry 202 receives while writing instruction from host computer system 1000, bug check can produce corresponding bug check and correcting code (Error Checking and Correcting Code for the corresponding data that this writes instruction with correcting circuit 256, ECC Code), and memory management circuitry 202 corresponding these data that write instruction can be write in duplicative non-volatile memory module 106 with corresponding bug check and correcting code.Afterwards, when memory management circuitry 202 can read bug check corresponding to these data and correcting code during reading out data from duplicative non-volatile memory module 106 simultaneously, and bug check and correcting circuit 256 can be according to this bug check and correcting code to read data execution error inspection and correction programs.

Fig. 4 and Fig. 5 are according to the schematic diagram of the shown management duplicative of embodiment non-volatile memory module.

It must be appreciated, when this describes the operation of entity erase unit of duplicative non-volatile memory module 106, with words such as " extraction ", " exchange ", " grouping ", " rotating ", carrying out application entity erase unit is concept in logic.That is to say, the physical location of the entity erase unit of duplicative non-volatile memory module is not changed, but in logic the entity erase unit of duplicative non-volatile memory module is operated.

Please refer to Figure 1A, Fig. 2 A and Fig. 4, Memory Controller 104 can logically be grouped into a plurality of regions by the entity erase unit of duplicative non-volatile memory module 106 304 (0)～304 (R), for example, be data field 402,404, system region, idle district 406 and replacement district 408.In another embodiment, replace district 408 and also can share the entity erase unit that comprises invalid data with idle district 404.

Data field 402 is in order to storage, to come from the data of host computer system 1000 with the entity erase unit in idle district 404.Specifically, data field 402 is entity erase units of having stored data, and the entity erase unit in idle district 404 is the entity erase units in order to replacement data district 402.Therefore, the entity erase unit in idle district 404 be sky or spendable entity erase unit, i.e. no record data or be labeled as invalid data useless.That is to say, the entity erase unit in idle district 404 has been performed erase operation, or the entity erase unit in idle district 404 is extracted for storing the entity erase unit extracting before data and can be first performed erase operation.Therefore, the entity erase unit of the entity erase unit in idle district 404 for being used.

The entity erase unit that belongs in logic system region 406 is in order to register system data, and wherein this system data comprises about the manufacturer of memory chip and model, the entity erase unit number of memory chip, the entity sequencing unit number of each entity erase unit etc.

Belonging in logic the entity erase unit replacing in district 408 is to substitute entity erase unit.For example, duplicative non-volatile memory module can be reserved 4% entity erase unit and uses as changing when dispatching from the factory.That is to say, when the entity erase unit in data field 402,404Yu system region, idle district 406 is damaged, the entity erase unit of reserving in replacing district 408 is in order to replacing damaged entity erase unit (that is, bad entity erase unit (bad block)).Therefore, if when still having normal entity erase unit in replacement district 408 and the damage of entity erase unit occurring, Memory Controller 104 can extract the entity erase unit that normal entity erase unit is changed damage from replace district 408.If when replacing in district 408 without normal entity erase unit and the damage of entity erase unit occurring, Memory Controller 104 can be declared as write protection (write protect) state by whole memory storage apparatus 100, and data writing again.

Particularly, the quantity of the entity erase unit in data field 402,404, system region, idle district 406 and replacement district 408 can be different according to different storer specifications.In addition, it must be appreciated, in the operation of memory storage apparatus 100, entity erase unit is associated to data field 402,404, system region, idle district 406 can dynamically change with the grouping relation that replaces district 408.For example, the entity erase unit in idle district damages and the entity erase unit that is substituted district while replacing, and the entity erase unit that originally replaces district can be associated to idle district.

Please refer to Figure 1A, Fig. 2 A, Fig. 3, Fig. 4 and Fig. 5, as mentioned above, data field 402 is data that the mode of rotating comes host system 1000 to write with the entity erase unit in idle district 404.In the present embodiment, Memory Controller 104 can be beneficial in the entity erase unit of storage data, carrying out data access in the above-mentioned mode of rotating in configuration logic address 502 (0)～502 (A).For example, for example, when memory storage apparatus 100 (is passed through file system by data transmission interface 1110, FAT 32) when format, logical address 502 (0)～502 (A) maps to the entity erase unit 304 (0)～304 (D) (also claiming first instance erase unit) of data field 402 respectively.At this, memory management circuitry 202 can be set up logical address～entity erase unit mapping table (logicaladdress-physical erase unit mapping table), to record the mapping relations between logical address and entity erase unit.In one embodiment, a volumes of storage space corresponding to logical address is the capacity of an entity erase unit, and now logical address is also referred to as logical block addresses (logical block address).Yet in other embodiments, volumes of storage space corresponding to logical address be the capacity of an entity sequencing unit also.The present invention is the corresponding volumes of storage space in circumscription logic address not.

For instance, when host computer system 1000 will write to data 504 entity erase unit 304 (0), that can assign access logical address 502 (0) (also claiming the first logical address) writes instruction to memory management circuitry 202.Memory management circuitry 202 can find the entity erase unit 304 (0) (also claiming second instance erase unit) that maps to logical address 502 (0) according to logical address～-entity erase unit mapping table.In the present embodiment, memory management circuitry 202 can judge that entity sequencing unit in entity erase unit 304 (0), whether once continuously by sequencing, if so, represents that host computer system 1000 is likely in dump or backs up a large amount of data.Now, it is to write with the first sequencing pattern that memory management circuitry 202 can be set an entity erase unit (also claiming the 3rd entity erase unit), and data 504 are write to so far entity erase unit.Because the sequencing speed of the sequencing velocity ratio of entity erase unit under the first sequencing pattern under the second sequencing pattern is fast, therefore can fast data 504 be write.

Specifically, memory management circuitry 202 can first judge and received write instruction (also claiming that first writes instruction) and whether be one and write continuously instruction.For example, when assign first write instruction before, host computer system 1000 has also been assigned second and has been write instruction to memory management circuitry 202.If first writes instruction indication, want the logical address and second of access to write instruction indication to want the logical address of access identical, memory management circuitry 202 is understood and is judged first to write instruction be not to write continuously instruction.Or, if first writes instruction indication, want the logical address and second of access to write instruction to indicate that to want the logical address of access be to be mapped to same entity erase unit, but with programmed sequence, first writes instruction, and to want the entity sequencing unit of access be to write before instruction wants the entity sequencing unit of access second, and memory management circuitry 202 also can judge first to write instruction be not to write continuously instruction.In all the other situations, memory management circuitry 202 can judgement first write instruction for writing continuously instruction.In another embodiment, memory management circuitry 202 also can judge that first writes instruction indication and want the logical address of access whether to continue to write after instruction indicates and want the logical address of access second, if so, judge that first writes instruction for writing continuously instruction.In other words, if one writes instruction for writing continuously instruction, represent that it is continuous data that host computer system 1000 is likely writing a large amount of and logical address, yet how the present invention not limits storage management circuit 202 judges and received writes instruction for writing continuously instruction.

If current the received instruction that writes not is to write continuously instruction, the entity erase unit that memory management circuitry 202 meetings write to idle district 404 by data 504 (also claims the 4th entity erase unit, for example, entity erase unit 304 (D+1)).Yet it is to write or the second sequencing pattern writes with the first sequencing pattern that memory management circuitry 202 can be set entity erase unit 304 (D+1), the present invention is also not subject to the limits.And memory management circuitry 202 can record entity erase unit 304 (D+1) not be a continuous write state.In addition, judge that whether entity erase unit 304 (D+1) is so that the first sequencing pattern writes or the mode that the second sequencing pattern writes, can write in data fashionable, for example, in the redundant area of the entity sequencing unit under the entity erase unit 304 (D+1) (only mark in first lower entity sequencing unit) or in logical address-entity erase unit mapping table, utilize a byte, the mode of coming annotation to write, or judge whether the data in the upper entity sequencing unit of entity erase unit 304 (D+1) are all 0xFFFF.If so, judgement is to write with the first sequencing pattern, and the present invention is also not subject to the limits.

In the present embodiment, when an entity erase unit is noted down as continuous write state, the entity sequencing unit that represents in this entity erase unit to surpass a preset ratio in a Preset Time once by continuously by sequencing.For example, this preset ratio can be set as 75%, 100% or by the number of the entity sequencing unit of sequencing, and the present invention is also not subject to the limits.It should be noted that Preset Time can be represented by the number of times of sequencing with entity erase unit.For example, if Preset Time represents once, memory management circuitry 202 be according to an entity erase unit upper during once by sequencing, wherein 75% entity sequencing unit, whether continuously by sequencing, judges whether this entity erase unit is continuous write state.Yet, in other embodiments, memory management circuitry 202 also can be at entity erase unit nearest twice during by sequencing, and wherein 75% entity sequencing unit is all continuously by after sequencing, and just setting this entity erase unit is continuous write state.In one embodiment, memory management circuitry 202 can be noted down an entity sequencing unit in entity erase unit recently whether continuously by sequencing with a finite state machine (finite state machine) or list, and the present invention is also not subject to the limits.For instance, finite state machine comprises a plurality of states, the entity sequencing unit that each state records an entity erase unit front n time whether by continuous sequencing.Wherein, some states can be continuous write states, and other states are not continuous write states.When an entity erase unit is during by sequencing, all can whether by sequencing, the state of this entity erase unit be switched to another state (or resting on state originally) continuously according to entity sequencing unit wherein.On the other hand, memory management circuitry 202 also can learn when an entity erase unit last time is by sequencing with a timer.When an entity erase unit is continuous write state, represent that it is continuous data that host computer system 1000 likely writes logical address to some specific logical address.

It is worth mentioning that, in order to store the entity erase unit of user's data, all can map to one of them of logical address 502 (0)～502 (A).Therefore, in another embodiment, memory management circuitry 202 also can judge in the level of logical address whether a logical address is continuous write state.For instance, in a logical address, also comprise a plurality of logical addresses (for example, a logical erase element address comprises a plurality of logical programs element address).When a logical address is noted down as continuous write state, the inferior logical address that represents in this logical address to surpass a preset ratio in a Preset Time once by continuously by sequencing.In other words, when an entity erase unit is continuous write state, represent that the logical address of shining upon is also continuous write state.It is to note down continuous write state at entity or the level of logic that the present invention does not limit.

When judgement receive after to write instruction be to write instruction continuously, memory management circuitry 202 can judge whether entity erase unit 304 (0) was not written into.If entity erase unit 304 (0) was not written into, memory management circuitry 202 can write to entity erase unit 304 (0) with the second sequencing pattern by data.

If judgement entity erase unit 304 (0) was once written into, memory management circuitry 202 can further judge whether entity erase unit 304 (0) is to write with the first sequencing pattern.

If entity erase unit 304 (0) is to write with the first sequencing pattern, memory management circuitry 202 can be extracted an idle entity erase unit, and with the first sequencing pattern, data 504 is write to so far idle entity erase unit.When an entity erase unit is during for idle entity erase unit, represent that this entity erase unit do not store any active data.For example, the entity erase unit that is grouped into idle district 404 is idle entity erase unit.In order to extract an idle entity erase unit, memory management circuitry 202 can judge whether the number of idle entity erase blocks in idle district 404 is not less than first preset number.For example, this first preset number is 1.Also, now, as long as the number of idle entity erase blocks is not less than 1, just can complete the action writing.

Fig. 6 illustrates that according to an embodiment second instance erase unit is with the first sequencing pattern, to write the schematic diagram of fashionable write operation.

Please refer to Fig. 3, Fig. 4 and Fig. 6, when entity erase unit 304 (0) is to write fashionablely with the first sequencing pattern, represent the data volume less (compared to the second sequencing pattern) wherein can store.In the present embodiment, the capacity of the corresponding storage space of logical address 502 (0) is upper entity sequencing unit and the lower entity sequencing unit of an entity erase unit.Therefore,, except entity erase unit 304 (0), the data that part belongs to logical address 502 (0) also can be stored in another entity erase unit 304 (1).Number at the idle entity erase unit of this hypothesis is not less than the first preset number (for example, entity erase unit 304 (D+1) is idle entity erase unit).Memory management circuitry 202 can obtain entity erase unit 304 (D+1), and the some of data 504 is write to entity erase unit 304 (D+1) with the first sequencing pattern.In addition, also can to set entity erase unit 304 (D+1) be continuous write state to memory management circuitry 202.It should be noted that, after entity erase unit 304 (D+1) is fully written, what also in presentation-entity erase unit 304 (0), store is invalid data, and the data that now belong to logical address 502 (0) are to be stored in the middle of entity erase unit 304 (D+1) and 304 (1).Next, memory management circuitry 202 can be assigned the instruction of wiping to entity erase unit 304 (0), and another part of data 504 is write to entity erase unit 304 (0).After completing above-mentioned steps, the data that belong to logical address 502 (0) are to be stored in entity erase unit 304 (D+1) and 304 (0), and what in entity erase unit 304 (1), store is invalid data.After being wiped free of, entity erase unit 304 (1) just can become idle entity erase unit, in order to use when the reception next one writes instruction.

Yet if now the number of idle entity erase blocks is less than the first preset number, memory management circuitry 202 can be carried out and merges (merge) operation or data are write to idle entity sequencing unit.Specifically, memory management circuitry 202 can copy to same entity erase unit by the valid data in two or more entity erase units.And memory management circuitry can be carried out the operation of wiping to not storing the entity erase unit of valid data, this entity erase unit that is performed erase operation just can become idle entity erase unit.Next, the mode of memory management circuitry 202 shown in just can Fig. 6 writes so far idle entity erase unit by data 504 in the mode of the first sequencing pattern.Or, when memory management circuitry 202 is to take entity sequencing unit when base unit is managed duplicative non-volatile memory module 106, even if the number of idle entity erase blocks is less than the first preset number, but entity sequencing unit that may be idle in addition in some entity erase units.Now, memory management circuitry 202 can write to data 504 any idle entity sequencing unit, and the present invention is also not subject to the limits.

On the other hand, if entity erase unit 304 (0) is continuous write state, but not to write with the first sequencing pattern, memory management circuitry 202 also can write data 504 in the mode of the first sequencing pattern.Yet, when an entity erase unit is while storing data with the first sequencing pattern, the number of the entity sequencing unit that can use less (compared to the second sequencing pattern).Therefore, memory management circuitry 202 can judge whether the number of idle entity erase unit in idle district 404 is not less than the second preset number.For example, this second preset number represents the number of entity sequencing unit in each entity sequencing unit group, is 2 in the present embodiment.Yet in other embodiments, the second preset number can be also other positive integer, the present invention is also not subject to the limits.

Fig. 7 illustrates that according to an embodiment second instance erase unit is not with the first sequencing pattern, to write the schematic diagram of fashionable write operation.

Please refer to Fig. 3 and Fig. 7, number at the idle entity erase unit of this hypothesis memory management circuitry 202 judgement is not less than the second preset number, and wherein entity erase unit 304 (D+1) is idle entity erase unit with 304 (D+2) (also referred to as the 3rd entity erase unit).On the other hand, in this logic of propositions address 502 (0), be that original mappings is to entity erase unit 304 (0).Memory management circuitry 202 can write to entity erase unit 304 (D+1) and 304 (D+2) with the first sequencing pattern by data 504, and setting entity erase unit 304 (D+1) are continuous write state with 304 (D+2).In addition, memory management circuitry 202 also can the logical address 502 (0) to entity erase unit 304 (0) remap original mappings to entity erase unit 304 (D+1) and 304 (D+2).

Fig. 8 illustrates that according to an embodiment second instance erase unit is not to write with the first sequencing pattern, and the schematic diagram of the write operation of the number of idle entity erase unit while being less than the second preset number.

Please refer to Fig. 3 and Fig. 8, if entity erase unit 304 (0) is continuous write state, not to write with the first sequencing pattern, and when the number of idle entity erase unit is less than the second preset number, memory management circuitry 202 also can further judge whether the number of idle entity erase unit is not less than the first preset number.Number at the idle entity erase unit of this hypothesis is not less than the first preset number, and entity erase unit 304 (D+3) (also claiming the 5th entity erase unit) is idle entity erase unit.Logical address 502 (0) is that original mappings is to entity erase unit 304 (0).Memory management circuitry 202 can write to entity erase unit 304 (D+3) with the second sequencing pattern by data 504, and setting entity erase unit 304 (D+3) are continuous write state.In addition, memory management circuitry 202 also can the logical address 502 (0) to entity erase unit 304 (0) remap original mappings to entity erase unit 304 (D+3).On the other hand, if when the number of idle entity erase unit is less than the first preset number, memory management circuitry 202 can be carried out union operation or data be write to idle entity sequencing unit.Yet write operation when idle entity erase unit is not enough has illustrated as above, just repeats no more at this.

When entity erase unit 304 (0) is not continuous write state, whether the memory management circuitry 202 first number of the idle entity erase unit of judgement is not less than the first preset number.If the number of idle entity erase unit is not less than the first preset number, memory management circuitry 202 can obtain an idle entity erase unit (also claiming the 6th entity erase unit), and data 504 are write to so far the 6th entity erase unit with the second sequencing pattern.Yet this step is similar to the example shown in Fig. 8, below will coordinate graphic explanation in the lump.

Fig. 9 A～Fig. 9 C illustrates the process flow diagram of method for writing data according to an embodiment.

Please refer to Fig. 3 and Fig. 9 A, in step S602, memory management circuitry 202 can receive one write instruction, and this writes instruction indication one piece of data is write in the middle of at least one logical address (also claiming the first logical address).Wherein the first logical address is to map to second instance erase unit.

In step S604, whether what memory management circuitry 202 meeting judgements received writes instruction for writing continuously instruction.

If the instruction that writes receiving is not to write continuously instruction,, in step S606, memory management circuitry 202 can write to a 4th entity erase unit by data.And it is not continuous write state that memory management circuitry 202 can be set the 4th entity erase unit.

If the instruction that writes receiving is to write continuously instruction, in step S608, memory management circuitry 202 can judge that whether second instance erase unit is not by sequencing.

If second instance erase unit is not by sequencing, in step S610, memory management circuitry 202 can write to second instance erase unit with the second sequencing pattern by data.

If second instance erase unit is once by sequencing, in step S612, memory management circuitry 202 can judge whether second instance erase unit is continuous write state.

If second instance erase unit is continuous write state, in step S614, memory management circuitry 202 can judge whether second instance erase unit is to write with the first sequencing pattern.

If second instance erase unit is to write with the first sequencing pattern, in step S616, memory management circuitry 202 can judge whether the number of idle entity erase unit is not less than the first preset number.

If the number of idle entity erase unit is not less than the first preset number, in step S618, memory management circuitry 202 can obtain an idle entity erase unit (also claiming the 3rd entity erase unit).Memory management circuitry 202 can write so far the 3rd entity erase unit with the first sequencing pattern by data, and to set the 3rd entity erase unit be continuous write state.

If the number of idle entity erase unit is less than the first preset number, in step S620, memory management circuitry 202 can write to idle entity sequencing unit by data.

If the result at step S614 is "No", please refer to Fig. 9 B, in step S622, memory management circuitry 202 can judge whether the number of idle entity erase unit is not less than the second preset number.If so, in step S624, memory management circuitry 202 can obtain two the 3rd entity erase units, and data are write to the 3rd entity erase unit with the first sequencing pattern, and to set the 3rd entity erase unit be continuous write state.

If the result of step S622 is "No", in step S626, memory management circuitry 202 can judge that the number of idle entity erase unit is not less than the first preset number.

If the result of step S626 is "Yes", in step S628, memory management circuitry 202 can write to a 5th entity erase unit with the second sequencing pattern by data, and to set the 5th entity erase unit be continuous write state.

If the result of step S626 is "No", in step S630, memory management circuitry 202 can write to idle entity sequencing unit by data.

If the result of step S612 is "No", please refer to Fig. 9 C, in step S632, memory management circuitry 202 can judge whether the number of idle entity erase unit is not less than the first preset number.

The result of step S632 is " being ", and in step S634, memory management circuitry 202 can write to a 6th entity erase unit with the second sequencing pattern by data, and sets the 6th entity erase unit and meet continuous write state.

If the result of step S632 is "No", in step S636, memory management circuitry 202 can write to idle entity sequencing unit by data.

In Fig. 9 A～Fig. 9 C, memory management circuitry 202 is first to judge received whether to write instruction for writing continuously instruction, then judges whether data to be write with the first sequencing pattern.Yet in another embodiment, it is all to write continuously instruction that memory management circuitry 202 also can be preset the received instruction that writes, does not therefore judge and whether write instruction for writing continuously instruction.

Please refer to Fig. 3 and Figure 10, in step S 1002, memory management circuitry 202 can receive one and write instruction.This writes instruction indication one piece of data is written to at least one logical address, and this at least one logical address is to map to a second instance erase unit.

In step S 1004, memory management circuitry 202 judges whether second instance erase unit is continuous write state.

If second instance erase unit is continuous write state, in step S 1006, memory management circuitry 202 can write to the 3rd entity erase unit with the first sequencing pattern by data.

If second instance erase unit is not continuous write state, in step S 1008, memory management circuitry 202 can write to an idle entity erase unit with the first sequencing pattern or the second sequencing pattern by data.

Yet in Figure 10, each step has described in detail as above, just repeats no more at this.

Whether it is worth mentioning that, in another embodiment, memory management circuitry 202 as shown in Figure 3 also can logically be divided into one or more entity erase unit a solid element, and be that continuous write state carrys out data writing according to solid element.Specifically, a solid element can comprise 2,4 or 8 entity erase units, but the present invention not subject to the limits.The entity sequencing unit that surpasses a preset ratio in a solid element is by sequencing continuously in a Preset Time, and memory management circuitry 202 can these solid elements of judgement be continuous write state.On the other hand, memory management circuitry 202 also can be grouped into one or more logical address a logical block, and a logical block is to map to a solid element.

Or, between entity erase unit, can be also that the mode with alternating expression (interleave) writes.Fashionable when writing in the mode of alternating expression, the mode that judgement writes continuously can be also alternating expression.For instance, if what host computer system as shown in Figure 1A 1000 was wanted access is to be numbered 0～100 logical address, an entity erase unit can belong in order to storage the data of the logical address of numbering 0,2,4...100, and another entity erase unit can belong in order to storage the data of the logical address of numbering 1,3,5...99.If above-mentioned situation, these two entity erase units also can be continuous write state, and then carry out data by the first sequencing pattern, and the present invention is also not subject to the limits.

In sum, the method for writing data that the embodiment of the present invention proposes, Memory Controller and memory management circuitry, can, when host computer system 1000 as shown in Figure 1A will be to the continuous data of a certain logic region, accelerate the speed that data write.。

Finally it should be noted that: each embodiment, only in order to technical scheme of the present invention to be described, is not intended to limit above; Although the present invention is had been described in detail with reference to aforementioned each embodiment, those of ordinary skill in the art is to be understood that: its technical scheme that still can record aforementioned each embodiment is modified, or some or all of technical characterictic is wherein equal to replacement; And these modifications or replacement do not make the essence of appropriate technical solution depart from the scope of various embodiments of the present invention technical scheme.

Claims

1. a method for writing data, be used for controlling a duplicative non-volatile memory module, wherein this duplicative non-volatile memory module comprises a plurality of entity erase units, each those entity erase unit comprises a plurality of entity sequencing unit group, each those entity sequencing unit group comprises a plurality of entity sequencing unit, those entity sequencing unit of each those entity sequencing unit group comprise entity sequencing unit on the unit of entity sequencing and, wherein, the speed of those lower entity sequencing unit programs is faster than entity sequencing unit on those, a plurality of logical addresses are a plurality of first instance erase units that map in those entity erase units, it is characterized in that, this method for writing data comprises:

Receive one first and write instruction, this first writes instruction indication and one data is write to at least one first logical address of those logical addresses, and wherein this at least one first logical address is the second instance erase unit mapping in those first instance erase units;

Judge whether this second instance erase unit is a continuous write state, those entity sequencing unit that this continuous write state represents in this second instance erase unit to surpass a preset ratio in a Preset Time once by sequencing continuously; And

If this second instance erase unit is this continuous write state, these data are write to one the 3rd entity erase unit in those entity erase units with one first sequencing pattern, wherein this first sequencing modal representation on those entity sequencing unit be non-program.

2. method for writing data according to claim 1, is characterized in that, before judging whether this second instance erase unit is the step of this continuous write state, this method for writing data also comprises:

Judge that first whether write instruction be one to write continuously instruction for this, wherein this writes continuously instruction and represents that this at least one first logical address is to write after instruction indication wants the logical address of access one second, and this second write instruction be received in this first write instruction before.

3. method for writing data according to claim 2, is characterized in that, also comprises:

If this first writes instruction for this writes instruction continuously, these data are write to one the 4th entity erase unit in those entity erase units; And

Setting the 4th entity erase unit is not this continuous write state.

4. method for writing data according to claim 1, is characterized in that, before judging whether this second instance erase unit is the step of this continuous write state, this method for writing data also comprises:

Judge that whether this second instance erase unit was for not being written into; And

If this second instance erase unit was not written into, these data are write to this second instance erase unit with one second sequencing pattern, wherein those entity sequencing unit of this second sequencing modal representation can be by sequencing.

5. method for writing data according to claim 1, it is characterized in that, if this second instance erase unit is this continuous write state, the step that these data are write to the 3rd entity erase unit in those entity erase units with the first sequencing pattern comprises:

Judge whether this second instance erase unit is to write with this first sequencing pattern;

If this second instance erase unit is to write with this first sequencing pattern, judge whether the number of the idle entity erase unit of one in those entity erase units is not less than one first preset number; And

If the number of this idle entity erase unit is not less than this first preset number, these data are write to the 3rd entity erase unit with this first sequencing pattern; And

Setting the 3rd entity erase unit is this continuous write state.

6. method for writing data according to claim 1, is characterized in that, if this second instance erase unit is this continuous write state, the step that these data are write to the 3rd entity erase unit with this first sequencing pattern comprises:

If this second instance erase unit is not to write with this first sequencing pattern, judge whether the number of the idle entity erase unit of one in those entity erase units is not less than one second preset number; And

If the number of this idle entity erase unit is not less than this second preset number, these data are write to the 3rd entity erase unit with this first sequencing pattern, and to set the 3rd entity erase unit be this continuous write state.

7. method for writing data according to claim 6, also comprises:

If the number of this idle entity erase unit is less than this second preset number, judge whether the number of this idle entity erase unit is not less than one first preset number, wherein this second preset number is greater than this first preset number;

If the number of this idle entity erase unit is not less than this first preset number, these data are write to one the 5th entity erase unit in those entity erase units with one second sequencing pattern, and wherein those entity sequencing unit of this second sequencing modal representation can be by sequencing; And

Setting the 5th entity erase unit is this continuous write state.

8. method for writing data according to claim 1, also comprises:

If this second instance erase unit is not this continuous write state, judge whether the number of an idle entity erase unit in those entity erase units is not less than one first preset number;

If the number of this idle entity erase unit is not less than this first preset number, these data are write to one the 6th entity erase unit in those entity erase units with one second sequencing pattern, and wherein those entity sequencing unit of this second sequencing modal representation can be by sequencing; And

Setting the 6th entity erase unit is this continuous write state.

9. a memory storage apparatus, is characterized in that, comprising:

A connector, in order to be electrically connected to a host computer system;

One duplicative non-volatile memory module, comprise a plurality of entity erase units, wherein each those entity erase unit comprises a plurality of entity sequencing unit group, each those entity sequencing unit group comprises a plurality of entity sequencing unit, those entity sequencing unit of each those entity sequencing unit group comprise entity sequencing unit on the unit of entity sequencing and, wherein, the speed of these lower entity sequencing unit programs is faster than entity sequencing unit on these, and a plurality of logical addresses are a plurality of first instance erase units that map in those entity erase units, and

One Memory Controller, be electrically connected to this connector and this duplicative non-volatile memory module, in order to receive one first, write instruction, wherein this first writes instruction indication and one data is write to at least one first logical address of those logical addresses, and this at least one first logical address is the second instance erase unit mapping in those first instance erase units

This Memory Controller is also in order to judge whether this second instance erase unit is a continuous write state, those entity sequencing unit that wherein this continuous write state represents in this second instance erase unit to surpass a preset ratio in a Preset Time once by sequencing continuously

If this second instance erase unit is this continuous write state, this Memory Controller is also in order to write to these data one the 3rd entity erase unit of those entity erase units with one first sequencing pattern, wherein this first sequencing modal representation on those entity sequencing unit be non-program.

10. according to the memory storage apparatus described in claim the 9, it is characterized in that, this Memory Controller is also in order to judge that first whether write instruction be one to write continuously instruction for this, wherein this writes continuously instruction and represents that this at least one first logical address is to write after instruction indication wants the logical address of access one second, and this second write instruction by this Memory Controller be received in this first write instruction before.

11. memory storage apparatus according to claim 10, it is characterized in that, if this first writes instruction for this writes instruction continuously, this Memory Controller is also in order to these data are write to one the 4th entity erase unit in those entity erase units, and to set the 4th entity erase unit be not this continuous write state.

12. memory storage apparatus according to claim 9, is characterized in that, this Memory Controller is also in order to judge whether this second instance erase unit was not written into,

If this second instance erase unit was not written into, this Memory Controller is also in order to write to this second instance erase unit by these data with one second sequencing pattern, and wherein those entity sequencing unit of this second sequencing modal representation can be by sequencing.

13. memory storage apparatus according to claim 9, is characterized in that, this Memory Controller is also in order to judge whether this second instance erase unit is to write with this first sequencing pattern,

If this second instance erase unit is to write with this first sequencing pattern, this Memory Controller is also in order to judge whether the number of the idle entity erase unit of one in those entity erase units is not less than one first preset number,

If the number of this idle entity erase unit is not less than this first preset number, this Memory Controller is also in order to these data are write to the 3rd entity erase unit with this first sequencing pattern, and to set the 3rd entity erase unit be this continuous write state.

14. memory storage apparatus according to claim 9, is characterized in that, this Memory Controller is also in order to judge whether this second instance erase unit is to write with this first sequencing pattern,

If this second instance erase unit is not to write with this first sequencing pattern, this Memory Controller is also in order to judge whether the number of the idle entity erase unit of one in those entity erase units is not less than one second preset number,

If the number of this idle entity erase unit is not less than this second preset number, this Memory Controller is also in order to these data are write to the 3rd entity erase unit with this first sequencing pattern, and to set the 3rd entity erase unit be this continuous write state.

15. memory storage apparatus according to claim 14, it is characterized in that, if the number of this idle entity erase unit is less than this second preset number, this Memory Controller is also in order to judge whether the number of this idle entity erase unit is not less than one first preset number, wherein this second preset number is greater than this first preset number

If the number of this idle entity erase unit is not less than this first preset number, this Memory Controller is also in order to write to this data one second sequencing pattern one the 5th entity erase unit of those entity erase units, wherein those entity sequencing unit of this second sequencing modal representation can be by sequencing

This Memory Controller is also this continuous write state in order to set the 5th entity erase unit.

16. memory storage apparatus according to claim 9, it is characterized in that, if this second instance erase unit is not this continuous write state, this Memory Controller is also in order to judge whether the number of an idle entity erase unit in those entity erase units is not less than one first preset number

If the number of this idle entity erase unit is not less than this first preset number, this Memory Controller is also in order to these data are write to one the 6th entity erase unit in those entity erase units with this first sequencing pattern, and to set the 6th entity erase unit be this continuous write state.

17. 1 kinds of Memory Controllers, for controlling a duplicative non-volatile memory module, is characterized in that, this Memory Controller comprises:

One host interface, in order to be electrically connected to a host computer system;

One memory interface, in order to be electrically connected to this duplicative non-volatile memory module, wherein this duplicative non-volatile memory module comprises a plurality of entity sequencing unit, each those entity sequencing unit group comprises a plurality of entity sequencing unit, those entity sequencing unit of each those entity sequencing unit group comprise entity sequencing unit on the unit of entity sequencing and, wherein, the speed of these lower entity sequencing unit programs is faster than entity sequencing unit on these, and a plurality of logical addresses are a plurality of first instance erase units that map in those entity erase units, and

One memory management circuitry, be electrically connected to this host interface and this memory interface, in order to receive one first, write instruction, wherein this first writes instruction indication and one data is write to at least one first logical address of those logical addresses, and this at least one first logical address is the second instance erase unit mapping in those first instance erase units

This memory management circuitry is also in order to judge whether this second instance erase unit is a continuous write state, those entity sequencing unit that wherein this continuous write state represents in this second instance erase unit to surpass a preset ratio in a Preset Time once by sequencing continuously

If this second instance erase unit is this continuous write state, this memory management circuitry is also in order to write to these data one the 3rd entity erase unit of those entity erase units with one first sequencing pattern, wherein this first sequencing modal representation on those entity sequencing unit be non-program.

18. Memory Controllers according to claim 17, it is characterized in that, this memory management circuitry is also in order to judge that first whether write instruction be one to write continuously instruction for this, wherein this writes continuously instruction and represents that this at least one first logical address is to write after instruction indication wants the logical address of access one second, and this second write instruction by this memory management circuitry be received in this first write instruction before.

19. Memory Controllers according to claim 18, it is characterized in that, if this first writes instruction for this writes instruction continuously, this memory management circuitry is also in order to these data are write to one the 4th entity erase unit in those entity erase units, and to set the 4th entity erase unit be not this continuous write state.

20. Memory Controllers according to claim 17, is characterized in that, this memory management circuitry is also in order to judge whether this second instance erase unit was not written into,

If this second instance erase unit was not written into, this memory management circuitry is also in order to write to this second instance erase unit by these data with one second sequencing pattern, and wherein those entity sequencing unit of this second sequencing modal representation can be by sequencing.

21. Memory Controllers according to claim 17, is characterized in that, this memory management circuitry is also in order to judge whether this second instance erase unit is to write with this first sequencing pattern,

If this second instance erase unit is to write with this first sequencing pattern, this memory management circuitry is also in order to judge whether the number of the idle entity erase unit of one in those entity erase units is not less than one first preset number,

If the number of this idle entity erase unit is not less than this first preset number, this memory management circuitry is also in order to these data are write to the 3rd entity erase unit with this first sequencing pattern, and to set the 3rd entity erase unit be this continuous write state.

22. Memory Controllers according to claim 17, is characterized in that, this memory management circuitry is also in order to judge whether this second instance erase unit is to write with this first sequencing pattern,

If this second instance erase unit is not to write with this first sequencing pattern, this memory management circuitry is also in order to judge whether the number of the idle entity erase unit of one in those entity erase units is not less than one second preset number,

If the number of this idle entity erase unit is not less than this second preset number, this memory management circuitry is also in order to these data are write to the 3rd entity erase unit with this first sequencing pattern, and to set the 3rd entity erase unit be this continuous write state.

23. Memory Controllers according to claim 22, it is characterized in that, if the number of this idle entity erase unit is less than this second preset number, this memory management circuitry is also in order to judge whether the number of this idle entity erase unit is not less than one first preset number, wherein this second preset number is greater than this first preset number

If the number of this idle entity erase unit is not less than this first preset number, this memory management circuitry is also in order to write to this data one second sequencing pattern one the 5th entity erase unit of those entity erase units, wherein those entity sequencing unit of this second sequencing modal representation can be by sequencing

This memory management circuitry is also this continuous write state in order to set the 5th entity erase unit.

24. Memory Controllers according to claim 17, it is characterized in that, if this second instance erase unit is not this continuous write state, this memory management circuitry is also in order to judge whether the number of an idle entity erase unit in those entity erase units is not less than one first preset number

If the number of this idle entity erase unit is not less than this first preset number, this memory management circuitry is also in order to these data are write to one the 6th entity erase unit in those entity erase units with this first sequencing pattern, and to set the 6th entity erase unit be this continuous write state.