CN102866955A - Flash data management method and system - Google Patents
Flash data management method and system Download PDFInfo
- Publication number
- CN102866955A CN102866955A CN2012103414635A CN201210341463A CN102866955A CN 102866955 A CN102866955 A CN 102866955A CN 2012103414635 A CN2012103414635 A CN 2012103414635A CN 201210341463 A CN201210341463 A CN 201210341463A CN 102866955 A CN102866955 A CN 102866955A
- Authority
- CN
- China
- Prior art keywords
- page
- logical
- lpage
- physical
- buffer memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/0292—User address space allocation, e.g. contiguous or non contiguous base addressing using tables or multilevel address translation means
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
- G06F12/0871—Allocation or management of cache space
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0893—Caches characterised by their organisation or structure
- G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/10—Providing a specific technical effect
- G06F2212/1016—Performance improvement
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/72—Details relating to flash memory management
- G06F2212/7201—Logical to physical mapping or translation of blocks or pages
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/72—Details relating to flash memory management
- G06F2212/7203—Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System (AREA)
Abstract
The invention is adapted to the technical field of a solid-state storage technology, in particular to a flash data management method and a flash data management system. The flash data management method comprises the following steps of: managing address mapping, building a logic physical address mapping table mapped on the same physical page by a plurality of logic pages, setting the logic pages as index of the logic physical address mapping table, wherein each logic page corresponds to a physical page value, the physical page value comprises data segments of index values which respectively point to the actual physical page address and correspond to one of the logic pages, and arbitrary logic sequences between the plurality of logic pages in the physical page are relevant; and mapping the logic page to the physical page and updating the logic physical mapping table during writing data operation, or reading the logic physical address mapping table according to the logic pages during reading data operation, and indexing to the corresponding physical page. Therefore, the plurality of logic pages can be mapped to the same physical page according to the size of the physical page and the sizes of the logic pages, reduction of ready-modify-write (RMW) operation is facilitated, and the writing performance is improved.
Description
Technical field
The present invention relates to the solid state storage technologies field, relate in particular to a kind of flash data management method and system.
Background technology
FTL (Flash Translation layer at existing solid state hard disc, flash translation layer (FTL)) in, based on the page or leaf mapping techniques all be with the physical page size of NAND FLASH (NAND type flash memory) as the logical page (LPAGE) size, namely Physical Page and logical page (LPAGE) are one to one.Although the minimum operation unit of host computer system is logical block, its size is 512B, but actual reading and writing of files is 4KB (being determined by file system) often, and the physical page size of NAND FLASH in the past all is to be not more than 4KB, so need not to distinguish logical page (LPAGE) and Physical Page.But the physical page size of NAND FLASH mainly is 8KB/16KB at present, even larger.In this case, still adopt Physical Page as logical page (LPAGE), the main frame random writing can produce the operation of a large amount of 4KB sizes, and the granularity of operation and actual physics page or leaf size produces contradiction so.As shown in Figure 1, when main frame (host) write the 4KB data, solid state hard disc at first read the 12K data according to mapping table from Physical Page (PPA) x, and after the merging of the 4KB data of main frame, write among the Physical Page t again.Namely produce a large amount of RMW (Read-Modify-Write reads-revise-write) operation, not only affect write performance, and make the rubbish page or leaf reclaim frequent occurrence, it is large that thereby WA (Write Amplification writes amplification) becomes, and reduces the life-span of solid state hard disc.
In summary, existing flash data management method and system obviously exist inconvenience and defective in actual use, so be necessary to be improved.
Summary of the invention
For above-mentioned defective, the object of the present invention is to provide a kind of flash data management method and system, can according to physical page size and logical page (LPAGE) size cases, a plurality of logical page (LPAGE)s be mapped in the Same Physical page or leaf, be conducive to reduce the generation of RMW, improve write performance.
To achieve these goals, the invention provides a kind of flash data management method, described method comprises:
Set up the logical physical address mapping table that a plurality of logical page (LPAGE)s are mapped to the Same Physical page or leaf, described logical physical address mapping table is take logical page (LPAGE) as index, the corresponding Physical Page value of each logical page (LPAGE), this Physical Page value comprises the data segment of the index value that points to respectively actual physics page address and a corresponding logical page (LPAGE);
When data writing operation, this logical page (LPAGE) is mapped to a Physical Page and upgrades described logical physical mapping table, perhaps when read data operates, then read the logical physical address mapping table according to described logical page (LPAGE), index corresponding Physical Page.
According to flash data management method of the present invention, described this logical page (LPAGE) is mapped to a Physical Page and upgrades also comprise before the logical physical mapping table:
A plurality of logical blocks that file system is sent are logical page (LPAGE) according to the size conversion of logical page (LPAGE);
Judge whether Physical Page needs to upgrade;
Be then to obtain new Physical Page as up-to-date Physical Page and the Physical Page updating mark is set, otherwise the Physical Page updating mark directly is set.
According to flash data management method of the present invention, judge that the step whether Physical Page needs to upgrade is specially:
Whether at first inquire about the updating mark value of up-to-date Physical Page of current record greater than threshold value, this threshold value is the number of the logical page (LPAGE) of corresponding Same Physical page or leaf;
If upgrade Physical Page greater than needs, then do not need to upgrade Physical Page if be not more than.
According to flash data management method of the present invention, describedly read the logical physical mapping table according to this logical page (LPAGE), also comprise before indexing the step of corresponding Physical Page:
Whether the decision logic page or leaf is invalid logical page (LPAGE);
Operate if then directly current Physical Page is passed to the flash memory management module, more current Physical Page is passed to the flash memory management module after the described logical physical address mapping table and operate otherwise upgrade according to described logical page (LPAGE).
According to flash data management method of the present invention, describedly read the logical physical address mapping table according to this logical page (LPAGE), also comprise before indexing the step of corresponding Physical Page;
A plurality of logical blocks that file system is sent are logical page (LPAGE) according to the size conversion of logical page (LPAGE).
According to flash data management method of the present invention, describedly read the logical physical address mapping table according to this logical page (LPAGE), also comprise after indexing the step of corresponding Physical Page;
Check whether this Physical Page is without mapping;
If it is arrange without mapping and indicate that then this Physical Page being passed to the flash memory management module operates; Otherwise directly this Physical Page being passed to the flash memory management module operates.
According to flash data management method of the present invention, described method also comprises:
Set up other second level buffer memory of a plurality of logical page (LPAGE) levels and other first order buffer memory of Physical Page level;
The start logical block that receive data management channels data writing is operated and logic length;
The logical block that writes according to the large young pathbreaker of logical page (LPAGE) changes into logical page (LPAGE);
Judge whether described logical page (LPAGE) hits described second level buffer memory, if hit then according to data in the buffer memory of the described second level of the information updating of the contained logical block of logical page (LPAGE), if missly judge whether described first order buffer memory overflows;
If do not overflow, this logical page (LPAGE) as new second level buffer memory, is upgraded described first order buffer memory;
Write flash memory if overflow then the data in first order buffer memory and the second level buffer memory to be brushed out, create a new first order buffer memory, this logical page (LPAGE) as new second level buffer memory, and is upgraded described first order buffer memory.
According to flash data management method of the present invention, described method also comprises: when host requirements or overtime, the data in described first order buffer memory and the second level buffer memory are write in the flash memory.
According to flash data management method of the present invention, when host requirements or overtime, the step that the data in described first order buffer memory and the second level buffer memory are write in the flash memory is specially:
Check whether there is described first order buffer memory;
If otherwise end operation is whether described second level buffer memory number reaches threshold value if then check;
If reach threshold value, then the output of the data in described first order buffer memory and the second level buffer memory is stored;
If do not reach threshold value, then after the additional invalid logical page (LPAGE) data output of the data in described first order buffer memory and the second level buffer memory is stored.
The present invention is corresponding to provide a kind of flash data management system, and described system comprises:
Mapping management unit, address, be used for setting up the logical physical address mapping table that a plurality of logical page (LPAGE)s are mapped to the Same Physical page or leaf, described logical physical mapping table is take logical page (LPAGE) as index, the corresponding Physical Page value of each logical page (LPAGE), described Physical Page value comprises the data segment of the index value that points to respectively actual physics page address and a corresponding logical page address; Mapping management unit, address also is used for when data writing operation described logical page (LPAGE) is mapped to a Physical Page and upgrades the logical physical address mapping table, perhaps when read data operates, then read the logical physical address mapping table according to described logical page (LPAGE), index corresponding Physical Page.
Data cache management unit is set up two-level cache mechanism, is divided into logical page (LPAGE) level buffer memory and Physical Page level buffer memory, the data that main frame is write, carry out hitting, force to refresh or the management such as overtime of L2 cache, according to the different set condition, the data in the buffer memory are brushed out write flash memory at last.
In the mapping algorithm of the present invention, has a logical page (LPAGE) in the same Physical Page at least, mapping table is as index with logical page address, its intermediate value is corresponding Physical Page value, and this Physical Page value contains two data segments, be respectively the index value that points to actual physics page address and corresponding certain physical page address, the logical page (LPAGE) that is to say the Same Physical page or leaf is to realize distinguishing by index value, does not have any relation between a plurality of logical page (LPAGE)s.Can a plurality of logical page (LPAGE)s be mapped in the Same Physical page or leaf according to physical page size and logical page (LPAGE) size cases, realize that a plurality of logical page (LPAGE) write operations change into the Physical Page write operation one time, thereby reduced the RMW operation, improve write performance.Whereby, the present invention can be mapped to a plurality of logical page (LPAGE)s in the Same Physical page or leaf according to physical page size and logical page (LPAGE) size cases, is conducive to reduce the generation of RMW, improves write performance.
Description of drawings
Fig. 1 is the RMW operation chart of existing flash memory mapping mechanism;
Fig. 2 is the process flow diagram of a kind of flash data management method of the present invention;
Fig. 3 is the synoptic diagram that among the present invention a plurality of logical page (LPAGE)s is mapped to a Physical Page;
Fig. 4 is the synoptic diagram of the logical physical address mapping table of an embodiment of the present invention;
Fig. 5 is the process flow diagram of the mapping process of the write operation of embodiment among the present invention one;
Fig. 6 is the process flow diagram of mapping process of the read operation of an embodiment of the present invention;
Fig. 7 is the synoptic diagram that the two-stage of an embodiment of the present invention is write caching mechanism;
Fig. 8 is the buffer memory process flow diagram of the write operation of an embodiment of the present invention;
Fig. 9 be among the present invention when host requirements or overtime, the data in first order buffer memory and the second level buffer memory are write a kind of specific embodiment process flow diagram in the flash memory; And
Figure 10 is the principle assumption diagram of a kind of flash data management system of the present invention.
Embodiment
In order to make purpose of the present invention, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, is not intended to limit the present invention.
As shown in Figure 2, a kind of flash data management method of the present invention comprises:
Step S201, set up the logical physical address mapping table that a plurality of logical page (LPAGE)s are mapped to the Same Physical page or leaf, the logical physical address mapping table is take logical page (LPAGE) as index, the corresponding Physical Page value of each logical page (LPAGE), this Physical Page value comprises the data segment of the index value that points to respectively actual physics page address and a corresponding logical page (LPAGE).
Step S202 is mapped to this logical page (LPAGE) one Physical Page and upgrades the logical physical address mapping table when data writing operation, perhaps then read the logical physical address mapping table according to this logical page (LPAGE) when read data operates, and indexes corresponding Physical Page.
A plurality of logical page (LPAGE)s involved in the present invention are mapped to the technical scheme of Same Physical page or leaf for convenience of description, in the embodiment shown in fig. 3 the size of logical page (LPAGE) and Physical Page is specialized, take logical page (LPAGE) as 4K, Physical Page is that 16K is example, certainly in the practical embodiments, the size of logical page (LPAGE) and Physical Page all is configurable (such as 4K/8K/16K/32KBytes).As can be seen from Fig. 3, using least unit in host side (host) is with logical block (LBA, 512Bytes), the least unit of flash translation layer (FTL) of the present invention (FTL) is logical page (LPAGE) (LPA, 4KBytes), and the least unit Physical Page (PPA, 16Kbytes) of NAND FLASH (NAND type flash memory) end.The conversion of size unit from the logical block to the logical page (LPAGE), without mapping relations, namely such as LBA0～LBA8 in LPA0.And logical page (LPAGE) is mapping relations to Physical Page, and namely LPA0 and uncertain in which Physical Page need to have the logical physical address mapping table to determine.In same Physical Page, maximum can be held 4 logical page (LPAGE)s, still owing to the restriction of host requirements and timeout mechanism, can exist to be less than 4 logical page (LPAGE)s, this programme is taked the method for the invalid logical page (LPAGE) of additional some, makes the data that 4 logical page (LPAGE)s are arranged in the Physical Page all the time.
In the mapping algorithm of the present invention, have in the same Physical Page and have an effective logical page (LPAGE) at least, mapping table be with logical page address as index, its intermediate value is corresponding Physical Page value.And this Physical Page value contains two data segments, is respectively the index value that points to actual physics page address and corresponding certain logical page (LPAGE), and the logical page (LPAGE) that is to say the Same Physical page or leaf is to realize distinguishing by index value.Such as LPA1 and LPA8, be present in simultaneously in the PPA5, in the mapping algorithm, the PPA value that LPA1 is corresponding is respectively PPA5 and index 0, and PPA value corresponding to LPA1 is respectively PPA5 and index 1.Simultaneously, do not have any relation between a plurality of logical page (LPAGE)s, as shown in Figure 3, Figure 4, two and discontinuous LPA_n and LPA_s are in mapping table (Mapping Table), corresponding (mapping) be same PPA_t, i.e. LPA_n and LPA_m PPA_t of correspondence all.
In the mapping algorithm of the present invention, has a logical page (LPAGE) in the same Physical Page at least, mapping table is as index with logical page address, its intermediate value is corresponding Physical Page value, and this Physical Page value contains two data segments, be respectively the index value that points to actual physics page address and corresponding certain physical page address, the logical page (LPAGE) that is to say the Same Physical page or leaf is to realize distinguishing by index value, does not have any relation between a plurality of logical page (LPAGE)s.Can a plurality of logical page (LPAGE)s be mapped in the Same Physical page or leaf according to physical page size and logical page (LPAGE) size cases, realize that a plurality of logical page (LPAGE) write operations change into the Physical Page write operation one time, thereby reduced the RMW operation, improve write performance.Whereby, the present invention can be mapped to a plurality of logical page (LPAGE)s in the Same Physical page or leaf according to physical page size and logical page (LPAGE) size cases, is conducive to reduce the generation of RMW, improves write performance.
Fig. 5 is the process flow diagram of mapping process of the write operation of one embodiment of the invention, and this flow process mainly comprises the steps:
Step S501, a plurality of logical blocks that file system is sent are logical page (LPAGE) according to the size conversion of logical page (LPAGE).
Step S502 judges whether Physical Page needs to upgrade.Be then to enter step S503, otherwise enter step S504.
Step S503 obtains new Physical Page as up-to-date Physical Page, enters step S504.Judge that the step whether Physical Page needs to upgrade is specially: whether at first inquire about the updating mark value of up-to-date Physical Page of current record greater than threshold value, this threshold value is the number of the logical page (LPAGE) of corresponding Same Physical page or leaf; If upgrade Physical Page greater than needs, then do not need to upgrade Physical Page if be not more than.Wherein, value of statistical indicant is software variable, in internal memory.As long as read this value during use.Threshold value is that the concrete logical page (LPAGE) of set basis and physical page size determine, comprises 4 logical page (LPAGE)s such as setting Physical Page, and then threshold value is 4.
Step S504 arranges the Physical Page updating mark.
Step S505, whether the decision logic page or leaf is invalid logical page (LPAGE).If then enter step S507, otherwise enter step S506.
Step S506 upgrades the logical physical address mapping table according to logical page (LPAGE), enters step S507.In this step, need this logical page (LPAGE) is mapped to current Physical Page and upgrades the logical physical address mapping table.
Step S507 passes to the flash memory management module with current Physical Page and operates.
Fig. 6 is the process flow diagram of mapping process of the read operation of an embodiment of the present invention, and this flow process mainly comprises the steps:
Step S601, a plurality of logical blocks that file system is sent are logical page (LPAGE) according to the size conversion of logical page (LPAGE).
Step S602 reads the logical physical address mapping table according to this logical page (LPAGE), indexes corresponding Physical Page.
Step S603 checks whether this Physical Page is without mapping.If yes then enter step S604, otherwise enter step S605.For the zone that main frame was never write, software shines upon these zones without any the actual physics page or leaf, is referred to as without mapping.
Step S604 arranges without the mapping sign, and enters step S605.
Step S605 passes to the flash memory management module with this Physical Page and operates.Physical Page is delivered to the flash memory management module by the mode of software global variable.
In the present invention, owing to the mapping method of the corresponding Physical Page of many logical page (LPAGE)s, must need to consider to control the problem of granularity and time degree, on data are processed, the present invention is by adopting two-stage to write mechanism, a plurality of other buffer memorys of logical page (LPAGE) level and a Physical Page rank buffer memory of buffer memory.
As shown in Figure 7, of the present invention writing in the cache algorithm adopts the mode of software administration internal memory to realize two-level cache mechanism: logical page (LPAGE) rank buffer memory and Physical Page rank buffer memory.
Logical page (LPAGE) rank buffer memory (second level buffer memory) is used in certain hour, as long as write when dropping on same logical page (LPAGE) such as logical block these data of buffer memory.Such as Fig. 7 for the position of logical block in logical page (LPAGE) without limits, can allow to produce " cavity " (laying respectively at logical page (LPAGE) end to end such as two logical blocks) and overlapping (the logical block interval of two orders is overlapping).Because a plurality of logical page (LPAGE) buffer memorys are arranged, thus can be behind the logical block of some, continue the logical block of cache hit (order write LPA the same with the LPA of record in the buffer memory).
Physical Page rank buffer memory (first order buffer memory) is used for a plurality of logical page (LPAGE)s of buffer memory in the management certain hour.This Physical Page rank buffer memory (overflows) when logical page (LPAGE) satisfies the Physical Page requirement for the logical page (LPAGE) out-of-order requirement of buffer memory, just writes among the NAND FLASH data cached; Perhaps when host requirements or overtime, after the invalid logical page (LPAGE) data of additional some, write among the NAND FLASH.Host requirements refers in the SSD standard, and main frame sends Cache Flush order when thinking need to be with the data Flush in the SSD buffer memory time, and Flush exports the data of buffer zone by force, namely empties buffer data; Overtime refer to main frame in setting-up time without any action, exceed this time to be referred to as overtime.
Fig. 8 is the buffer memory process flow diagram of the write operation of an embodiment of the present invention, and this flow process comprises:
Step S801 sets up other second level buffer memory of a plurality of logical page (LPAGE) levels and other first order buffer memory of Physical Page level.
Step S802, the start logical block that receive data management channels data writing is operated and logic length.
Step S803, the logical block that writes according to the large young pathbreaker of logical page (LPAGE) changes into logical page (LPAGE), processes.
Whether step S804, decision logic page or leaf hit certain second level buffer memory, are then to enter step S805, otherwise enter step S806.
Step S805 is if hit then according to data in the information updating second level buffer memory of the contained logical block of logical page (LPAGE).
Step S806 judges whether first order buffer memory overflows; If then enter step S807, otherwise enter step S809.
Step S807 brushes out the data in first order buffer memory and the second level buffer memory and writes flash memory, and the data that are about in first order buffer memory and the second level buffer memory write in the flash memory, enter step S808.
Step S808 creates new first order buffer memory, and enters step S809.
Step S809 as new second level buffer memory, upgrades described first order buffer memory with this logical page (LPAGE).
Fig. 9 be among the present invention when host requirements or overtime, the data in first order buffer memory and the second level buffer memory are write a kind of specific embodiment process flow diagram in the flash memory, this flow process comprises the steps:
Step S901 checks whether there is first order buffer memory, namely checks whether there is Physical Page rank buffer memory.If then enter step S902, otherwise end operation.
Step S902 checks whether second level buffer memory number reaches threshold value, reaches threshold value and then enters step S904, does not reach threshold value and then enters step S903.
Step S903 replenishes invalid logical page (LPAGE) data, and enters step S904.Replenishing invalid logical page (LPAGE) data is specially: choose the logical page (LPAGE) value of a main frame outside visible as invalid logical page (LPAGE), choose the data (any data all can) of one section logical page (LPAGE) length at internal memory.For example, in same Physical Page, maximum can be held 4 logical page (LPAGE)s, but because the restriction of host requirements and timeout mechanism, can exist and be less than 4 logical page (LPAGE)s, this programme is taked the method for the invalid logical page (LPAGE) of additional some, makes the data that 4 logical page (LPAGE)s are arranged in the Physical Page all the time.
Step S904 stores the data output of first order buffer memory and second level buffer memory.
The present invention writes the mechanism of buffer memory by adopting two-stage on data are processed, a plurality of logical page (LPAGE) levels other buffering and a Physical Page rank buffer memory.A plurality of logical page (LPAGE) ranks are cached with to be beneficial to provides logical block to hit probability.Other buffer memory of Physical Page level effectively the steering logic page or leaf quantity and refresh opportunity, thereby reach balance between write performance and the data buffer storage, prevent that long-time data are not in the write store.
As shown in figure 10, the present invention is corresponding to provide a kind of flash data management system 100, and system 100 comprises:
Mapping management unit, address 10, be used for setting up the logical physical address mapping table that a plurality of logical page (LPAGE)s are mapped to the Same Physical page or leaf, described logical physical mapping table is take logical page (LPAGE) as index, the corresponding Physical Page value of each logical page (LPAGE), described this Physical Page value comprises the data segment of the index value that points to respectively actual physics page address and a corresponding logical page address; Mapping management unit, address 10 also is used for when data writing operation this logical page (LPAGE) is mapped to a Physical Page and upgrades the logical physical address mapping table, perhaps when read data operates, then read the logical physical address mapping table according to this logical page (LPAGE), index corresponding Physical Page.
Data cache management unit 20 is used for setting up two-level cache mechanism, is divided into logical page (LPAGE) level buffer memory and Physical Page buffer memory, with data buffer memory progressively, when reaching a physical page size or overtime and main frame requirement when refreshing, writes in the flash memory data cached.
In sum, in the mapping algorithm of the present invention, has a logical page (LPAGE) in the same Physical Page at least, mapping table is as index with logical page address, its intermediate value is corresponding Physical Page value, and this Physical Page value contains two data segments, is respectively the index value that points to actual physics page address and corresponding certain physical page address, the logical page (LPAGE) that is to say the Same Physical page or leaf is to realize distinguishing by index value, does not have any relation between a plurality of logical page (LPAGE)s.Can a plurality of logical page (LPAGE)s be mapped in the Same Physical page or leaf according to physical page size and logical page (LPAGE) size cases, realize that a plurality of logical page (LPAGE) write operations change into the Physical Page write operation one time, thereby reduced the RMW operation, improve write performance.Whereby, the present invention can be mapped to a plurality of logical page (LPAGE)s in the Same Physical page or leaf according to physical page size and logical page (LPAGE) size cases, is conducive to reduce the generation of RMW, improves write performance.
Certainly; the present invention also can have other various embodiments; in the situation that does not deviate from spirit of the present invention and essence thereof; those of ordinary skill in the art work as can make according to the present invention various corresponding changes and distortion, but these corresponding changes and distortion all should belong to the protection domain of the appended claim of the present invention.
Claims (10)
1. a flash data management method is characterized in that, described method comprises:
Set up the logical physical address mapping table that a plurality of logical page (LPAGE)s are mapped to the Same Physical page or leaf, described logical physical address mapping table is take described logical page (LPAGE) as index, the corresponding Physical Page value of each logical page (LPAGE), this Physical Page value comprises the data segment of the index value that points to respectively actual physics page address and a corresponding logical page (LPAGE);
When data writing operation, this logical page (LPAGE) is mapped to a Physical Page and upgrades described logical physical mapping table, perhaps when read data operates, then read the logical physical address mapping table according to described logical page (LPAGE), index corresponding Physical Page.
2. flash data management method according to claim 1 is characterized in that, describedly also comprises before this logical page (LPAGE) being mapped to a Physical Page and upgrading the step of logical physical mapping table:
A plurality of logical blocks that file system is sent are logical page (LPAGE) according to the size conversion of logical page (LPAGE);
Judge whether Physical Page needs to upgrade;
Be then to obtain new Physical Page as up-to-date Physical Page and the Physical Page updating mark is set, otherwise the Physical Page updating mark directly is set.
3. flash data management method according to claim 2 is characterized in that, the described step of judging whether Physical Page needs to upgrade is specially:
Whether at first inquire about the updating mark value of up-to-date Physical Page of current record greater than threshold value, this threshold value is the number of the logical page (LPAGE) of corresponding Same Physical page or leaf;
If upgrade Physical Page greater than needs, then do not need to upgrade Physical Page if be not more than.
4. flash data management method according to claim 1 is characterized in that, describedly reads the logical physical mapping table according to this logical page (LPAGE), also comprises before indexing the step of corresponding Physical Page:
Whether the decision logic page or leaf is invalid logical page (LPAGE);
Directly current Physical Page is passed to the flash memory management module and operate if then need not to upgrade the logical physical address mapping table, more current Physical Page is passed to the flash memory management module after the described logical physical address mapping table and operate otherwise upgrade according to described logical page (LPAGE).
5. flash data management method according to claim 1 is characterized in that, describedly reads the logical physical address mapping table according to this logical page (LPAGE), also comprises before indexing the step of corresponding Physical Page;
A plurality of logical blocks that file system is sent are logical page (LPAGE) according to the size conversion of logical page (LPAGE).
6. flash data management method according to claim 1 is characterized in that, describedly reads the logical physical address mapping table according to this logical page (LPAGE), also comprises after indexing the step of corresponding Physical Page;
Check whether this Physical Page is without mapping;
If it is arrange without mapping and indicate that then this Physical Page being passed to the flash memory management module operates; Otherwise directly this Physical Page being passed to the flash memory management module operates.
7. flash data management method according to claim 1 is characterized in that, described method also comprises:
Set up other second level buffer memory of a plurality of logical page (LPAGE) levels and other first order buffer memory of Physical Page level;
The start logical block that receive data management channels data writing is operated and logic length;
The logical block that writes according to the large young pathbreaker of logical page (LPAGE) changes into logical page (LPAGE);
Judge whether described logical page (LPAGE) hits described second level buffer memory, if hit then according to data in the buffer memory of the described second level of the information updating of the contained logical block of logical page (LPAGE), if missly judge whether described first order buffer memory overflows;
If do not overflow, this logical page (LPAGE) as new second level buffer memory, is upgraded described first order buffer memory;
Write flash memory if overflow then the data in first order buffer memory and the second level buffer memory to be brushed out, create a new first order buffer memory, this logical page (LPAGE) as new second level buffer memory, and is upgraded described first order buffer memory.
8. flash data management method according to claim 7 is characterized in that, described method also comprises: when host requirements or overtime, the data in described first order buffer memory and the second level buffer memory are write in the flash memory.
9. flash data management method according to claim 8 is characterized in that, when host requirements or overtime, the step that the data in described first order buffer memory and the second level buffer memory are write in the flash memory is specially:
Check whether there is described first order buffer memory;
If otherwise end operation is whether described second level buffer memory number reaches threshold value if then check;
If reach threshold value, then the output of the data in described first order buffer memory and the second level buffer memory is stored;
If do not reach threshold value, then after the additional invalid logical page (LPAGE) data output of the data in described first order buffer memory and the second level buffer memory is stored.
10. a flash data management system is characterized in that, described system comprises:
Mapping management unit, address, be used for setting up the logical physical address mapping table that a plurality of logical page (LPAGE)s are mapped to the Same Physical page or leaf, described logical physical mapping table is take logical page (LPAGE) as index, the corresponding Physical Page value of each logical page (LPAGE), described Physical Page value comprises the data segment of the index value that points to respectively actual physics page address and a corresponding logical page address; Mapping management unit, described address also is used for when data writing operation described logical page (LPAGE) is mapped to a Physical Page and upgrades the logical physical address mapping table, perhaps when read data operates, then read the logical physical address mapping table according to described logical page (LPAGE), index corresponding Physical Page.
Data cache management unit is set up two-level cache mechanism, is divided into logical page (LPAGE) level buffer memory and Physical Page level buffer memory, the data that main frame is write, carry out hitting, force to refresh or the management such as overtime of L2 cache, according to the different set condition, the data in the buffer memory are brushed out write flash memory at last.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012103414635A CN102866955A (en) | 2012-09-14 | 2012-09-14 | Flash data management method and system |
| PCT/CN2013/077387 WO2014040441A1 (en) | 2012-09-14 | 2013-06-18 | Flash data management method and system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012103414635A CN102866955A (en) | 2012-09-14 | 2012-09-14 | Flash data management method and system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102866955A true CN102866955A (en) | 2013-01-09 |
Family
ID=47445834
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2012103414635A Pending CN102866955A (en) | 2012-09-14 | 2012-09-14 | Flash data management method and system |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN102866955A (en) |
| WO (1) | WO2014040441A1 (en) |
Cited By (22)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103425600A (en) * | 2013-08-23 | 2013-12-04 | 中国人民解放军国防科学技术大学 | Address mapping method for flash translation layer of solid state drive |
| CN103440206A (en) * | 2013-07-25 | 2013-12-11 | 记忆科技(深圳)有限公司 | Solid state hard disk and mixed mapping method of solid state hard disk |
| CN103455631A (en) * | 2013-09-22 | 2013-12-18 | 广州中国科学院软件应用技术研究所 | Method, device and system for processing data |
| WO2014040441A1 (en) * | 2012-09-14 | 2014-03-20 | 记忆科技(深圳)有限公司 | Flash data management method and system |
| CN103744798A (en) * | 2013-12-17 | 2014-04-23 | 记忆科技(深圳)有限公司 | Garbage recycling method of solid state discs |
| CN104102591A (en) * | 2013-04-08 | 2014-10-15 | 香港理工大学 | Computer subsystem and method for implementing flash translation layer in computer subsystem |
| CN104484283A (en) * | 2014-11-27 | 2015-04-01 | 记忆科技(深圳)有限公司 | Method for reducing write amplification of solid state disk |
| CN105095113A (en) * | 2015-07-21 | 2015-11-25 | 浪潮(北京)电子信息产业有限公司 | Cache management method and system |
| WO2016123748A1 (en) * | 2015-02-03 | 2016-08-11 | 北京麓柏科技有限公司 | Flash memory storage system and read/write and delete methods therefor |
| CN106708416A (en) * | 2015-11-13 | 2017-05-24 | 群联电子股份有限公司 | Data reconstruction method and system, and memory control circuit unit |
| CN107391391A (en) * | 2017-07-19 | 2017-11-24 | 深圳大普微电子科技有限公司 | The method, system and solid state hard disc of data copy are realized in the FTL of solid state hard disc |
| CN108062203A (en) * | 2017-12-15 | 2018-05-22 | 北京京存技术有限公司 | A kind of flash data management method, device and memory |
| CN109408416A (en) * | 2018-09-20 | 2019-03-01 | 新华三技术有限公司 | A kind of address of cache list item page management method and device |
| CN109582230A (en) * | 2018-11-20 | 2019-04-05 | 深圳松诺技术有限公司 | A kind of data access method and access system based on matrix form index |
| CN109684238A (en) * | 2018-12-19 | 2019-04-26 | 湖南国科微电子股份有限公司 | A kind of storage method, read method and the solid state hard disk of solid state hard disk mapping relations |
| CN111177034A (en) * | 2019-12-27 | 2020-05-19 | 鸿秦（北京）科技有限公司 | Self-adaptive FTL algorithm of solid state disk |
| CN111338562A (en) * | 2018-12-18 | 2020-06-26 | 慧荣科技股份有限公司 | Data storage device and data processing method |
| CN111625188A (en) * | 2020-05-19 | 2020-09-04 | 合肥康芯威存储技术有限公司 | Memory and data writing method and memory system thereof |
| CN112506438A (en) * | 2020-12-14 | 2021-03-16 | 深圳大普微电子科技有限公司 | Mapping table management method and solid state disk |
| CN113626347A (en) * | 2021-07-29 | 2021-11-09 | 武汉新芯集成电路制造有限公司 | Storage device and working method thereof |
| CN116383098A (en) * | 2023-06-05 | 2023-07-04 | 成都佰维存储科技有限公司 | Address indexing method and device, readable storage medium and electronic equipment |
| CN117472295A (en) * | 2023-12-28 | 2024-01-30 | 合肥康芯威存储技术有限公司 | Memory, data processing method, device and medium |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1504896A (en) * | 2002-10-28 | 2004-06-16 | 三因迪斯克公司 | Method and apparatus for performing cache storage of block in non-volatile memory system |
| CN1705936A (en) * | 2002-10-28 | 2005-12-07 | 桑迪士克股份有限公司 | Method and apparatus for splitting a logical block |
| CN101281493A (en) * | 2008-05-26 | 2008-10-08 | 中兴通讯股份有限公司 | And non flash memory device and management method thereof |
| CN101625661A (en) * | 2008-07-07 | 2010-01-13 | 群联电子股份有限公司 | Data management method, storage system and controller used for flash memory |
| US20100199024A1 (en) * | 2009-02-03 | 2010-08-05 | Samsung Electronics Co., Ltd. | Method and apparatus for managing data of flash memory via address mapping |
| CN102467459A (en) * | 2010-11-11 | 2012-05-23 | 群联电子股份有限公司 | Data write method, memory controller and memory device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102866955A (en) * | 2012-09-14 | 2013-01-09 | 记忆科技(深圳)有限公司 | Flash data management method and system |
-
2012
- 2012-09-14 CN CN2012103414635A patent/CN102866955A/en active Pending
-
2013
- 2013-06-18 WO PCT/CN2013/077387 patent/WO2014040441A1/en active Application Filing
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1504896A (en) * | 2002-10-28 | 2004-06-16 | 三因迪斯克公司 | Method and apparatus for performing cache storage of block in non-volatile memory system |
| CN1705936A (en) * | 2002-10-28 | 2005-12-07 | 桑迪士克股份有限公司 | Method and apparatus for splitting a logical block |
| CN101281493A (en) * | 2008-05-26 | 2008-10-08 | 中兴通讯股份有限公司 | And non flash memory device and management method thereof |
| CN101625661A (en) * | 2008-07-07 | 2010-01-13 | 群联电子股份有限公司 | Data management method, storage system and controller used for flash memory |
| US20100199024A1 (en) * | 2009-02-03 | 2010-08-05 | Samsung Electronics Co., Ltd. | Method and apparatus for managing data of flash memory via address mapping |
| CN102467459A (en) * | 2010-11-11 | 2012-05-23 | 群联电子股份有限公司 | Data write method, memory controller and memory device |
Cited By (35)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2014040441A1 (en) * | 2012-09-14 | 2014-03-20 | 记忆科技(深圳)有限公司 | Flash data management method and system |
| CN104102591A (en) * | 2013-04-08 | 2014-10-15 | 香港理工大学 | Computer subsystem and method for implementing flash translation layer in computer subsystem |
| CN103440206A (en) * | 2013-07-25 | 2013-12-11 | 记忆科技(深圳)有限公司 | Solid state hard disk and mixed mapping method of solid state hard disk |
| CN103440206B (en) * | 2013-07-25 | 2016-06-01 | 记忆科技(深圳)有限公司 | A kind of solid state hard disc and mixed-use developments method thereof |
| CN103425600B (en) * | 2013-08-23 | 2016-01-20 | 中国人民解放军国防科学技术大学 | Address mapping method in a kind of solid-state disk flash translation layer (FTL) |
| CN103425600A (en) * | 2013-08-23 | 2013-12-04 | 中国人民解放军国防科学技术大学 | Address mapping method for flash translation layer of solid state drive |
| CN103455631A (en) * | 2013-09-22 | 2013-12-18 | 广州中国科学院软件应用技术研究所 | Method, device and system for processing data |
| CN103744798A (en) * | 2013-12-17 | 2014-04-23 | 记忆科技(深圳)有限公司 | Garbage recycling method of solid state discs |
| CN104484283A (en) * | 2014-11-27 | 2015-04-01 | 记忆科技(深圳)有限公司 | Method for reducing write amplification of solid state disk |
| CN104484283B (en) * | 2014-11-27 | 2018-03-27 | 记忆科技(深圳)有限公司 | A kind of method for reducing solid state disk write amplification |
| WO2016123748A1 (en) * | 2015-02-03 | 2016-08-11 | 北京麓柏科技有限公司 | Flash memory storage system and read/write and delete methods therefor |
| CN105095113A (en) * | 2015-07-21 | 2015-11-25 | 浪潮(北京)电子信息产业有限公司 | Cache management method and system |
| CN105095113B (en) * | 2015-07-21 | 2018-06-29 | 浪潮(北京)电子信息产业有限公司 | A kind of buffer memory management method and system |
| CN106708416A (en) * | 2015-11-13 | 2017-05-24 | 群联电子股份有限公司 | Data reconstruction method and system, and memory control circuit unit |
| CN106708416B (en) * | 2015-11-13 | 2020-06-09 | 群联电子股份有限公司 | Data reconstruction method and system and memory control circuit unit thereof |
| CN107391391A (en) * | 2017-07-19 | 2017-11-24 | 深圳大普微电子科技有限公司 | The method, system and solid state hard disc of data copy are realized in the FTL of solid state hard disc |
| CN108062203A (en) * | 2017-12-15 | 2018-05-22 | 北京京存技术有限公司 | A kind of flash data management method, device and memory |
| CN109408416A (en) * | 2018-09-20 | 2019-03-01 | 新华三技术有限公司 | A kind of address of cache list item page management method and device |
| CN109408416B (en) * | 2018-09-20 | 2021-01-26 | 新华三技术有限公司 | Address mapping table entry page management method and device |
| CN109582230B (en) * | 2018-11-20 | 2022-04-08 | 深圳松诺技术有限公司 | Matrix index-based data access method and access system |
| CN109582230A (en) * | 2018-11-20 | 2019-04-05 | 深圳松诺技术有限公司 | A kind of data access method and access system based on matrix form index |
| CN111338562A (en) * | 2018-12-18 | 2020-06-26 | 慧荣科技股份有限公司 | Data storage device and data processing method |
| CN111338562B (en) * | 2018-12-18 | 2023-06-09 | 慧荣科技股份有限公司 | Data storage device and data processing method |
| CN109684238A (en) * | 2018-12-19 | 2019-04-26 | 湖南国科微电子股份有限公司 | A kind of storage method, read method and the solid state hard disk of solid state hard disk mapping relations |
| CN111177034A (en) * | 2019-12-27 | 2020-05-19 | 鸿秦（北京）科技有限公司 | Self-adaptive FTL algorithm of solid state disk |
| CN111625188A (en) * | 2020-05-19 | 2020-09-04 | 合肥康芯威存储技术有限公司 | Memory and data writing method and memory system thereof |
| CN111625188B (en) * | 2020-05-19 | 2023-08-08 | 合肥康芯威存储技术有限公司 | Memory, data writing method thereof and memory system |
| CN112506438A (en) * | 2020-12-14 | 2021-03-16 | 深圳大普微电子科技有限公司 | Mapping table management method and solid state disk |
| CN112506438B (en) * | 2020-12-14 | 2024-03-26 | 深圳大普微电子科技有限公司 | Mapping table management method and solid state disk |
| CN113626347A (en) * | 2021-07-29 | 2021-11-09 | 武汉新芯集成电路制造有限公司 | Storage device and working method thereof |
| CN113626347B (en) * | 2021-07-29 | 2023-12-15 | 武汉新芯集成电路制造有限公司 | Storage device and working method thereof |
| CN116383098A (en) * | 2023-06-05 | 2023-07-04 | 成都佰维存储科技有限公司 | Address indexing method and device, readable storage medium and electronic equipment |
| CN116383098B (en) * | 2023-06-05 | 2023-09-12 | 成都佰维存储科技有限公司 | Address indexing method and device, readable storage medium and electronic equipment |
| CN117472295A (en) * | 2023-12-28 | 2024-01-30 | 合肥康芯威存储技术有限公司 | Memory, data processing method, device and medium |
| CN117472295B (en) * | 2023-12-28 | 2024-03-22 | 合肥康芯威存储技术有限公司 | Memory, data processing method, device and medium |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2014040441A1 (en) | 2014-03-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102866955A (en) | Flash data management method and system | |
| US9477596B2 (en) | LBA bitmap usage | |
| US10915475B2 (en) | Methods and apparatus for variable size logical page management based on hot and cold data | |
| US9977623B2 (en) | Detection of a sequential command stream | |
| US10678768B2 (en) | Logical band-based key-value storage structure | |
| US9514057B2 (en) | Storage module and method for managing logical-to-physical address mapping | |
| US20180356984A1 (en) | Memory system and method of controlling memory system | |
| EP2472405B1 (en) | Handling dynamic and static data for a system having a non-volatile memory | |
| CN108369818B (en) | Flash memory device refreshing method and device | |
| US20140372675A1 (en) | Information processing apparatus, control circuit, and control method | |
| US20150074328A1 (en) | Dynamic map pre-fetching for improved sequential reads of a solid-state media | |
| US9928166B2 (en) | Detecting hot spots through flash memory management table snapshots | |
| US10936203B2 (en) | Memory storage device and system employing nonvolatile read/write buffers | |
| Lee et al. | HFTL: hybrid flash translation layer based on hot data identification for flash memory | |
| US20150127886A1 (en) | Memory system and method | |
| US11003373B2 (en) | Systems and methods for managing physical-to- logical address information | |
| US20140372673A1 (en) | Information processing apparatus, control circuit, and control method | |
| US20140325123A1 (en) | Information processing apparatus, control circuit, and control method | |
| JP2017126334A (en) | Storage devices, operating methods thereof and systems | |
| CN109725850B (en) | Memory system and memory device | |
| CN112506438A (en) | Mapping table management method and solid state disk | |
| US9218294B1 (en) | Multi-level logical block address (LBA) mapping table for solid state | |
| US9727453B2 (en) | Multi-level table deltas | |
| KR20090110923A (en) | Memory system | |
| Kim et al. | A new hash algorithm exploiting triple-state bucket directory for flash storage devices |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C12 | Rejection of a patent application after its publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20130109 |