CN102710280B - Partitioned and expanded high-speed pipelining shift dispreading method and device - Google Patents
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Abstract
The invention discloses a high-speed pipelining shift dispreading method and method. The method comprises the following steps: storing a local dispreading pseudorandom sequence with length of n in an isometric local data unit; performing zero clearing on the data in the dispreading data unit with length of n; at every turn, inputting to-be-dispread data from an external data input interface; taking out every bit data sequentially from the local data unit; according to 0 or 1, performing symbolization on the bit wide expanded data to obtain the data or opposite results; numbering the taken data from the local data unit as k; according to the serial number k, adding the data obtained from the last step with the data of k-1 in the dispreading data unit respectively; storing the result in the dispreading data unit with the next serial number; for the 0 data, directly obtaining the result; for the processing result of the nth data, directly outputting the result; repeatedly executing the steps above on the inputted external data sequentially for n times, and outputting the data of dispreading data unit with the serial number of n-1.
Description
Technical field
The invention belongs to digital communication technology field, particularly a kind of high-speed flow line displacement despreading method and device that is applicable to the piecemeal arbitrarily of Resistant DS Spread Spectrum System and expands.
Background technology
In direct sequence spread spectrum communication system, low speed information source data sequence through hundred times, even, after the spread processing of thousands of times, directly changes high-speed data sequence at transmitting terminal.And at receiving terminal, change the principle of Communication System Design in the past, and first need the high-speed data receiving, carry out quick despreading, then carry out subsequent demodulation processing.Be that the symmetry principle that it does not follow communication system (at the first spread spectrum of transmitting terminal, then is modulated.And by symmetry principle, should be in the first demodulation of receiving terminal, then despreading), first carry out despreading, then carry out demodulation process.Thereby reduced by a link that high-speed data is processed, reduced implementation complexity, and improved reliability.Two tradable essence of process of its receiving terminal are that despreading and demodulation are all the property taken advantage of calculating, commutative order.Therefore, at a high speed effective despreading treatment technology, is the important leverage that realizes the effective reliably working of direct sequence spread spectrum communication system.
In traditional despreader scheme, the despreading method extensively adopting is the Series correlation method multiplying each other by symbol.First the method is kept at input data in shift register, then multiply each other in each position corresponding to local despread data content register of shift register, result deposits in despreading output register, finally by all data accumulations in despreading output register, its result is the local despread data in shift register, is to be kept at the despreading result of inputting the content of data and local despread data content register in shift register.But, in actual applications, as in the spread spectrum communication system of higher speed, the processing speed of data is required just very high.And Series correlation method all must complete cumulative (N is related content length, and is integer) N time within a cycle, when speed is too high or related content length is long, cannot realize.And because the local sequence of despreading is conventionally long, often whole despreading algorithm can not be achieved on the monolithic hardware chip of resource-constrained.Therefore, it can not reach at a high speed and the requirement of length arbitrarily of despreading sequence simultaneously.
Summary of the invention
What the present invention is directed to that existing Direct Sequence Spread Spectrum Communication receiver exists cannot realize the shortcomings such as above method when speed is too high, related data content is long or hardware resource limitations is dumb, and a kind of method and apparatus that is applicable to Resistant DS Spread Spectrum System that can avoid above-mentioned shortcoming and defect is provided---be shifted despreading method and device of piecemeal and the high-speed flow line expanded arbitrarily.
The present invention takes following technical scheme:
A kind of basic high-speed flow line displacement despreading method, it comprises the following steps: initialization step, input data bit width spread step, symbol treatment step, data are added and preserve the repeated execution of steps for the treatment of step and above-mentioned concrete steps, and the implementation process of the method is as follows:
Initialization step: will grow for the local despreading pseudo random sequence of n is kept in isometric local data unit, and this sequence is binary sequence; Data zero clearing in the despread data unit that is n by length, is about to its all value and is made as " 0 "; Wherein, the numbering of data cell is since 0; N is integer, represents despreading length;
Input data bit width spread step: at every turn from external data input interface, input input data for the treatment of despreading, and be saved in bit width extension unit, and complete bit wide expansion; The method of bit wide expansion is: original input data is as the lowest of this longer bit wide unit, and by several bit data above of deficiency, replaces with the highest order of former input data;
Get symbol treatment step: from local data unit, take out in order each Bit data, according to " 0 " or " 1 ", by the data of previous step bit wide expansion gained, carry out symbolism processing, obtain respectively the result of data itself or its negate; Another from local data unit the numbering of the data of going, as the numbering k of this step the data obtained, k is integer, 0≤k≤n-1;
Data are added treatment step: by previous step the data obtained, by data number k, respectively with despread data unit in the data of reference numeral k-1 be added, and result is kept in the despread data unit of next sequence number; Because the 0th data do not have the data of " 1 " individual sequence number corresponding, therefore these data do not need to be added, directly obtain result; And for the result of n data, directly output, and no longer preserve;
Finally, successively to inputted external data, repeatedly carry out above-mentioned steps, until process after n time, be numbered the data of the despread data unit of n-1, be the end product of n input data after n local despreading sequence despreading, and by its output.
Finally, form corresponding stream treatment structure, i.e. data of every input, Output rusults (being numbered the data in the despread data unit of n-1).Be that it is former data, remove outside first data, then add the data that obtain after the local data unit despreading that the sequence of last new input data gained is n by length, and circulation successively, until despreading processing finishes.In addition, by the Output rusults of the method, with respective threshold contrast, and draw the judge mark that despreading sequence frame is synchronous.So that after completing synchronously, export the despread data of required correct sequential always.Wherein, the corresponding thresholding of frame synchronization, the signal to noise ratio that can work according to this spread spectrum system, is obtained by corresponding emulation, needs to make this thresholding can guarantee more than 99% synchronous accuracy rate.
The invention also discloses a kind of basic high-speed flow line displacement despreading device, it comprises take lower module: the bit wide extended menory of input data-interface, arbitrarily long as n(n be any lint-long integer) local despreading pseudo random sequence data storage (hereinafter to be referred as local data memory, data bit width is 1), get symbol processor (representing with getting sign function Sgn (.)), adder, overflow determining device, despreading calculation result data memory (hereinafter to be referred as despread data memory, data bit width is j), output data-interface;
Described bit wide extended menory, the input interface that comprises 1 i Bit data and this i bit input data are expanded to the memory cell of j bit, and i, j be integer, j >=i, and j is the quantization bit figure place during despreading is processed; Data storage adopts the complement representation after quantizing, and the input data of i bit bit wide expand to the data of the despreading processing bit wide of j bit bit wide, adopt lowest order to represent with former, and remaining j-i position, all fills by the highest order of input data; Bit wide extended menory, for the bit wide expansion of data, increases denotable scope, reduces overflowing in calculating;
Described local data memory, the memory cell that comprises n storage 1 Bit data, for preserving local despread data;
The described symbol processor of getting, for judging the symbol of input data, is equivalent to the data of many bits bit wide and the calculating of the multiplication of single-bit bit wide data; Get total n of symbol processor, and each processor comprises 2 input data (being respectively 1 bit and j Bit data) and 1 j bit output data, and there is following functions: according to 1 Bit data of input, be " 0 " or " 1 ", by another j Bit data, carry out symbol manipulation, obtain respectively j Bit data itself, or the negate result of these data, and output; Wherein, inversion operation is: each bit of data is put instead, be about to transfer to " 1 " that data are " 0 ", otherwise transfer " 0 " to, and in last position of result, add data " 1 ";
Described adder, for the addition of the data of bit bit wide more than two: 2 input data are added, and accumulation result is exported; As run into, overflow, carry out saturated processing, the several maximums that can represent (overflowing for forward) that are j by this length or minimum value (overflowing for negative sense), carry out the result after approximate substitution is added;
Whether the described determining device that overflows, after judging that adder is calculated, occur that forward or negative sense overflow;
Described despread data memory, the memory cell that comprises n storage j Bit data, for preserving the ephemeral data of despreading processing procedure;
The data output interface that described output data-interface comprises 1 j bit;
The implementation step of described basic high-speed flow line displacement despreading device is as follows:
First, when initialization, by long, be kept in isometric local data memory for the local despreading pseudo random sequence of n; Data zero clearing in the despread data memory that is n by length; N is integer;
Secondly, outer input data is saved in to bit wide expander, completes bit wide expansion;
Again, from local data memory, take out in order each Bit data, according to " 0 " or " 1 ", bit wide is expanded to the data of gained, carry out symbolism operation, obtain respectively data itself, or the negate result of data; And the numbering of the data of going from local data unit, as the numbering k of this step the data obtained, k is integer, 0≤k≤n-1;
Afterwards, by previous step the data obtained, by data number k, respectively with the local data memory of middle reference numeral k-1 in data carry out addition calculation, obtain accumulation result; Because the 0th data do not have the data of " 1 " individual sequence number corresponding, therefore these data are directly exported as a result of; For the result of n data, also need output;
Finally, by above step acquired results, be stored in the despread data memory of reference numeral k; Above-mentioned steps is carried out in input repeatedly successively, until through n external data input, and after above-mentioned steps is processed, be numbered the data of the despread data memory of n-1, be the end product of n input data after n local despreading sequence despreading, and by its output.
The high-speed flow line displacement despreading method that the invention also discloses a kind of piecemeal arbitrarily and expand, it comprises the following steps: step is controlled in despread data piecemeal treatment step, comparison step, despread data output, and the specific implementation process of the method is as follows:
First, the aforesaid basic high-speed flow line displacement of a plurality of employings despreading method is connected into corresponding cascade stream treatment structure, i.e. data of every input, Output rusults, as the primary data input of next stage despread unit, as its input parameter 2 inputs; And the data of despreading are treated in outside input, respectively as its input parameter 1 input, and every 1 despread data treatment step, between the external data of input, needing to adopt interval sequence number length is the input data of n; Through k despread data step and after n * k time despread data is processed, obtain final length for the despreading result after nk series processing;
Secondly, by the despreading result after nk series processing, in comparison step, contrast with respective threshold, and draw the judge mark that despreading sequence frame is synchronous; So that after completing synchronously, control the despread data of the required accurate synchronization of output; Wherein, the corresponding decision threshold of frame synchronization, the parameters such as signal to noise ratio that can work according to this spread spectrum system, are obtained by software simulation, make this thresholding can guarantee more than 99% synchronous accuracy rate;
Finally, the result judging according to comparison step, according to whether being greater than decision threshold, and by despread data output, as last Output rusults.
The present invention is piecemeal and the high-speed flow line displacement despreading device expanded arbitrarily, and it comprises with lower module: external data buffer, despread data module, comparator, the despread data o controller of temporarily storing external data;
Described external data buffer, treats the outer input data of despreading for buffer memory;
Described comparator, for judging whether input data are greater than certain set-point;
Described despread data o controller, according to external control signal, exports required data;
Described the piecemeal arbitrarily and implementation step of the high-speed flow line displacement despreading device expanded is as follows:
First, a plurality of aforesaid basic high-speed flow lines displacement despreading devices are connected into corresponding stream treatment structure, i.e. data of every input, Output rusults, as the primary data input of next stage despread unit, inputs at " In2 " interface; And the data of despreading are treated in outside input, respectively in the input of " In1 " interface, and every 1 despread data, process soon, between the external data of input, need the input data that interval sequence number length is n; Through k despread data module and after n * k time flowing structure is processed, can obtain length is the despreading result of nk;
Secondly, by its Output rusults, in comparator, contrast with respective threshold, and draw the judge mark that despreading sequence frame is synchronous;
Finally, according to the control signal of comparator output, export required despread data.
The present invention has realized by above-mentioned streamline displacement despreading method or device the quick despreading target that is applicable to Resistant DS Spread Spectrum System, and meanwhile, the method or device can reduce the implementation complexity of system, have greatly improved its efficiency.In addition, also can form the long despreading processor of longer m * n by the long despreading module of the some n of cascade (as m, m is integer), the hardware platforms such as easy-to-use Field Programmable Gate Array (FPGA) are realized.
Accompanying drawing explanation
Fig. 1 is the structure chart of the basic high-speed flow line displacement despreading method of the embodiment of the present invention.
Fig. 2 is the structure chart of the high-speed flow line that piecemeal is expanded the arbitrarily displacement despreading method of the embodiment of the present invention.
Fig. 3 is the structure chart of the basic high-speed flow line displacement despreading device of the embodiment of the present invention.
Fig. 4 is the structure chart of the high-speed flow line that piecemeal is expanded the arbitrarily displacement despreading device of the embodiment of the present invention.
Embodiment
Below by specific embodiment, also the present invention is described in further detail by reference to the accompanying drawings.
Iterative demodulation system and method provided by the present invention can be applicable to tells spread spectrum communication system technical field.The present invention is stored in local data unit through the initialization of local despreading pseudo random sequence successively, external data input, utilize the positive and negative of this external data input of local data unit Data Control, by corresponding sequence number, will revise the external data of symbol and the data accumulation of despread data unit, and result has been stored in the despread data unit of next sequence number.After the external data input through all local despread data length and cumulative etc. is processed, in the end a despread data unit obtains final despreading result.Below choose typically can piecemeal high-speed flow line displacement despreading method and system specifics the specific embodiment of the present invention.
As shown in Figure 1, be the structure chart of the basic high-speed flow line displacement despreading method of the embodiment of the present invention.When system initialization, by long for the local despreading pseudo random sequence of n C[0], C[1], C[2], C[3] ..., C[n-1] } be kept in isometric local data unit, and this sequence is binary sequence, n is integer.Separately by long for the despread data unit of n R[0], R[1], R[2], R[3] ..., R[n-1] } interior data zero clearing, be about to its all value and be made as " 0 "; Secondly, at every turn from input data for the treatment of despreading of outside input, and be saved in bit width extension unit, and completed bit wide expansion.The method of bit wide expansion is, initial data is as the lowest of this longer bit wide unit, and several bit data above, replaces with the highest order of input data; Again, from local data unit, take out in order each Bit data, according to " 0 " or " 1 ", bit wide is expanded to the data of gained, carry out symbolism operation, obtain respectively data itself, or the negate result of data.And the numbering of fetching data from local data unit, as the numbering of this step the data obtained, as numbering k, and k is integer, 0≤k≤n-1; Afterwards, by previous step the data obtained, by data number (as numbering k), respectively with local data unit in the data R[k-1 of reference numeral k-1] be added, obtain result.Note, because the 0th data do not have the data of " 1 " individual sequence number corresponding, therefore these data do not need and any number cumulative (or being equivalent to 0 cumulative), directly obtain result.And for the result of n data, also need output; Finally, by above step acquired results, be stored in the despread data unit of reference numeral k.According to inputted external data, repeatedly carry out above-mentioned steps successively, until through n external data input, and after above-mentioned processing, be numbered the data of the despread data unit of n-1, be the end product of n input data after n local despreading sequence despreading, and by its output.
As shown in Figure 2, be the structure chart of the high-speed flow line that piecemeal is expanded the arbitrarily displacement despreading method of the embodiment of the present invention.On embodiment basis as shown in Figure 1, by a plurality of these embodiment, the high-speed flow line displacement despreading method that forms a total piecemeal arbitrarily and expand, the method includes the steps of: despread data piecemeal treatment step, step is controlled in comparison step and despread data output, specific implementation process is as follows: basic high-speed flow line displacement despreading method embodiment shown in Fig. 1 is arranged to corresponding stream treatment structure, be data of every input, Output rusults (be the despread unit data R[n-1 that is numbered n-1 shown in Fig. 1]), primary data input as next stage despread unit, at " In2 " interface, input.And the data of despreading are treated in outside input, respectively in the input of " In1 " interface, and every 1 despread data step, between the external data of input, need the input data that interval sequence number length is n.Through k despread data piecemeal and after n * k time flowing structure is as shown in Figure 1 processed, can obtain final length is the despreading result of nk.In addition, also need its Output rusults, in comparator, contrast with respective threshold, and draw the judge mark that despreading sequence frame is synchronous.So that after completing synchronously, control the despread data of the required accurate synchronization of output.Wherein, the corresponding decision threshold of frame synchronization, the parameters such as signal to noise ratio that can work according to this spread spectrum system, are obtained by corresponding emulation, can pass through software simulation, make this thresholding can guarantee more than 99% synchronous accuracy rate.
As shown in Figure 3, structure chart for the basic high-speed flow line displacement despreading device of the embodiment of the present invention, this device comprises: bit wide extended menory, local despreading pseudo random sequence data storage (is called for short local data memory, data storage bit wide is 1), symbol processor (representing with getting sign function Sgn (.)), adder, overflow determining device and despreading calculation result data memory and (be called for short despread data memory, data storage bit wide is j), the implementation process of this device is as follows: when system initialization, by long for the local despreading pseudo random sequence of n be kept at isometric local data memory C[0], C[1], C[2], C[3], C[n-1] } in, and this sequence is binary sequence, n is integer.Separately by long for the despread data memory of n R[0], R[1], R[2], R[3] ..., R[n-1] } in data zero clearing, be about to its all value and be made as " 0 "; Secondly, from data for the treatment of despreading of outside input, be saved in bit wide expander, and completed bit wide expansion.The method of bit wide expansion is, initial data is as the lowest of this longer bit wide unit, and several bit data above, replaces with the highest order of input data; Again, from local data memory, take out in order each Bit data, according to " 0 " or " 1 ", bit wide is expanded to the data of gained, carry out symbolism operation, obtain respectively data itself, or the negate result of data.And the numbering of the data of going from local data unit, as the numbering of this step the data obtained, as numbering k, and k is integer, 0≤k≤n-1; Afterwards, by previous step the data obtained, by data number (as numbering k), respectively with the local data memory R[k-1 of middle reference numeral k-1] in data carry out addition calculation, obtain accumulation result.Because the 0th data do not have the data of " 1 " individual sequence number corresponding, therefore these data do not need addition, directly as a result of.And for the result of n data, also need output; Finally, by above step acquired results, be stored in the despread data memory of reference numeral k.Above-mentioned steps is carried out in input repeatedly successively, until through n external data input, and after above-mentioned processing, be numbered the data of the despread data memory of n-1, be the end product of n input data after n local despreading sequence despreading, and by its output.
As shown in Figure 4, structure chart for the high-speed flow line that piecemeal is expanded the arbitrarily displacement despreading device of the embodiment of the present invention, this device comprises: the external data buffer of temporarily storing external data, despread data processing module, comparator and despreading data output controller, it is on embodiment basis as shown in Figure 3, by a plurality of these embodiment, the high-speed flow line displacement despreading device that forms a total piecemeal arbitrarily and expand, the implementation process of this device is as follows: basic high-speed flow line displacement despreading device shown in Fig. 3 is arranged to corresponding stream treatment structure, be data of every input, Output rusults (be the despreading memory R[n-1 that is numbered n-1 shown in Fig. 3] data), primary data input as next stage despread unit, at " In2 " interface, input.And the data of despreading are treated in outside input, respectively in the input of " In1 " interface, and every 1 despread data, process soon, between the external data of input, need the input data that interval sequence number length is n.After flowing structure shown in k despread data module and n * k Fig. 3 is processed, can obtain final length is the despreading result of nk.In addition, also need its Output rusults, in comparator, contrast with respective threshold, and draw the judge mark that despreading sequence frame is synchronous.So that after completing synchronously, control the despread data of the required accurate synchronization of output.Wherein, the corresponding decision threshold of frame synchronization, the parameters such as signal to noise ratio that can work according to this spread spectrum system, are obtained by corresponding emulation, can pass through software simulation, make this thresholding can guarantee more than 99% synchronous accuracy rate.
System of the present invention realizes in the mode of streamline, is applicable to the despreading of position despreading sequence arbitrarily and processes, and can required despread data length is carried out to flexible piecemeal, and partitioned organization be consistent according to actual hardware resource, and the convenient general module that adopts is realized.
The present invention has improved the treatment effeciency of despreading end in Resistant DS Spread Spectrum System: by the arbitrary-bit high-speed streamline despreader that is shifted, except reducing realizing cost, improve real-time, improving processing speed of system, also can realize serially concatenated piecemeal, facilitate hardware to realize flexibly.
Above-mentioned the several preferred embodiments of the present invention are described in detail; for those of ordinary skill in the art; without departing from the principles and spirit of the present invention; can carry out multiple variation, modification, replacement and distortion to these embodiment, and these changes also fall into protection scope of the present invention.
Claims (5)
1. a basic high-speed flow line displacement despreading method, is characterized in that comprising the following steps:
Initialization step: will grow for the local despreading pseudo random sequence of n is kept in isometric local data unit, and this sequence is binary sequence; Data zero clearing in the despread data unit that is n by length; Wherein, the numbering of data cell is since 0; N is integer, represents despreading length;
Input data bit width spread step: at every turn from external data input interface, input input data for the treatment of despreading, and be saved in bit width extension unit, and complete bit wide expansion; The method of bit wide expansion is: original input data is as the lowest of new longer bit wide unit, and by several bit data above of deficiency, replaces with the highest order of former input data;
Get symbol treatment step: from local data unit, take out in order each Bit data, according to " 0 " or " 1 ", by the data of previous step bit wide expansion gained, carry out symbolism processing, obtain respectively the result of data itself or its negate; Another numbering of fetching data from local data unit, as the numbering k of this step the data obtained, k is integer, 0≤k≤n-1;
Data are added treatment step: by previous step the data obtained, by data number k, respectively with despread data unit in the data of reference numeral k-1 be added, and result is kept in the despread data unit of next sequence number; The 0th directly obtains result; And for the result of n data, directly output;
Finally, successively to inputted external data, repeatedly carry out above-mentioned steps, until process after n time, be numbered the data of the despread data unit of n-1, be the end product of n input data after n local despreading sequence despreading, and by its output.
2. a basic high-speed flow line displacement despreading device, is characterized in that comprising and take lower module: the bit wide extended menory of input data-interface, arbitrarily the long local despreading pseudo random sequence data storage for n be local data memory, get symbol processor, adder, overflow determining device, despreading calculation result data memory is despread data memory, export data-interface; The data bit width of local data memory is 1, and the data bit width of despread data memory is j;
Described bit wide extended menory, the input interface that comprises 1 i Bit data and this i bit input data are expanded to the memory cell of j bit, i, j are integer, j >=i, j is the quantization bit figure place during despreading is processed; Data storage adopts the complement representation after quantizing, and the input data of i bit bit wide expand to the data of the despreading processing bit wide of j bit bit wide, adopt lowest order to represent with former, and remaining j-i position, all fills by the highest order of input data; Bit wide extended menory, for the bit wide expansion of data, increases denotable scope, reduces overflowing in calculating;
Described local data memory, the memory cell that comprises n storage 1 Bit data, for preserving local despread data;
The described symbol processor of getting, for judging the symbol of input data, is equivalent to the data of many bits bit wide and the calculating of the multiplication of single-bit bit wide data; Get total n of symbol processor, and each processor comprises, and 2 input data are respectively 1 bit and j Bit data, 1 j bit are exported data, and there is following functions: according to 1 Bit data of input, be " 0 " or " 1 ", by another j Bit data, carry out symbol manipulation, obtain respectively j Bit data itself, or the negate result of these data, and output; Wherein, inversion operation is: each bit of data is put instead, be about to transfer to " 1 " that data are " 0 ", otherwise transfer " 0 " to, and in last position of result, add data " 1 ";
Described adder, for the addition of the data of bit bit wide more than two: 2 input data are added, and accumulation result is exported;
Whether the described determining device that overflows, after judging that adder is calculated, occur that forward or negative sense overflow;
Described despread data memory, the memory cell that comprises n storage j Bit data, for preserving the ephemeral data of despreading processing procedure;
The data output interface that described output data-interface comprises 1 j bit;
The implementation step of described basic high-speed flow line displacement despreading device is as follows:
First, when initialization, by long, be kept in isometric local data memory for the local despreading pseudo random sequence of n; Data zero clearing in the despread data memory that is n by length; N is integer;
Secondly, outer input data is saved in to bit wide expander, completes bit wide expansion;
Again, from local data memory, take out in order each Bit data, according to " 0 " or " 1 ", bit wide is expanded to the data of gained, carry out symbolism operation, obtain respectively data itself, or the negate result of data; And the numbering of fetching data from local data unit, as the numbering k of this step the data obtained, k is integer, 0≤k≤n-1;
Afterwards, by previous step the data obtained, by data number k, respectively with the local data memory R[k-1 of reference numeral k-1] in data carry out addition calculation, obtain accumulation result; The 0th data are directly exported as a result of; For the result of n data, also need output;
Finally, by above step acquired results, be stored in the despread data memory of reference numeral k; Above-mentioned steps is carried out in input repeatedly successively, until through n external data input, and after above-mentioned steps is processed, be numbered the data of the despread data memory of n-1, be the end product of n input data after n local despreading sequence despreading, and by its output.
3. basic high-speed flow line displacement despreading device as claimed in claim 2, it is characterized in that: described adder, if run into, overflow, carry out saturated processing, the several maximums that can represent or the minimum value that by this length, are j, carry out the result after approximate substitution is added; Described maximum is overflowed for forward, and minimum value is overflowed for negative sense.
4. the high-speed flow line displacement despreading method of can piecemeal and expanding, is characterized in that comprising the following steps:
First, the corresponding flowage structure of a plurality of employings basic high-speed flow line displacement despreading method as claimed in claim 1 is connected into corresponding cascade stream treatment structure, that is: data of every input, Output rusults, as the primary data input of next stage despread unit, as its input parameter 2 inputs; And the data of despreading are treated in outside input, respectively as its input parameter 1 input, and every 1 despread data treatment step, between the external data of input, needing to adopt interval sequence number length is the input data of n; Through k despread data step and after n * k time despread data is processed, obtain final length for the despreading result after nk series processing;
Secondly, by the despreading result after nk series processing, in comparison step, contrast with respective threshold, and draw the judge mark that despreading sequence frame is synchronous; So that after completing synchronously, control the despread data of the required accurate synchronization of output;
Finally, the result judging according to comparison step, according to whether being greater than decision threshold, and by despread data output, as last Output rusults.
5. the high-speed flow line displacement despreading device of can piecemeal and expanding, is characterized in that comprising with lower module: external data buffer, despread data module, comparator, the despread data o controller of temporarily storing external data;
Described external data buffer, treats the outer input data of despreading for buffer memory;
Described comparator, for judging whether input data are greater than certain set-point;
Described despread data o controller, according to external control signal, exports required data;
The implementation step of the described high-speed flow line displacement despreading device of can piecemeal and expanding is as follows:
First, a plurality of basic high-speed flow lines displacement despreading devices as claimed in claim 2 are connected into corresponding stream treatment structure, that is: data of every input, Output rusults, as the primary data input of next stage despread unit, at " In2 " interface, input; And the data of despreading are treated in outside input, respectively in the input of " In1 " interface, and every 1 despread data processing block, between the external data of input, need the input data that interval sequence number length is n; Through k despread data module and after n * k time flowing structure is processed, can obtain length is the despreading result of nk;
Secondly, by its Output rusults, in comparator, contrast with respective threshold, and draw the judge mark that despreading sequence frame is synchronous;
Finally, according to the control signal of comparator output, export required despread data.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210163434.4A CN102710280B (en) | 2012-05-21 | 2012-05-21 | Partitioned and expanded high-speed pipelining shift dispreading method and device |
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| CN1287425A (en) * | 2000-09-22 | 2001-03-14 | 信息产业部电信传输研究所 | Multiphase orthogonal spectrum spreading code design and its spread-eliminating method |
| CN201341132Y (en) * | 2009-02-17 | 2009-11-04 | 东南大学 | Despreading apparatus based on MSK differential detection demodulation |
| CN201541257U (en) * | 2009-11-11 | 2010-08-04 | 傲世通科技（苏州）有限公司 | Serial descrambling and despreading device for mobile communication system |
| JP2011087223A (en) * | 2009-10-19 | 2011-04-28 | Nec Corp | Communication apparatus, communication method and program |
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| JP3484072B2 (en) * | 1998-04-14 | 2004-01-06 | 株式会社日立国際電気 | Despreading circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1287425A (en) * | 2000-09-22 | 2001-03-14 | 信息产业部电信传输研究所 | Multiphase orthogonal spectrum spreading code design and its spread-eliminating method |
| CN201341132Y (en) * | 2009-02-17 | 2009-11-04 | 东南大学 | Despreading apparatus based on MSK differential detection demodulation |
| JP2011087223A (en) * | 2009-10-19 | 2011-04-28 | Nec Corp | Communication apparatus, communication method and program |
| CN201541257U (en) * | 2009-11-11 | 2010-08-04 | 傲世通科技（苏州）有限公司 | Serial descrambling and despreading device for mobile communication system |
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