CN201341132Y

CN201341132Y - Despreading apparatus based on MSK differential detection demodulation

Info

Publication number: CN201341132Y
Application number: CNU2009200370821U
Authority: CN
Inventors: 刘昊; 唐玲; 蒋富龙; 姚国良; 吴建辉; 时龙兴
Original assignee: Southeast University
Current assignee: Southeast University
Priority date: 2009-02-17
Filing date: 2009-02-17
Publication date: 2009-11-04
Anticipated expiration: 2019-02-17

Abstract

The utility model discloses a despreading apparatus based on MSK differential detection demodulation belonging to the spread spectrum communication system despreading field, which comprises a clock control circuit, a 32 bits shift register, an inclusive-OR addition circuit, a 32 bits cycle shift register, a 6 bits subtracter, a maximal absolute value latch, a comparator, a symbol latch, a 3 bits counter and a 4 bits shift register. Despreading by the can reduce half of the related operand; can reduce work frequency and circuit power consumption if a serial correlator is used in the inclusive-OR addition circuit; and can simplifies the circuit if a parallel correlator is used.

Description

A kind of despreading device based on the MSK differential detection and demodulation

Technical field

The utility model relates to a kind of despreading device of communication system receiver, relates in particular to a kind of despreading device based on the MSK differential detection and demodulation, belongs to field of spread spectrum communication.

Background technology

The IEEE802.15.4 standard definition physical layer and two standards of media access control layer of low-speed wireless individual domain network (LR-WPAN).The characteristics of low rate, low-power consumption and the short-distance transmission of IEEE 802.15.4 standard make it be fit to be applied to the wireless sensor network field.IEEE 802.15.4 standard physical layer has been stipulated two frequency ranges: i.e. 2.4GHz frequency range and 868/915MHz frequency range, in the 2.4GHz of global general-use frequency range, regulation and stipulation employing 0-QPSK modulation scheme and direct sequence spread spectrum technology.

Because the O-QPSK modulation scheme that the IEEE802.15.4 standard adopts is the 0-QPSK modulation scheme of band half-sine pulse shaping, so this modulation scheme is equivalent to minimum shift keying (MSK) modulation, can adopt the method for MSK differential detection and demodulation and certain encoding process to realize demodulation to IEEE802.15.4 standard modulated signal.

In the prior art, despreading device directly carries out differential coding to demodulating data, carries out related operation again, with or interlock circuit in same or correlator quantity is more, make circuit comparatively complicated.

Summary of the invention

The utility model proposes a kind of despreading device based on the MSK differential detection and demodulation for the problem that solves related operation amount in the despreading.

A kind of despreading device based on the MSK differential detection and demodulation, its structure comprises: clock control circuit, 32 bit shift register, with or adder circuit, 32 circulating registers, 6 subtracters, the maximum value latch, comparator, the symbol latch, 3 digit counters and 4 bit shift register, wherein: the output of clock control circuit connects the input of 32 circulating registers respectively, the input of maximum value latch, the input of 3 digit counters, the input of the input of symbol latch and 4 bit shift register, input same or adder circuit connects the output of 32 bit shift register and the output of 32 circulating registers respectively, output same or adder circuit connects the input of 6 subtracters, the output of 6 subtracters connects the input of symbol latch respectively, the input of the input of comparator and maximum value latch, the output of maximum value latch connects the input of comparator, the output of comparator connects the input of maximum value latch and the input of symbol latch respectively, the output of 3 digit counters connects the input of symbol latch, and the output of symbol latch connects the input of 4 bit shift register.

The utility model is a kind of despreading device based on the MSK differential detection and demodulation of the IEEE802.15.4 of being applicable to standard, the related operation amount has reduced half than the general solution expanding method in its despreading, with or adder circuit in the minimizing of correlator quantity system power dissipation is reduced, circuit is simple.

Description of drawings

Fig. 1 is a structural representation of the present utility model.

Embodiment

As shown in Figure 1, a kind of despreading device based on the MSK differential detection and demodulation, its structure comprises: clock control circuit, 32 bit shift register, with or adder circuit, 32 circulating registers, 6 subtracters, the maximum value latch, comparator, the symbol latch, 3 digit counters and 4 bit shift register, wherein: with or adder circuit can be with 32 Bits Serial or parallel correlator, the output of clock control circuit connects the input of 32 circulating registers respectively, the input of maximum value latch, the input of 3 digit counters, the input of the input of symbol latch and 4 bit shift register, input same or adder circuit connects the output of 32 bit shift register and the output of 32 circulating registers respectively, output same or adder circuit connects the input of 6 subtracters, the output of 6 subtracters connects the input of symbol latch respectively, the input of the input of comparator and maximum value latch, the output of maximum value latch connects the input of comparator, the output of comparator connects the input of maximum value latch and the input of symbol latch respectively, the output of 3 digit counters connects the input of symbol latch, and the output of symbol latch connects the input of 4 bit shift register.

Clock control circuit utilizes the bit synchronization clock pulse in_chipclk_en of system clock in_clk and synchronous circuit output to produce smbclk_en, cclk_en and bitclk_en pulse signal, the duration of in_chipclk_en, smbclk_en, cclk_en and bitclk_en signal high level all is the clock cycle of in_clk.Suppose that in_clk is 16MHz, corresponding 1 cclk_en of 4 in_chipclk_en then, 16 corresponding 1 smbclk_en of in_chipclk_en, 1 corresponding 4 bitclk_en of smbclk_en.As shown in Figure 1, cclk_en exports to 32 circulating registers, maximum value latch and 3 digit counters respectively; Smbclk_en exports to maximum value latch, 3 digit counters, symbol latch and 4 bit shift register respectively; Bitclk_en exports to 4 bit shift register.

Despreading method is: per four of 32 PN0 sign indicating numbers to the symbol0 correspondence of IEEE802.15.4 standard code carry out (1,-1,-1,1) mapping obtains sequence PN0_1, again it is carried out the differential decoding computing and obtain sequence of symhols PN0_2, sequence of symhols PN0_2 is stored in 32 circulating registers; Whenever 32 bit data that receive and sequence of symhols PN0_2 and four bit sequences that whenever move to right under clock control thereof carry out together or related operation, obtain correlation logic_cvalue, and logic_cvalue deducts 16 and obtains signed_cvalue in 6 subtracters; The absolute value of signed_cvalue is compared with the value in the maximum value latch, if the absolute value of signed_cvalue greatly then deposit it in maximum value latch, the bigger signal is effective simultaneously, and the value of symbol of signed_cvalue deposits the highest order of symbol latch in when the bigger signal is effective; 3 digit counters begin counting when smbclk_en is effective, receive that whenever cclk_en pulse 3 digit counters add one, if the bigger signal is effective, then the value of 3 digit counters are deposited in low three in the symbol latch; Value in the symbol latch is written into 4 bit shift register when smbclk_en is effective, under the control of bitclk_en, carry out and go here and there conversion, serial output be the Bit data that final despreading is come out.

Claims

1, a kind of despreading device based on the MSK differential detection and demodulation, it is characterized in that: comprise clock control circuit, 32 bit shift register, with or adder circuit, 32 circulating registers, 6 subtracters, the maximum value latch, comparator, the symbol latch, 3 digit counters and 4 bit shift register, wherein: the output of clock control circuit connects the input of 32 circulating registers respectively, the input of maximum value latch, the input of 3 digit counters, the input of the input of symbol latch and 4 bit shift register, input same or adder circuit connects the output of 32 bit shift register and the output of 32 circulating registers respectively, output same or adder circuit connects the input of 6 subtracters, the output of 6 subtracters connects the input of symbol latch respectively, the input of the input of comparator and maximum value latch, the output of maximum value latch connects the input of comparator, the output of comparator connects the input of maximum value latch and the input of symbol latch respectively, the output of 3 digit counters connects the input of symbol latch, and the output of symbol latch connects the input of 4 bit shift register.