CN106656213A - Implementation method for low-complexity polarization code folding hardware framework based on k-segment decomposition - Google Patents
Implementation method for low-complexity polarization code folding hardware framework based on k-segment decomposition Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/65—Purpose and implementation aspects
- H03M13/6502—Reduction of hardware complexity or efficient processing
Abstract
The invention discloses an implementation method for a low-complexity polarization code folding hardware framework based on k-segment decomposition. The method comprises the following steps of S1.decomposing an n-stage SC decoding algorithm into k segments, wherein k is a factor of n and meets a relation that n is equal to kp, p is an integer, the code length of a polarization code is N and N is equal to 2n; S2.configuring (k-1) secondary decoders for the decomposed k-segment SC decoding algorithm and computing a folding set of each segment, wherein the number of decoding stages of each decoder is p stage; and S3.constructing the polarization code folding hardware framework according to the folding set of each segment, which is obtained in the step S2. According to the method, the hardware complexity is greatly reduced, the hardware resource consumption is reduced and the node resource utilization rate is increased.
Description
Technical field
The present invention relates to polarization code folds the implementation method of hardware architecture, the low complexity more particularly to decomposed based on k sections
Degree polarization code folds the implementation method of hardware architecture.
Background technology
Ar1kan proposes that polar code is the first kind of channel coding, is almost capable of achieving the symmetrical discrete nothing of binary system
The capacity (B-DMCs) of memory channel.Because its relatively low computation complexity is O (NlogN), wherein N is polarization code length；With
And the decoding architecture of fast Fourier transform Fast Fourier Transformation (FFT) forms, serial counteracting decoding
Successive cancellation (SC) algorithm has become one of maximally effective polarization decoding algorithm.Most of polarization codes
Decoding scheme has all entered row decoding process based on SC.
But the basic decoding principle that follows of SC decoding algorithms be using with the bit information feedback information the most that translates by
Enter row decoding according to order bit-by-bit, such decoded operation brings huge hardware resource consumption problem.For N-bit code
Long polarization code, the computing unit needed for it is N log2N, through existing sequential hardware optimal design, with precomputation
Mixed node hardware architecture in, the hardware processing element number for needing altogether is N-1.It can thus be seen that when the code length of polarization code
When the order of magnitude is larger, the hardware processing element needed for decoding is in the same order of magnitude with code length.Such hardware configuration is consumed
Substantial amounts of hardware resource.According to the property of polarization code itself, polarization code can be only achieved when code length tends to infinite and approach perfume (or spice)
The property of dense line.When our hardware platform resources occupation is limited, traditional SC decoding hardwares are designed to restrict pole
Change the lethal factor of code code length.
The content of the invention
Goal of the invention：It is an object of the invention to provide a kind of can effectively reduce decomposing based on k sections for hardware resource consumption
Low complex degree polarization code fold hardware architecture implementation method.
Technical scheme：To reach this purpose, the present invention is employed the following technical solutions：
It is of the present invention based on k sections decompose low complex degree polarization code fold hardware architecture implementation method, including with
Lower step：
S1：N level SC decoding algorithms are decomposed into into k sections, k is the factor of n, meet the relational expression of n=kp, p is integer, polarized
The code length of code is N, and N=2n；
S2：For decomposed k sections SC decoding algorithm, the individual secondary decoder of configuration (k-1), the decoding level of each decoder
Number is p levels, and according to formula (1) each section of folding set is calculated：
......
In formula (1), SiFor i-th section of folding set, 1≤i≤(k-1), total operation that w is each folding set is made
Number, i.e. SiIn have w element,Then x1=w/2p-1-2n-p,It is per section of folding operation vector,Represent i-th
M-th folding operation of section,
S3：The each section of folding set obtained according to step S2 builds polarization code and folds hardware architecture.
Further, step S1 is comprised the following steps：
S1.1：It is determined that input：For N number of input data [y of a frame polarization code1,y2,...,yN], try to achieve corresponding LLR
Value, is designated asWhereinForThe situation of middle q=0, r=1,1≤t≤N, q represents decoding
The LLR of device i-stage output, r represent the r time node result of calculation of going forward side by side in original decoder；Determine that code length to be decoded is N,
The hop count of required segmentation is k；
S1.2：Segmentation decoding function is set up according to following steps：
S1.2.1：If n=log2N, and p=n/k；
S1.2.2：Judge whether hop count k is 1：If k=1, willIt is 2 to be input into into code lengthpSolution
Code device carries out traditional decoding and calculates, and obtains 2pBit decoding resultAnd willAs decoding letter
Several output, terminates the operation of epicycle；Otherwise, if variable h=1, subsequently into step S1.2.3；
S1.2.3：If h≤2p/ 2, then variable j=2h-1, i=1 are made, subsequently into step S1.2.4；Otherwise, enter
Step S1.2.9；
S1.2.4：If i≤2n-p, then willInput code a length of 2pDecoder passed
The decoding of system is calculated, and calculates the corresponding LLR value in jth positionSubsequently into step S1.2.5；Otherwise, into step
S1.2.6；
S1.2.5：The numerical value of variable i adds one, and into step S1.2.4；
S1.2.6：Call segmentation decoding functionBy segmentation decoding
The output of function is assigned to variable
S1.2.7：Call segmentation decoding functionBy segmentation decoding function
Output be assigned to variable
S1.2.8：The numerical value of variable h adds one, and into step S1.2.3；
S1.2.9：Obtain N-bit decoding resultAnd willAs the defeated of segmentation decoding function
Go out, terminate epicycle operation.
Beneficial effect：The invention discloses a kind of low complex degree polarization code decomposed based on k sections folds the reality of hardware architecture
Existing method, for the high problem of script long code polarization code hardware resource consumption, is decomposed into k sections by SC decoding algorithms first, each
Section can be 2 by code lengthpShort code decoding procedure combination complete.Then in corresponding hardware architecture design, pass through
The iteration of short code polarization code framework is folded, and realizes that long code is decoded.Hardware complexity is greatly reduced, hardware resource is reduced and is disappeared
Consumption, improves node resource utilization rate.
Description of the drawings
Fig. 1 is the 8 bit SC decoding flow charts of traditional SC decoding algorithms；
Fig. 2 folds showing for hardware architecture for the 8 bit SC decodings decomposed based on k=3 sections of the specific embodiment of the invention
It is intended to；
Fig. 3 folds showing for hardware architecture for the 64 bit SC decodings decomposed based on k=3 sections of the specific embodiment of the invention
It is intended to.
Specific embodiment
Technical scheme is further introduced with reference to specific embodiment.
Traditional SC decoding algorithms are introduced first.
Consider a polarization code (N, K, A), wherein N represents the code length of polarization code, and K represents effective information number in polarization code, A
Represent effective information bit set.If the vector to be decoded that receiving terminal is received is yi=(y1,...,yN), the decoding of receiving terminal
As a result it is expressed asIf uiIt is not effective information bit, we willZero setting.Otherwise decoding bit can be with table
It is shown as：
Wherein,Define transmission probability.LLR (log- used in decoding computing
Likelihood ratio) calculating, LLR is defined as follows：
The algorithm of LLR meets following recurrence Relation：
Traditional SC decoders meet FFT dish decoding rules.
Butterfly decoding flow process degree is shown in Fig. 1.Fig. 1 gives a 8 bit SC decoding flow chart, has altogether in this decoding flow process
Contain 3 grades (3=log8).
The low complex degree polarization code decomposed based on k sections that this specific embodiment is described below folds hardware architecture
Implementation method, comprises the following steps：
S1：N level SC decoding algorithms are decomposed into into k sections, k is the factor of n, meet the relational expression of n=kp, p is integer, polarized
The code length of code is N, and N=2n；
Step S1 is comprised the following steps：
S1.1：It is determined that input：For N number of input data [y of a frame polarization code1,y2,...,yN] (the i.e. input of decoder
Data), corresponding LLR value is tried to achieve, it is designated asWhereinForThe feelings of middle q=0, r=1
Condition, 1≤t≤N, q represents that the LLR that decoder i-stage is exported, r represent the r time node result of calculation of going forward side by side in original decoder；
Determine that code length to be decoded is N, the hop count of required segmentation is k；
S1.2：Segmentation decoding function is set up according to following steps：
S1.2.1：If n=log2N, and p=n/k；
S1.2.2：Judge whether hop count k is 1：If k=1, willIt is 2 to be input into into code lengthpSolution
Code device carries out traditional decoding and calculates, and obtains 2pBit decoding resultAnd willAs decoding letter
Several output, terminates the operation of epicycle；Otherwise, if variable h=1, subsequently into step S1.2.3；
S1.2.3：If h≤2p/ 2, then variable j=2h-1, i=1 are made, subsequently into step S1.2.4；Otherwise, enter
Step S1.2.9；
S1.2.4：If i≤2n-p, then willInput code a length of 2pDecoder passed
The decoding of system is calculated, and calculates the corresponding LLR value in jth positionSubsequently into step S1.2.5；Otherwise, into step
S1.2.6；
S1.2.5：The numerical value of variable i adds one, and into step S1.2.4；
S1.2.6：Call segmentation decoding functionBy segmentation decoding
The output of function is assigned to variable
S1.2.7：Call segmentation decoding functionBy segmentation decoding function
Output be assigned to variable
S1.2.8：The numerical value of variable h adds one, and into step S1.2.3；
S1.2.9：Obtain N-bit decoding resultAnd willAs the defeated of segmentation decoding function
Go out, terminate epicycle operation.
S2：For decomposed k sections SC decoding algorithm, decoder is configured.If each section of all one decoder of distribution is hard
Part framework, then need k p level decoder to complete the n level design of encoder of script altogether.In each section, due to only distributing
One decoder, then to complete the coding tasks of this section of script needs to carry out the folding multiplexing of different number of times.Following table gives often
One section of folding times for completing p level decoders needed for a primitive operation.
Each section of table 1 completes the folding times of p level decoders needed for a primitive operation
From the folding times of upper table it is found that there is the possibility of parallel work-flow between compartment.For example, i-th section of decoding is defeated
First group 2 is gone outpThe decoding result of individual LLR, then i+1 section can start working, at the same time, i-th section still in work shape
State carries out next group 2pThe decoding of individual LLR.Thus it is rational that we set a short code decoder on per section.But need
It should be noted that the folding times of final stage are one, that is to say, that be not the presence of parallel computation between last two sections, then
We merge into a p level decoder by last two sections.The final decoder of this sample specific embodiment is set as that (k-1) is individual
P level decoders.Each section of folding set is calculated according to formula (4)：
......
In formula (4), SiFor i-th section of folding set, 1≤i≤(k-1) makes total operand that w is each folding set, i.e. SiMiddle tool
There is w element,Then x1=w/2p-1-2n-p,It is per section of folding operation vector,Represent i-th
M-th folding operation of section,
S3：The each section of folding set obtained according to step S2 builds polarization code and folds hardware architecture.
In addition, the folding operation for each section, can be calculated in the form of streamline.Because the folding in section
It is folded to be not related to mutual feedback information, so the operation of section interior folding can greatly shorten because of folding band using streamline form
The time delay for coming increases.
Using the decoding frameworks of the polarization code SC with precomputation function as the basis for folding.Each secondary decoder is deferred to
The design basis of the framework.Fig. 2 gives the 8- bit decoder hardware architecture figures based on three sections of decomposition.It is original with estimated
Calculating 8 bit decoders of function needs 7 mixed node modules.8 bits have corresponded to 3 grades of decodings.In this embodiment,
Original three-level decoding algorithm is first divided into three sections by us, then per section is completed by the secondary decoder that series is 1, further according to hardware
Two sections fold the rule for merging after in design, and eventually through two secondary decoders all operations are completed.Each secondary decoder
For 2- bit decoders.Then final folding framework only needs to two mixed node modules, compared to 7 original mixed nodes
Module, the design substantially reduces original hardware complexity.
Fig. 3 gives the 64- bit decoder hardware architecture figures based on three sections of decomposition.It is original with precomputation function
64 bit decoders need 63 mixed node modules.64 bits have corresponded to 6 grades of decodings.In the design, we first will be original
Six grades of decoding algorithms be divided into three sections, then per section is completed by the secondary decoder that series is 2, further according to two sections after in hardware design
The rule for merging is folded, eventually through two secondary decoders all operations are completed.Each secondary decoder is 4- bit decodings
Device.Then final folding framework only needs to 6 mixed node modules, and compared to 63 original mixed node modules, this is concrete
Embodiment substantially reduces original hardware complexity.
For the hardware superiority that more preferable comparative analysis the design brings, index " hardware resource utilization " is defined for decoding
The ratio of required computing unit number and the computing unit number of the actual offer of hardware.Calculating list in SC decoding algorithms, needed for decoding
First number is N log2N, and under different hardware designs, actual computing unit number is the computing module that hardware structure includes in itself
Quantity is multiplied by has translated the delay cycle that a frame is consumed.
According to the mentality of designing of the individual secondary decoder of this specific embodiment (k-1), it is easy to obtain the design framework institute
The computing unit number M of consumption is as follows：
According to the pile line operation in the distribution of folding set, and each section, the time delay that the design is consumed can be calculated
Quantity L is as follows：
It is possible thereby to calculate the hardware resource utilization (HUR) of the design：
According to the computing formula of HUR, Frame analysis can be carried out from different segmentation situations k to different code lengths N, analyze
The results list is as follows：
HUR contrast tables under the difference N of table 2 and k values
As k=1, only 1 section altogether is represented, that is, do not carry out a section operation splitting, it is original in other words
Decoding framework does not carry out a section interior folding.Find out from upper table, the folding framework that this specific embodiment is proposed when k is not 1
It is significantly improved on hardware resource utilization, this illustrates that the design of this specific embodiment is effective.
Hardware resource consumption analysis is carried out below：
The core of this specific embodiment is intended to reduce the hardware complexity of SC decodings.In other words, this specific embodiment party
The core of formula be ensure that hardware resource it is limited in the case of still can complete long code SC decoding demand.This specific embodiment party
Formula is folded mainly for decoding computing unit.After folding, hardware resource consumption is expressed according to decoding computing unit number.
Lower table analysis illustrates the decoding computing unit number needed for this specific embodiment：
Hardware structure computing unit resource comparison table under the difference N of table 3 and k values
From table 3 it can be seen that as k=1, representing only 1 section altogether, that is, a section operation splitting is not carried out, change sentence
Talking about exactly original decoding framework does not carry out a section interior folding.From table 3 it can be seen that when k not be 1 when this specific embodiment
The folding framework of proposition has obvious reduction in hardware resource consumption, and this illustrates that the design of this specific embodiment is effective
's.
VLSI site-test analysis are carried out below：
According to the thought of this specific embodiment, it is each with k that inventor realizes different N on Altera Stratix V
Specification decoder, its resource consumption is as follows：
Decoder hardware under the different polarization code specifications of table 4 realizes that resource consumption is contrasted
Table 4 gives the contrast of two groups of code lengths.For the decoder of 8- bits, the decoder after 2 sections of decomposition has been carried out
Resource consumption is the half being segmented.For the decoder of 024- bits, the resource of the decoder after 3 sections of decomposition has been carried out
Consumption is 1/10th for being segmented.Hard-wired True Data again demonstrates the effective of this specific embodiment
Property.
Claims (2)
1. the low complex degree polarization code for being decomposed based on k sections folds the implementation method of hardware architecture, it is characterised in that：Including following step
Suddenly：
S1：N level SC decoding algorithms are decomposed into into k sections, k is the factor of n, meet the relational expression of n=kp, p is integer, polarization code
Code length is N, and N=2n；
S2：For decomposed k sections SC decoding algorithm, (k-1) individual secondary decoder is configured, the decoding series of each decoder is
P levels, according to formula (1) each section of folding set is calculated：
In formula (1), SiFor i-th section of folding set, 1≤i≤(k-1), total operand that w is each folding set is made,
That is SiIn have w element,Then x1=w/2p-1-2n-p,It is per section of folding operation vector,Represent i-th
M-th folding operation of section,
S3：The each section of folding set obtained according to step S2 builds polarization code and folds hardware architecture.
2. the low complex degree polarization code decomposed based on k sections according to claim 1 folds the implementation method of hardware architecture, its
It is characterised by：Step S1 is comprised the following steps：
S1.1：It is determined that input：For N number of input data [y of a frame polarization code1,y2,...,yN], corresponding LLR value is tried to achieve, remember
ForWhereinForThe situation of middle q=0, r=1,1≤t≤N, q represents decoder i-th
The LLR of level output, r represent the r time node result of calculation of going forward side by side in original decoder；Code length to be decoded is determined for N, required point
The hop count of section is k；
S1.2：Segmentation decoding function is set up according to following steps：
S1.2.1：If n=log2N, and p=n/k；
S1.2.2：Judge whether hop count k is 1：If k=1, willIt is 2 to be input into into code lengthpDecoder
Carry out traditional decoding to calculate, obtain 2pBit decoding resultAnd willAs decoding functions
Output, terminates the operation of epicycle；Otherwise, if variable h=1, subsequently into step S1.2.3；
S1.2.3：If h≤2p/ 2, then variable j=2h-1, i=1 are made, subsequently into step S1.2.4；Otherwise, into step
S1.2.9；
S1.2.4：If i≤2n-p, then willInput code a length of 2pDecoder carry out it is traditional
Decoding is calculated, and calculates the corresponding LLR value in jth positionSubsequently into step S1.2.5；Otherwise, into step S1.2.6；
S1.2.5：The numerical value of variable i adds one, and into step S1.2.4；
S1.2.6：Call segmentation decoding functionBy segmentation decoding function
Output be assigned to variable
S1.2.7：Call segmentation decoding functionBy the defeated of segmentation decoding function
Go out to be assigned to variable
S1.2.8：The numerical value of variable h adds one, and into step S1.2.3；
S1.2.9：Obtain N-bit decoding resultAnd willAs the output of segmentation decoding function, knot
Beam epicycle is operated.
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