CN113988279A - Output current reading method and system of storage array supporting negative value excitation - Google Patents
Output current reading method and system of storage array supporting negative value excitation Download PDFInfo
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Abstract
The invention discloses a method and a system for reading out output current of a storage array supporting negative value excitation, wherein the system comprises the following steps: the device comprises a complement code coding module, a control module, a current reversing module, an accumulation module, an activation module, a pooling module and an analog-to-digital conversion module. The excitation is input bit by bit in a binary complement mode, the output current is converted into voltage through the current reversing module and the accumulating module, and then the reading is finished through the activating module, the pooling module and the digital-to-analog conversion module. The application of the complementary code coding can effectively represent negative value excitation, and the problem of low neural network reasoning precision caused by discarding the negative value excitation is avoided; the current reversal module is enabled when reading out the sign bit current, realizes conversion from binary complement to decimal by matching with a coding mode, finishes accumulation of output current in an analog domain, reduces analog-to-digital conversion times required in the reading process, and reduces the power consumption and the time delay of a reading system. Based on the two points, the reading system realizes more perfect support for negative excitation.
Description
Technical Field
The invention relates to a storage array output current reading method and system supporting negative value excitation, and belongs to the field of neural network algorithm hardware implementation.
Background
In recent years, a storage and computation integrated architecture has been widely focused and researched, and the basic idea is to store weight mapping into a storage and computation array, so that some simple but huge data amount logic computation functions are completed in a memory, and the data transmission amount and the transmission distance between the memory and a processor are reduced.
The principle of operation of a classical non-volatile memory array is shown in FIG. 1, in order to compute two multiplication matrices
Storing the values of the weight matrix W in a storage array in the form of conductance, and exciting
The value of the voltage is input to the input end of the storage and calculation array in a voltage mode, the operation result in a current mode is obtained from the output end of the storage and calculation array, and the reading system is used for reading the output current of the storage and calculation array to complete the storage and calculation integration process. The storage and computation integrated architecture is very fit with a neural network algorithm due to the characteristic of being suitable for matrix operation, and is often used as a hardware implementation architecture of the neural network algorithm.
As neural network algorithms develop, the negative inputs (stimuli at the current level) and outputs (stimuli passed to the next level) take an increasingly important position in training and reasoning. This trend of neural network algorithms is also reflected in the application of activation functions: i.e. more and more activation functions with negative output, such as Tanh function, leak _ Relu function, etc., are used for the construction of the network structure. This is because, when the problem faced by the algorithm is more complex or the algorithm is used in certain characteristic fields, these negative values carry part of the critical information, which is indispensable for implementing the whole network function.
However, the existing storage array output current sensing system cannot support negative excitation well due to the constraint that binary representation negative values are difficult to realize in a hardware domain and the like. In the face of negative excitations that may occur, current readout systems have mainly two processing modes as shown in fig. 2.
As shown in fig. 2(a), the first approach is to simply replace the activation function with a non-negative output, such as the leakage _ Relu function with the Relu function, to ensure that after passing through the activation function, no negative excitation passes to the next layer. The processing mode avoids the problem of negative value excitation, but essentially only abandons the negative value and does not solve the problem of the requirement on negative value operation. When some neural network algorithms applied to specific fields are faced, the adoption of the processing mode can cause poor network training effect and low inference precision. From the interpretability deep learning point of view analysis, this is because simply discarding the negative value excitation causes too much information to be lost, and the neural network itself needs the part of information to update the network parameters. Therefore, the processing mode is only suitable for a small part of scenes and has considerable limitation.
As shown in fig. 2(b), the second approach is to first perform analog-to-digital conversion on the output result of the storage array through an analog-to-digital conversion device, and then process the negative excitation in the digital domain instead of the analog domain. The treatment method has the following defects: 1. each bit of data needs to be subjected to analog-to-digital conversion, and the excessive times of analog-to-digital conversion bring huge power consumption and quite high time delay; 2. the digital domain is limited by binary system, the processing of negative value is complex, and the circuit implementation needs more logic units, resulting in the increase of circuit cost and area, so the processing mode can seriously affect the performance of the circuit such as energy consumption ratio, computing power and the like, and is not suitable for the hardware implementation scene of large-scale neural network.
Disclosure of Invention
The invention provides a storage and computation array output current reading method and system supporting negative value excitation, and aims to solve the problems that an existing storage and computation array output current reading system cannot well support negative value excitation, so that the neural network algorithm hardware is poor in training effect, low in reasoning precision, high in power consumption and the like when being realized.
A first object of the present invention is to provide a method and a system for reading out an output current of a storage array supporting negative excitation, wherein the system comprises: the device comprises a complement coding module, a control module, a current reversing module, an accumulation module, an activation module, a pooling module and an analog-to-digital conversion module;
the current reversing module, the accumulating module, the activating module, the pooling module and the analog-to-digital conversion module are sequentially connected;
the control module is used for providing a control signal; the complement coding module is used for converting the original excitation into a complement form and inputting the complement form into the storage and calculation array; the current reversing module is used for reversing the output current of the storage and calculation array; the accumulation module is used for accumulating the current bit by bit; the activation module is used for activating function operation in a hardware implementation algorithm; the pooling module is used for pooling operation in a hardware implementation algorithm; the analog-to-digital conversion module is used for converting an analog signal and a digital signal. Optionally, the input excitation complement generated by the complement coding module includes N-bit values, including 1-bit sign bit and N-1-bit data bits.
Optionally, the process of inputting the complement of the original excitation into the storage array includes: and inputting bit by bit, namely inputting the lowest bit of the data bits, sequentially inputting the data bits from low to high, and finally inputting the sign bit.
Optionally, the control signal provided by the control module includes: and enabling signals of the current reversing module.
Optionally, the enabling signal of the current reversal module controls whether the current reversal module works, and the specific process includes:
when a data bit is input, the current reversing module is not enabled, and does not work;
and when the sign bit is input, enabling the current reversing module to work, wherein the current reversing module is used for reversing the output current of the computing array corresponding to the sign bit.
Optionally, the working process of the system includes:
s1: the original excitation is converted into complementary excitation after passing through a complementary coding module, the complementary code has a code width of N bits and comprises a 1-bit sign bit and an N-1 bit data bit;
s2: inputting the complementary code form excitation into a calculation array bit by bit for calculation: inputting the lowest order bit of the data bit, inputting each data bit from low to high in sequence, and finally inputting the sign bit;
s3: processing and calculating the output current of the array bit by bit, and accumulating the output current in an accumulation module according to the sequence from the low bit of data to the high bit of data to the sign bit;
for the output current corresponding to the N-1 data bits, the current reversing module is not enabled, and the output current is not reversed;
enabling the current reversing module for the output current corresponding to the 1 sign bit, and enabling the output current to flow into the accumulating module after the output current is reversed;
s4: after all the data bits and sign bits are accumulated, transmitting the accumulated value to a subsequent activation module and a subsequent pooling module, and obtaining an operation result V _ out of the layer network after activation and pooling;
s5: and transmitting the V _ out to an analog-to-digital conversion module, converting the V _ out into a digital code value and outputting the digital code value. And (5) transmitting the output result to a lower-layer network if necessary, and repeating the process.
Optionally, the input excitation complement is an 8-bit complement.
A second object of the present invention is to provide a method for reading out output current of a storage array supporting negative excitation, which is implemented based on the above system for reading out output current of a storage array supporting negative excitation, and the method includes:
the method comprises the following steps: the original excitation is converted into complementary excitation after passing through a complementary coding module, the complementary code has a code width of N bits and comprises a 1-bit sign bit and an N-1 bit data bit;
step two: inputting the complementary code form excitation into a calculation array bit by bit for calculation: inputting the lowest order bit of the data bit, inputting each data bit from low to high in sequence, and finally inputting the sign bit;
step three: processing and calculating the output current of the array bit by bit, and accumulating the output current in an accumulation module according to the sequence from the low bit of data to the high bit of data to the sign bit;
for the output current corresponding to the N-1 data bits, the current reversing module is not enabled, and the output current is not reversed;
enabling the current reversing module for the output current corresponding to the 1 sign bit, and enabling the output current to flow into the accumulating module after the output current is reversed;
step four: after all the data bits and sign bits are accumulated, transmitting the accumulated value to a subsequent activation module and a subsequent pooling module, and obtaining an operation result V _ out of the layer network after activation and pooling;
step five: and transmitting the V _ out to an analog-to-digital conversion module, converting the V _ out into a digital code value and outputting the digital code value. And (5) transmitting the output result to a lower-layer network if necessary, and repeating the process.
A third object of the present invention is to provide a neural network computing apparatus, comprising:
a receive port for receiving an input stimulus;
storing and calculating an array; the output current reading system of the storage array supporting negative excitation is used for outputting a calculation result.
A fourth object of the present invention is to provide a neural network hardware system, wherein the hardware system includes:
the neural network computing device described above;
a memory for storing input data;
and the processor is used for reading the input data from the memory and inputting the input data into the neural network computing device so as to calculate the input data.
Optionally, the memory is further configured to: storing a computer program;
the processor is further configured to: invoking the computer program from the memory to run the neural network computing device.
The invention has the beneficial effects that:
compared with the existing reading system scheme, firstly, the excitation input to the storage array in the reading system adopts a binary complement form, and can effectively represent a negative value, so that the problems of poor neural network training effect and low inference precision caused by discarding the negative value excitation are solved;
secondly, the introduction of the current reversal module helps to realize the process of converting binary complement to decimal in a hardware domain, the readout system of the invention completes the accumulation of the output current of the array in an analog domain, reduces the required analog-to-digital conversion times, and for the excitation of an N-bit complement form, the conventional scheme needs to perform N times of analog-to-digital conversion, and the scheme of the invention only needs to perform 1 time of analog-to-digital conversion after the accumulation is completed, thereby reducing the power consumption and the time delay of the readout system. The reading system of the invention realizes more perfect support for negative excitation based on the two points.
In addition, the current reversal module introduced by the invention can be realized by only a plurality of MOS tubes, and the circuit cost is low. In the working process of the reading system, the reverse module only needs to work once for each group of output current, and the power consumption of the module is low. The control module additionally draws a signal with only 1 bit for enabling the current reversal module, and the control time sequence is simple.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 shows a schematic diagram of the operation of a non-volatile memory array.
FIG. 2 shows a block diagram of two approaches to negative excitation for a prior art readout system; where fig. 2(a) is a block diagram of processing by an activation function that replaces the output without negative values, and fig. 2(b) is a block diagram of processing negative value excitations in the digital domain by analog-to-digital conversion.
Fig. 3 shows a block diagram of the read-out system of the invention.
Fig. 4 shows an 8T current-reversing module circuit diagram of one embodiment of the invention.
Fig. 5 shows a flow chart of the operation of the read-out system of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
The first embodiment is as follows:
the embodiment provides a system for reading out output current of a storage array supporting negative value excitation, which is characterized by comprising: the device comprises a complement coding module, a control module, a current reversing module, an accumulation module, an activation module, a pooling module and an analog-to-digital conversion module;
the current reversing module, the accumulating module, the activating module, the pooling module and the analog-to-digital conversion module are sequentially connected;
the control module is used for providing a control signal; the complement coding module is used for converting the original excitation into a complement form and inputting the complement form into the storage and calculation array; the current reversing module is used for reversing the output current of the storage and calculation array; the accumulation module is used for accumulating the current bit by bit; the activation module is used for activating function operation in a hardware implementation algorithm; the pooling module is used for pooling operation in a hardware implementation algorithm; the analog-to-digital conversion module is used for converting an analog signal and a digital signal.
The reading system of the embodiment inputs the data in a complementary code form at the input end of the memory array, can effectively represent negative value excitation, and avoids the problems of poor neural network training effect and low inference precision caused by discarding the negative value excitation; meanwhile, in the system reading process, accumulation of the output current of the memory array is completed in an analog domain, and the required analog-to-digital conversion times are reduced. The system realizes good support for negative value excitation by combining complementary form excitation and a current reversal module.
Example two:
the embodiment provides a system for reading out output current of a storage array supporting negative value excitation, which is characterized by comprising: the device comprises a complement coding module, a control module, a current reversing module, an accumulation module, an activation module, a pooling module and an analog-to-digital conversion module;
the current reversing module, the accumulating module, the activating module, the pooling module and the analog-to-digital conversion module are sequentially connected;
the control module is used for providing control signals of the current reversing module, the accumulating module, the activating module, the pooling module and the analog-to-digital converter;
the complement coding module is used for converting the original excitation into a complement form and inputting the complement form into the storage array, wherein the input excitation complement comprises N-bit numerical values which comprise 1-bit sign bit and N-1-bit data bit;
the process of inputting the complement of the original excitation into the computational array includes: and inputting bit by bit, namely inputting the lowest bit of the data bits, sequentially inputting the data bits from low to high, and finally inputting the sign bit.
The current reversing module is used for realizing the reversing of the output current of the memory array; the circuit diagram of the current reversing module in this embodiment is shown in fig. 4. The enabling signal of the current reversal module controls whether the current reversal module works, and the specific process comprises the following steps:
when a data bit is input, the current reversing module is not enabled, and does not work;
and when the sign bit is input, enabling the current reversing module to work, wherein the current reversing module is used for reversing the output current of the computing array corresponding to the sign bit.
The accumulation module is used for accumulating the current bit by bit; the analog-to-digital conversion module is used for converting an analog signal and a digital signal.
The working process of the computing array output current reading system based on the current reversing module of the embodiment comprises the following steps:
s1: the original excitation is converted into complementary excitation after passing through a complementary coding module, the complementary code has a code width of N bits and comprises a 1-bit sign bit and an N-1 bit data bit;
s2: inputting the complementary code form excitation into a calculation array bit by bit for calculation: inputting the lowest order bit of the data bit, inputting each data bit from low to high in sequence, and finally inputting the sign bit;
s3: processing and calculating the output current of the array bit by bit, and accumulating the output current in an accumulation module according to the sequence from the low bit of data to the high bit of data to the sign bit;
for the output current corresponding to the N-1 data bits, the current reversing module is not enabled, and the output current is not reversed;
enabling the current reversing module for the output current corresponding to the 1 sign bit, and enabling the output current to flow into the accumulating module after the output current is reversed;
s4: after all the data bits and sign bits are accumulated, transmitting the accumulated value to a subsequent activation module and a subsequent pooling module, and obtaining an operation result V _ out of the layer network after activation and pooling;
s5: and transmitting the V _ out to an analog-to-digital conversion module, converting the V _ out into a digital code value and outputting the digital code value. And (5) transmitting the output result to a lower-layer network if necessary, and repeating the process.
The reading system of the embodiment inputs the data in a complementary code form at the input end of the memory array, can effectively represent negative value excitation, and avoids the problems of poor neural network training effect and low inference precision caused by discarding the negative value excitation; meanwhile, in the system reading process, accumulation of the output current of the memory array is completed in an analog domain, and the required analog-to-digital conversion times are reduced. The system realizes good support for negative value excitation by combining complementary form excitation and a current reversal module.
In addition, the current reversal module in the embodiment only uses 8 MOS tubes, so that the circuit cost is low; in the working process of the reading system, the input current reversing module excited by each group of complement forms only needs to work once, and the power consumption of the module is low. The control module additionally draws a signal with only 1 bit for enabling the current reversal module, and the control time sequence is simple.
Example three:
the present embodiment provides a method for reading out an output current of a storage array supporting negative excitation, which is implemented based on a system for reading out an output current of a storage array supporting negative excitation in the second embodiment, and the method in the present embodiment includes the following steps:
the method comprises the following steps: the original excitation is converted into complementary excitation after passing through a complementary coding module, the complementary code has a code width of N bits and comprises a 1-bit sign bit and an N-1 bit data bit;
step two: inputting the complementary code form excitation into a calculation array bit by bit for calculation: inputting the lowest order bit of the data bit, inputting each data bit from low to high in sequence, and finally inputting the sign bit;
step three: processing and calculating the output current of the array bit by bit, and accumulating the output current in an accumulation module according to the sequence from the low bit of data to the high bit of data to the sign bit;
for the output current corresponding to the N-1 data bits, the current reversing module is not enabled, and the output current is not reversed;
enabling the current reversing module for the output current corresponding to the 1 sign bit, and enabling the output current to flow into the accumulating module after the output current is reversed;
step four: after all the data bits and sign bits are accumulated, transmitting the accumulated value to a subsequent activation module and a subsequent pooling module, and obtaining an operation result V _ out of the layer network after activation and pooling;
step five: and transmitting the V _ out to an analog-to-digital conversion module, converting the V _ out into a digital code value and outputting the digital code value. And (5) transmitting the output result to a lower-layer network if necessary, and repeating the process.
Example four:
the embodiment provides a method and a system for reading out output current of a storage array supporting negative excitation.
Taking the multiplication of two matrices of size 2 x 2 as an example, the calculation
And
the convolution result of (c):
Y＝-2*3+0+2*5+0＝4
the matrix X is represented in 4bits complement form as shown in the following four tables:
sign bit:
| 1 | 0 |
| 0 | 0 |
bit 2 of data bit:
| 1 | 0 |
| 0 | 0 |
| 1 | 0 |
| 0 | 0 |
bit 0 of the data bit:
| 0 | 0 |
| 1 | 1 |
the excitation signals are input bit by bit and are respectively operated with the matrix W, and four operation results of each bit are added. The operation results from the sign bit to the 0 th bit of the data bit are respectively: 3,5,3,2.
And obtaining an output result after accumulation: out 3 (-8) +5 4+3 + 2+ 1-4
According to the calculation result, the convolution result calculated by using the traditional mathematical calculation method is equal to the convolution result obtained by using the method provided by the invention, so that the correctness of the scheme provided by the invention can be verified.
Example five: verification of the feasibility of the readout system from a mathematical point of view
For convenience of understanding, the present embodiment uses two matrices of the minimum matrix unit size 2 × 2 as an operation object; the 8-bit complement is used as a specific encoding format, and the complement includes a 1-bit sign bit and a 7-bit data bit. In practical use, the reading system has no limit on the size of the matrix, and the matrix operation of different sizes does not influence the feasibility of the scheme. In practical use, the present readout system has no limitation on the number of encoding bits, and the specific number of encoding bits depends on the size of the operation parameter.
For arbitrary matrix
And
the convolution results are shown in the following formula (1):
Y＝X11*W11+X12*W12+X21*W21+X22*W22 (1)
when the elements in the matrix X are converted into two's complement, the binary relation is shown in the following formula (2):
wherein b issSign bit, b0～b6Refers to the data bits.
X＝bs*(-27)+b6*26+b5*25+b4*24+b3*23+b2*22+b1*21+b0*20 (2)
When the complementary excitation is input bit by bit and accumulated, the output result is shown as the following formula (3):
wherein the content of the first and second substances,
finger XijAt x position of (e.g.
Finger X11The sign bit of (c).
From the above calculation results, it can be seen that equation (1) is equal to equation (3), and the correctness of the calculation method of the present invention can be verified.
Some steps in the embodiments of the present invention may be implemented by software, and the corresponding software program may be stored in a readable storage medium, such as an optical disc or a hard disk.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (10)
1. A storage array output current sensing system supporting negative excitation, the system comprising: the device comprises a complement coding module, a control module, a current reversing module, an accumulation module, an activation module, a pooling module and an analog-to-digital conversion module;
the current reversing module, the accumulating module, the activating module, the pooling module and the analog-to-digital conversion module are sequentially connected;
the control module is used for providing a control signal; the complement coding module is used for converting the original excitation into a complement form and inputting the complement form into the storage and calculation array; the current reversing module is used for reversing the output current of the storage and calculation array; the accumulation module is used for accumulating the current bit by bit; the activation module is used for activating function operation in a hardware implementation algorithm; the pooling module is used for pooling operation in a hardware implementation algorithm; the analog-to-digital conversion module is used for converting an analog signal and a digital signal.
2. The system of claim 1, wherein the input excitation complement generated by the complement encoding module comprises an N-bit value including a 1-bit sign bit and N-1-bit data bits.
3. The system of claim 2, wherein inputting the complement of the original excitation into the computational array comprises: and inputting bit by bit, namely inputting the lowest bit of the data bits, sequentially inputting the data bits from low to high, and finally inputting the sign bit.
4. The system of claim 3, wherein the control signals provided by the control module comprise: and enabling signals of the current reversing module.
5. The system according to claim 4, wherein the enabling signal of the current reversing module controls whether the current reversing module operates or not, and the specific process comprises:
when a data bit is input, the current reversing module is not enabled, and does not work;
and when the sign bit is input, enabling the current reversing module to work, wherein the current reversing module is used for reversing the output current of the computing array corresponding to the sign bit.
6. The system of claim 5, wherein the operation of the system comprises:
s1: the original excitation is converted into complementary excitation after passing through a complementary coding module, the complementary code has a code width of N bits and comprises a 1-bit sign bit and an N-1 bit data bit;
s2: inputting the complementary code form excitation into a calculation array bit by bit for calculation: inputting the lowest order bit of the data bit, inputting each data bit from low to high in sequence, and finally inputting the sign bit;
s3: processing and calculating the output current of the array bit by bit, and accumulating the output current in an accumulation module according to the sequence from the low bit of data to the high bit of data to the sign bit;
for the output current corresponding to the N-1 data bits, the current reversing module is not enabled, and the output current is not reversed;
enabling the current reversing module for the output current corresponding to the 1 sign bit, and enabling the output current to flow into the accumulating module after the output current is reversed;
s4: after all the data bits and sign bits are accumulated, transmitting the accumulated value to a subsequent activation module and a subsequent pooling module, and obtaining an operation result V _ out of the layer network after activation and pooling;
s5: and transmitting the V _ out to an analog-to-digital conversion module, converting the V _ out into a digital code value, outputting the digital code value, transmitting an output result to a lower-layer network if necessary, and repeating the process.
7. A method for reading output current of a storage array supporting negative excitation, wherein the method is implemented based on the storage array output current reading system supporting negative excitation in any one of claims 1 to 6, and the method comprises:
the method comprises the following steps: the original excitation is converted into complementary excitation after passing through a complementary coding module, the complementary code has a code width of N bits and comprises a 1-bit sign bit and an N-1 bit data bit;
step two: inputting the complementary code form excitation into a calculation array bit by bit for calculation: inputting the lowest order bit of the data bit, inputting each data bit from low to high in sequence, and finally inputting the sign bit;
step three: processing and calculating the output current of the array bit by bit, and accumulating the output current in an accumulation module according to the sequence from the low bit of data to the high bit of data to the sign bit;
for the output current corresponding to the N-1 data bits, the current reversing module is not enabled, and the output current is not reversed;
enabling the current reversing module for the output current corresponding to the 1 sign bit, and enabling the output current to flow into the accumulating module after the output current is reversed;
step four: after all the data bits and sign bits are accumulated, transmitting the accumulated value to a subsequent activation module and a subsequent pooling module, and obtaining an operation result V _ out of the layer network after activation and pooling;
step five: and transmitting the V _ out to an analog-to-digital conversion module, converting the V _ out into a digital code value, outputting the digital code value, transmitting an output result to a lower-layer network if necessary, and repeating the process.
8. A neural network computing device, comprising:
a receive port for receiving an input stimulus;
storing and calculating an array;
the output current sensing system of a storage array supporting negative excitation of any of claims 1-6, for outputting the calculation.
9. A neural network hardware system, comprising:
the neural network computing device of claim 8;
a memory for storing input data;
and the processor is used for reading the input data from the memory and inputting the input data into the neural network computing device so as to calculate the input data.
10. The neural network hardware system of claim 9,
the memory is further configured to: storing a computer program;
the processor is further configured to: invoking the computer program from the memory to run the neural network computing device.
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| CN114400031B (en) * | 2022-03-24 | 2022-07-08 | 之江实验室 | Complement mapping RRAM (resistive random access memory) storage and calculation integrated chip and electronic equipment |
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