CN102663987B - Display driving method and display driving device of dual-channel video signals - Google Patents
Display driving method and display driving device of dual-channel video signals Download PDFInfo
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- CN102663987B CN102663987B CN201210073331.9A CN201210073331A CN102663987B CN 102663987 B CN102663987 B CN 102663987B CN 201210073331 A CN201210073331 A CN 201210073331A CN 102663987 B CN102663987 B CN 102663987B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
- G06F3/1423—Digital output to display device ; Cooperation and interconnection of the display device with other functional units controlling a plurality of local displays, e.g. CRT and flat panel display
- G06F3/1431—Digital output to display device ; Cooperation and interconnection of the display device with other functional units controlling a plurality of local displays, e.g. CRT and flat panel display using a single graphics controller
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
- G09G5/39—Control of the bit-mapped memory
- G09G5/393—Arrangements for updating the contents of the bit-mapped memory
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2352/00—Parallel handling of streams of display data
Abstract
Embodiments of the invention disclose a display driving method and a display driving device of dual-channel video signals, relating the field of signal processing. The method and the device can merge dual-channel video signals into one-channel video signal containing dual-channel video information, wherein the dual-channel video signals are different in clock frequencies and completely different in contents. The method comprises reading and temporarily storing first video signals and second video signals in an interval of a clock period, and outputting the read and temporarily stored first and second video signals in the same clock period, wherein sub-pixels of the outputted first and second video signals are assigned at intervals. The method and the device of the invention are applied in dual-vision display.
Description
Technical field
The present invention relates to signal transacting field, particularly relate to a kind of display drive method and device thereof of two-way video-signal.
Background technology
The development of display technique has brought double-vision display, and this display on same display screen, can demonstrate different images, and is presented to the user be positioned at right side on the left of display respectively.
Such as, on automobile, driver needs to check GPS by display, and the passenger simultaneously on front passenger's seat wants to watch entertainment by display, and a regular display can not meet the demand of both sides certainly simultaneously.Double vision shows this new technology can solve this problem well.While the information showing GPS to driver, double-vision display can also show to passenger the entertainment that passenger wants.
But, inventor is realizing finding in process of the present invention, double-vision display of the prior art also fails to solve well a problem for the vision signal completely independently vision signals different for two clock frequencies permeated simultaneously containing two video image informations, and this makes troubles to the application of double-vision display.
Summary of the invention
Technical matters to be solved by this invention is the display drive method and the device thereof that provide a kind of two-way video-signal, can be not identical and the diverse vision signal of content merges into the vision signal that a road comprises two-path video information by two-way clock frequency.
For solving the problems of the technologies described above, the display drive method of two-way video-signal of the present invention and device thereof adopt following technical scheme:
A display drive method for two-way video-signal, described two-way video-signal comprises the first vision signal and the second vision signal, and described method comprises:
Read with the interval of a clock period and keep in the first vision signal and the second vision signal;
With the identical clock period by described reading and the first temporary vision signal and the second vision signal export, export the sub-pixel intervals arrangement of the first vision signal and the second vision signal.
Read with the interval of a clock period and keep in the first vision signal and the second vision signal is specially:
Read the second vision signal with the interval of the clock period of second vision signal and be temporarily stored in fifo registers;
Read with the interval of the clock period of first vision signal the second vision signal of being temporarily stored in fifo registers and be temporarily stored in random access memory;
Read the first vision signal with the interval of the clock period of first vision signal and be temporarily stored in the second vision signal in random access memory, and the first vision signal of described reading and the second vision signal are kept in a buffer.
Described first vision signal of described reading and the second vision signal being kept in is specially in a buffer:
By temporary in a buffer for the sub-pixel data interval of the first vision signal of described reading and the second vision signal.
A display drive apparatus for two-way video-signal, described two-way video-signal comprises the first vision signal and the second vision signal, and described device comprises:
Reading cells, for reading with the interval of a clock period and keeping in the first vision signal and the second vision signal;
Output unit, for the identical clock period by described reading and the first temporary vision signal and the second vision signal export, export the sub-pixel intervals arrangement of the first vision signal and the second vision signal.
Described reading cells comprises:
First reads memory module, for reading the second vision signal with the interval of the clock period of second vision signal and being temporarily stored in fifo registers,
With
For reading the second vision signal of being temporarily stored in fifo registers with the interval of the clock period of first vision signal and being temporarily stored in random access memory;
Second reads memory module, for the second vision signal reading the first vision signal with the interval of the clock period of first vision signal and be temporarily stored in random access memory, and the first vision signal of described reading and the second vision signal are kept in a buffer.
Described second read memory module specifically for:
Read the first vision signal with the interval of the clock period of first vision signal and be temporarily stored in the second vision signal in random access memory, and by temporary in a buffer for the sub-pixel data interval of the first vision signal of described reading and the second vision signal.
In the inventive solutions, read with the interval of a clock period and keep in the first vision signal and the second vision signal, afterwards, with the identical clock period by described reading and the first temporary vision signal and the second vision signal export, by the first vision signal read and the second vision signal are synchronously kept in and are exported simultaneously, and export the sub-pixel intervals arrangement of the first vision signal and the second vision signal, be equivalent to output one tunnel process process and comprise the vision signal of two-path video signal content, disparity barrier on double vision display panel or the effect of lenticulation, the effect of the double vision display that can realize ideal.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, below the accompanying drawing used required in describing embodiment is briefly described, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is the display drive method process flow diagram one of two-way video-signal in the embodiment of the present invention;
Fig. 2 is the display drive method flowchart 2 of two-way video-signal in the embodiment of the present invention;
Fig. 3 is the second video frequency signal time sequence figure in the embodiment of the present invention;
Fig. 4 is the first video frequency signal time sequence figure in the embodiment of the present invention;
Fig. 5 is buffer memory space schematic diagram in the embodiment of the present invention;
Fig. 6 is the display drive apparatus schematic diagram of two-way video-signal in the embodiment of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
Embodiment one
The embodiment of the present invention provides a kind of display drive method of two-way video-signal, and described two-way video-signal comprises the first vision signal and the second vision signal, and as shown in Figure 1, the method comprises:
Step S101, to read with the interval of a clock period and to keep in the first vision signal and the second vision signal;
In order to realize the object of simultaneous display two-path video signal simultaneously on a display panel, each two field picture of each road vision signal shows the content of half pixel on this display panel to multipotency.In the prior art, each clock period, one tunnel vision signal inputs the data of a pixel to display device, so, in order to can show two-path video signal and ensure certain display resolution on same display screen simultaneously, concerning each road vision signal, read this road vision signal with the interval of a clock period and namely mean the pixel data reading this road vision signal with the interval of a pixel.
After respectively the first vision signal and the second vision signal being read with the interval of a clock period, by the first vision signal read and the second vision signal are synchronously kept in and exported simultaneously, can realize showing synchronous while of the first vision signal and the second vision signal on same display panel.
As shown in Figure 2, step S101 is specially:
Step S1011, read the second vision signal with the interval of the clock period of second vision signal and be temporarily stored in fifo registers;
As shown in Figure 3, within the t1 time period, second vision signal enable signal is high level, this shows within this time period, when the rising edge of each the second video signal clock signal arrives, second vision signal upgrades the pixel data on the data bus of display device, and before the rising edge of next second video signal clock signal arrives, the pixel data on data bus remains unchanged.
The second counter in Fig. 3 is a binary addition counter, and the second vision signal enable signal is the enable signal of the second counter, and when the second vision signal enable signal is high level, the second counter is activated, and starts to carry out plus coujnt.When the second vision signal enable signal is high level and the rising edge of the second video signal clock signal arrives, the second counter does a binary addition operation; And when the second vision signal enable signal becomes low level, the second counter O reset.Particularly, before the start time of t1 time period arrives, the value of the second counter is zero, after entering the t1 time period, when first rising edge of the second video signal clock signal arrives, second counter be originally 0 output valve on add 1, then the output valve of the second counter becomes 1; When second rising edge of the second video signal clock signal arrives, second counter adds 1 to the output valve being originally 1, then according to binary addition rule, the output valve strain of the second counter is 10, but the second counter is a up counter, and output valve only has one, then now the last position 0 of 10 got by the second counter, house the first 1, now the output valve of the second counter becomes 0 from 1.
Fifo registers, being called for short FIFO, FIFO is a kind of typical high-speed buffer device, and the reading and writing data of synchronization fifo is driven by outside clock signal, is applicable to carry out buffer memory to video data stream at a high speed.In embodiments of the present invention, it drives jointly by the second counter and the second video signal clock signal, when the output valve of the second counter is 1 and the second video signal clock signal is negative edge, the pixel data that FIFO reads the second vision signal from data bus is temporarily stored in a storage space in FIFO, then as shown in Figure 3, within the t2 time period, the data of FIFO not on readout data bus, then between the pixel data that reads each time of FIFO and the front pixel data once read, a clock period of interval does not carry out reads pixel data, then after the second vision signal inputs the pixel data of a two field picture to the data bus of display device, FIFO in fact only reads and has kept in the pixel data of the half of second this two field picture of vision signal.
It should be noted that, binary figure place that the storage space of FIFO can store is just the number of bits of a pixel data, then each storage space in FIFO can only store a pixel data.
Step S1012, read with the interval of the clock period of first vision signal the second vision signal of being temporarily stored in fifo registers and be temporarily stored in random access memory;
As shown in Figure 4, similar with Fig. 3, within the t3 time period, first vision signal enable signal is high level, at this moment in section, when the rising edge of the first video signal clock signal arrives, the first vision signal upgrades the pixel data in another data bus.Similar with the second counter, the first vision signal enable signal is the enable signal of the first counter, and when the first vision signal enable signal is low level, the output valve of the first counter is always 0; When the first vision signal enable signal is high level, the output valve of the first counter changes when the rising edge of each the first video signal clock signal arrives, be a binary addition counter because the first counter is the same with the second counter, then the output valve of the first counter is the same with the second counter changes between 1 and 0.Concrete as shown in Figure 4, within the t3 time period, when the rising edge of the first video signal clock signal arrives, the output valve of the first counter becomes 1 or become 0 from 1 from 0.
Random access memory, be called for short RAM, when the output valve of the first counter is 0 and has pixel data in FIFO, read a pixel data in FIFO and write in a storage space in RAM, the pixel data that RAM reads each time all writes the storage space pointed by writing address of RAM, and after RAM terminates write, writing address upgrades, RAM adds 1 on existing writing address, and the storage space that the storage space that the writing address after renewal points to points to the front writing address of renewal is adjacent.
The output valve of the first counter be 0 but in FIFO without pixel data time, RAM does not perform read-write operation, meanwhile, does not also change and points to the writing address of storage space.
It should be noted that, the feature of FIFO is sequentially written in data sequence to export data, and the input sequence of the half-pixel data being equivalent to the second vision signal according to pixels data carries out buffer memory.
In the prior art, in vision signal after the data bus input one-row pixels data of display device, vision signal enters row off time, within this period of row off time, vision signal is suspended to display device input pixel data, be expert at after terminating off time, vision signal is to the pixel data of display device input next line.
Similarly, in vision signal after the pixel data of the complete frame of display device input, vision signal can enter the frame gap time, and within the frame gap time, vision signal is suspended to display device input pixel data.The length of frame gap time is the several times of horizontal-scanning interval, and the concrete length of horizontal-scanning interval is row data transmission period and row sum off time.
When the second vision signal is in row off time or frame gap time, the second vision signal is suspended to display device input pixel data, and the number of the pixel data stored in FIFO does not increase.And now no matter whether the first vision signal enable signal is still high level, all there is the moment that the first counter is 0, so be expert in off time or frame gap time, if there is pixel data in FIFO, RAM continues to perform the task of reading pixel data in FIFO, even if be expert at off time or frame gap time arrive before have pixel data in FIFO, the residual pixel data after arbitrary off time in FIFO all can be emptied by the reading-write activity of RAM.
Further, the price of high-capacity FIFO is comparatively high, for the consideration of cost, capacity for FIFO video data being carried out to buffer memory is less, in embodiments of the present invention, the minimum capacity of FIFO is the half of one-row pixels data size, and the minimum capacity of RAM can be designed to the size of a half-pixel data of a two field picture.
Especially, after the frame gap time, when the view data of next frame arrives, when RAM learns that the pixel data of now the second vision signal input is first pixel data of a two field picture according to the control signal of the second vision signal, RAM is by its writing address zero setting.
Step S1013, the second vision signal reading the first vision signal with the interval of the clock period of first vision signal and be temporarily stored in random access memory, and by the first vision signal of described reading and the second vision signal temporary in a buffer.
Particularly, by temporary in a buffer for the sub-pixel data interval of the first vision signal of described reading and the second vision signal.
As shown in Figure 4, within the t3 time period, first vision signal is to display device input pixel data, when the output valve of the first counter is 1 and the negative edge of the first video signal clock signal arrives, impact damper reads a pixel data of the first vision signal and a pixel data of the second vision signal simultaneously and is stored in the mode that sub-pixel intervals stores by two pixel datas in six storage spaces in impact damper successively, as shown in Figure 5, for six storage spaces of impact damper, 1a, 1b, 1c tri-storage spaces are for depositing three sub-pixel data of a pixel of the first vision signal, 2a, 2b, 2c tri-storage spaces are for depositing three sub-pixel data of a pixel of the second vision signal.
The pixel data of the first vision signal that impact damper reads inputs the data bus of data from the first vision signal, the pixel data of the second vision signal read is from the storage space of in RAM, whenever impact damper reads a pixel data in RAM, RAM is read address and is added 1.
It should be noted that, when the control signal of the first vision signal shows that the first vision signal inputs the picture signal of a new frame to display device, RAM is read address zero setting, point to first storage space in RAM, whenever impact damper reads a pixel data in RAM, RAM is read address and is added 1.
Step S102, with the identical clock period by described reading and the first temporary vision signal and the second vision signal export, export the sub-pixel intervals arrangement of the first vision signal and the second vision signal.
Because the first vision signal and the second vision signal are two-way completely independently vision signals, so the phase relation that the clock of two-path video signal is not fixed, even, the clock frequency of two-path video signal is not identical.In order to can show on same display panel simultaneously, reached after object unified to the clock of the first vision signal and the second vision signal, frequency by temporary first vision signal and the second vision signal, then export through the first temporary vision signal with the identical clock period with the second vision signal.
In embodiments of the present invention, output video signal clock signal is identical with the first video signal clock signal, and output video signal enable signal is the time delay of the first vision signal enable signal, and delay time is the one-period of the first video signal clock signal.When output video signal enable signal is high level and the rising edge of the first video signal clock signal arrives, impact damper is by storage space 1a, 2b, data in 1c export output video signal bus to, when the rising edge of next first video signal clock signal arrives, impact damper is by storage space 2a, 1b, data in 2c export output video signal bus to, when display panel shows, on display panel, laterally two adjacent pixels show two pixel datas sent when two adjacent rising edges arrive respectively, disparity barrier on double vision display panel or the effect of lenticulation, can reach to make way on the left of display and see the object of different video images with the user on right side.
In the technical scheme of the present embodiment, read with the interval of a clock period and keep in the first vision signal and the second vision signal, afterwards, with the identical clock period by described reading and the first temporary vision signal and the second vision signal export, by the first vision signal read and the second vision signal are synchronously kept in and are exported simultaneously, and export the sub-pixel intervals arrangement of the first vision signal and the second vision signal, be equivalent to output one tunnel process process and comprise the vision signal of two-path video signal content, disparity barrier on double vision display panel or the effect of lenticulation, the effect of the double vision display that can realize ideal.
Embodiment two
The embodiment of the present invention provides a kind of display drive apparatus of two-way video-signal, and as shown in Figure 6, this device comprises:
Reading cells 11, for reading with the interval of a clock period and keeping in the first vision signal and the second vision signal;
In order to realize the object of simultaneous display two-path video signal simultaneously on a display panel, each two field picture of each road vision signal shows the content of half pixel on this display panel to multipotency.In the prior art, each clock period, one tunnel vision signal inputs the data of a pixel to display device, so, in order to can show two-path video signal and ensure certain display resolution on same display screen simultaneously, concerning each road vision signal, reading cells 11 reads this road vision signal with the interval of a clock period and namely means the pixel data reading this road vision signal with the interval of a pixel.
After respectively the first vision signal and the second vision signal being read with the interval of a clock period, by the first vision signal read and the second vision signal are synchronously kept in and exported simultaneously, can realize showing synchronous while of the first vision signal and the second vision signal on same display panel.
As shown in Figure 6, shown reading cells 11 specifically comprises:
First reads memory module 111, for reading the second vision signal with the interval of the clock period of second vision signal and being temporarily stored in fifo registers, with for reading the second vision signal of being temporarily stored in fifo registers with the interval of the clock period of first vision signal and being temporarily stored in random access memory;
Particularly, as shown in Figure 3, within the t1 time period, second vision signal enable signal is high level, this shows within this time period, and when the rising edge of each the second video signal clock signal arrives, the second vision signal upgrades the pixel data on the data bus of display device, before the rising edge of next second video signal clock signal arrives, the pixel data on data bus remains unchanged.
The second counter in Fig. 3 is a binary addition counter, and the second vision signal enable signal is the enable signal of the second counter, and when the second vision signal enable signal is high level, the second counter is activated, and starts to carry out plus coujnt.When the second vision signal enable signal is high level and the rising edge of the second video signal clock signal arrives, the second counter does a binary addition operation; And when the second vision signal enable signal becomes low level, the second counter O reset.Particularly, before the start time of t1 time period arrives, the value of the second counter is zero, after entering the t1 time period, when first rising edge of the second video signal clock signal arrives, second counter be originally 0 output valve on add 1, then the output valve of the second counter becomes 1; When second rising edge of the second video signal clock signal arrives, second counter adds 1 to the output valve being originally 1, then according to binary addition rule, the output valve strain of the second counter is 10, but the second counter is a up counter, and output valve only has one, then now the last position 0 of 10 got by the second counter, house the first 1, now the output valve of the second counter becomes 0 from 1.
Fifo registers, being called for short FIFO, FIFO is a kind of typical high-speed buffer device, and the reading and writing data of synchronization fifo is driven by outside clock signal, is applicable to carry out buffer memory to video data stream at a high speed.In embodiments of the present invention, it drives jointly by the second counter and the second video signal clock signal, when the output valve of the second counter is 1 and the second video signal clock signal is negative edge, the pixel data that FIFO reads the second vision signal from data bus is temporarily stored in a storage space in FIFO, then as shown in Figure 3, within the t2 time period, the data of FIFO not on readout data bus, then between the pixel data that reads each time of FIFO and the front pixel data once read, a clock period of interval does not carry out reads pixel data, then after the second vision signal inputs the pixel data of a two field picture to the data bus of display device, FIFO in fact only reads and has kept in the pixel data of the half of second this two field picture of vision signal.
It should be noted that, binary figure place that the storage space of FIFO can store is just the number of bits of a pixel data, then each storage space in FIFO can only store a pixel data.
As shown in Figure 4, similar with Fig. 3, within the t3 time period, first vision signal enable signal is high level, at this moment in section, when the rising edge of the first video signal clock signal arrives, the first vision signal upgrades the pixel data in its data bus.Similar with the second counter, the first vision signal enable signal is the enable signal of the first counter, and when the first vision signal enable signal is low level, the output valve of the first counter is always 0; When the first vision signal enable signal is high level, the output valve of the first counter changes when the rising edge of each the first video signal clock signal arrives, be a binary addition counter because the first counter is the same with the second counter, then the output valve of the first counter is the same with the second counter changes between 1 and 0.Concrete as shown in Figure 4, within the t3 time period, when the rising edge of the first video signal clock signal arrives, the output valve of the first counter becomes 1 or become 0 from 1 from 0.
Random access memory, be called for short RAM, when the output valve of the first counter is 0 and has pixel data in FIFO, read a pixel data in FIFO and write in a storage space in RAM, the pixel data that RAM reads each time all writes the storage space pointed by writing address of RAM, and after RAM terminates write, writing address upgrades, RAM adds 1 on existing writing address, and the storage space that the storage space that the writing address after renewal points to points to the front writing address of renewal is adjacent.
The output valve of the first counter be 0 but in FIFO without pixel data time, RAM does not perform read-write operation, meanwhile, does not also change and points to the writing address of storage space.
It should be noted that, the feature of FIFO is sequentially written in data sequence to export data, and the input sequence of the half-pixel data being equivalent to the second vision signal according to pixels data carries out buffer memory.
In the prior art, in vision signal after the data bus input one-row pixels data of display device, vision signal enters row off time, within this period of row off time, vision signal is suspended to display device input pixel data, be expert at after terminating off time, vision signal is to the pixel data of display device input next line.
Similarly, in vision signal after the pixel data of the complete frame of display device input, vision signal can enter the frame gap time, and within the frame gap time, vision signal is suspended to display device input pixel data.The length of frame gap time is the several times of horizontal-scanning interval, and the concrete length of horizontal-scanning interval is row data transmission period and row sum off time.
When the second vision signal is in row off time or frame gap time, the second vision signal is suspended to display device input pixel data, and the number of the pixel data stored in FIFO does not increase.And now no matter whether the first vision signal enable signal is still high level, all there is the moment that the first counter is 0, so be expert in off time or frame gap time, if there is pixel data in FIFO, RAM continues to perform the task of reading pixel data in FIFO, even if be expert at off time or frame gap time arrive before have pixel data in FIFO, the residual pixel data after arbitrary off time in FIFO all can be emptied by the reading-write activity of RAM.
Further, the price of high-capacity FIFO is comparatively high, for the consideration of cost, capacity for FIFO video data being carried out to buffer memory is less, in embodiments of the present invention, the minimum capacity of FIFO is the half of one-row pixels data size, and the minimum capacity of RAM can be designed to the size of a half-pixel data of a two field picture.
Especially, after the frame gap time, when the view data of next frame arrives, when RAM learns that the pixel data of now the second vision signal input is first pixel data of a two field picture according to the control signal of the second vision signal, RAM is by its writing address zero setting.
Second reads memory module 112, for the second vision signal reading the first vision signal with the interval of the clock period of first vision signal and be temporarily stored in random access memory, and the first vision signal of described reading and the second vision signal are kept in a buffer.
Described second read memory module 112 specifically for: read the first vision signal with the interval of the clock period of first vision signal and be temporarily stored in the second vision signal in random access memory, and by temporary for the sub-pixel data interval of the first vision signal of described reading and the second vision signal in a buffer.
As shown in Figure 4, within the t3 time period, first vision signal is to display device input pixel data, when the output valve of the first counter is 1 and the negative edge of the first video signal clock signal arrives, impact damper reads a pixel data of the first vision signal and a pixel data of the second vision signal simultaneously and is stored in the mode that sub-pixel intervals stores by two pixel datas in six storage spaces in impact damper successively, as shown in Figure 5, for six storage spaces of impact damper, 1a, 1b, 1c tri-storage spaces are for depositing three sub-pixel data of a pixel of the first vision signal, 2a, 2b, 2c tri-storage spaces are for depositing three sub-pixel data of a pixel of the second vision signal.
The pixel data of the first vision signal that impact damper reads inputs the data bus of data from the first vision signal, the pixel data of the second vision signal read is from the storage space of in RAM, whenever impact damper reads a pixel data in RAM, RAM is read address and is added 1.
It should be noted that, when the control signal of the first vision signal shows that the first vision signal inputs the picture signal of a new frame to display device, RAM is read address zero setting, point to first storage space in RAM, whenever impact damper reads a pixel data in RAM, RAM is read address and is added 1.
Output unit 12, for the identical clock period by described reading and the first temporary vision signal and the second vision signal export, export the sub-pixel intervals arrangement of the first vision signal and the second vision signal.
Because the first vision signal and the second vision signal are two-way completely independently vision signals, so the phase relation that the clock of two-path video signal is not fixed, even, the clock frequency of two-path video signal is not identical.In order to can show on same display panel simultaneously, reached after object unified to the clock of the first vision signal and the second vision signal, frequency by temporary first vision signal and the second vision signal, output unit 12 exports through the first temporary vision signal with the identical clock period with the second vision signal again.
In embodiments of the present invention, output video signal clock signal is identical with the first video signal clock signal, and output video signal enable signal is the time delay of the first vision signal enable signal, and delay time is the one-period of the first video signal clock signal.When output video signal enable signal is high level and the rising edge of the first video signal clock signal arrives, impact damper is by storage space 1a, 2b, data in 1c export output video signal bus to, when the rising edge of next first video signal clock signal arrives, impact damper is by storage space 2a, 1b, data in 2c export output video signal bus to, when display panel shows, on display panel, laterally two adjacent pixels show two pixel datas sent when two adjacent rising edges arrive respectively, disparity barrier on double vision display panel or the effect of lenticulation, can reach to make way on the left of display and see the object of different video images with the user on right side.
In the technical scheme of the present embodiment, read with the interval of a clock period and keep in the first vision signal and the second vision signal, afterwards, with the identical clock period by described reading and the first temporary vision signal and the second vision signal export, by the first vision signal read and the second vision signal are synchronously kept in and are exported simultaneously, and export the sub-pixel intervals arrangement of the first vision signal and the second vision signal, be equivalent to output one tunnel process process and comprise the vision signal of two-path video signal content, disparity barrier on double vision display panel or the effect of lenticulation, the effect of the double vision display that can realize ideal.
Through the above description of the embodiments, those skilled in the art can be well understood to the mode that the present invention can add required common hardware by software and realize, and can certainly pass through hardware, but in a lot of situation, the former is better embodiment.Based on such understanding, technical scheme of the present invention can embody with the form of software product the part that prior art contributes in essence in other words, this computer software product is stored in the storage medium that can read, as the floppy disk of computing machine, hard disk or CD etc., comprise some instructions and perform method described in each embodiment of the present invention in order to make a computer equipment (can be personal computer, server, or the network equipment etc.).
The above; be only the specific embodiment of the present invention, but protection scope of the present invention is not limited thereto, is anyly familiar with those skilled in the art in the technical scope that the present invention discloses; change can be expected easily or replace, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection domain of described claim.
Claims (4)
1. a display drive method for two-way video-signal, described two-way video-signal comprises the first vision signal and the second vision signal, it is characterized in that, described method comprises:
Read with the interval of a clock period and keep in the first vision signal and the second vision signal, being specially: read the second vision signal with the interval of the clock period of second vision signal and be temporarily stored in fifo registers; Read with the interval of the clock period of first vision signal the second vision signal of being temporarily stored in fifo registers and be temporarily stored in random access memory; Read the first vision signal with the interval of the clock period of first vision signal and be temporarily stored in the second vision signal in random access memory, and by the first vision signal of described reading and the second vision signal of reading from random access memory temporary in a buffer;
With the clock period identical with the first video signal clock signal by described reading and the first temporary vision signal and the second vision signal export, export the first vision signal and the second vision signal sub-pixel intervals arrangement.
2. method according to claim 1, is characterized in that, described first vision signal of described reading and the second vision signal being kept in is specially in a buffer:
By temporary in a buffer for the sub-pixel data interval of the first vision signal of described reading and the second vision signal.
3. a display drive apparatus for two-way video-signal, described two-way video-signal comprises the first vision signal and the second vision signal, it is characterized in that, described device comprises:
Reading cells, for reading with the interval of a clock period and keeping in the first vision signal and the second vision signal; Described reading cells comprises: first reads memory module, for reading the second vision signal with the interval of the clock period of second vision signal and being temporarily stored in fifo registers, with for reading the second vision signal of being temporarily stored in fifo registers with the interval of the clock period of first vision signal and being temporarily stored in random access memory; Second reads memory module, for the second vision signal reading the first vision signal with the interval of the clock period of first vision signal and be temporarily stored in random access memory, and by the first vision signal of described reading and the second vision signal of reading from random access memory temporary in a buffer;
Output unit, for the clock period identical with the first video signal clock signal by described reading and the first temporary vision signal and the second vision signal export, export the first vision signal and the second vision signal sub-pixel intervals arrangement.
4. device according to claim 3, is characterized in that, described second read memory module specifically for:
Read the first vision signal with the interval of the clock period of first vision signal and be temporarily stored in the second vision signal in random access memory, and by temporary in a buffer for the sub-pixel data interval of the first vision signal of described reading and the second vision signal.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210073331.9A CN102663987B (en) | 2012-03-19 | 2012-03-19 | Display driving method and display driving device of dual-channel video signals |
| PCT/CN2012/084003 WO2013139126A1 (en) | 2012-03-19 | 2012-11-02 | Display driving method of dual-channel video signals, and device thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201210073331.9A CN102663987B (en) | 2012-03-19 | 2012-03-19 | Display driving method and display driving device of dual-channel video signals |
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| CN102663987A CN102663987A (en) | 2012-09-12 |
| CN102663987B true CN102663987B (en) | 2015-04-01 |
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| CN102663987B (en) * | 2012-03-19 | 2015-04-01 | 京东方科技集团股份有限公司 | Display driving method and display driving device of dual-channel video signals |
| CN108234818B (en) * | 2017-12-13 | 2020-10-20 | 苏州长风航空电子有限公司 | Method for realizing video frame memory round searching operation algorithm |
| CN110072124B (en) | 2018-01-24 | 2020-08-04 | 杭州海康威视数字技术股份有限公司 | Method and device for compounding video signals and electronic equipment |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1138800A (en) * | 1995-02-17 | 1996-12-25 | 株式会社日立制作所 | Method of and system for distributing digital audio image data |
| CN1549947A (en) * | 2002-05-16 | 2004-11-24 | ���ǵ�����ʽ���� | Liquid crystal display and method for driving the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5724063A (en) * | 1995-06-07 | 1998-03-03 | Seiko Epson Corporation | Computer system with dual-panel LCD display |
| JP2001249644A (en) * | 2000-03-03 | 2001-09-14 | Kyocera Corp | Liquid crystal display device |
| CN102663987B (en) * | 2012-03-19 | 2015-04-01 | 京东方科技集团股份有限公司 | Display driving method and display driving device of dual-channel video signals |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1138800A (en) * | 1995-02-17 | 1996-12-25 | 株式会社日立制作所 | Method of and system for distributing digital audio image data |
| CN1549947A (en) * | 2002-05-16 | 2004-11-24 | ���ǵ�����ʽ���� | Liquid crystal display and method for driving the same |
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| CN102663987A (en) | 2012-09-12 |
| WO2013139126A1 (en) | 2013-09-26 |
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