JP2001249644A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory interface circuit whose cost is low. SOLUTION: In a memory interface circuit 1 in an analog-to-digital converting circuit 2 converting an analog data signal for lighting a CRT or the like into the digital signal needed for lighting a simple matrix type liquid crystal panel, when a piece of a FIFO memory 5 having capacity enabling to store a data signal equivalent to one screen of the panel is used, the control of the memory operation of the memory is performed so that display data equivalent to one pixel of an upper screen and display data equivalent to one pixel of a lower screen are written in the memory in a form in which they are arranged alternatively by a memory control circuit when the input data signal is written in the memory. Then, the driving of the simple matrix type liquid crystal panel by a dual scanning system is performed by performing an ordinary data read-out operation with respect to the memory in which the data are stored by the above described operation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data conversion circuit for converting an analog signal used for lighting a CRT or a TFT liquid crystal panel into a digital signal required for lighting a simple matrix type liquid crystal panel. The present invention relates to a liquid crystal display device provided on a simple matrix type liquid crystal panel in which two screens are driven by a dual scan method.

[0002]

2. Description of the Related Art In order to drive a simple matrix type STN liquid crystal panel, usually, a voltage is applied to one selected scanning electrode, and the selected electrode is sequentially scanned in one frame. Drive is used.

However, this simple matrix type ST
When the N liquid crystal panel becomes a large liquid crystal panel of a VGA class or higher, the number of scanning electrodes increases, which shortens the selection time of the electrodes and makes it impossible to secure a sufficient effective driving voltage. The quality was degraded.

In order to solve such a problem, a dual-scan drive is used in which the display screen of the large liquid crystal panel is divided into an upper screen and a lower screen, and each screen is scanned simultaneously.

[0005] By using the dual scan drive, 6
Even a liquid crystal panel of 40 × 480 size has a substantial number of scanning electrodes of 240, so that it can be driven as a large liquid crystal panel while ensuring the same display quality as a small panel. Was.

However, dual scan driving is performed using single scan data such as an analog signal used to turn on a CRT or a TFT liquid crystal panel or a data signal for a simple matrix type liquid crystal panel which performs a normal line sequential driving. In such a case, a memory interface circuit for performing data signal array conversion between the single scan data output device and the dual scan drive liquid crystal panel is required.

According to this memory interface circuit, the input single scan data can be converted into a data array for dual scan and output by using one dual port memory or one random access general-purpose memory. it can.

However, since a memory having such a random access function has a plurality of address signal terminals, the number of input / output terminals increases, and a signal line used for input / output of the address signal also has a circuit. It had to be arranged on the substrate, which complicated the substrate design.

In addition, the designation of the memory address is performed at any time for one operation of writing or reading data to or from the memory. That is, address signals of a plurality of lines change in response to data writing and reading performed at high speed, but the plurality of address signals that change at high speed become noise sources, causing malfunction of the circuit,
Alternatively, the display quality of the liquid crystal panel was reduced.

In order to solve such a problem, there has been proposed a method of using a FIFO memory which does not require addressing in manufacturing a memory interface circuit.

Normally, the FIFO memory sequentially writes input data signals from an external circuit into the memory in accordance with the input arrangement, and also reads out data in the order stored in the memory, that is, when the data is input. An operation such as sequential reading is performed according to the order. Further, the data write operation and the read operation can be performed completely separately and asynchronously, and therefore, the data output operation is often used for a display memory which needs to be continuously output.

The schematic structure of a liquid crystal display device 28 using such a FIFO memory will be described below with reference to FIG.

According to FIG. 1, an analog-to-digital conversion circuit 25 (hereinafter referred to as A-to-D conversion circuit) converts an analog data signal into a digital data signal required for lighting a simple matrix type liquid crystal panel. -D
And a liquid crystal display device 28 comprising a simple scan type liquid crystal panel 3 driven by dual scan.
And in the memory interface circuit,
FIFO memories 26 and 29 are used.

The A / D conversion circuit 25 converts an input analog data signal into a digital data signal.
-D converter), a memory interface circuit 27 that performs data array conversion for driving the dual scan type liquid crystal panel, and a gray scale generator 13 that performs gray scale control when the liquid crystal panel is turned on. .

FIG. 14 is an image diagram showing the internal operation of the FIFO memories 26 and 29 in the memory interface circuit 27, and also shows the relationship between the output data and the liquid crystal panel 3. In the drawing, Du of the input / output data is data for lighting the upper screen, and Dl is data for lighting the lower screen.

When a FIFO memory is used in a dual scan memory interface circuit, data is output in the order of input.
For this purpose, as shown in FIG. 14, data arrangement conversion is performed by two FIFO memories, one for each of the upper and lower screens of the liquid crystal panel. The interface circuit receives single scan data (Du1,... DuN, Dl1,..., DIN) for one screen on the display surface, and the upper display surface data (Du1,.
Are written in sequence to the remaining lower screen display data (Dl1,
, DIN) is written to the other FIFO memory 29.

As described above, the upper screen display data and the lower screen display data are separately written using the two FIFO memories, so that the upper screen display data and the lower screen display data can be read separately. Lighting data for pixels at the same address on the upper and lower screens as shown in the A or B portions in FIG. 14 can be output separately and simultaneously, thereby realizing dual scan driving of the liquid crystal panel.

[0018]

However, the FIF
According to the liquid crystal display device 28 using the O memory, the general-purpose RA
Compared to M and dual port memory, FIFO memory, which has simple input / output lines and is often used for processing display data due to the operation method at the time of data input / output, is used for dual scan memory e-interface circuit. In addition, a total of two memories are required for the upper and lower screens of the liquid crystal panel irrespective of the capacity of the memory, thus increasing the cost of the memory interface circuit.

Therefore, an object of the present invention is to make it possible to control with a single FIFO memory having a capacity of one screen in a memory interface circuit for converting single scan data into dual scan data, and to reduce the number of memories as compared with the prior art. Another object of the present invention is to provide a low-cost liquid crystal display device by using a low-cost memory interface circuit.

[0020]

The liquid crystal display device of the present invention uses a CRT or TF for a simple matrix type liquid crystal panel in which two screens are driven by a dual scan method.
A simple matrix type liquid crystal display device provided with a data conversion circuit for converting an analog signal used for lighting a T liquid crystal panel into a digital signal, wherein the data conversion circuit converts the analog data signal into a digital data signal. An analog-to-digital converter, a memory unit having a capacity for storing a data signal for one screen of a liquid crystal panel converted into a digital signal by the analog-to-digital converter, and an input data signal being written into the memory unit. A memory control circuit that performs operation control on the memory means, and a data conversion circuit that converts a serial data signal read from the memory means into a parallel data signal such that data corresponding to the two screens are simultaneously output, The memory control circuit has an array of lighting pixels and a corresponding array. Means for writing a continuous input data signal to the memory means by writing alternately the display data for one pixel on one screen and the display data for one pixel on the other screen Is provided.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a liquid crystal display device of the present invention will be described in detail with reference to the drawings. FIG. 1 shows a simple matrix type liquid crystal display device of the present invention in which a data conversion circuit is provided for a simple matrix type liquid crystal panel in which two screens are driven.

An A / D conversion circuit 2 having a memory interface circuit 1 is arranged on a simple matrix type liquid crystal panel 3, thereby constituting a liquid crystal display device 4.

The liquid crystal panel 3 is driven by a dual scan system in which the display surface is divided into upper and lower parts so that the scanning electrodes are halved, and each of the scanning electrodes on the upper screen 6 and the lower screen 7 is simultaneously selected. Is done. Therefore, the LCD panel 3
A set of a segment-side driver 8 for inputting a display data signal and a set of a common-side driver 9 for inputting a signal to a scan electrode are provided for each of the upper and lower screens.

The memory interface circuit 1 constitutes a memory 5, and the memory 5 performs a FIFO operation for inputting and outputting data signals, and has a capacity capable of storing display data for one screen of the liquid crystal panel 3. .

Such a liquid crystal display device 4 has a CRT or a T
An analog signal used to turn on an FT liquid crystal panel or the like is input. This analog signal is mainly composed of a data signal including a luminance component, a horizontal synchronizing signal and a vertical synchronizing signal. Among these data signals, it is necessary to perform data processing for lighting a simple matrix type liquid crystal panel. After being converted into a digital signal by the A / D converter 10, it is temporarily stored in the memory 5. The horizontal synchronizing signal and the vertical synchronizing signal are input to the memory control circuit 11 to be used as reference signals for memory control.

Next, FIG. 2 shows a method of operating the memory. FIG. 1 is a conceptual diagram showing a general internal operation of the FIFO memory. The inside of the memory 14 is divided into a plurality of cells 15, and one cell stores data necessary for lighting one pixel. Shall be performed. Also figure
FIG. 3 is a simple operation timing chart at the time of the operation.

As described above, the FIFO memory does not have an address signal for specifying the address of a cell in the memory. ).

The FIFO memory continuously stores an input data signal in a cell inside the memory in the order of input in a data write operation, and continuously stores the data signal in a memory-internal cell arrangement order in a data read operation. Output. That is, in the normal operation of the FIFO memory, the input data 16 and the output data 17 have exactly the same arrangement.

In the input data signals shown in the figure, Du is data for lighting the upper screen of the display screen, Dl is data for lighting the lower screen, and Du1,..., DuN, Dl1,. The array means a data array when a single scan is performed on the display screen.

The above-described write operation and read operation are performed by a serial write clock (hereinafter, referred to as a serial write clock).
SWCK), serial read clock (hereinafter S)
RCK), and their operations can be performed asynchronously.

The write operation to the memory is generally performed by WE
The operation of the memory according to the signal levels of the WE signal and the IE signal is controlled by the signal and the IE signal, as shown in FIG.

That is, the operation inside the memory at the time of data writing is as follows: (1) store data in the memory, move one address pointer, and (2) move one address pointer according to the signal levels of the WE signal and the IE signal. Movement (Data is not stored at this time), (3) No operation,
Can be selected.

Next, a method of operating the memory according to the present invention will be described. FIGS. 5 and 7 are image diagrams showing the internal operation of the FIFO memory at the time of writing data, and FIGS. 6 and 8 are simple operation timing diagrams at the time of each operation.

In the present invention, at the time of data write operation, data storage (operation (1) in FIG. 4) and increment of the address pointer (operation (2) in FIG. 4) are alternately performed. Internally, this is an operation of sequentially storing input data while creating one empty cell as shown in FIG.

The display data for one screen of the liquid crystal panel (Du1,
.., DuN, Dl1,..., DlN), that is, when the data for the upper screen (Du1,. (Referred to as RSTW), the address pointer in the memory is reset, and the lower screen display data is written.

FIG. 7 shows an operation image inside the memory at this time, and FIG. 8 shows an operation timing. The writing of the lower screen display data is performed by alternately repeating the operations (1) and (2) shown in FIG. 4 on the empty cells created during the above-described upper screen display data writing operation. .

FIG. 9 shows an image at the time of reading data from the memory. In the normal operation of the FIFO memory, the data stored according to the arrangement of the input data is stored in a form in which the upper screen display data and the lower screen display data are alternately arranged by performing the operation method of the present invention. Therefore, when reading the data stored in the memory, the same operation as the general reading of the FIFO memory is performed, so that the upper screen display data and the lower screen display data are alternately arranged as shown in FIG. It is possible to output continuously with the obtained data.

However, in order to drive the liquid crystal panel by the dual scan method, it is necessary to convert a serial data signal output from the memory into a parallel data signal output to two systems of an upper screen and a lower screen. . Such data processing is performed by the data conversion circuit 12 shown in FIG.

FIG. 11 shows a data conversion circuit 18 composed of four flip-flops (hereinafter referred to as FFs) as an example of this circuit. FIG. 12 shows a simple operation timing of the conversion circuit 18.

In FIG. 11, FF19 and FF of the first and second stages are shown.
20 includes a clock S used for reading the memory.
A clock 21 having the same cycle as RCK is inputted, and a clock 24 having a cycle twice as long as the clock 21 is inputted to two FFs 22 and FF23 arranged in the third stage. Thereby, FF
The data for the upper screen display and the data for the lower screen display of the liquid crystal panel are separately output from Q22 and Q23 which are the outputs of the FF23 and FF23, respectively.

Here, the output data signal is a signal obtained by converting an analog signal for lighting a CRT or the like into a digital signal, and data for lighting one pixel is usually composed of a plurality of bits. Therefore, instead of directly inputting the digital signal to the liquid crystal panel, the digital signal is once input to the grayscale generator 13 in FIG. 1 and subjected to grayscale processing, and then to the upper screen display driver and the lower screen display driver. The liquid crystal panel is turned on by outputting the data.

Thus, according to the liquid crystal display device 4 having the above-described configuration, data processing conventionally performed by two FIFO memories can be performed by one FIFO memory.

[0043]

As described above, according to the liquid crystal display device of the present invention, in the writing operation of the FIFO memory used for the memory interface circuit in the A / D conversion circuit, in the ordinary FIFO memory, according to the arrangement of the input data. The data stored in the memory is controlled so that the data storage operation and the address pointer increment operation in the memory are alternately performed, so that the data for displaying the upper screen of the liquid crystal panel is stored in one empty cell in the memory. Can be written sequentially while making, and the remaining lower screen display data can be stored in the empty cell created earlier, thus the upper screen display data and lower screen display data of the liquid crystal panel inside the memory If data is stored in an alternate array, normal data read operation is performed Thus, the liquid crystal panel can be driven by the dual scan method, whereby the data processing conventionally performed by two FIFO memories is performed by one FIFO memory, and as a result, a lower price is obtained. A memory interface circuit could be provided, which provided a low-cost liquid crystal display device.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram having a block of an AD conversion circuit in a liquid crystal display device of the present invention.

FIG. 2 is an image diagram showing an internal operation of a conventional FIFO memory.

FIG. 3 is an operation timing chart of a conventional FIFO memory.

FIG. 4 is an explanatory diagram showing the operation contents of the memory with respect to the signal levels of the WE signal and the IE signal in the data write operation of the FIFO memory;

FIG. 5 is an image diagram showing an internal operation of the memory when data is written in the FIFO memory control according to the present invention.

FIG. 6 is an operation timing chart of a memory when writing upper screen display data of a display device in the FIFO memory control according to the present invention.

FIG. 7 is an image diagram showing an operation inside the memory at the time of data writing in the FIFO memory control according to the present invention.

FIG. 8 is an operation timing chart of a memory when writing lower screen display data of a display device in the FIFO memory control according to the present invention.

FIG. 9 is an image diagram showing an internal operation of the memory at the time of reading data in the FIFO memory control according to the present invention.

FIG. 10 is an operation timing diagram when reading data stored in a memory in FIFO memory control according to the present invention.

FIG. 11 is an internal configuration diagram of a data conversion circuit that performs serial-parallel conversion.

FIG. 12 is an operation timing chart when serial data is converted to parallel data in the data conversion circuit.

FIG. 13 is an explanatory diagram having blocks of an AD conversion circuit in a conventional liquid crystal display device.

FIG. 14 is an explanatory diagram showing an operation of a FIFO memory in a conventional memory interface circuit.

[Explanation of symbols]

 1,27 Memory interface circuit 2,25 Analog-digital conversion circuit 3 Simple matrix type liquid crystal panel 4,28 Liquid crystal display 5,14,26,29 FIFO memory 6 Upper screen 7 Lower screen 8 Segment driver 9 Common driver 10 analog-digital converter 11 memory control circuit 12, 18 data conversion circuit 13 gradation generator 15 cells 16 input data 17 output data 19, 20, 22, 23 flip-flops 21, 24 clocks

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2H093 NA10 NA13 NA33 NC22 NC23 NC24 NC29 NC49 NC90 ND34 ND50 ND54 5C006 AA11 AC17 AC24 AF03 AF27 AF42 AF43 AF81 BB12 BB14 BC16 BF02 FA05 FA12 FA51 5C080 AA10 BB06 DD08 DD27 EE29 FF12 JJ03 JJ04

Claims (1)

[Claims] 1. A simple matrix type liquid crystal panel in which two screens are driven by a dual scan system, and a simple data conversion circuit for converting an analog signal used for lighting a CRT or TFT liquid crystal panel into a digital signal. A matrix-type liquid crystal display device, wherein the data conversion circuit converts an analog data signal into a digital data signal, and a screen of a liquid crystal panel converted into a digital signal by the analog-digital converter. Memory means having a capacity for storing data signals for each minute, a memory control circuit for performing operation control when writing an input data signal to the memory means, and a serial data signal read out from the memory means for each of the two screens. Parallel data that outputs corresponding data at the same time And a data conversion circuit for converting the input data signal into a data signal. When the memory control circuit writes a continuous input data signal to the memory means in a corresponding array of the illuminated pixels, the memory control circuit is used for displaying one pixel of one screen. A liquid crystal display device comprising a writing means for alternately arranging and writing data and display data for one pixel of the other screen.