WO2013139126A1

WO2013139126A1 - Display driving method of dual-channel video signals, and device thereof

Info

Publication number: WO2013139126A1
Application number: PCT/CN2012/084003
Authority: WO
Inventors: 解红军
Original assignee: 京东方科技集团股份有限公司
Priority date: 2012-03-19
Filing date: 2012-11-02
Publication date: 2013-09-26
Also published as: CN102663987B; CN102663987A

Abstract

A display driving method of dual-channel video signals, and a device thereof relate to the field of signal processing, are applied in dual view display, and can merge dual-channel video signals, being different in clock frequencies and completely different in contents, into one-channel video signal comprising dual-channel video information. The method comprises: reading and temporarily storing first video signals and second video signals at an interval of a clock period (S101); and outputting the read and temporarily stored first and second video signals in the same clock period, sub-pixels of the output first and second video signals being arranged at intervals (S102).

Description

Dual-channel video signal display driving method and device thereof

The present invention relates to the field of signal processing, and in particular, to a display driving method and device for a dual video signal. Background technique

The development of display technology has brought people a dual-view display that can display different images on the same display and present them to the users on the left and right sides of the display.

For example, in a car, the driver needs to view the global positioning system through the display, and the passengers in the passenger seat want to watch the entertainment through the display. A normal display certainly cannot meet the needs of both parties. Dual vision shows that this new technology can solve this problem well. While displaying the GPS information to the driver, the dual vision display can also display the entertainment program desired by the passenger to the passenger.

However, in the process of implementing the present invention, the inventors have found that the dual-view display in the prior art has not been able to solve the problem of merging two independent video signals with different clock frequencies into one channel and two video image information. The problem of video signals, which brings inconvenience to the application of dual-view displays. Summary of the invention

The technical problem to be solved by the present invention is to provide a display driving method and device for a dual video signal, which can combine two video signals with different clock frequencies and completely different contents into one video signal containing two video information.

According to an embodiment of the present invention, a display driving method for a dual video signal is provided, where the dual video signal includes a first video signal and a second video signal, and the method includes:

Reading and temporarily storing the first video signal and the second video signal every other clock cycle;

The read and temporarily stored first video signal and second video signal are outputted in the same clock cycle, and the sub-pixels of the first video signal and the second video signal are output.

In one example, reading and temporarily storing the first video signal and the second video signal every other clock cycle are:

Reading the second video signal every other clock cycle of the second video signal and temporarily presenting first in first out In the register;

Reading a second video signal temporarily stored in the first-in first-out register every other first video signal clock period and temporarily storing it in the random access memory;

Reading the first video signal and the second video signal temporarily stored in the random access memory every other clock cycle of the first video signal, and temporarily buffering the read first video signal and the second video signal In the device.

In one example, the temporarily storing the read first video signal and the second video signal in a buffer are specifically:

The read first video signal and the sub-pixel data interval of the second video signal are temporarily stored in the buffer.

According to an embodiment of the present invention, a display driving device for a dual video signal is provided, where the dual video signal includes a first video signal and a second video signal, and the device includes:

Reading a storage unit, configured to read and temporarily store the first video signal and the second video signal every other clock cycle;

And an output unit, configured to output the read and temporarily stored first video signal and the second video signal in the same clock cycle, and output sub-pixel intervals of the first video signal and the second video signal.

In one example, the reading the storage unit includes:

a first read storage module, configured to read the second video signal every other clock cycle of the second video signal and temporarily stored in the first-in first-out register, and to read the clock cycle of every other first video signal There is a second video signal in the first-in first-out register and temporarily stored in the random access memory;

a second read storage module, configured to read the first video signal and the second video signal temporarily stored in the random access memory in a clock cycle of every other first video signal, and read the read first video signal And the second video signal is temporarily stored in the buffer.

In an example, the second read storage module is specifically configured to:

Reading the first video signal and the second video signal temporarily stored in the random access memory every other clock cycle of the first video signal, and reading the read first video signal and the sub-pixel data of the second video signal The interval is temporarily stored in the buffer.

In the embodiment of the present invention, the first video signal and the second video signal are read and temporarily stored every other clock cycle, and then the read and temporarily stored first video signal and the second are performed in the same clock cycle. Video signal output, by temporarily storing the read first video signal and the second video signal Outputting, and dividing the sub-pixels outputting the first video signal and the second video signal, equivalent to outputting a video signal processed and containing two video signal contents, passing through a parallax barrier on the dual-view display panel or It is the function of the lens grating, which can achieve the ideal double-view display effect. DRAWINGS

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments will be briefly described below. It is obvious that the drawings in the following description are only the present invention. For some embodiments, other drawings may be obtained from those of ordinary skill in the art without departing from the drawings.

1 is a flowchart 1 of a display driving method for a dual video signal according to an embodiment of the present invention; FIG. 2 is a second flowchart of a display driving method for a dual video signal according to an embodiment of the present invention; FIG. 3 is a second embodiment of the present invention; Video signal timing diagram;

4 is a timing diagram of a first video signal according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of a buffer storage space according to an embodiment of the present invention; FIG.

FIG. 6 is a schematic diagram of a display driving device for a dual video signal according to an embodiment of the present invention. detailed description

The technical solutions in the embodiments of the present invention are clearly and completely described in the following with reference to the accompanying drawings in the embodiments of the present invention. It is obvious that the described embodiments are a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present invention without making creative labor are within the scope of the present invention.

Embodiment 1

An embodiment of the present invention provides a display and driving method for a dual-channel video signal. The dual-channel video signal includes a first video signal and a second video signal. As shown in FIG. 1, the method includes:

Step S101: Read and temporarily store the first video signal and the second video signal every other clock cycle;

In order to realize the simultaneous simultaneous display of two video signals on one display panel, each frame image of each video signal can display at most half pixel content on the display panel. In the prior art, one video signal inputs a pixel point data to the display device every clock cycle, so that in order to simultaneously display two video signals on the same display screen and ensure a certain display definition, for each channel For video signals, the video signal is read every other clock cycle. That is to say, one pixel data of the video signal is read every other pixel.

After reading the first video signal and the second video signal every other clock cycle, by synchronously storing the read first video signal and the second video signal and simultaneously outputting, the first video signal and the first video signal can be realized. The two video signals are simultaneously synchronized and displayed on the same display panel.

As shown in FIG. 2, step S101 is specifically:

Step S1011: The second video signal is read every other second video signal clock period and temporarily stored in the first-in first-out register;

As shown in FIG. 3, during the tl time period, the second video signal enable signal is at a high level, which indicates that during the time period, when the rising edge of each second video signal clock signal arrives, the second video The signal updates the pixel data on the data bus of the display device, and the pixel data on the data bus remains unchanged until the rising edge of the next second video signal clock signal.

The second counter in FIG. 3 is a one-bit binary addition counter, the second video signal enable signal is an enable signal of the second counter, and when the second video signal enable signal is high, the second counter is started, starting Perform addition counting. When the second video signal enable signal is high and the rising edge of the second video signal clock signal comes, the second counter performs a one-bit binary addition; and when the second video signal enable signal goes low, The second counter is cleared. Specifically, the value of the second counter is zero before the start time of the t1 time period, and after entering the t1 time period, when the first rising edge of the second video signal clock signal arrives, the second counter is originally 0. When the output value is incremented by 1, the output value of the second counter becomes 1; when the second rising edge of the second video signal clock signal comes, the second counter adds 1 to the output value of the original 1, then according to binary addition The law, the output value of the second counter is 10, but the second counter is an adder counter, and the output value has only one bit. At this time, the second counter takes the last 0 of 10, and the first bit is 1, and the second counter is at this time. The output value changes from 1 to 0.

The first-in first-out register, referred to as FIFO, is a typical high-speed buffer device. The data read and write of the FIFO is driven by an external clock signal, which is suitable for buffering high-speed video data streams. In the embodiment of the present invention, the second counter and the second video signal clock signal are jointly driven. When the output value of the second counter is 1 and the second video signal clock signal is a falling edge, the FIFO reads from the data bus. A pixel data of the second video signal is temporarily stored in a storage space in the FIFO. As can be seen from FIG. 3, during the t2 time period, the FIFO does not read the data on the data bus, and the pixel data read by the FIFO each time The clock period of two second video signals is separated between the previously read pixel data, and then the second video signal inputs pixels of one frame image to the data bus of the display device. After the data, the FIFO actually reads and temporarily stores half of the pixel data of the frame image of the second video signal.

It should be noted that the number of binary digits that can be stored in one storage space of the FIFO is exactly one binary digit of one pixel data, and only one pixel data can be stored in each storage space in the FIFO.

Step S1012: reading a second video signal temporarily stored in the first-in first-out register every other first video signal clock period and temporarily storing it in the random access memory;

As shown in FIG. 4, similar to FIG. 3, during the t3 period, the first video signal enable signal is at a high level, during which time, when the rising edge of the first video signal clock signal arrives, A video signal updates pixel data in another data bus. Similar to the second counter, the first video signal enable signal is an enable signal of the first counter, and when the first video signal enable signal is low, the output value of the first counter is always 0; When the signal enable signal is high, the output value of the first counter changes when the rising edge of each first video signal clock signal arrives. Since the first counter is the same as the second counter, it is a binary adder, The output value of a counter varies between 1 and 0 as the second counter. Specifically, as shown in FIG. 4, during the t3 period, when the rising edge of the first video signal clock signal comes, the output value of the first counter changes from 0 to 1 or from 1 to 0.

Random access memory, referred to as RAM, when the output value of the first counter is 0 and there is pixel data in the FIFO, one pixel data in the FIFO is read and written into a storage space in the RAM, and each RAM is read. The pixel data is written into the storage space pointed to by the write address of the RAM. After the RAM finishes writing, the write address is updated, and the RAM is incremented by 1 to the existing write address, and the updated write address points to the storage space. Adjacent to the storage space pointed to by the write address before the update.

When the output value of the first counter is 0 but there is no pixel data in the FIFO, the RAM does not perform read and write operations, and does not change the write address to the memory space.

It should be noted that the FIFO is characterized by sequentially writing data sequentially outputting data, which is equivalent to half of the pixel data of the second video signal being buffered in the input order of the pixel data.

In the prior art, after the video signal inputs a row of pixel data to the data bus of the display device, the video signal enters a line gap time, during which the video signal pauses inputting pixel data to the display device during the line gap time. After the end, the video signal inputs the pixel data of the next line to the display device.

Similarly, after the video signal inputs the pixel data of the complete frame to the display device, the video signal The frame gap time is entered, and during the frame gap time, the video signal pauses to input pixel data to the display device. The length of the frame gap time is several times of the line scan time, and the specific length of the line scan time is the sum of the line data transmission time and the line gap time.

When the second video signal is at the line gap time or the frame gap time, the second video signal suspends input of pixel data to the display device, and the number of pixel data stored in the FIFO does not increase. At this time, regardless of whether the first video signal enable signal is still at a high level, there is a time when the first counter is 0, so if there is pixel data in the FIFO during the line gap time or the frame gap time of the second video signal The RAM continues to perform the task of reading the pixel data in the FIFO. Even if the FIFO memory has pixel data before the line gap time or the frame gap time of the second video signal, the remaining pixel data in the FIFO will be RAM after any gap time. The read-write action is cleared.

Further, the large-capacity FIFO is relatively expensive, and the capacity of the FIFO for buffering the video data is small for cost reasons. In the embodiment of the present invention, the minimum capacity of the FIFO is half of the size of one row of pixel data. The minimum capacity of the RAM can be designed to be the size of half of the pixel data of one frame of image.

In particular, after the frame gap time of the second video signal, when the image data of the next frame of the second video signal arrives, the RAM knows the pixel data input by the second video signal according to the control signal of the second video signal. When it is the first pixel data of one frame of image, the RAM writes it to the address setting step S1013, reads the first video signal and the second video temporarily stored in the random access memory in the clock cycle of every other first video signal. Signaling, and temporarily storing the read first video signal and the second video signal in a buffer.

Specifically, the read first video signal and the sub-pixel data interval of the second video signal are temporarily stored in the buffer.

As shown in FIG. 4, during the t3 period, the first video signal inputs pixel data to the display device. When the output value of the first counter is 1 and the falling edge of the first video signal clock signal arrives, the buffer simultaneously reads. Taking one pixel data of the first video signal and one pixel data of the second video signal and storing the two pixel data in a sub-pixel interval in the six storage spaces in the buffer, as shown in FIG. , for the six storage spaces of the buffer, three storage spaces la, lb, and lc are used to store three sub-pixel data of one pixel of the first video signal, and two storage spaces of 2a, 2b, and 2c are used for storing the second. Three sub-pixel data of one pixel of the video signal.

The pixel data of the first video signal read by the buffer is from the number of input data of the first video signal According to the bus, the pixel data of the read second video signal comes from a storage space in the RAM. Whenever the buffer reads a pixel data in the RAM, the RAM increments its read address by one.

It should be noted that when the control signal of the first video signal indicates that the first video signal inputs a new frame image signal to the display device, the RAM sets its read address to zero, pointing to the first storage space in the RAM, each When the buffer reads one pixel of data in the RAM, the RAM increments its read address by one.

Step S102: output the read and temporarily stored first video signal and the second video signal in the same clock cycle, and output sub-pixel spacing of the first video signal and the second video signal.

Since the first video signal and the second video signal are two completely independent video signals, the clocks of the two video signals have no fixed phase relationship, and even the clock frequencies of the two video signals are different. In order to be able to display on the same display panel at the same time, by temporarily storing the first video signal and the second video signal to achieve the purpose of unifying the clock and frequency of the first video signal and the second video signal, the temporary storage is performed. A video signal and a second video signal are output in the same clock cycle.

In the embodiment of the present invention, the output video signal clock signal is the same as the first video signal clock signal, and the output video signal enable signal is a delay of the first video signal enable signal, and the delay time is the first video signal clock signal. A cycle. When the output video signal enable signal is high and the rising edge of the first video signal clock signal comes, the buffer outputs the data in the storage spaces la, 2b, lc to the output video signal bus, in the next first video. When the rising edge of the signal clock signal comes, the buffer outputs the data in the storage space 2a, lb, 2c to the output video signal bus. When the display panel is displayed, two pixels adjacent to each other laterally on the display panel respectively display two The two pixel data sent when the adjacent rising edge arrives, through the parallax barrier or the lens grating on the dual-view display panel, can achieve the purpose of letting the users on the left and right sides of the display see different video images. .

In the technical solution of the embodiment, the first video signal and the second video signal are read and temporarily stored every other clock cycle, and then the read and temporarily stored first video signal and the same clock cycle are a second video signal output, by temporarily storing the read first video signal and the second video signal and simultaneously outputting, and outputting the sub-pixels of the output first video signal and the second video signal at intervals, corresponding to output The video signal processed and containing two video signal contents can realize the ideal double-view display effect through the parallax barrier or the lens grating on the dual-view display panel.

Embodiment 2

Embodiments of the present invention provide a display driving device for a dual video signal, as shown in FIG. The device includes:

The reading storage unit 11 is configured to read and temporarily store the first video signal and the second video signal every other clock cycle;

In order to realize the simultaneous simultaneous display of two video signals on one display panel, each frame image of each video signal can display at most half of the pixel content on the display panel. In the prior art, one video signal inputs a pixel point data to the display device every clock cycle, so that in order to simultaneously display two video signals on the same display screen and ensure a certain display definition, for each channel For the video signal, the read memory unit 11 reads the video signal every other clock cycle, that is, it reads one pixel data of the video signal every other pixel.

As shown in FIG. 6, the read storage unit 11 specifically includes:

The first read storage module 111 is configured to read the second video signal every other clock period of the second video signal and temporarily store it in the first-in first-out register, and read the clock cycle of every other first video signal The second video signal temporarily stored in the first-in first-out register is temporarily stored in the random access memory.

Specifically, as shown in FIG. 3, during the time period of tl, the second video signal enable signal is at a high level, which indicates that during the time period, when the rising edge of each second video signal clock signal arrives, The second video signal updates the pixel data on the data bus of the display device, and the pixel data on the data bus remains unchanged until the rising edge of the next second video signal clock signal.

The second counter in FIG. 3 is a one-bit binary addition counter, the second video signal enable signal is an enable signal of the second counter, and when the second video signal enable signal is high, the second counter is started, starting Perform addition counting. When the second video signal enable signal is high and the rising edge of the second video signal clock signal comes, the second counter performs a one-bit binary addition; and when the second video signal enable signal goes low, The second counter is cleared. Specifically, the value of the second counter is zero before the start time of the t1 time period, and after entering the t1 time period, when the first rising edge of the second video signal clock signal arrives, the second counter is originally 0. When the output value is incremented by 1, the output value of the second counter becomes 1; when the second rising edge of the second video signal clock signal comes, the second counter adds 1 to the output value of the original 1, then according to binary addition law, The output value of the second counter is strained to 10, but the second counter is a one-bit addition counter, and the output value has only one bit. At this time, the second counter takes the last 0 of 10, and sets the first bit, and the output of the second counter. The value changes from 1 to 0.

The first-in first-out register, FIFO for short, is a typical high-speed buffer device. The data read and write of the FIFO is driven by an external clock signal, which is suitable for buffering high-speed video data streams. In the embodiment of the present invention, the second counter and the second video signal clock signal are jointly driven. When the output value of the second counter is 1 and the second video signal clock signal is a falling edge, the FIFO reads from the data bus. A pixel data of the second video signal is temporarily stored in a storage space in the FIFO. As can be seen from FIG. 3, during the t2 time period, the FIFO does not read the data on the data bus, and the pixel data read by the FIFO each time The pixel data of the previous reading is separated by two clock cycles. When the second video signal inputs the pixel data of one frame of image to the data bus of the display device, the FIFO actually reads and temporarily stores the second video signal. Half of the pixel data of this frame image.

As shown in FIG. 4, similar to FIG. 3, during the t3 period, the first video signal enable signal is at a high level, during which time, when the rising edge of the first video signal clock signal arrives, A video signal updates pixel data within its data bus. Similar to the second counter, the first video signal enable signal is an enable signal of the first counter, and when the first video signal enable signal is low, the output value of the first counter is always 0; When the signal enable signal is high, the output value of the first counter changes when the rising edge of each first video signal clock signal arrives. Since the first counter is the same as the second counter, it is a binary adder, The output value of a counter varies between 1 and 0 as the second counter. As can be seen from FIG. 4, during the t3 time period, when the rising edge of the first video signal clock signal comes, the output value of the first counter changes from 0 to 1 or from 1 to 0.

When the output value of the first counter is 0 but there is no pixel data in the FIFO, the RAM does not perform reading and writing. At the same time, the write address pointing to the storage space is not changed.

Similarly, after the video signal inputs the pixel data of the complete frame to the display device, the video signal enters the frame gap time, and during the frame gap time, the video signal pauses input of the pixel data to the display device. The length of the frame gap time is several times the line scan time, and the specific length of the line scan time is the sum of the line data transmission time and the line gap time.

In particular, after the frame gap time of the second video signal, when the image data of the next frame of the second video signal arrives, the RAM knows the pixel data input by the second video signal according to the control signal of the second video signal. When it is the first pixel data of one frame of image, the RAM writes the address to the second read storage module 112, and reads the first video signal every other first video signal clock period and temporarily stores the random data. And taking a second video signal in the memory, and temporarily storing the read first video signal and the second video signal in a buffer.

The second read storage module 112 is specifically configured to: read a first video signal and a second video signal temporarily stored in the random access memory every other clock cycle of the first video signal, and The sub-pixel data intervals of the read first video signal and the second video signal are temporarily stored in the buffer.

The pixel data of the first video signal read by the buffer is from the data bus of the first video signal input data, and the pixel data of the read second video signal is from a storage space in the RAM, whenever the buffer reads One pixel of data in the RAM, the RAM increments its read address by one.

The output unit 12 is configured to output the read and temporarily stored first video signal and the second video signal in the same clock cycle, and output the sub-pixel spacing of the first video signal and the second video signal.

Since the first video signal and the second video signal are two completely independent video signals, the clocks of the two video signals have no fixed phase relationship, and even the clock frequencies of the two video signals are different. In order to be able to display on the same display panel at the same time, after temporarily storing the first video signal and the second video signal to achieve the purpose of unifying the clock and frequency of the first video signal and the second video signal, the output unit 12 will pass the temporary The stored first video signal and second video signal are output in the same clock cycle.

In the embodiment of the present invention, the output video signal clock signal is the same as the first video signal clock signal, and the output video signal enable signal is a delay of the first video signal enable signal, and the delay time is the first video signal clock signal. A cycle. When the output video signal enable signal is high and the rising edge of the first video signal clock signal comes, the buffer outputs the data in the storage spaces la, 2b, lc to the output video signal bus, in the next first video. When the rising edge of the signal clock signal comes, the buffer outputs the data in the storage space 2a, lb, 2c to the output video signal bus. When the display panel is displayed, two pixels adjacent to each other laterally on the display panel respectively display two Adjacent rising edge The two pixel data sent out, through the parallax barrier or the lens grating on the dual-view display panel, can achieve the purpose of allowing users on the left and right sides of the display to see different video images.

In the technical solution of the embodiment, the first video signal and the second video signal are read and temporarily stored at intervals of one clock cycle, and then the first video that is read and temporarily stored is performed in the same clock cycle. And outputting the signal and the second video signal by temporarily synchronizing the read first video signal and the second video signal and simultaneously outputting, and arranging the sub-pixels of the output first video signal and the second video signal, respectively The output of a video signal that is processed and contains two video signal contents, through the parallax barrier or the lens grating on the dual-view display panel, can achieve an ideal dual-view display effect.

Through the description of the above embodiments, those skilled in the art can clearly understand that the present invention can be implemented by means of software plus necessary general hardware, and of course, by hardware, but in many cases, the former is a better implementation. . Based on such understanding, the technical solution of the present invention, which is essential or contributes to the prior art, may be embodied in the form of a software product stored in a readable storage medium, such as a floppy disk of a computer. A hard disk or optical disk or the like includes instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform the methods described in various embodiments of the present invention.

The above is only the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily think of changes or substitutions within the technical scope of the present invention. It should be covered by the scope of the present invention. Therefore, the scope of the invention should be determined by the scope of the appended claims.

Claims

Claim

A display driving method for a dual video signal, the dual video signal comprising a first video signal and a second video signal, the method comprising:

The method according to claim 1, wherein the first video signal and the second video signal are read and temporarily stored every other clock cycle:

Reading the second video signal every other clock cycle of the second video signal and temporarily storing it in the first-in first-out register;

The method according to claim 2, wherein the temporarily storing the read first video signal and the second video signal in a buffer are:

4. A display driving device for a dual video signal, the dual video signal comprising a first video signal and a second video signal, the device comprising:

The device according to claim 4, wherein the read storage unit comprises: a first read storage module, configured to read the second video signal every other second video signal and temporarily store the first video signal Reading out a register in a first-out register, and reading a second video signal temporarily stored in the first-in first-out register for every other first video signal and temporarily storing it in the random access memory; a second read storage module, configured to read the first video signal and the second video signal temporarily stored in the random access memory in a clock cycle of every other first video signal, and read the read first video signal And the second video signal is temporarily stored in the buffer.

The device according to claim 5, wherein the second read storage module is configured to: read the first video signal every other first video signal and temporarily store the first in the random access memory And two sub-pixel data intervals of the read first video signal and the second video signal are temporarily stored in the buffer.