CN108234818B - Method for realizing video frame memory round searching operation algorithm - Google Patents
Method for realizing video frame memory round searching operation algorithm Download PDFInfo
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- CN108234818B CN108234818B CN201711323132.8A CN201711323132A CN108234818B CN 108234818 B CN108234818 B CN 108234818B CN 201711323132 A CN201711323132 A CN 201711323132A CN 108234818 B CN108234818 B CN 108234818B
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- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
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Abstract
The invention discloses a method for realizing a video frame memory wheel searching operation algorithm, which is applied to an airborne cockpit display, comprises a Field Programmable Gate Array (FPGA), and comprises the following steps of: the method comprises a video signal clock unifying step, a video signal line-field synchronization unifying step and a video frame storing three-interval operation step. Compared with the traditional video frame storage ping-pong operation method, the video frame storage ping-pong operation method can thoroughly solve the problems of frame break and tearing of the dynamic picture, and the picture display effect is clearer and more stable.
Description
Technical Field
The invention relates to a method for realizing a video frame memory round searching operation algorithm, belonging to the technical field of video image processing.
Background
In a modern airborne comprehensive display system, a plurality of paths of video signals with different time sequences are often sent to an airborne display, and the airborne display can only display pictures with one set of fixed time sequences in the actual display process, so that the time sequences of the plurality of paths of video signals need to be unified.
The traditional time sequence unifying mode is that an RAM memory is mounted outside an FPGA, the FPGA divides the RAM into two intervals A, B according to an address segment, and the intervals A, B are read and written in turn according to a ping-pong operation mode. However, due to the inconsistency of the read/write timing, in the process of switching the read/write sequence of the A, B interval, a part of data written or read inside the a or B is a current frame, and another part is a previous frame. If the input video is a dynamic picture, the content of the current frame and the content of the previous frame are different inevitably, and finally the problem of frame break or tearing occurs on the display picture, which seriously affects the picture display effect.
Disclosure of Invention
The invention aims to solve the problems that the prior art is insufficient, and the display effect of a picture is influenced by the difference of multiple paths of video signals, and provides a method for realizing a video frame memory round searching operation algorithm.
In order to achieve the purpose, the technical scheme adopted by the invention is as follows:
a method for realizing a video frame memory wheel searching operation algorithm is applied to an airborne cockpit display, comprises a Field Programmable Gate Array (FPGA), and is characterized by comprising the following steps of:
s1, video signal clock unification, namely, taking a first-in first-out queue FIFO in a field programmable gate array FPGA as a line buffer, writing data into the first-in first-out queue FIFO by using the clock of the first path of video signals, and reading the data from the first-in first-out queue FIFO by using the clock of the second path of video signals, so that the clock unification of the first path of video signals and the second path of video signals is realized;
s2, line and field synchronization unification of the video signals, namely, a Field Programmable Gate Array (FPGA) is mounted with a group of RAM memories, internal logic of the FPGA controls read-write operation of the RAM memories, line and field synchronization signals of a first path of video signals are used for writing data into the RAM memories, and then line and field synchronization signals of a second path of video signals are used as references for reading the data from the RAM memories, so that unification of the first path of video synchronization signals and the second path of video synchronization signals is realized;
s3, storing video frames in a three-interval operation step,
when operating the RAM memory frame, the FPGA divides the RAM memory into 3 sections A, B, C according to the address field, the read-write operation sequence is executed according to the following logic,
when writing A, reading B or C;
when B is written, C or A is read;
when writing C, read A or B.
The invention has the following beneficial effects:
compared with the traditional video frame storage ping-pong operation method, the video frame storage ping-pong operation method can thoroughly solve the problems of frame break and tearing of the dynamic picture, and the picture display effect is clearer and more stable.
Drawings
Fig. 1 is a schematic structural diagram of an implementation method of a video frame memory round search operation algorithm according to the present invention.
Detailed Description
The invention provides a method for realizing a video frame memory round searching operation algorithm. The technical solution of the present invention is described in detail below with reference to the accompanying drawings so that it can be more easily understood and appreciated.
A method for realizing a video frame memory round searching operation algorithm is applied to an airborne cockpit display, the hardware of the method consists of 1 FPGA and 1 external RAM memory, and the FPGA consists of a video clock unified module, a line buffer FIFO module and an RAM control module, as shown in figure 1. The method comprises the following steps:
1) the clocks of the video signals are unified;
taking FPGA of Altera corporation as a core device, utilizing abundant on-chip FIFO resources as line Buffer, writing data into FIFO by using the clock of the first path of video signal, and reading the data from FIFO by using the clock of the second path of video signal, thereby realizing the unification of the clocks of the two paths of video signals;
2) the line-field synchronization of the video signals is unified;
a group of RAM memories are mounted outside the FPGA, and the read-write operation of the FPGA is controlled by the internal logic of the FPGA. The line and field synchronizing signals of the first path of video signals are used for writing data into the RAM, and then the line and field synchronizing signals of the second path of video signals are used as references for reading the data from the RAM, so that the unification of the two paths of video synchronizing signals is realized;
3) a three-interval operation mode of video frame storage;
when the FPGA operates the external RAM frame memory, the external RAM frame memory is divided into 3 intervals A, B, C according to the address field, and the read-write operation sequence is executed according to the following logic:
when writing A, reading B or C. If the A is not completely written after the C is completely read, continuing to read the C;
when writing B, read C or A. If the B is not completely written after the A is completely read, continuing to read the A;
when writing C, read A or B. And if the C is not completely written after the B is completely read, continuing to read the B.
Through the above description, it can be found that the implementation method of the video frame storage and round searching operation algorithm can be applied to an airborne cockpit display, and compared with the traditional video frame storage and ping-pong operation method, the video frame storage and round searching operation implemented by the invention can thoroughly solve the problems of frame break and tearing of a dynamic picture, and the picture display effect is clearer and more stable.
The technical solutions of the present invention are fully described above, it should be noted that the specific embodiments of the present invention are not limited by the above description, and all technical solutions formed by equivalent or equivalent changes in structure, method, or function according to the spirit of the present invention by those skilled in the art are within the scope of the present invention.
Claims (1)
1. A method for realizing a video frame memory wheel searching operation algorithm is applied to an airborne cockpit display, comprises a Field Programmable Gate Array (FPGA), and is characterized by comprising the following steps of:
s1, video signal clock unification, namely, taking a first-in first-out queue FIFO in a field programmable gate array FPGA as a line buffer, writing data into the first-in first-out queue FIFO by using the clock of the first path of video signals, and reading the data from the first-in first-out queue FIFO by using the clock of the second path of video signals, so that the clock unification of the first path of video signals and the second path of video signals is realized;
s2, line and field synchronization unification of the video signals, namely, a Field Programmable Gate Array (FPGA) is mounted with a group of RAM memories, internal logic of the FPGA controls read-write operation of the RAM memories, line and field synchronization signals of a first path of video signals are used for writing data into the RAM memories, and then line and field synchronization signals of a second path of video signals are used as references for reading the data from the RAM memories, so that unification of the first path of video synchronization signals and the second path of video synchronization signals is realized;
s3, storing video frames in a three-interval operation step,
when operating the RAM memory frame, the FPGA divides the RAM memory into 3 sections A, B, C according to the address field, the read-write operation sequence is executed according to the following logic,
when writing A, reading B or C; if the A is not completely written after the C is completely read, continuing to read the C;
when B is written, C or A is read; if the B is not completely written after the A is completely read, continuing to read the A;
when writing C, reading A or B; and if the C is not completely written after the B is completely read, continuing to read the B.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US20150347023A1 (en) * | 2011-08-04 | 2015-12-03 | Alexandr Konovalov | Memory coalescing computer-implemented method, system, apparatus and computer-readable media |
| CN105872432A (en) * | 2016-04-21 | 2016-08-17 | 天津大学 | Rapid self-adaptive frame rate conversion device and method |
| CN106791488A (en) * | 2016-12-28 | 2017-05-31 | 浙江宇视科技有限公司 | A kind of synchronous tiled display methods and device |
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| CN101236528A (en) * | 2008-02-20 | 2008-08-06 | 华为技术有限公司 | Ping-pong control method and apparatus |
| CN102663987B (en) * | 2012-03-19 | 2015-04-01 | 京东方科技集团股份有限公司 | Display driving method and display driving device of dual-channel video signals |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20150347023A1 (en) * | 2011-08-04 | 2015-12-03 | Alexandr Konovalov | Memory coalescing computer-implemented method, system, apparatus and computer-readable media |
| CN105872432A (en) * | 2016-04-21 | 2016-08-17 | 天津大学 | Rapid self-adaptive frame rate conversion device and method |
| CN106791488A (en) * | 2016-12-28 | 2017-05-31 | 浙江宇视科技有限公司 | A kind of synchronous tiled display methods and device |
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