CN100555391C - The apparatus and method of processing signals - Google Patents

The apparatus and method of processing signals Download PDF

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Publication number
CN100555391C
CN100555391C CNB2004101037457A CN200410103745A CN100555391C CN 100555391 C CN100555391 C CN 100555391C CN B2004101037457 A CNB2004101037457 A CN B2004101037457A CN 200410103745 A CN200410103745 A CN 200410103745A CN 100555391 C CN100555391 C CN 100555391C
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data
line
frame
frame memory
input
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CN1645464A (en
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权秀现
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Samsung Display Co Ltd
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Samsung Electronics Co Ltd
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/395—Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen
    • G09G5/397—Arrangements specially adapted for transferring the contents of two or more bit-mapped memories to the screen simultaneously, e.g. for mixing or overlay
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0252—Improving the response speed
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0261—Improving the quality of display appearance in the context of movement of objects on the screen or movement of the observer relative to the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/04—Changes in size, position or resolution of an image
    • G09G2340/0407—Resolution change, inclusive of the use of different resolutions for different screen areas
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/16—Determination of a pixel data signal depending on the signal applied in the previous frame
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G09G2360/126—The frame memory having additional data ports, not inclusive of standard details of the output serial port of a VRAM

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Liquid Crystal (AREA)

Abstract

The invention provides a kind of device of processing signals, this device comprises: frame memory is used to store two frame data; And signal processing unit, be used for during the input of data line, two line data being written to frame memory or reading two line data from frame memory.

Description

The apparatus and method of processing signals
Technical field
The present invention relates to a kind of apparatus and method of processing signals.
Background technology
Usually, LCD (LCD) comprises a counter plate, and this panel comprises a plurality of pixel electrodes, public electrode and is inserted in liquid crystal (LC) layer between two panels, and has dielectric anisotropy (dielectricanisotropy).Pixel electrode is arranged with matrix and is connected with the on-off element of for example thin film transistor (TFT) (TFT).Provide data voltage to pixel electrode line by line by TFT.Public electrode is positioned on the whole surface of (range over) panel and provides common electric voltage.The edge has arranged that the pixel electrode of LC layer and public electrode constitute the LC capacitor in circuit diagram therebetween, and LC capacitor and on-off element are the primary elements that constitutes pixel.
By voltage is applied on the electrode, LCD produces electric field in the LC layer, and obtains desired images by control electric field intensity with the optical transmission rate that change is incident on the LC layer.At this moment, owing to apply the destruction to liquid crystal such as one-way electric field for a long time, data voltage periodically is reversed in the unit of frame, row or point with respect to the polarity of common electric voltage in order to prevent.
LCD is used to show moving image day by day, and the slow-response time of liquid crystal comes on the scene.Especially, the increase of the size of display device and resolution seriously needs the improvement of response time.
In detail, the slow-response time of liquid crystal makes to take time and allows pixel reach the brightness of expectation.The required time of brightness that obtains expectation is depended on for the difference between the precharge voltage of the target voltage of expecting brightness and the LC capacitor that strides across pixel.If this voltage difference is very big, pixel may can't reach the brightness of expectation in the time that gives so.
In order to address this problem, proposed under the situation that does not change the liquid crystal self character, to improve the dynamic capacitance compensation (DCC) of response time.DDC to the LC capacitor apply one than the also high voltage of target voltage to reduce in order to reach the time that expectation brightness needs.
After the view data between the two or three continuous frames was compared, DCC produced amended view data, thereby it needs at least one frame memory to be used for the view data of storage frame.
But frame memory has increased the area of production cost and control panel.
Summary of the invention
The invention provides a kind of device of processing signals, it comprises: a frame memory is used to store two frame data; And signal processing unit, be used for during the input of data line, two line data being written to frame memory or reading two line data from frame memory.
Write and read and to replace.
Signal processing unit can comprise writing line storer and read line storage, and signal processing unit will be written in the writing line storer from the input data of external unit and will be written to from the storage data of frame memory and read in the line storage.
Signal processing unit can be written to frame memory to the view data from the writing line storer.
The input data can be that to be used for the data of present frame and to store data can be the data that are used for previous frame.
Writing line storer and read line storage and can comprise FIFO or both-end RAM.
Signal processing unit can be written to the odd-numbered line data of present frame in the writing line storer in the process of odd-numbered line data of input present frame and the odd and even number line data that is stored in the previous frame in the frame memory is written to and read in the line storage, and the odd and even number line data that signal processing unit can be in the process of the even number of lines certificate of input present frame be written to the even number of lines of present frame certificate in the writing line storer and be stored in the present frame that reads in the line storage be written in the frame memory.
Signal processing unit can be compared being stored in the data of the present frame in the writing line storer and being stored in the data that read the previous frame in the line storage, and can relatively revise the data of present frame based on this.
Frame memory can receive and export two data at a clock.
Frame memory can comprise DDR SDRAM.
Signal processing unit can conversion be imported the figure place and the operating frequency of data, and the data of conversion can be deposited in the frame memory.
The figure place of the data of institute's conversion can equal 32.
Display device can comprise above-mentioned device.
The invention provides a kind of method of processing signals, it comprises: receive the input data from external unit; In the process of input delegation input data, two row input data are written in the frame memory; And the storage data that in the process of input delegation input data, from frame memory, read two row.
The data that data that described input data can be present frames and described storage data are previous frames.
Write and read and to hocket.
This method can also comprise: compare the data of present frame and the data of previous frame; And relatively revise the data of present frame based on this.
This method also comprises: the figure place and the operating frequency of conversion input data; And the data of institute's conversion are written in the frame memory.
Description of drawings
Embodiments of the present invention is described in detail by coming with reference to the accompanying drawings, and it is clearer that the present invention will become, wherein:
Fig. 1 is the calcspar of LCD according to an embodiment of the invention;
Fig. 2 is the equivalent circuit diagram of the pixel of LCD according to an embodiment of the invention;
Fig. 3 is the calcspar of signal handling equipment 40 according to an embodiment of the invention;
The example waveform of the input signal that is input to signal processing unit shown in Fig. 4 key diagram 3;
Fig. 5 explanation is from the example waveform of the output signal of data converter;
Fig. 6 explanation is from the example waveform of the output signal of line storage and data IOB;
Another example waveform of the signal that is used for signal processing unit and frame memory shown in Fig. 7 A-7C key diagram 3;
Fig. 8 explanation is from another example waveform of the output signal of data converter;
Fig. 9 explanation is from another example waveform of the output signal of line storage and frame memory; With
The example of Figure 10 explanation operation of signal processing unit in the process of the view data of N frame of input.
Embodiment
Now will come with reference to the accompanying drawings the present invention is made more detailed description hereinafter, wherein show the preferred embodiments of the present invention.But the present invention can be by a lot of multi-form enforcements, and should not be interpreted as being limited in the scope of the embodiment that sets forth here.
In the drawings, the thickness and the zone of layer have for clarity sake been amplified.Identical label is represented identical parts in full.Be appreciated that when expression for example the parts of layer, zone or substrate be called as at " on ", in the time of on another parts, it can be directly on another parts, perhaps also can have insertion parts (inverteningelement).On the contrary, when pointing out parts " directly on another parts ", just there is not insertion parts.
Now, with reference to the accompanying drawings to according to the signal processing apparatus and the method for the embodiment of the invention and comprise that the display device of this signal processing apparatus is described in detail.
To be described in detail LCD with reference to Fig. 1 and 2 according to the embodiment of the invention.
Fig. 1 is to be equivalent circuit diagram according to the LCD pixel of the embodiment of the invention according to the calcspar of the LCD of the embodiment of the invention and Fig. 2.
With reference to figure 1, comprise: LC panel assembly 300, the gate drivers 400 that is connected to panel assembly 300 and data driver 500, be connected to the grayscale voltage generator 800 of data driver 500 and control the signal controller 600 of above-mentioned parts according to the LCD of present embodiment.
In circuit diagram, panel assembly 300 comprises many display signal line G 1-Gn and D 1-D mAnd a plurality of pixels that are connected to the there and arrange by matrix basically.
Display signal line G 1-Gn and D 1-D mThe gate lines G that comprises many transmission signals (being also referred to as " sweep signal ") 1The data line D of-Gn and many transmission of data signals 1-D mGate lines G 1-Gn extends on line direction basically substantially in parallel to each other, and data line D 1-D mBasically on column direction, extend substantially in parallel to each other.
Each pixel comprises and is connected to signal wire G 1-Gn and data line D 1-D mSwitch block Q and be connected to the LC capacitor C of switch block Q LCWith holding capacitor C STJust can be if not essential holding capacitor C STIgnore.
Switch block Q is provided on the lower panel 100, and this switch block has three terminals: be connected to gate lines G 1The control end of one of-Gn; Be connected to data line D 1-D mOne of input end; Be connected to LC capacitor C LCWith holding capacitor C STOutput terminal.
LC capacitor C LCComprise being provided at the pixel electrode 190 on the lower panel 100 and being provided at public electrode 270 on the top panel 200 as two ends.Be arranged on 3 LC capacitor of the LC layer C between two electrodes 190 and 270 LCThe effect of dielectric (dielectric).Pixel electrode 190 is connected to switch block Q and public electrode 270 is connected to common electric voltage V ComGo up and cover the whole surface of top panel 200.Different with Fig. 2, can be provided at public electrode 270 on the lower panel 100, and electrode 190 and 270 can all be bar shaped or band shape.
Define holding capacitor C by pixel electrode 190 and the overlapping (overlap) that is provided at the independent lines (not shown) on the lower panel 100 STAnd provide for example common electric voltage V to it ComPredetermined voltage.Perhaps, also can be by pixel electrode 190 and its last gate lines G I-1Define holding capacitor through piling up of insulator.
For color monitor, each pixel can be represented its oneself color by one of a plurality of red, green and blue color look color filters 230 are provided in the zone corresponding to pixel electrode 190.Being provided in the relevant range of top panel 200 at the color filter shown in Fig. 2 230.Alternatively, can be provided at color filter 230 above or below the pixel electrode 190 on the lower panel 100.
One or more polarizer (not shown) are attached at least one of panel 100 and 200 light is carried out polarization.
Refer again to Fig. 1, grayscale voltage generator 800 produces two groups of a plurality of grayscale voltages about the pixel transmission rate.It is positive polarity that grayscale voltage in one group has with respect to common electric voltage Vcom, and those grayscale voltages in another group have the polarity for bearing with respect to common electric voltage Vcom.
Gate drivers 400 is connected to the gate lines G of panel assembly 300 1-Gn, and a signal from external unit is applied to gate lines G 1-Gn.This signal is the combination of gate-on voltage Von and gate off voltage Voff.
Data driver 500 is connected to the data line D of panel assembly 300 1-D mAnd from grayscale voltage generator 800, select grayscale voltage and be applied to data line D as data-signal 1-D mOn.
Gate drivers 400 or data driver 500 can comprise a plurality of driver ICs (IC), directly are assembled to these integrated circuit on the panel assembly 300 or are installed on the flexible printed circuit film strip-like carrier encapsulation (tape carrier package) that appends to panel assembly 300 with formation.Perhaps, can be integrated into gate drivers 400 or data driver 500 in the panel assembly.
Signal controller 600 control gate drivers 400, data driver 500 etc.
Next, the operation of LCD will be described in detail.
R, G and B received image signal are provided and are used to control the input control signal of its demonstration to signal controller 600 from the external graphics controller (not shown), for example vertical synchronizing signal Vsync, horizontal-drive signal Hsync, master clock signal MCLK, data enable signal DE, etc.Signal controller 600 changes received image signal R, G and B and provides amended picture signal R ', G ' and B ' for data driver 500 based on the operating environment of panel assembly 300.And, signal controller 600 produces a plurality of grid control signal CONT1 and data controlling signal CONT2 based on received image signal and input control signal, and it provides grid control signal CONT1 and provide data controlling signal CONT2 for data driver 500 for gate drivers 400.
Grid control signal CONT1 comprises output at least one clock signal regularly that is used to indicate the scanning start signal STV of gate-on voltage Von scanning beginning and is used to control gate-on voltage Von.
Data controlling signal CONT2 comprises the horizontal synchronization start signal STH that is used to notify the pixel column data transmission, is used for indication data voltage is applied to data line D 1-D mLoad signal LOAD or TP, be used for the upset control signal RVS and the data clock signal HCLK of roll data voltage (with respect to common electric voltage Vcom) polarity.
Data driver 500 receives from signal controller 600 and is used for view data R ', the G ' of pixel column and the packets of information of B '.Data driver 500 converts view data R ', G ' and B ' to select analog data voltage from the grayscale voltage of grayscale voltage generator 800, and in response to the data controlling signal CONT2 from signal controller 600 this data voltage is applied to data line D 1-D m
In response to the grid control signal CONT1 from signal controller 600, gate drivers 400 is applied to gate lines G to gate-on voltage Von 1-Gn is the switch block Q conducting that connects on it thus.Switch block Q by conducting is applied to data line D 1-D mData voltage be applied to corresponding pixel.
By repeating with horizontal cycle (it also is expressed as " 1H " and equals the cycle of a horizontal-drive signal Hsync and data enable signal DE) is this process of unit, in a frame to all gate lines G 1-Gn applies gate-on voltage Von successively, provides data voltage to all pixels thus.After finishing a frame during beginning next frame, the upset control signal RVS that control is applied to data driver 500 makes the polarity upset (being called " frame upset " here) of data voltage.Also can control upset control signal RVS and make the polarity upset (for example, row upset and some upset) that in a frame, flows through the data voltage of a data line, the polarity of the data voltage in a packets of information that perhaps overturns (for example, row upset and some upset).
Now, will the signal processing apparatus that can be used among the above-mentioned LCD be described in detail.
Fig. 3 is the calcspar of signal processing apparatus 40 according to an embodiment of the invention.
As shown in Figure 3, the frame memory 44 on signal processing apparatus 40 comprises signal processing unit 42 and is connected it according to an embodiment of the invention.The input and output of signal processing unit 42 are as the input and output of signal processing apparatus 40.
Signal processing unit 42 comprises data converter 46, is connected to the line storage 47 of data converter 46 and is connected to line storage 47 and has data-conditioner 48 as the output of signal processing apparatus 40.
Data converter 46 receives the 48 bit image data G be used for present frame (hereinafter be called " current image date ,) from external unit n, and these 48 bit image data G nConvert 24 bit data to.These 48 input image data G of the first predetermined clock frequency transmission with for example 54MHz n, and with the second predetermined clock frequency transmission, the 24 bit data G of for example 108MHz n
Line storage 47 can be with the view data of behavior unit's storage multirow, and storage is from 24 current data G of data converter 46 nAnd with current image date G nBe transferred in the frame memory 44, and receive and be used for the previous frame view data G of (hereinafter being called " in preceding view data ") in the frame memory 44 being stored in N-1Store.
Frame memory 44 storages are from the current image date G of line storage 47 nAnd handle is at preceding view data G N-1Output to line storage 47.Frame memory 44 storage current image date G nWith at preceding view data G N-1
Data-conditioner 48 receives current image date G nAnd with it with at preceding view data G N-1Relatively and produce to be transferred to data driver 500 about current image date G nAdjusting view data G ' n
Signal processing apparatus 40 is done as a whole or only can be integrated in the signal controller 600 as signal processing unit 42.
With reference to figure 4-6, will be described in more detail the frequency of view data in signal processing unit 42 and the conversion of figure place.
Fig. 4 represents the example waveform of the input signal of input signal processing unit shown in Figure 3, and Fig. 5 represents to represent example waveform from the output signal of line storage and frame memory from the example waveform of the output signal of data converter and Fig. 6.
Fig. 4 represents to be input to each 48 input image data R, G of signal processing unit 42 and B and comprises two 24 seat data (data_in[47:24] and dat a_in[23:0]).Data stream (data_in[47:24] and data_in[23:0]) and input clock CLOCK1 are synchronous.Reference number shown in Figure 4 " 2T " indication is corresponding to the cycle of first preset frequency, and it is the frequency of input clock CLOCK1, for example, and 54MHz.
Fig. 5 represents by 24 bit data of data converter 46 conversion (data1[23:0]).
Can realize data converter 46 simply with multiplexer.For example, multiplexer can be selected input traffic (data_in[47:24]) at the high level place of input clock CLOCK1 and select input traffic (data_in[23:0]) at the low level place of input clock CLOCK1, produces data stream (data1[23:0]) corresponding to the cycle " T " being synchronized with the clock CLOCK2 with frequency 108MHz thus.
Line storage 47 receiving data streams (data1[23:0]) and output stream (data2[23:0]).Be input to line storage 47 and comprise identical information, but they have different transformation periods with data from its output.
Can realize line storage 47 by using FIFO (first-in first-out) or both-end RAM, it has independently input end and output terminal, can synchronously transmit input data and output data with different clock frequencies like this.The output clock that the line storage of realizing with FIFO or both-end RAM 47 need have input clock CLOCK2 doubled frequency.
In addition, can realize line storage 47 by two single-ended RAM and a multiplexer.In this case, the output clock can have the frequency that equates with input clock CLOCK2.
Frame memory 44 can comprise DDR RAM (Double Data Rate random access storage device).The DDR RAM of this DDR of being also referred to as SDRAM (synchronous dynamic ram) carries out read and write at the rising and falling edges that is applied to the clock on it.Opposite, SDR SDRAM (single data rate SDRAM) or SDRAM only read or write at the rising edge of clock or negative edge.Therefore, DDR RAM has the speed of SDRAM twice.In other words, DDR RAM to be used to store the needed time of data of specified rate be SDRAM half.
With reference to figure 6, can be respectively the rising edge of clock CLOCK2 and negative edge to 24 bit data streams (data2[23:0] read and write.Owing to handle by a clock-unit in the data stream shown in Fig. 5 (data1[23:0]), therefore can handle 8 data 1-8 with the time of 8T.Opposite, (data1[23:0]) handles by half clock-unit because data stream, therefore can with the time of 4T handle the data stream shown in Fig. 6 (data2[23:0] 8 data 1-8.Therefore, DDR SDRAM has reduced to half with data processing time, can handle two frame data like this in the input process of frame data.
For example, because a pixel needs 48 view data, SXGA (super XGA (Extended Graphics Array)) display device one frame that therefore has 1280 * 1024 pixels needs the view data of 1280 * 1024 * 24=31457280 position.If 24 bit data are provided in the frame memory that can store 32 bit data, the 8 remaining bit data storage spaces that then are used for the address are not used, and the total storage space that is provided by frame memory that frame data of storage SXGA display device need equals 1280 * 1024 * 32=41943040, and this is greater than the total position of data amount.As a result, the DDR SDRAM of 128M position can store two frame data that are used for the SXGA display device.
Simultaneously, commercially available storer has 16 or 32 bit data bus.Therefore, the use that meets 24 LCD view data can reduce the efficient of storer.That is to say that only store 24 bit data if can store 32 bit memory addresses of 32 bit data, remaining 8 bit data storage spaces are just useless.Therefore, another embodiment of the present invention is converted to 32 bit image data in order to use storer effectively with view data.
With reference to figure 7A-9, the conversion of the frequency and the figure place of view data in the signal processing unit 42 will be described in greater detail in.
Another example waveform of the signal that is used for signal processing unit and frame memory shown in Fig. 7 A-7C presentation graphs 3, Fig. 8 represents to represent another example waveform from the output signal of line storage and frame memory from another example waveform of the output signal of data converter and Fig. 9.
Signal processing unit 42 will be converted under 32 bit data and the clock frequency at 81MHz in 48 input data transmitting under the clock frequency of 54MHz 32 bit data will be transferred to frame memory 44.
Fig. 7 A be illustrated in 24 bit data streams of each shown in Fig. 5 (data1[23:0]) comprise three 8 seat data (DATA[23:16], DATA[15:8] and DATA[7:0]).
Fig. 7 B represent by data converter 46 from 32 bit data of 24 bit image data (datal[23:0]) conversion (data[31:24], data[23:16] and data[15:8] and data[7:0]).Particularly, data converter 46 will comprise the one 32 bit image data of four subdata R1, G1, B1 and R2 with generation at three digital data R1, G1 of first clock and B1 and in that the subdata R2 of first clock is synthetic, and data converter 46 deposits the one 32 bit image data in first address that is included in interim storage space (not shown) wherein in.Similarly, data converter 46 will comprise the 2 32 bit image data of four subdata G2, B2, R3 and G3 with generation at two subdata G2 of second clock and B2 and in that two subdata R3 of the 3rd clock and G3 are synthetic, and data converter 46 deposits the 2 32 bit image data in second address of interim storage space in.Same, to comprise the 3 32 bit image data of four subdata B3, R4, G4 and B4 with formation in that the subdata B3 of the 3rd clock and three the subdata R4 at the 4th clock, G4 and B4 are synthetic, these data be deposited in the three-address of interim storage space with time of two clocks.In four clocks (or 4T) process, equal to be input to the number of 48 input image data R1-B4 the data converter 46 from the number of 32 output image data R1-B4 of data converter 46 output.With such method, the input data-switching is become will deposit in 32 bit data of interim storage space.Interim storage space can comprise above-mentioned FIFO or both-end RAM.
As mentioned above, the output clock frequency of interim storage space equals the 81MHz corresponding to 4T/3.Fig. 7 C represents that three 32 bit image data R1-B4 are synchronized with 81MHz and export from interim storage space.
Fig. 8 represents the output stream of data converter 46, this data stream and in the view data equivalence shown in Fig. 7 C.8 24 bit data 1-8 with six 32 bit image data 1 '-6 of time of 8T input ' be equivalent in the identical time of usefulness shown in Fig. 5.
Line storage 47 is received in the data stream shown in Fig. 8 (DATA3[31:0]) and output at the data stream shown in Fig. 9 (data4[31:0]).Also can realize line storage 47 by FIFO or both-end RAM or by two single-ended RAM and multiplexer.In this case, the output clock can have the frequency that equates with input clock CLOCK2.
Frame memory 44 also can comprise DDR RAM.With reference to figure 9, can be respectively in the rising and falling edges read and write data stream of clock signal C LOCK3.Owing to can be the read and write that unit carries out data stream,, in the input process of frame data, can handle two frame data like this so data processing time reduces to half with half clock.
For example, the WUXGA display device with 1920 * 1200 pixels need be used for the view data of 1920 * 1200 * 24=55296000 position of a frame.Because 32 bit data are provided in the frame memory 44 that storage capacity is 32 bit data, so used frame memory 44 effectively.Therefore, DDR SDRAM in 128M position can store the data that two frames are used for the WUXGA display device.
It maybe can be that line storage 47 is own that above-mentioned interim storage space can be included in line storage 47.
To describe the data-conditioner read and write in detail in preceding and operation current image date with reference to Figure 10.
Figure 10 is illustrated in the example of signal processing unit operation in the process of importing the N frame image data.
Suppose to comprise a plurality of pixel columns according to the LCD of present embodiment, for example, m pixel column.Be illustrated in the N frame image data after the conversion of figure place shown in Fig. 6 and 9 and clock frequency with D (N), and with D (N) iBe illustrated in and be used for the i pixel column view data of (hereinafter being called " i line data ") in the N frame image data.
With reference to Figure 10, signal processing unit 42 is handled and is used for the two pixel columns conversion image data of (hereinafter being called " two row view data ") in 1H.For example, signal processing unit 42 reads or writes this two row view data for frame memory 44.
At the first line data D (N) 1Input under, signal processing unit 42 is with the first line data D (N) 1Deposit line storage 47 in, and signal processing unit 42 is read the first and second line data D (N) of previous frame from frame memory 44 1And D (N) 2, and they are deposited in line storage 47.
At the second line data D (N) 2Input under, signal processing unit 42 will be from the D (N) of line storage 47 1Write frame memory 44, and D (N) 2Deposit line storage 47 in and with D (N) 2Write frame memory 44.Simultaneously, signal processing unit 42 is D (N-1) 1And D (N-1) 1After from line storage 47, reading both are compared, and produce the adjusting view data.
At the third line data D (N) 3Input under, signal processing unit 42 is with D (N) 3Deposit line storage 47 in and from frame memory 44, read the third and fourth line data D (N-1) 3D (N-1) with previous frame 4And deposit them in line storage 47.In addition, signal processing unit 42 is D (N-1) 2And D (N-1) 2After from line storage 47, reading both are compared, and produce the adjusting view data.
At fourth line data D (N) 4Input under, signal processing unit 42 will be from the D (N) of line storage 47 3Write frame memory 44, and with D (N) 4Deposit line storage 47 in also D (N) 4Write frame memory 44.Simultaneously, signal processing unit 42 is D (N-1) 3And D (N-1) 4After from line storage 47, reading both are compared, and produce the adjusting view data.
Signal processing unit 42 repeats this operation for the view data from the 5th pixel column and m pixel column.
Because frame memory 44 is with the view data of two frame units storage from line storage 47, so the view data of next frame can replace the view data of previous frame rather than the view data of present frame, wherein the image data storage of previous frame and present frame is in frame memory 44, the view data of frame memory 44 storage previous frames and present frame.
In this way, signal processing unit 42 writes frame memory 44 with D (N) and reads D (N-1) and relatively producing the adjusting view data behind D (N) and the D (N-1) from frame memory 44.As a result, can handle current image date D (N) and at preceding view data D (N-1) by only using a frame memory.
As mentioned above, DDR SDRAM made as the conversion of the use of frame memory and number of bits and clock frequency only use a frame memory can store two frame data, and reduce frame memory area occupied and production cost.
Although above described the preferred embodiments of the present invention in detail, but can be expressly understood, for those skilled in the art, in many variations of the key concept of the present invention of this instruction and/or revise and all still can fall within the spirit and scope of the present invention that define in the incidental claim.

Claims (18)

1. the device of a processing signals, this device comprises:
A frame memory is used to store two frame data; And
Signal processing unit is used for during the input of data line two line data being written to frame memory or reading two line data from frame memory.
2. according to the device of claim 1, wherein, write and read and hocket.
3. according to the device of claim 2, wherein, signal processing unit comprises: writing line storer and read line storage, and signal processing unit will be written to the writing line storer from the input data of external unit and will be written to from the storage data of frame memory and read line storage.
4. according to the device of claim 3, wherein, signal processing unit will be written to frame memory from the view data of writing line storer.
5. according to the device of claim 4, wherein, described input data are that the data and the described storage data that are used for present frame are the data that are used for previous frame.
6. according to the device of claim 5, wherein, writing line storer and read line storage and comprise FIFO or both-end RAM.
7. according to the device of claim 6, wherein, signal processing unit is written to the odd-numbered line data of present frame in the writing line storer in the process of odd-numbered line data of input present frame and the odd and even number line data that will be stored in the previous frame in the frame memory is written to and reads in the line storage, and signal processing unit is written to the even number of lines of present frame in the frame memory according to the odd and even number line data that is written in the writing line storer and will be stored in the present frame that reads in the line storage in the process of the even number of lines certificate of input present frame.
8. according to the device of claim 7, wherein, signal processing unit will be stored in the data of the present frame in the writing line storer and be stored in the data that read the previous frame in the line storage and compare, and relatively revise the data of present frame based on this.
9. device according to Claim 8, wherein, frame memory receives and exports two data at a clock.
10. according to the device of claim 9, wherein, frame memory comprises DDR SDRAM.
11. according to the device of claim 2, wherein, the figure place and the operating frequency of signal processing unit conversion input data, and the data of institute's conversion are deposited in in the frame memory.
12. according to the device of claim 11, wherein, the figure place of the data of institute's conversion equals 32.
13. display device that comprises the device of claim 1.
14. the method for a processing signals, this method comprises:
Receive the input data from external unit;
In the process of input delegation input data, two row input data are written in the frame memory; And
In the process of input delegation input data, from frame memory, read the storage data of two row.
15. according to the method for claim 14, wherein, the data that data that described input data are present frames and described storage data are previous frames.
16., wherein, write and read and hocket according to the method for claim 15.
17. the method according to claim 16 also comprises:
The data of present frame and the data of previous frame are compared; And
Relatively revise the data of present frame based on this.
18. the method according to claim 17 also comprises:
The figure place and the operating frequency of conversion input data; And
The data of institute's conversion are written in the frame memory.
CNB2004101037457A 2003-11-26 2004-11-26 The apparatus and method of processing signals Expired - Fee Related CN100555391C (en)

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