ZA841345B - Associative array - Google Patents

Associative array

Info

Publication number
ZA841345B
ZA841345B ZA841345A ZA841345A ZA841345B ZA 841345 B ZA841345 B ZA 841345B ZA 841345 A ZA841345 A ZA 841345A ZA 841345 A ZA841345 A ZA 841345A ZA 841345 B ZA841345 B ZA 841345B
Authority
ZA
South Africa
Prior art keywords
associative array
associative
array
Prior art date
Application number
ZA841345A
Other languages
English (en)
Inventor
Steven Gregory Morton
John Michael Cotton
Original Assignee
Int Standard Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Int Standard Electric Corp filed Critical Int Standard Electric Corp
Publication of ZA841345B publication Critical patent/ZA841345B/xx

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G06F15/8023—Two dimensional arrays, e.g. mesh, torus

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Devices For Executing Special Programs (AREA)
  • Multi Processors (AREA)
ZA841345A 1983-03-08 1984-02-23 Associative array ZA841345B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/473,362 US4580215A (en) 1983-03-08 1983-03-08 Associative array with five arithmetic paths

Publications (1)

Publication Number Publication Date
ZA841345B true ZA841345B (en) 1984-10-31

Family

ID=23879229

Family Applications (1)

Application Number Title Priority Date Filing Date
ZA841345A ZA841345B (en) 1983-03-08 1984-02-23 Associative array

Country Status (4)

Country Link
US (1) US4580215A (ja)
JP (1) JPS59223874A (ja)
PH (1) PH24645A (ja)
ZA (1) ZA841345B (ja)

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JPH05500124A (ja) * 1990-05-30 1993-01-14 アダプティブ・ソリューションズ・インコーポレーテッド Ｓｉｍｄアーキテクチャにおける並行演算／通信機構
US5175858A (en) * 1991-03-04 1992-12-29 Adaptive Solutions, Inc. Mechanism providing concurrent computational/communications in SIMD architecture
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US5805913A (en) * 1993-11-30 1998-09-08 Texas Instruments Incorporated Arithmetic logic unit with conditional register source selection
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US5557734A (en) * 1994-06-17 1996-09-17 Applied Intelligent Systems, Inc. Cache burst architecture for parallel processing, such as for image processing
US5586300A (en) * 1994-07-20 1996-12-17 Emc Corporation Flexible addressing memory controller wherein multiple memory modules may be accessed according to comparison of configuration addresses
KR100186918B1 (ko) * 1994-10-21 1999-05-01 모리시다 요이치 신호처리장치
US6507362B1 (en) * 1994-12-09 2003-01-14 Neomagic Israel Ltd. Digital image generation device for transmitting digital images in platform-independent form via the internet
US6502180B1 (en) * 1997-09-12 2002-12-31 California Institute Of Technology Asynchronous circuits with pipelined completion process
US6263424B1 (en) * 1998-08-03 2001-07-17 Rise Technology Company Execution of data dependent arithmetic instructions in multi-pipeline processors
KR100774135B1 (ko) * 1999-05-07 2007-11-07 모픽스 테크놀로지 아이엔씨 프로그래머블 데이터경로 연산 어레이 장치 및 방법
US6732126B1 (en) * 1999-05-07 2004-05-04 Intel Corporation High performance datapath unit for behavioral data transmission and reception
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US8145880B1 (en) 2008-07-07 2012-03-27 Ovics Matrix processor data switch routing systems and methods
US8327114B1 (en) 2008-07-07 2012-12-04 Ovics Matrix processor proxy systems and methods
US7870365B1 (en) 2008-07-07 2011-01-11 Ovics Matrix of processors with data stream instruction execution pipeline coupled to data switch linking to neighbor units by non-contentious command channel / data channel
US7958341B1 (en) 2008-07-07 2011-06-07 Ovics Processing stream instruction in IC of mesh connected matrix of processors containing pipeline coupled switch transferring messages over consecutive cycles from one link to another link or memory
US8131975B1 (en) 2008-07-07 2012-03-06 Ovics Matrix processor initialization systems and methods
US8438522B1 (en) 2008-09-24 2013-05-07 Iowa State University Research Foundation, Inc. Logic element architecture for generic logic chains in programmable devices
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Also Published As

Publication number Publication date
PH24645A (en) 1990-09-07
US4580215A (en) 1986-04-01
JPS59223874A (ja) 1984-12-15
JPH0160865B2 (ja) 1989-12-26

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