YU45619B

YU45619B - CIRCUIT FOR BRANCHING CHANNELS OF TERMINAL MULTIPLEXERS

Info

Publication number: YU45619B
Application number: YU80784A
Authority: YU
Inventors: M. Blokar
Original assignee: Iskra-Sozd Elektrokovinske Industrije
Priority date: 1984-05-08
Filing date: 1984-05-08
Publication date: 1992-07-20
Also published as: DE3516594A1; IT8567416A1; SE8502216L; IT8567416A0; SE8502216D0; YU80784A; IT1183822B

Abstract

VEZJE ZA RAZVEJEVANJE KANALOV TERMINALNIH MULTIPLEKSERJEV, v komunikacijskem sistemu z 2048 kbit/s pretokom digitalnih informacij, ki se uporablja pri medsebojno oddaljenih terminalnih multiplekserjih, označen s tem, da terminalne multiplekserje (MUXA,MUXB,...MUXN), v katerih dodamo vezju za vrednotenje alarmnih stanj dodatno alarmno vezje (DAV), ki skrbi za delovanje komunikacijskega sistema ob alarmnih stanjih in za ugotavljanje mesta ovare, preko njihovih 2048 kbit/s vhodov in izhodov, povežemo v digitalno komunikacijsko zanko, s tem da izhod poljubno izbranega multiplekserja (MUXA) vežemo na vhod multiplekserja (MUXB), čigar izhod je vezan na vhod naslednjega multiplekserja (MUXC) v digitalni komunikacijski zanki, itn. do zadnjega multiplekserja (MUXN) v digitalni komunikacijski zanki, čigar izhod vežemo na vhod multiplekserja (MUXA), pri čemer v multiplekserjih (MUXA, MUXB, ...MUXN) na mesta, ki pripadajo komunikacijskim kanalom, ki naj se pri omenjenih multiplekserjih zaključijo, vstavimo kanalska vezja (KV), oziroma v multiplekserjih (MUXA, MUXB, ... MUXN) na mesta, ki pripadajo komunikacijskim kanalom, ki naj se prepustijo do enega naslednjih multiplekserjev, vstavimo prespojna vezja (PV), katerih en del prespaja informacijski kanal in drugi del signalizacijski kanal, s tem da v vsakem časovnem okviru sprejeto informacijo komunikacijskega oziroma signalizacijskega kanala prespoji iz vhoda na izhod multiplekserja, pri čemer sprejemno vpisno logično vezje (VLS1) oz. (VLS2) na ukaz signala (MSPR) oz. (M16SPR), ki ga odda centralni del multiplekserja, krmmili sprejemni register (SR1) oz. (SR2) tako, da omenjeno informacijo sprejme in jo prepiše v vmesni pomnilnik (VP1) oz. (VP2), do koder se informacija prenose v oddajni register (OR1) oz (OR2) in se nato odda v omenjenemu komunikacijskemu kanalu namenjeno časovno okno oddajnega okvira, kar krmili oddajno vpisno logično vezje (VLO1) oz. (VLO2) na ukaz signala (MODD) oz. (M16OSS), ki ga odda centralni del multiplekserja. Prijava vsebuje še 3 patentne zahtevke.CHANNEL FOR BRANCHING CHANNELS OF TERMINAL MULTIPLEXERS, in a communication system with 2048 kbit / s digital information flow, used in mutually remote terminal multiplexers, characterized in that terminal multiplexers (MUXA, MUXB, ... MUXN), in which we add for the evaluation of alarm states, an additional alarm circuit (DAV), which takes care of the operation of the communication system in case of alarm states and for determining the location of the obstacle, via their 2048 kbit / s inputs and outputs, is connected to a digital communication loop by outputting an arbitrarily selected multiplexer ( MUXA) is connected to the input of a multiplexer (MUXB), the output of which is connected to the input of the next multiplexer (MUXC) in the digital communication loop, etc. to the last multiplexer (MUXN) in the digital communication loop, the output of which is connected to the input of the multiplexer (MUXA), whereby in the multiplexers (MUXA, MUXB, ... MUXN) to the places belonging to the communication channels to be terminated at the mentioned multiplexers , insert channel circuits (KV), or in multiplexers (MUXA, MUXB, ... MUXN) in places belonging to the communication channels to be passed to one of the next multiplexers, insert switching circuits (PV), one part of which connects the information the channel and the second part of the signaling channel, by switching the received information of the communication or signaling channel from the input to the output of the multiplexer in each time frame, whereby the receiving input logic circuit (VLS1) or (VLS2) at the signal command (MSPR) or. (M16SPR), transmitted by the central part of the multiplexer, controls the receiving register (SR1) or. (SR2) by receiving said information and overwriting it in the buffer memory (VP1) or (VP2), until which the information is transmitted to the transmitting register (OR1) or (OR2) and then transmitted in said communication channel dedicated time window of the transmitting frame, which controls the transmitting input logic circuit (VLO1) or. (VLO2) at the signal command (MODD) or. (M16OSS) transmitted by the central part of the multiplexer. The application contains 3 more patent claims.