YU43047B - Memory control device with an equipment performing in alternating manner the processing of memory claims by means of waiting lines - Google Patents

Memory control device with an equipment performing in alternating manner the processing of memory claims by means of waiting lines

Info

Publication number
YU43047B
YU43047B YU2580/81A YU258081A YU43047B YU 43047 B YU43047 B YU 43047B YU 2580/81 A YU2580/81 A YU 2580/81A YU 258081 A YU258081 A YU 258081A YU 43047 B YU43047 B YU 43047B
Authority
YU
Yugoslavia
Prior art keywords
memory
control device
processing
alternating manner
equipment performing
Prior art date
Application number
YU2580/81A
Other languages
English (en)
Other versions
YU258081A (en
Inventor
R B Johnson
C M Nibby
Original Assignee
Honeywell Inf Systems
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell Inf Systems filed Critical Honeywell Inf Systems
Publication of YU258081A publication Critical patent/YU258081A/xx
Publication of YU43047B publication Critical patent/YU43047B/xx

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1642—Handling requests for interconnection or transfer for access to memory bus based on arbitration with request queuing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Signal Processing (AREA)
  • Dram (AREA)
  • Bus Control (AREA)
  • Memory System (AREA)
  • Multi Processors (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
YU2580/81A 1980-10-31 1981-10-30 Memory control device with an equipment performing in alternating manner the processing of memory claims by means of waiting lines YU43047B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/202,821 US4451880A (en) 1980-10-31 1980-10-31 Memory controller with interleaved queuing apparatus

Publications (2)

Publication Number Publication Date
YU258081A YU258081A (en) 1983-12-31
YU43047B true YU43047B (en) 1989-02-28

Family

ID=22751401

Family Applications (1)

Application Number Title Priority Date Filing Date
YU2580/81A YU43047B (en) 1980-10-31 1981-10-30 Memory control device with an equipment performing in alternating manner the processing of memory claims by means of waiting lines

Country Status (12)

Country Link
US (1) US4451880A (fi)
EP (1) EP0051426A1 (fi)
JP (1) JPS57120164A (fi)
KR (1) KR860000986B1 (fi)
AU (1) AU551810B2 (fi)
BR (1) BR8106954A (fi)
CA (1) CA1172771A (fi)
ES (1) ES506564A0 (fi)
FI (1) FI77124C (fi)
MX (1) MX151385A (fi)
PH (1) PH18137A (fi)
YU (1) YU43047B (fi)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4558429A (en) * 1981-12-17 1985-12-10 Honeywell Information Systems Inc. Pause apparatus for a memory controller with interleaved queuing apparatus
JPS6025854A (ja) * 1983-07-22 1985-02-08 Nippon Seiko Kk 電気式動力舵取装置
JPS6025853A (ja) * 1983-07-22 1985-02-08 Nippon Seiko Kk 電気式動力舵取装置
CA1221464A (en) * 1983-12-26 1987-05-05 Hidehiko Nishida Data processor system having improved data throughput of multiprocessor system
JPH0331665Y2 (fi) * 1984-09-05 1991-07-04
ES2004078A6 (es) * 1986-01-29 1988-12-01 Digital Equipment Corp Sistema de tratamiento de datos, panel y subsistema de memoria para dicho sistema,y metodo de almacenar datos.
US4937770A (en) * 1986-02-07 1990-06-26 Teradyne, Inc. Simulation system
US5327542A (en) * 1987-09-30 1994-07-05 Mitsubishi Denki Kabushiki Kaisha Data processor implementing a two's complement addressing technique
US5471637A (en) * 1988-12-30 1995-11-28 Intel Corporation Method and apparatus for conducting bus transactions between two clock independent bus agents of a computer system using a transaction by transaction deterministic request/response protocol and burst transfer
US5363486A (en) * 1989-11-13 1994-11-08 Zenith Data Systems Corporation Variable size queue circuit for buffering data transfers from a processor to a memory
US6807609B1 (en) * 1989-12-04 2004-10-19 Hewlett-Packard Development Company, L.P. Interleaving read and write operations on a bus and minimizing buffering on a memory module in a computer system
US5265229A (en) * 1990-07-02 1993-11-23 Digital Equipment Corporation Single load, multiple issue queue with error recovery capability
CA2051222C (en) * 1990-11-30 1998-05-05 Pradeep S. Sindhu Consistent packet switched memory bus for shared memory multiprocessors
DE4292241T1 (de) * 1991-07-02 1994-05-05 Intel Corp Asynchrone modulare Bus-Architektur mit Burst-Fähigkeit
FR2695227B1 (fr) * 1992-09-02 1994-10-14 Aton Systemes Procédé pour le transfert entrelacé des données entre la mémoire d'un ordinateur et un équipement périphérique constitué d'un système de gestion et de plusieurs unités de stockage.
DE19503022A1 (de) * 1994-04-08 1995-10-12 Hewlett Packard Co Master/Slave-Buskonfiguration für schnelle erweiterbare Speichersysteme
US6295586B1 (en) * 1998-12-04 2001-09-25 Advanced Micro Devices, Inc. Queue based memory controller
US6557090B2 (en) * 2001-03-09 2003-04-29 Micron Technology, Inc. Column address path circuit and method for memory devices having a burst access mode
US20040054864A1 (en) * 2002-09-13 2004-03-18 Jameson Neil Andrew Memory controller
US7461218B2 (en) * 2005-06-29 2008-12-02 Intel Corporation Size-based interleaving in a packet-based link
CN101432061B (zh) 2006-04-28 2012-09-26 旭化成化学株式会社 气体分离膜
US9268720B2 (en) 2010-08-31 2016-02-23 Qualcomm Incorporated Load balancing scheme in multiple channel DRAM systems

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3735354A (en) * 1972-04-07 1973-05-22 Sperry Rand Corp Multiplexed memory request interface
US3961312A (en) * 1974-07-15 1976-06-01 International Business Machines Corporation Cycle interleaving during burst mode operation
US4000485A (en) * 1975-06-30 1976-12-28 Honeywell Information Systems, Inc. Data processing system providing locked operation of shared resources
US4151598A (en) * 1978-03-27 1979-04-24 Honeywell Information Systems Inc. Priority assignment apparatus for use in a memory controller
US4281381A (en) * 1979-05-14 1981-07-28 Bell Telephone Laboratories, Incorporated Distributed first-come first-served bus allocation apparatus

Also Published As

Publication number Publication date
EP0051426A1 (en) 1982-05-12
AU551810B2 (en) 1986-05-15
JPH039495B2 (fi) 1991-02-08
US4451880A (en) 1984-05-29
FI77124B (fi) 1988-09-30
ES8303746A1 (es) 1983-02-01
FI813266L (fi) 1982-05-01
FI77124C (fi) 1989-01-10
ES506564A0 (es) 1983-02-01
JPS57120164A (en) 1982-07-27
BR8106954A (pt) 1982-07-13
PH18137A (en) 1985-04-03
MX151385A (es) 1984-11-13
YU258081A (en) 1983-12-31
CA1172771A (en) 1984-08-14
AU7690381A (en) 1982-05-06
KR830008242A (ko) 1983-11-16
KR860000986B1 (ko) 1986-07-24

Similar Documents

Publication Publication Date Title
YU258081A (en) Memory control device with an equipment performing in alternating manner the processing of memory claims by means of waiting lines
GB2084037B (en) Processing apparatus
GB2079997B (en) Data processing apparatus
DE3169741D1 (en) Data processing apparatus
GB2079995B (en) Portable data processing apparatus
GB2072902B (en) Data processing apparatus
DE3176513D1 (en) Data processing apparatus
DE3464013D1 (en) Object processing device
JPS5720858A (en) Portable device for calculating or processing data
JPS5734281A (en) Segmentation device
JPS5768389A (en) Inspecting device
DE3068568D1 (en) Control method and circuit for performing the method
JPS5755287A (en) Dock device
GB8413274D0 (en) Information processing apparatus
JPS56162154A (en) Pipeline processing system
GB2075708B (en) Dimensional checking apparatus
JPS5789133A (en) Text-stream changing device in word processing system
DE3164722D1 (en) Data processing apparatus for processing sparse vectors
GB2091525B (en) Information processing apparatus
DE3166292D1 (en) Text processing device with display device
GB2075707B (en) Dimensional checking apparatus
GB2077947B (en) Film processing apparatus
DE3168948D1 (en) An electromagnetic device
ATA533581A (de) Textverarbeitungsgeraet
GB2078902B (en) Feedscrew device