WO2026011997A1 - 服务系统、输入输出机箱、设备机箱以及机箱识别方法 - Google Patents

服务系统、输入输出机箱、设备机箱以及机箱识别方法

Info

Publication number
WO2026011997A1
WO2026011997A1 PCT/CN2025/098014 CN2025098014W WO2026011997A1 WO 2026011997 A1 WO2026011997 A1 WO 2026011997A1 CN 2025098014 W CN2025098014 W CN 2025098014W WO 2026011997 A1 WO2026011997 A1 WO 2026011997A1
Authority
WO
WIPO (PCT)
Prior art keywords
chassis
identification information
identification
input
component
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/CN2025/098014
Other languages
English (en)
French (fr)
Inventor
刘振
王海波
贾会娟
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Suzhou Metabrain Intelligent Technology Co Ltd
Original Assignee
Suzhou Metabrain Intelligent Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Suzhou Metabrain Intelligent Technology Co Ltd filed Critical Suzhou Metabrain Intelligent Technology Co Ltd
Publication of WO2026011997A1 publication Critical patent/WO2026011997A1/zh
Pending legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/16—Constructional details or arrangements
    • G06F1/18—Packaging or power distribution

Definitions

  • This application relates to the field of computer technology, and in particular to a service system, an input/output chassis, a device chassis, and a chassis identification method.
  • Converged architecture decouples the system into independent modules such as computing resource pools, memory resource pools, and I/O (Input/Output) device resource pools. This facilitates flexible configuration and rapid upgrades of key devices such as CPUs (Central Processing Units), memory, GPUs (Graphics Processing Units), and SSDs (Solid State Disks or Solid State Drives).
  • CPUs Central Processing Units
  • memory GPUs
  • SSDs Solid State Disks or Solid State Drives.
  • all I/O resources within a rack are centralized in an I/O Box. Terminal devices are mounted under the I/O Box via CDFP connectors (CDFP connectors, short for 400Gb/s (16 x 25Gb/s) Pluggable Transceivers, i.e., 16-way pluggable connectors).
  • Management software can allocate I/O resources based on the actual device access.
  • SSD resource pools exist as independent boxes.
  • customers selectively mount one, two, or more SSD boxes under the IO Box according to their own needs. Since these SSD boxes have identical physical structures, the CDFP connector itself does not have any extra pins for ID identification, meaning it cannot identify two or more SSD boxes.
  • embodiments of this application provide a service system based on a converged architecture, an input/output chassis, a device chassis, and a chassis identification method.
  • embodiments of this application provide a service system, which includes an input/output chassis and at least one device chassis.
  • the input/output chassis includes a plurality of first pluggable connectors
  • the device chassis includes a plurality of second pluggable connectors. At least one second pluggable connector is coupled to at least one first pluggable connector.
  • the equipment chassis also includes multiple identification components coupled to a second pluggable connector.
  • the identification components are used to manage the identification information of the coupled second pluggable connector, and the identification information is used to indicate the type and quantity of the equipment chassis.
  • the input/output chassis scans multiple first pluggable connectors, reads the identification information managed by the identification components under the second pluggable connectors coupled to each first pluggable connector, and identifies the type and quantity of the equipment chassis based on the identification information.
  • the input/output chassis determines whether identical identification information exists in response to reading the identification information
  • the input/output chassis In response to determining that there is identical identification information and identifying the target device chassis corresponding to the identical identification information, the input/output chassis sends a change command to at least one target device chassis.
  • the change command instructs at least one target device chassis to change the identification information managed by its included identification components.
  • the target device chassis Upon receiving a change command, the target device chassis modifies the identification information managed by its included identification components;
  • the input/output chassis rescans multiple first pluggable connectors to read the modified identification information and identifies the number of chassis of the same type based on the modified identification information.
  • the data width of the identification information is N bits, wherein the k-th to m-th bits of the identification information are type bits, which are used to indicate the type of the device chassis; N is a positive integer greater than 1, 1 ⁇ k ⁇ m ⁇ N, and k and m are integers;
  • the input/output chassis identifies the type of the device chassis based on the value of the type bit in the identification information.
  • the (m+1)th to (N-1)th bits of the identification information are quantity bits, which are used to distinguish equipment chassis of the same type.
  • the input/output chassis generates a change command based on the number of identical identification information, and the change command indicates the value of a specified bit in the quantity bits to be changed.
  • the input/output chassis in response to determining that the number of identical identification information is 2, the input/output chassis generates a first change command, the first change command indicating the value of a first specified bit in the change quantity bit; the input/output chassis determines a first target device chassis and a second target device chassis among two target device chassis with identical identification information, and sends the first change command to the first target device chassis;
  • the input/output chassis In response to determining that the number of identical identification information is 3, the input/output chassis generates a first change command and a second change command, wherein the second change command indicates the value of the second specified bit in the change quantity bit; the input/output chassis determines the first target device chassis, the second target device chassis and the third target device chassis among the three target device chassis with identical identification information, and sends the first change command to the first target device chassis and the second change command to the second target device chassis;
  • the input/output chassis In response to determining that the number of identical identification information is 4, the input/output chassis generates a first change command, a second change command, and a third change command.
  • the third change command indicates that the values of the first specified bit and the second specified bit in the quantity bits are changed simultaneously.
  • the input/output chassis determines the first target device chassis, the second target device chassis, the third target device chassis, and the fourth target device chassis among the four target device chassis with identical identification information, and sends the first change command to the first target device chassis, the second change command to the second target device chassis, and the third change command to the third target device chassis.
  • the 0th to (k-1)th bits of the identification information are interface bits, which are used to indicate the number of the second pluggable connector.
  • the input/output chassis further includes an identification component and a two-wire serial bus expansion component.
  • the identification component is coupled to the two-wire serial bus expansion component, and the two-wire serial bus expansion component is coupled to the identification component and a plurality of first pluggable connectors, respectively.
  • the two-wire serial bus expansion component expands one I2C channel of the identification component into multiple I2C channels, and couples the multiple I2C channels to the plurality of first pluggable connectors.
  • the identification component scans its I2C channel, reads the identification information managed by the identification component under the second pluggable connector coupled to each first pluggable connector, and identifies the type and quantity of the equipment chassis based on the identification information.
  • the input/output chassis further includes a storage component and a multiplexer; the storage component is coupled to the multiplexer, and the multiplexer is coupled to the identification component and the baseboard management controller of the input/output chassis;
  • the identification component controls the multiplexer to close the data interaction link between the storage component and the baseboard management controller, and opens the data interaction link between the identification component and the storage component; in response to the completion of device chassis type identification, the identification component generates the system interconnect configuration relationship and writes the system interconnect configuration relationship into the storage component;
  • the identification component controls the multiplexer to open the data interaction link between the storage component and the baseboard management controller, and notifies the baseboard management controller that the system interconnect configuration relationship has been written.
  • the baseboard management controller in response to a notification from the identification component, obtains the system interconnect configuration relationship from the storage component.
  • the identification component includes a first identification component and a second identification component
  • each second pluggable connector includes an input port and an output port, the input port being coupled to the first identification component and the output port being coupled to the second identification component
  • the input/output chassis scans multiple first pluggable connectors and reads the identification information managed by the second identification component; if the same identification information exists, the target device chassis corresponding to the same identification information is determined, and a change command is sent to the first identification component of at least one target device chassis.
  • the change command is used to instruct the first identification component to change the identification information managed by its corresponding second identification component; the second identification component corresponding to the first identification component is the second identification component coupled to the same second pluggable connector.
  • the first identification component Upon receiving a change command, the first identification component changes the identification information managed by its corresponding second identification component;
  • the input/output chassis rescans multiple first pluggable connectors to read the modified identification information and identifies the number of chassis of the same type based on the modified identification information.
  • the address of the first identification component is a first fixed address
  • the address of the second identification component is a second fixed address
  • inventions of this application provide an input/output chassis coupled to at least one device chassis.
  • the input/output chassis includes a plurality of first pluggable connectors
  • the device chassis includes a plurality of second pluggable connectors. At least one second pluggable connector is coupled to at least one first pluggable connector.
  • the device chassis also includes a plurality of identification components coupled to the second pluggable connectors. The identification components are used to manage identification information of the coupled second pluggable connectors, and the identification information is used to indicate the type and quantity of the device chassis.
  • the input/output chassis scans multiple first pluggable connectors, reads the identification information managed by the identification components under the second pluggable connectors coupled to each first pluggable connector, and identifies the type and quantity of the equipment chassis based on the identification information.
  • embodiments of this application provide a device chassis coupled to an input/output chassis;
  • the input/output chassis includes a plurality of first pluggable connectors
  • the device chassis includes a plurality of second pluggable connectors, and at least one second pluggable connector is coupled to at least one first pluggable connector;
  • the equipment chassis also includes multiple identification components coupled to a second pluggable connector.
  • the identification components manage identification information of the coupled second pluggable connector, which indicates the type and quantity of the equipment chassis.
  • embodiments of this application provide a chassis identification method, characterized in that the method is applied to a service system provided in any embodiment of this application.
  • the service system includes an input/output chassis and at least one device chassis.
  • the input/output chassis includes a plurality of first pluggable connectors
  • the device chassis includes a plurality of second pluggable connectors and a plurality of identification components.
  • At least one second pluggable connector is coupled to at least one first pluggable connector, and the identification components are coupled to the second pluggable connectors.
  • the methods include:
  • multiple first pluggable connectors are scanned, and the identification information managed by the identification components under the second pluggable connectors coupled to each first pluggable connector is read.
  • the type and quantity of the equipment chassis are identified based on the identification information.
  • embodiments of this application provide a computer program product, including a computer program, characterized in that the computer program, when executed by a processor, implements the chassis identification method of embodiments of this application.
  • embodiments of this application provide an electronic device, including a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus; the memory is used to store computer programs; and the processor is used to implement the chassis identification method of embodiments of this application when executing the programs stored in the memory.
  • embodiments of this application provide a computer non-volatile storage medium storing a computer program thereon, which, when executed by a processor, implements the chassis identification method of embodiments of this application.
  • the service system of this application embodiment manages identification information representing the type and quantity of device chassis through an identification component.
  • Input/output chassis scan their CDFP interfaces, read the identification information managed by the identification component within the chassis, and identify the type and quantity of the chassis based on this identification information. This allows the input/output chassis to accurately identify the type and quantity of the coupled chassis, thereby enabling data commands to be precisely sent to the desired chassis. If identical identification information is found among the identification information read by the input/output chassis, it indicates the presence of identical chassis. In this case, the input/output chassis needs to distinguish between these identical chassis by sending a change command to the identical chassis to modify the quantity bits of the identification information of a particular chassis. The input/output chassis then distinguishes between identical chassis based on the modified quantity bits of the identification information.
  • Figure 1 shows a schematic diagram of the structure of the service system based on the converged architecture provided in an embodiment of this application;
  • Figure 2 shows a schematic diagram of the input/output chassis in the service system based on converged architecture provided in an embodiment of this application.
  • Figure 3 shows a schematic diagram of the input/output chassis in a service system based on a converged architecture provided in another embodiment of this application;
  • Figure 4 shows a schematic diagram of the device chassis in the service system based on converged architecture provided in an embodiment of this application.
  • Figure 5A shows a schematic diagram illustrating the connection relationship between the input/output chassis and the GPU chassis according to an embodiment of this application
  • Figure 5B shows a schematic diagram illustrating the connection relationship between the input/output chassis and the GPU chassis according to another embodiment of this application;
  • Figure 6 shows a schematic diagram of the identification information of all the identification components coupled to the CDFP interface of the GPUBox;
  • Figure 7A shows a schematic diagram of the structure of a service system based on a converged architecture provided in another embodiment of this application;
  • FIG. 7B shows a schematic diagram of the structure of the GPU Box 0 provided in an embodiment of this application.
  • FIG. 7C shows a schematic diagram of the structure of the GPU Box 1 provided in an embodiment of this application.
  • FIG. 8 shows a flowchart of the chassis identification method provided in an embodiment of this application.
  • Figure 9 shows a schematic diagram of the structure of the electronic device provided in an embodiment of this application.
  • Figure 1 shows a schematic diagram of the structure of a service system based on a converged architecture provided in an embodiment of this application.
  • the service system 100 based on a converged architecture includes an input/output chassis (IO Box) 101 and a device box 102.
  • the device box 102 may include, but is not limited to, a GPU (Graphics Processing Unit) Box, an SSD (Solid State Disk or Solid State Drive) Box, and a memory box.
  • GPU Graphics Processing Unit
  • SSD Solid State Disk or Solid State Drive
  • the input/output chassis 101 includes multiple first pluggable connectors 103 (CDFP connectors, short for 400Gb/s (16 x 25Gb/s) Pluggable Transceiver, i.e., 16-way pluggable connectors, hereinafter referred to as first CDFP interfaces).
  • the device chassis 102 includes multiple second pluggable connectors 104 (hereinafter referred to as second CDFP interfaces).
  • the first CDFP interfaces 103 and second CDFP interfaces 104 are coupled.
  • the device chassis 102 is coupled to the I/O chassis 101 through the first CDFP interfaces 103 and the second CDFP interfaces 104.
  • the device chassis coupled to the I/O chassis can be one or multiple.
  • the multiple device chassis coupled to the I/O chassis can be of the same type, such as two GPU Boxes, or they can be different, such as two GPU Boxes and one SSD Box.
  • the device chassis 102 also includes multiple identification components 105.
  • the identification components 105 are coupled to the second CDFP interface 104.
  • the number of identification components 105 is the same as the number of second CDFP interfaces 104, and each identification component 105 corresponds one-to-one with a second CDFP interface 104.
  • the identification component 105 manages the identification information of its coupled second CDFP interface, which indicates the type and quantity of the device chassis. Different types of device chassis correspond to different identification information.
  • the identification component may be a chip that converts I2C signals to IO signals, having programmable GPIO (General-Purpose Input/Output) pins, and managing the identification information by controlling the high and low levels of the GPIO pin outputs.
  • I2C Inter-Integrated Circuit
  • I2C is a multi-master, two-wire, low-speed serial communication bus, and the data transmitted by it is simply referred to as I2C signals.
  • the data width of the identification information is N bits, wherein the k-th to m-th bits of the identification information are type bits, which are used to indicate the type of the device chassis.
  • An IO chassis can identify the type of the device chassis based on the value of the type bit in the identification information.
  • the (m+1)-th to (N-1)-th bits of the identification information are quantity bits, which are used to distinguish device chassis of the same type.
  • An IO chassis can distinguish the same device chassis based on the value of the quantity bits in the identification information.
  • the 0-th to (k-1)-th bits of the identification information are interface bits, which are used to indicate the number of the second CDFP interface.
  • N is a positive integer greater than 1 ⁇ k ⁇ m ⁇ N, and k and m are integers.
  • the identification component is a PCA9554 chip.
  • the PCA9554 chip has 8 programmable GPIO pins, and the identification information it manages is 8 bits, with the 4th and 5th bits being type bits used to distinguish different types of chassis. For example, if bits 4 and 5 of the identification information are 10, the identification information indicates that the device chassis type is a GPU Box. If bits 4 and 5 are 01, the identification information indicates that the device chassis type is an SSD Box. If bits 4 and 5 are 11, the identification information indicates that the device chassis type is a Memory Box. Bits 6 and 7 are quantity bits, used to distinguish identical device chassis. The values of bits 6 and 7 include four possibilities: 00, 01, 10, and 11. By default, the value of bits 6 and 7 is 00. The values of bits 6 and 7 can distinguish four identical device chassis. Bits 0-3 are interface bits, used to distinguish the CDFP interface in the device chassis.
  • the IO chassis 101 scans the first CDFP interface 103, reads the identification information managed by the identification component 105 under the second CDFP interface 104 coupled to each first CDFP interface 103, and identifies the type of the device chassis 102 based on the identification information.
  • multiple device chassis of the same type may be coupled to an I/O chassis.
  • the identification information read by the I/O chassis contains identical identification information.
  • the I/O chassis identifies the target device chassis corresponding to the identical identification information and sends a change command to at least one target device chassis.
  • the change command instructs the target device chassis to change the identification information managed by its included identification component.
  • the change command instructs the target device chassis to change the value of the quantity bit in the identification information.
  • the target device chassis changes the identification information managed by its included identification component, for example, changing the value of the quantity bit in the identification information.
  • the I/O chassis rescans multiple first CDFP interfaces to read the changed identification information and distinguishes device chassis of the same type based on the changed identification information.
  • the service system of this application embodiment manages identification information representing the type and quantity of device chassis through an identification component.
  • the IO chassis scans its CDFP interface, reads the identification information managed by the identification component within the chassis, and identifies the type and quantity of the device chassis based on this identification information. This allows the IO chassis to accurately identify the type and quantity of the coupled device chassis, thereby enabling data commands to be accurately sent to the desired device chassis. If the identification information read by the IO chassis contains identical identification information, it indicates the presence of identical device chassis. In this case, the IO chassis needs to distinguish between these identical device chassis by sending a change command to the identical device chassis to modify the quantity bit of the identification information of a certain device chassis. The IO chassis distinguishes between identical device chassis based on the modified quantity bit of the identification information.
  • the IO chassis generates a change command based on the number of identical identification information bits.
  • This change command indicates a change to a specified bit in the quantity bits.
  • the number of identical identification information bits represents the number of identical device chassis in the service system. In cases with different numbers of identical device chassis, it is necessary to change the identification information of different numbers of device chassis. For example, if there are two identical device chassis, and the identification information of one device chassis needs to be changed, the IO chassis can generate a change command to change the identification information of one of the device chassis. Therefore, in response to determining that the number of identical identification information bits is 2, the IO chassis generates a first change command.
  • This first change command indicates a change to the value of a first specified bit in the quantity bits of the identification information (e.g., by default, the default values of bits 6 and 7 in the identification information are both 0, and the first change command indicates changing the value of bit 6 in the identification information to 1).
  • the IO chassis identifies a first target device chassis and a second target device chassis among the two target device chassis with identical identification information, and sends the first change command to the first target device chassis.
  • the first target device chassis can be any one of the two target device chassis, or the first target device chassis and the second target device chassis can be determined according to a specified strategy.
  • the first target device chassis and the second target device chassis can be determined according to the numbering order of the second CDFP interfaces (the numbering order of the CDFP interfaces can be determined according to the value of the interface bit of the identification information), and the target device chassis corresponding to the later second CDFP interface is used as the first target device chassis.
  • the service system when the service system has three identical device chassis, it is necessary to change the identification information of two of the device chassis.
  • the IO chassis needs to generate two different change commands to change the identification information of the two device chassis, so that the three identical device chassis have three different identification information. Therefore, in response to determining that the number of identical identification information is 3, the IO chassis generates a first change command and a second change command.
  • the first change command indicates changing the value of a first specified bit in the number bits of the identification information (for example, the default value of bits 6 and 7 in the identification information is 0 by default, and the first change command indicates changing the value of bit 6 in the identification information to 1)
  • the second change command indicates changing the value of a second specified bit in the number bits of the identification information (for example, the default value of bits 6 and 7 in the identification information is 0 by default, and the second change command indicates changing the value of bit 7 in the identification information to 1).
  • the IO chassis identifies a first target device chassis, a second target device chassis, and a third target device chassis among the three target device chassis with identical identification information, sends the first change command to the first target device chassis, and sends the second change command to the second target device chassis.
  • the IO chassis can determine the first target device chassis, the second target device chassis, and the third target device chassis according to the numbering order of the second CDFP interfaces.
  • the target device chassis coupled to the last second CDFP interface is designated as the first target device chassis
  • the target device chassis coupled to the first second CDFP interface is designated as the third target device chassis
  • the target device chassis coupled to the middle second CDFP interface is designated as the second target device chassis.
  • the identification information of three of the chassis needs to be changed.
  • the I/O chassis needs to generate three different change commands to modify the identification information of two of the chassis, so that the four identical chassis have four different identification information. Therefore, in response to determining that the number of identical identification information is four, the I/O chassis generates a first change command, a second change command, and a third change command.
  • the first change command instructs the user to change the value of the first specified bit in the number of bits of the identification information (e.g., the default value of bits 6 and 7 in the identification information is 0 by default, and the first change command instructs the user to change the value of bit 6 in the identification information to 1).
  • the second change command instructs the user to change the value of the second specified bit in the number of bits of the identification information (e.g., the default value of bits 6 and 7 in the identification information is 0 by default, and the second change command instructs the user to change the value of bit 7 in the identification information to 1).
  • the third change command instructs the user to change the values of both the first and second specified bits in the number of bits of the identification information (e.g., the default value of bits 6 and 7 in the identification information is 0 by default, and the third change command instructs the user to change the values of both bits 6 and 7 in the identification information to 1).
  • the IO chassis identifies a first target device chassis, a second target device chassis, a third target device chassis, and a fourth target device chassis among four target device chassis with the same identification information, and sends the first change command to the first target device chassis, the second change command to the second target device chassis, and the third change command to the third target device chassis.
  • FIG 2 shows a schematic diagram of the structure of the IO chassis in the service system provided in the embodiment of this application.
  • the IO chassis 200 includes a first pluggable connector 201 (hereinafter referred to as the first CDFP interface), an identification component 202, and a two-wire serial bus expansion component 203 (hereinafter referred to as the I2C expansion component).
  • the identification component 202 is coupled to the I2C expansion component 203.
  • the I2C expansion component 203 is coupled to the identification component 202 and multiple first CDFP interfaces 201.
  • the I2C expansion component 203 expands one I2C channel of the identification component 202 into multiple I2C channels, and couples the multiple I2C channels to the multiple first CDFP interfaces 201.
  • the first CDFP interfaces 201 are coupled to the second CDFP interface of the device chassis (refer to Figure 1).
  • the identification component 202 acting as the task initiator of the ID identification process within the I/O chassis, scans its I2C channels, reads the identification information managed by each identification component, and identifies the type of the device chassis based on the identification information.
  • the identification component 202 is a CPLD.
  • CPLD Complex Programmable Logic Device
  • Complex PLD a type of digital integrated circuit where the logic functions are constructed by the user according to their own needs.
  • I2C expansion component 203 expands the CPLD's single I2C channel into multiple I2C channels, and connects each of these multiple I2C channels to a different first CDFP interface.
  • first CDFP interface corresponds to a specific I2C channel
  • multiple I2C expansion components are required within the entire I/O chassis. This ensures that during installation, regardless of which first CDFP interface the device is plugged into or whether it is plugged in sequentially, it can be effectively recognized by the CPLD of the I/O chassis through a specific I2C channel.
  • the type and number of device chassis coupled to the IO chassis are identified by the identification component, eliminating the need for the baseboard management controller inside the IO chassis to perform identification, thus improving the identification speed of the service system.
  • the baseboard management controller does not participate in the process of identifying device chassis, which can avoid the problem of abnormal system configuration identification when the baseboard management controller fails.
  • Figure 3 shows a schematic diagram of the structure of the IO chassis of the service system provided in this application embodiment.
  • the IO chassis further includes a storage component 204, a multiplexer 205, and a baseboard management controller 206.
  • the storage component 204 is coupled to the multiplexer 205
  • the multiplexer 205 is coupled to the identification component 202 and the baseboard management controller 206 of the IO chassis.
  • the identification component 202 controls the multiplexer 205 to close the data interaction link between the storage component 204 and the baseboard management controller 206, and opens the data interaction link between the identification component 202 and the storage component 204.
  • the identification component 204 In response to the completion of device chassis type identification, the identification component 204 generates a system interconnect configuration relationship and writes it to the storage component 204.
  • This system interconnect configuration relationship indicates the type and number of device chassis coupled to the I/O chassis, as well as the coupling relationship between the first CDFP interface and the second CDFP interface.
  • the identification component 202 controls the multiplexer 205 to open the data interaction link between the storage component 204 and the baseboard management controller 206, and notifies the baseboard management controller 206 that the system interconnect configuration relationship has been written. For example, the identification component controls the MUX_SEL signal to open the data interaction link between the storage component and the baseboard management controller, and notifies the baseboard management controller to obtain the system interconnect configuration relationship of the storage component through the ID_READY signal.
  • the baseboard management controller 206 obtains the system interconnect configuration relationship from the storage component 204.
  • the data interaction link between the baseboard management controller and the storage component is disconnected via a multiplexer, preventing the baseboard management controller from reading the system interconnect configuration relationship before the chassis device identification is complete.
  • the data interaction link between the baseboard management controller and the storage component is reopened via a multiplexer, enabling the baseboard management controller to read the complete system interconnect configuration relationship, thus ensuring the integrity and accuracy of the system interconnect configuration relationship read by the baseboard management controller.
  • FIG 4 shows a schematic diagram of the equipment chassis of the service system according to an embodiment of this application.
  • each second CDFP interface of the equipment chassis includes an input port and an output port.
  • the input port is coupled to a first identification component
  • the output port is coupled to a second identification component.
  • the second identification component manages identification information representing the type and quantity of the equipment chassis, and the first identification component is used to configure the identification information managed by the second identification component.
  • the IO chassis scans multiple first CDFP interfaces and reads the identification information managed by the second identification component. If the same identification information exists, the IO chassis determines the target device chassis corresponding to the same identification information and sends a change command to the first identification component of at least one target device chassis. The change command is used to instruct the first identification component to change the identification information managed by its corresponding second identification component.
  • the second identification component corresponding to the first identification component is the second identification component coupled to the same second CDFP interface.
  • the first identification component Upon receiving a change command, the first identification component changes the identification information managed by its corresponding second identification component.
  • the IO chassis rescans multiple first CDFP interfaces, reads the identification information managed by the second identification component, and identifies the type of device chassis based on the identification information.
  • the address of the first identification component is a first fixed address
  • the address of the second identification component is a second fixed address. Setting the first and second identification components to fixed addresses respectively ensures that the I/O chassis can read the identification information when the device chassis is coupled to any CDFP interface of the I/O chassis.
  • Figures 5A, 5B, 6, 7, and 8 respectively illustrate a coupling relationship between the GPU Box and the IO Box.
  • Figure 6 shows a schematic diagram of the identification information managed by the identification components coupled to all CDFP interfaces of the GPU Box.
  • Figure 7 shows a schematic diagram of a service system based on a converged architecture.
  • Figure 8 shows a flowchart illustrating the chassis identification method provided in the embodiments of this application.
  • the IO Box serves as the IO resource management node for the entire service system. Its specific function is to expand, network, and allocate PCIe resources (high-speed serial computer expansion resources) from multiple different CPUs through the eight PCIe Switch chips (high-speed serial computer expansion components) contained within the IO Box.
  • the PCIe Switch chips provide expansion or aggregation capabilities, allowing more devices to connect to a single PCIe port.
  • PCIe Peripheral Component Interconnect Express
  • the entire IO Box ultimately provides 40 CDFP interfaces, each containing a set of high-speed PCIe 5.0 x16 IO signals.
  • a GPU Box is a container specifically designed to house standard GPU cards. Each GPU Box can accommodate up to 16 standard PCIe form factor GPUs.
  • the GPU Box provides 16 CDFP interfaces, which are coupled to the IO Box.
  • Figures 5A and 5B illustrate two different coupling relationships between the GPU Box and the IO Box.
  • the CDFP0-0, CDFP0-1, CDFP0-2, and CDFP0-3 interfaces of the IO Box are coupled to the CDFP0, CDFP1, CDFP2, and CDFP3 interfaces of GPU Box-1, respectively.
  • the CDFP4-0, CDFP4-1, CDFP4-2, and CDFP6-0 interfaces of the IO Box are coupled to the CDFP0, CDFP1, CDFP2, and CDFP8 interfaces of GPU Box-0, respectively.
  • the CDFP0-2, CDFP0-3, CDFP0-4, and CDFP2-2 interfaces of the IO Box are coupled to the CDFP0, CDFP1, CDFP2, and CDFP8 interfaces of the GPU Box-1, respectively.
  • the CDFP4-2, CDFP4-3, CDFP4-4, and CDFP5-0 interfaces of the IO Box are coupled to the CDFP0, CDFP1, CDFP2, and CDFP8 interfaces of the GPU Box-0, respectively.
  • the 16 CDFP interfaces of the GPU Box can connect to any 16 of the 40 CDFP interfaces of the IO Box, without requiring a specific plugging order.
  • the SSD Box is a container specifically designed to house NVMe U.2 hard drives.
  • Each SSD Box can hold up to 24 drives.
  • the SSD Box provides 6 CDFP interfaces, which are coupled to the IO Box via these interfaces.
  • the six CDFP interfaces can connect to any six of the 40 CDFP interfaces in the IO Box, without requiring a fixed insertion order.
  • the Memory Box is a dedicated container for holding memory. Internally, it uses a CXL Controller chip (CXL controller, where CXL (Compute Express Link) is a high-speed serial protocol that allows fast and reliable data transfer between different components within a computer system) to convert CXL signals (the physical layer of the PCIe protocol) into memory signals, thus enabling memory sharing.
  • CXL Controller chip CXL controller, where CXL (Compute Express Link) is a high-speed serial protocol that allows fast and reliable data transfer between different components within a computer system) to convert CXL signals (the physical layer of the PCIe protocol) into memory signals, thus enabling memory sharing.
  • Each Memory Box provides eight CDFP interfaces, which can connect
  • the IO Box provides 40 CDFP interfaces, which can couple up to 4 GPU Boxes.
  • the 4 GPU Boxes can be distinguished using 2-bit quantity bits.
  • the device chassis may include GPU Boxes, Memory Boxes, and SSD Boxes, which can be distinguished using 2-bit type bits.
  • GPU Boxes include the most CDFP interfaces (16 CDFP interfaces), which can be distinguished using 4-bit interface bits. Therefore, the identification information can be 8 bits.
  • the identification component inside the device chassis can be a PCA9554 chip. For example, bits 7 and 6 of the PCA9554 are used as quantity bits (i.e., Box Number) to distinguish identical Boxes. The default value of these two bits is 00.
  • Bits 5 and 4 are type bits used to distinguish different types of Boxes, allowing the IO Box to identify the type of device chassis after a single scan.
  • bits 5 and 4 are 10, indicating that the device chassis type is a GPU Box.
  • Bits 5 and 4 being 01 indicate that the device enclosure type is an SSD Box.
  • Bits 5 and 4 being 11 indicate that the device enclosure type is a Memory Box.
  • Bits 3, 2, 1, and 0 are interface bits (i.e., CDFP Number bits), used to distinguish each CDFP interface.
  • the identification information for GPU Box is shown in Table 1 below
  • the identification information for SSD Box is shown in Table 2 below
  • the identification information for Memory Box is shown in Table 3 below.
  • Figure 6 shows the identification information managed by the identification component coupled to all CDFP interfaces of the GPUBox. Different CDFP interfaces are distinguished by the values of the 0th to 3rd bits of the identification information.
  • "**100000” represents the 0th CDFP interface of the GPUBox (CDFP-0)
  • "**100001” represents the 1st CDFP interface of the GPUBox (CDFP-1)
  • "**100010” represents the 2nd CDFP interface of the GPUBox (CDFP-2).
  • the meanings of other identification information in Figure 6 are similar and will not be repeated here to avoid repetition.
  • Figure 7A shows a schematic diagram of the service system where two GPU Boxes are coupled to an IO Box.
  • Figure 7B shows a schematic diagram of the GPU Box 0 provided in an embodiment of this application.
  • Figure 7C shows a schematic diagram of the GPU Box 1 provided in an embodiment of this application. Referring to Figure 7A, taking two GPU Boxes as an example, the chassis identification principle in a scenario with multiple identical device chassis is explained. This solution is also applicable to other types of device chassis.
  • the CPLD in the IO Box is the identification component, acting as the task initiator for the chassis identification process.
  • the PCA9548 is a two-wire serial bus expansion component.
  • the PCA9548 expands the CPLD's single I2C channel into multiple channels, each connected to a different CDFP interface.
  • multiple PCA9548s are required within the entire IO Box. This ensures that during installation, regardless of which CDFP interface the device is plugged into within the IO Box or whether it is plugged in sequentially, it can be effectively identified by the CPLD of the IO Box through a specific I2C channel.
  • a storage unit (FRU) and a multiplexer (MUX) are introduced between the CPLD in the IO Box and the Baseboard Management Controller (BMC).
  • the CPLD in the IO Box is responsible for the entire chassis identification process.
  • the multiplexer always switches the I2C connection of the FRU to the CPLD; after identification is complete, the CPLD first stores the complete system interconnect configuration relationship into the FRU, then controls the MUX_SEL signal to switch the I2C connection to the Baseboard Management Controller, and finally notifies the Baseboard Management Controller that the system interconnect configuration relationship of the storage unit can be obtained through the ID_READY signal.
  • each GPU Box's CDFP interface includes an input port and an output port. Each input and output port is coupled to one PCA9554.
  • the PCA9554 acts as an identification component, managing the identification information of its coupled CDFP interface. The configuration and identification of the identification information are achieved through two PCA9554s paired with their internal CPLDs. These two PCA9554s are connected to the corresponding I2C channel of the CDFP. Referring to Figure 7, the output port of the CDFP interface is coupled to PCA9554 (1-0), and the input port is coupled to PCA9554 (1-A).
  • PCA9554 (1-0) is used to manage the identification information, and the I2C address of this type of PCA9554 within the entire GPU Box is a fixed value: 0100001X.
  • PCA9554(1-A) is used to configure the identification information managed by PCA9554(1-0), such as configuring bits 7 and 6 of PCA9554(1-0).
  • the I2C address of this type of PCA9554 is a fixed value: 0100010X throughout the GPU Box.
  • the CPLD inside the IO Box sequentially scans each I2C channel of the multiple PCA9548 chips beneath it. If its CDFP interface is already interconnected with the GPU Box's CDFP interface, the CPLD can scan for a PCA9554 with address 0100001X on this I2C channel. After scanning all 40 I2C channels, an IO CDFP ⁇ --> GPU CDFP mapping relationship is established and stored in the FRU. This allows identification of which ports of the IO Box are connected to which GPU within the GPU Box. If the IO Box is connected to different types of device chassis, and no chassis of the same type exist, the chassis identification process can be completed based on the type bit in the identification information.
  • the CPLD in the IO Box scans each I2C channel in sequence, it finds that the same 8-bit identification information is read from two channels. At this time, the CPLD cannot determine which BOX the coupled GPU belongs to based on these identical identification information. Therefore, the CPLD in the IO BOX will execute the next step: if the same identification information is read from two channels, it will send a command to the PCA9554 with address 0100010X through the I2C channel with the later sequence (for example, the PCA9554 (1-A) coupled to CDFP2 of GPU Box1), so that its IO[6] outputs 1 to the CPLD in the GPU Box.
  • the PCA9554 with address 0100010X
  • the later sequence for example, the PCA9554 (1-A) coupled to CDFP2 of GPU Box1
  • the CPLD in GPU Box1 After the CPLD in GPU Box1 detects the change in IO level, it needs to pull all the IO[6] of the corresponding PCA9554 (1-1) and PCA9554 (1-2) high, that is, set bit6 of the identification information managed by PCA9554 (1-1) and PCA9554 (1-2) to 1. Subsequently, the CPLD within the IO BOX scans all 40 I2C channels again to obtain the modified identification information. One set of identification information has a count bit (bits 7-6) of 00, while the other set has a count bit (bits 7-6) of 01, thus distinguishing the two identical GPU BOXes.
  • the IO Box can then establish a system configuration management relationship, namely, a mapping relationship between IO CDFP and GPU Box 0CDFP, and GPU Box 1CDFP.
  • the information is then stored in the storage component again, and the MUX_SEL and ID_READY signals are set. After the baseboard management controller finishes loading, the system configuration association is retrieved from the storage component.
  • FIG 8 shows a flowchart illustrating the chassis identification method provided in an embodiment of this application.
  • the chassis identification method includes:
  • the CPLD in the IO Box begins to identify the device chassis (in some embodiments of this application, the CPLD in the IO Box begins to identify the device chassis after a 5-second delay).
  • the identification component CPLD in the IO Box scans all I2C channels where CDFP interfaces are located, and identifies all identification components PCA9554(1-0) and PCA9554(1-1) with address 0100001X in the GPU Box.
  • the identification information of the identified PCA9554(1-0) and PCA9554(1-1) is read and summarized into the FRU.
  • the CPLD recognition component in the IO Box determines the number of duplicate identification information.
  • the identification component CPLD in the IO Box controls the MUX_SEL signal to switch the I2C connection to the BMC, and then notifies the BMC via the ID_READY signal. Upon receiving the notification, the BMC obtains the system interconnect configuration relationship from the FRU.
  • the CPLD in the IO BOX scans the 40 I2C channels again, rebuilds the mapping table, and then executes step 5) again.
  • the 6th bit of the identification information is set to 1, and a command is sent to the PCA9554 at address 0100010X through the 3rd sorting channel, so that its IO[7] outputs 1 to the CPLD in the GPU Box.
  • the CPLD detects the change in the IO level of the PCA9554 at address 0100010X, it pulls up all the signals of the corresponding PCA9554(1-0) and PCA9554(1-1)IO[7], that is, sets the 7th bit of the identification information of the corresponding PCA9554(1-0) and PCA9554(1-1) to 1. Then repeat step 8).
  • the CPLD After the CPLD detects the change in the IO level of PCA9554 at address 0100010X, it pulls up all the signals of the corresponding PCA9554(1-0) and PCA9554(1-1) IO[6], that is, sets the 6th bit in the identification information of the corresponding PCA9554(1-0) and PCA9554(1-1) to 1, and sends a command to PCA9554 at address 0100010X through the third sorting channel, so that its IO[7] outputs 1 to the CPLD in the GPU Box.
  • the CPLD detects the change in the IO level of PCA9554 at address 0100010X.
  • the service system based on fusion state features a novel hardware topology, identification information definition method, and identification process designed based on the identification component CPLD and the identification component PCA9554.
  • This solves the problem of identifying multiple device chassis with identical physical structures, enabling data commands to be accurately sent to the target device chassis. It can more quickly identify multiple identical device chassis and provide system interconnection configuration relationships.
  • the baseboard management controller only reads the system interconnection configuration relationships as a user and does not participate in the identification process, reducing the burden on the baseboard management controller, improving the system identification speed, and avoiding the problem of abnormal system configuration identification when the baseboard management controller fails.
  • Figure 9 shows a schematic diagram of the structure of an electronic device according to an embodiment of this application.
  • the electronic device includes:
  • the system includes a processor 901, a communication interface 902, a memory 903, and a communication bus 904.
  • the processor 901, communication interface 902, and memory 903 communicate with each other via the communication bus 904.
  • Memory 903 is used to store computer programs
  • the processor 901 when executing the program stored in the memory 903, implements the chassis identification method provided in the embodiments of this application.
  • the communication bus mentioned above can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc.
  • PCI Peripheral Component Interconnect
  • EISA Extended Industry Standard Architecture
  • This communication bus can be divided into address bus, data bus, control bus, etc. For ease of representation, only one thick line is used in the diagram, but this does not indicate that there is only one bus or one type of bus.
  • the communication interface is used for communication between the aforementioned terminal and other devices.
  • the memory may include random access memory (RAM) or non-volatile memory, such as at least one disk storage device.
  • RAM random access memory
  • non-volatile memory such as at least one disk storage device.
  • the memory may also be at least one storage device located remotely from the aforementioned processor.
  • processors mentioned above can be general-purpose processors, including central processing units (CPUs), network processors (NPs), etc.; they can also be digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.
  • CPUs central processing units
  • NPs network processors
  • DSPs digital signal processors
  • ASICs application-specific integrated circuits
  • FPGAs field-programmable gate arrays
  • programmable logic devices discrete gate or transistor logic devices, or discrete hardware components.
  • a computer non-volatile storage medium which stores instructions that, when run on a computer, cause the computer to perform any of the methods described in the above embodiments.
  • a computer program product containing instructions is also provided, which, when run on a computer, causes the computer to perform any of the methods described in the above embodiments.
  • implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof.
  • software When implemented in software, it can be implemented, in whole or in part, as a computer program product.
  • a computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the flow or function according to the embodiments of this application is generated.
  • the computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device.
  • the computer instructions can be stored in a computer non-volatile storage medium or transmitted from one computer non-volatile storage medium to another.
  • computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means.
  • the computer non-volatile storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media.
  • the available media can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., DVDs), or semiconductor media (e.g., solid state disks (SSDs)).

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Abstract

本申请实施例提供了一种服务系统、输入输出机箱、设备机箱以及机箱识别方法，涉及计算机技术领域。该服务系统包括输入输出机箱和设备机箱，输入输出机箱包括第一可插拔连接器，设备机箱包括第二可插拔连接器，第二可插拔连接器与第一可插拔连接器耦合；设备机箱还包括多个标识组件，标识组件与第二可插拔连接器耦合，标识组件用于管理其耦合的第二可插拔连接器的标识信息，标识信息指示设备机箱的类型和数量；输入输出机箱扫描多个第一可插拔连接器，读取标识组件管理的标识信息，根据标识信息识别设备机箱的类型和数量。该系统通过标识组件管理代表设备机箱类型和数量的标识信息，使得输入输出机箱准确地识别出设备机箱的类型和数量。

Description

服务系统、输入输出机箱、设备机箱以及机箱识别方法
相关申请的交叉引用
本申请要求于2024年7月10日提交中国专利局，申请号为202410921330.8，申请名称为“服务系统、输入输出机箱、设备机箱以及机箱识别方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及计算机技术领域，尤其涉及一种服务系统、输入输出机箱、设备机箱以及机箱识别方法。
背景技术
融合架构将系统解耦为计算资源池、内存资源池、I/O(Input/Output，输入/输出)设备资源池等独立模块，有利于CPU(Central Processing Unit，中央处理器)、内存、GPU(Graphics Processing Unit，图形处理器)、SSD(Solid State Disk或Solid State Drive，固态硬盘)等关键设备的灵活配置与快速升级。在融合架构下，一个机柜内的所有IO资源集中于一个IO Box(输入输出机箱)，终端设备通过CDFP连接器(CDFP连接器，全称为400Gb/s(16X 25Gb/s)Pluggable Transceiver，即16路可插拔连接器)挂载于IO Box之下。通过管理软件可针对设备实际接入情况对IO资源进行分配。但是，这种完全解耦式的多机箱组合设计方案对整系统的ID(Identifier,标识)识别带来了挑战。以SSD资源池为例，在融合架构内SSD资源池是以独立Box的形态存在的，客户实际使用时会依据自身需求选择性的在IO Box下挂载一个、两个或更多个SSD Box。由于这些SSD Box物理结构完全相同，CDFP连接器自身没有多余的管脚(pin)可用于ID识别，即无法识别出两个或更多个SSD Box。
发明内容
为解决上述技术问题或至少部分地解决上述技术问题，本申请实施例提供了一种基于融合架构的服务系统、输入输出机箱、设备机箱以及机箱识别方法。
第一方面，本申请实施例提供了一种服务系统，服务系统包括输入输出机箱和至少一个设备机箱，输入输出机箱包括多个第一可插拔连接器，设备机箱包括多个第二可插拔连接器，至少一个第二可插拔连接器与至少一个第一可插拔连接器耦合；
设备机箱还包括多个标识组件，标识组件与第二可插拔连接器耦合，标识组件用于管理其耦合的第二可插拔连接器的标识信息，标识信息用于指示设备机箱的类型和数量；
输入输出机箱扫描多个第一可插拔连接器，读取各个第一可插拔连接器耦合的第二可插拔连接器下的标识组件管理的标识信息，根据标识信息识别设备机箱的类型和数量。
在本申请的一些实施例中，输入输出机箱响应于读取到标识信息，判断是否存在相同的标识信息；
输入输出机箱响应于确定存在相同的标识信息，确定相同的标识信息对应的目标设备机箱，向至少一个目标设备机箱发送更改命令，更改命令指示至少一个目标设备机箱更改其所包括的标识组件管理的标识信息；
目标设备机箱响应于接收到更改命令，更改其所包括的标识组件管理的标识信息；
输入输出机箱重新扫描多个第一可插拔连接器，以读取更改后的标识信息，根据更改后的标识信息识别相同类型的设备机箱的数量。
在本申请的一些实施例中，标识信息的数据宽度为N位，其中，标识信息的第k位至第m位为类型位，类型位用于指示设备机箱的类型；N为大于1的正整数，1<k<m<N，且k和m为整数；
输入输出机箱根据标识信息的类型位的数值，识别设备机箱的类型。
在本申请的一些实施例中，标识信息的第(m+1)位至第(N-1)位为数量位，数量位用于区分类型相同的设备机箱。
在本申请的一些实施例中，输入输出机箱根据相同标识信息的数量，生成更改命令，更改命令指示更改数量位中指定位的数值。
在本申请的一些实施例中，输入输出机箱响应于确定相同标识信息的数量为2，生成第一更改命令，第一更改命令指示更改数量位中第一指定位的数值；输入输出机箱确定具有相同标识信息的2个目标设备机箱中的第一目标设备机箱和第二目标设备机箱，向第一目标设备机箱发送第一更改命令；
或者，
输入输出机箱响应于确定相同标识信息的数量为3，生成第一更改命令和第二更改命令，第二更改命令指示更改数量位中第二指定位的数值；输入输出机箱确定具有相同标识信息的3个目标设备机箱中的第一目标设备机箱、第二目标设备机箱和第三目标设备机箱，向第一目标设备机箱发送第一更改命令以及向第二目标设备机箱发送第二更改命令；
或者，
输入输出机箱响应于确定相同标识信息的数量为4，生成第一更改命令、第二更改命令和第三更改命令，第三更改命令指示同时更改数量位中第一指定位和第二指定位的数值；输入输出机箱确定具有相同标识信息的4个目标设备机箱中的第一目标设备机箱、第二目标设备机箱、第三目标设备机箱和第四目标设备机箱，向第一目标设备机箱发送第一更改命令、向第二目标设备机箱发送第二更改命令以及向第三目标设备机箱发送第三更改命令。
在本申请的一些实施例中，标识信息的第0位至第(k-1)位为接口位，接口位用于指示第二可插拔连接器的编号。
在本申请的一些实施例中，输入输出机箱还包括识别组件和两线式串行总线扩展组件，识别组件与两线式串行总线扩展组件耦合，两线式串行总线扩展组件分别与识别组件、多个第一可插拔连接器耦合；两线式串行总线扩展组件将识别组件的一路I2C通道扩展为多路I2C通道，并将多路I2C通道与多个第一可插拔连接器耦合；
识别组件扫描其I2C通道，读取各个第一可插拔连接器耦合的第二可插拔连接器下的标识组件管理的标识信息，根据标识信息识别设备机箱的类型和数量。
在本申请的一些实施例中，输入输出机箱还包括存储组件和多路复用器；存储组件与多路复用器耦合，多路复用器与识别组件和输入输出机箱的基板管理控制器耦合；
识别组件在设备机箱的类型识别完成之前，控制多路复用器关闭存储组件与基板管理控制器之间的数据交互链路，打开识别组件与存储组件之间的数据交互链路；识别组件响应于设备机箱的类型识别完成，生成系统互联配置关系，并将系统互联配置关系写入存储组件；
识别组件响应于将系统互联配置关系写入存储组件，控制多路复用器打开存储组件与基板管理控制器之间的数据交互链路，并通知基板管理控制器系统互联配置关系写入完成；
基板管理控制器响应于识别组件的通知，从存储组件获取系统互联配置关系。
在本申请的一些实施例中，标识组件包括第一标识组件和第二标识组件，各个第二可插拔连接器包括输入端口和输出端口，输入端口与第一标识组件耦合，输出端口与第二标识组件耦合；
输入输出机箱扫描多个第一可插拔连接器，读取第二标识组件管理的标识信息；在存在相同标识信息的情况下，确定相同的标识信息对应的目标设备机箱，向至少一个目标设备机箱的第一标识组件发送更改命令，更改命令用于指示第一标识组件更改其对应的第二标识组件管理的标识信息；第一标识组件对应的第二标识组件为耦合到同一个第二可插拔连接器的第二标识组件；
第一标识组件响应于接收到更改命令，更改其对应的第二标识组件管理的标识信息；
输入输出机箱重新扫描多个第一可插拔连接器，以读取更改后的标识信息，根据更改后的标识信息识别相同类型的设备机箱的数量。
在本申请的一些实施例中，第一标识组件的地址为第一固定地址，第二标识组件的地址为第二固定地址。
第二方面，本申请实施例提供了一种输入输出机箱，输入输出机箱与至少一个设备机箱耦合，输入输出机箱包括多个第一可插拔连接器，设备机箱包括多个第二可插拔连接器，至少一个第二可插拔连接器与至少一个第一可插拔连接器耦合；设备机箱还包括多个标识组件，标识组件与第二可插拔连接器耦合，标识组件用于管理其耦合的第二可插拔连接器的标识信息，标识信息用于指示设备机箱的类型和数量；
输入输出机箱扫描多个第一可插拔连接器，读取各个第一可插拔连接器耦合的第二可插拔连接器下的标识组件管理的标识信息，根据标识信息识别设备机箱的类型和数量。
第三方面，本申请实施例提供了一种设备机箱，其设备机箱与输入输出机箱耦合；输入输出机箱包括多个第一可插拔连接器，设备机箱包括多个第二可插拔连接器，至少一个第二可插拔连接器与至少一个第一可插拔连接器耦合；
设备机箱还包括多个标识组件，标识组件与第二可插拔连接器耦合，标识组件用于管理其耦合的第二可插拔连接器的标识信息，标识信息用于指示设备机箱的类型和数量。
第四方面，本申请实施例提供了一种机箱识别方法，其特征在于，方法应用于本申请任一实施例提供的服务系统，服务系统包括输入输出机箱和至少一个设备机箱，输入输出机箱包括多个第一可插拔连接器，设备机箱包括多个第二可插拔连接器和多个标识组件；至少一个第二可插拔连接器与至少一个第一可插拔连接器耦合，标识组件与第二可插拔连接器耦合，
方法包括：
响应于服务系统上电，扫描多个第一可插拔连接器，读取各个第一可插拔连接器耦合的第二可插拔连接器下的标识组件管理的标识信息，根据标识信息识别设备机箱的类型和数量。
第五方面，本申请实施例提供了一种计算机程序产品，包括计算机程序，其特征在于，计算机程序被处理器执行时实现本申请实施例的机箱识别方法。
第六方面，本申请实施例提供了一种电子设备，包括处理器、通信接口、存储器和通信总线，其中，处理器，通信接口，存储器通过通信总线完成相互间的通信；存储器，用于存放计算机程序；处理器，用于执行存储器上所存放的程序时，实现本申请实施例的机箱识别方法。
第七方面，本申请实施例提供了一种计算机非易失性存储介质，其上存储有计算机程序，计算机程序被处理器执行时实现本申请实施例的机箱识别方法。
本申请的实施例提供的技术方案至少带来以下有益效果：
本申请实施例的服务系统，通过标识组件管理代表设备机箱类型和数量的标识信息。输入输出机箱扫描其CDFP接口，读取设备机箱内标识组件所管理的标识信息，根据该标识信息识别设备机箱的类型和数量，使得输入输出机箱准确的识别出所耦合的设备机箱的类型和数量，进而使得数据指令能够精准发送到期望的设备机箱。若输入输出机箱读取的标识信息中存在相同的标识信息，则说明存在相同的设备机箱，此时输入输出机箱需要区分该相同的设备机箱，输入输出机箱向相同的设备机箱发送更改命令，以更改某个设备机箱的标识信息的数量位。输入输出机箱根据更改后的标识信息的数量位，区分相同的设备机箱。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍。
图1示出了本申请实施例提供的基于融合架构的服务系统的结构示意图；
图2示出了本申请实施例提供的基于融合架构的服务系统中输入输出机箱的结构示意图；
图3示出了本申请另一实施例提供的基于融合架构的服务系统中输入输出机箱的结构示意图；
图4示出了本申请实施例提供的基于融合架构的服务系统中设备机箱的结构示意图；
图5A示出了本申请一实施例提供的输入输出机箱与GPU机箱的连接关系示意图；
图5B示出了本申请另一实施例提供的输入输出机箱与GPU机箱的连接关系示意图；
图6示出了GPUBox的全部CDFP接口耦合的标识组件的标识信息的示意图；
图7A示出了本申请又一实施例提供的基于融合架构的服务系统的结构示意图；
图7B示出了本申请实施例提供的GPU Box 0的结构示意图；
图7C示出了本申请实施例提供的GPU Box 1的结构示意图；
图8示出了本申请实施例提供的机箱识别方法的流程示意图；
图9示出了本申请实施例提供的电子设备的结构示意图。
具体实施方式
以下结合附图对本申请的示范性实施例做出说明，其中包括本申请实施例的各种细节以助于理解，应当将它们认为仅仅是示范性的。因此，本领域普通技术人员应当认识到，可以对这里描述的实施例做出各种改变和修改，而不会背离本申请的范围和精神。
图1示出了本申请实施例提供的基于融合架构的服务系统的结构示意图。如图1所示，该基于融合架构的服务系统100包括输入输出机箱(简称IO机箱，IO Box)101和设备机箱(Device Box)102。设备机箱(Device Box)102例如可以包括但不限于GPU(Graphics Processing Unit，图形处理器)Box、SSD(Solid State Disk或Solid State Drive，固态硬盘)Box、Memory(内存)Box等。
其中，输入输出机箱101包括多个第一可插拔连接器103(CDFP连接器，全称为400Gb/s(16X 25Gb/s)Pluggable Transceiver，即16路可插拔连接器，以下简称第一CDFP接口)。设备机箱102包括多个第二可插拔连接器104(以下简称第二CDFP接口)。第一CDFP接口103与第二CDFP接口104耦合。通过第一CDFP接口103和第二CDFP接口104，将设备机箱102耦合到IO机箱101。在本申请的一些实施例中，耦合到IO机箱上的设备机箱可以是一个，也可以是多个。进一步地，耦合到IO机箱上的多个设备机箱的类型可以是相同的如2个GPU Box，也可以是不相同的例如2个GPU Box和1个SSD Box。
设备机箱102还包括多个标识组件105。标识组件105与第二CDFP接口104耦合。在本申请的一些实施例中，标识组件105的数量与第二CDFP接口104的数量相同，标识组件105与第二CDFP接口104一一对应。标识组件105用于管理其耦合的第二CDFP接口的标识信息，该标识信息用于指示设备机箱的类型和数量。不同类型的设备机箱对应的标识信息不同。在本申请的一些实施例中，标识组件可以是将I2C信号转换为IO信号的芯片，具有可编程的GPIO(General-Purpose Input/Output，通用型输入/输出)引脚，通过控制GPIO引脚输出的高低电平来管理标识信息。I2C(Inter-Integrated Circuit)是一种多主机、两线制、低速串行通信总线，其所传输的数据简称为I2C信号。在本申请的一些实施例中，标识信息的数据宽度为N位，其中，标识信息的第k位至第m位为类型位，该类型位用于指示设备机箱的类型。IO机箱可以根据标识信息中类型位的数值，识别设备机箱的类型。标识信息的第(m+1)位至第(N-1)位为数量位，该数量位用于区分类型相同的设备机箱。IO机箱可以根据标识信息中数量位的数值，区别相同的设备机箱。标识信息的第0位至第(k-1)位为接口位，该接口位用于指示第二CDFP接口的编号。N为大于1的正整数，1<k<m<N，且k和m为整数。作为本申请一些实施例中的示例，标识组件为PCA9554芯片，PCA9554芯片具有8个可编程的GPIO引脚，其管理的标识信息为8bit(比特)，第4位至第5位为类型位，用于区分不同类型的机箱。例如标识信息的第4位至第5位为10，则该标识信息表示设备机箱的类型为GPU Box。标识信息的第4位至第5位为01，则该标识信息表示设备机箱的类型为SSD Box。标识信息的第4位至第5位为11，则该标识信息表示设备机箱的类型为Memory Box。第6位至第7位为数量位，用于区分相同的设备机箱。第6位至第7位的数值包括4种情况，分别为：00、01、10、11。默认情况下，第6位至第7位的数值为00。通过第6位至第7位的数值可以区分出4个相同的设备机箱。第0位-第3位为接口位，用于区分设备机箱中的CDFP接口。
IO机箱101扫描第一CDFP接口103，读取各个第一CDFP接口103耦合的第二CDFP接口104下的标识组件105管理的标识信息，根据标识信息识别设备机箱102的类型。
在本申请的一些实施例中，可能有多个类型相同的设备机箱耦合到IO机箱。在此情况下，IO机箱读取到的标识信息中存在相同的标识信息。IO机箱响应于确定存在相同的标识信息，确定相同的标识信息对应的目标设备机箱，向至少一个目标设备机箱发送更改命令，更改命令指示目标设备机箱更改其所包括的标识组件管理的标识信息。例如该更改命令指示目标设备机箱更改标识信息中数量位的数值。目标设备机箱响应于接收到更改命令，更改其所包括的标识组件管理的标识信息，例如更改标识信息中数量位的数值。IO机箱重新扫描多个第一CDFP接口，以读取更改后的标识信息，根据更改后的标识信息区分相同类型的设备机箱。
本申请实施例的服务系统，通过标识组件管理代表设备机箱类型和数量的标识信息，IO机箱扫描其CDFP接口，读取设备机箱内标识组件所管理的标识信息，根据该标识信息识别设备机箱的类型和数量，使得IO机箱准确的识别出所耦合的设备机箱的类型和数量，进而使得数据指令能够精准发送到期望的设备机箱。若IO机箱读取的标识信息中存在相同的标识信息，则说明存在相同的设备机箱，此时IO机箱需要区分该相同的设备机箱，IO机箱向相同的设备机箱发送更改命令，以更改某个设备机箱的标识信息的数量位。IO机箱根据更改后的标识信息的数量位，区分相同的设备机箱。
在本申请的一些实施例中，IO机箱根据相同标识信息的数量，生成更改命令，该更改命令指示更改数量位中指定位的数值。其中，相同标识信息的数量表示了服务系统中相同设备机箱的数量。在不同数量的相同设备机箱的情况下，需要更改不同数量的设备机箱的标识信息。例如，具有2个相同设备机箱的情况下，需要改变一个设备机箱的标识信息，IO机箱可以生成一个更改命令以改变其中一个设备机箱的标识信息。因此，IO机箱响应于确定相同标识信息的数量为2，生成第一更改命令，第一更改命令指示更改标识信息的数量位中第一指定位的数值(例如默认情况下标识信息中第6位和第7位的默认值均为0，第一更改命令指示将标识信息中第6位的数值改为1)；IO机箱确定具有相同标识信息的2个目标设备机箱中的第一目标设备机箱和第二目标设备机箱，向第一目标设备机箱发送第一更改命令。其中，第一目标设备机箱可以是2个目标设备机箱中任意一个目标设备机箱，也可以根据指定的策略确定第一目标设备机箱和第二目标设备机箱，例如根据第二CDFP接口的编号顺序(可以根据标识信息的接口位的数值确定CDFP接口的编号顺序)来确定第一目标设备机箱和第二目标设备机箱，将靠后的第二CDFP接口对应的目标设备机箱作为第一目标设备机箱。
在本申请的一些实施例中，在服务系统具有3个相同设备机箱的情况下，需要改变其中两个设备机箱的标识信息。IO机箱需要生成两个不同的更改命令以更改其中两个设备机箱的标识信息，从而使得该3个相同的设备机箱具有3个不同的标识信息。因此，IO机箱响应于确定相同标识信息的数量为3，生成第一更改命令和第二更改命令。第一更改命令指示更改标识信息的数量位中第一指定位的数值(例如默认情况下标识信息中第6位和第7位的默认值均为0，第一更改命令指示将标识信息中第6位的数值改为1)，第二更改命令指示更改标识信息的数量位中第二指定位的数值(例如默认情况下标识信息中第6位和第7位的默认值均为0，第二更改命令指示将标识信息中第7位的数值改为1)。IO机箱确定具有相同标识信息的3个目标设备机箱中的第一目标设备机箱、第二目标设备机箱和第三目标设备机箱，向第一目标设备机箱发送第一更改命令以及向第二目标设备机箱发送第二更改命令。在本申请的一些实施例中，IO机箱可以根据第二CDFP接口的编号顺序来确定第一目标设备机箱、第二目标设备机箱和第三目标设备机箱，将最后的第二CDFP接口耦合的目标设备机箱作为第一目标设备机箱，将最前的第二CDFP接口耦合的目标设备机箱作为第三目标设备机箱，中间的第二CDFP接口耦合的目标设备机箱作为第二目标设备机箱。
又例如，在服务系统具有4个相同设备机箱的情况下，需要改变三个设备机箱的标识信息。IO机箱需要生成三个不同的更改命令以更改两个设备机箱的标识信息，从而使得该4个相同的设备机箱具有4个不同的标识信息。因此，IO机箱响应于确定相同标识信息的数量为4，生成第一更改命令、第二更改命令和第三更改命令。第一更改命令指示更改标识信息的数量位中第一指定位的数值(例如默认情况下标识信息中第6位和第7位的默认值均为0，第一更改命令指示将标识信息中第6位的数值改为1)，第二更改命令指示更改标识信息的数量位中第二指定位的数值(例如默认情况下标识信息中第6位和第7位的默认值均为0，第二更改命令指示将标识信息中第7位的数值改为1)，第三更改命令指示同时更改标识信息的数量位中第一指定位和第二指定位的数值(例如默认情况下标识信息中第6位和第7位的默认值均为0，第三更改命令指示将标识信息中第6位和第7位的数值均改为1)。IO机箱确定具有相同标识信息的4个目标设备机箱中的第一目标设备机箱、第二目标设备机箱、第三目标设备机箱和第四目标设备机箱，向第一目标设备机箱发送第一更改命令、向第二目标设备机箱发送第二更改命令以及向第三目标设备机箱发送第三更改命令。
图2示出了本申请实施例提供的服务系统中IO机箱的结构示意图。如图2所示，IO机箱200包括第一可插拔连接器201(以下简称第一CDFP接口)、识别组件202和两线式串行总线扩展组件203(以下简称I2C扩展组件)。
识别组件202与I2C扩展组件203耦合。I2C扩展组件203分别与识别组件202、多个第一CDFP接口201耦合。I2C扩展组件203将识别组件202的一路I2C通道扩展为多路I2C通道，并将多路I2C通道与多个第一CDFP接口201耦合。第一CDFP接口201与设备机箱的第二CDFP接口耦合(参考图1)。
其中，识别组件202作为IO机箱中ID识别进程的任务发起者，扫描其I2C通道，读取各个标识组件中所管理的标识信息，根据标识信息识别设备机箱的类型。作为本申请一些实施例中的示例，识别组件202为CPLD。CPLD(Complex Programmable Logic Device)是Complex PLD的简称，复杂可编程逻辑器件，是一种用户根据各自需要而自行构造逻辑功能的数字集成电路。
I2C扩展组件203将CPLD的1路I2C通道拓展为多路I2C通道，并将多路I2C通道分别连接至不同的第一CDFP接口。为保证每一个第一CDFP接口均对应一路特定的I2C通道，整个IO机箱内需多个I2C扩展组件，进而确保了设备机箱在安装时，无论其插接在IO机箱的哪个第一CDFP接口下、无论是否按顺序插接，均可通过某一路I2C通道被IO机箱的CPLD有效识别。
在本实施例中，通过识别组件识别耦合到IO机箱上的设备机箱的类型和数量，不需要IO机箱内的基板管理控制器进行识别，提高了服务系统的识别速度，另外基板管理控制器不参与识别设备机箱的过程，能够避免基板管理控制器宕机情况下的系统配置识别异常问题。
图3示出了本申请实施例提供的服务系统的IO机箱的结构示意图。如图3所示，在图2所示的IO机箱的基础上，该IO机箱还包括存储组件204、多路复用器205和基板管理控制器206。存储组件204与多路复用器205耦合，多路复用器205与识别组件202和IO机箱的基板管理控制器206耦合。
识别组件202在设备机箱的类型识别完成之前，控制多路复用器205关闭存储组件204与基板管理控制器206之间的数据交互链路，打开识别组件202与存储组件204之间的数据交互链路。识别组件204响应于设备机箱的类型识别完成，生成系统互联配置关系，并将系统互联配置关系写入存储组件204。该系统互联配置关系指示了IO机箱耦合的设备机箱的类型、数量以及第一CDFP接口与第二CDFP接口之间的耦合关系。
识别组件202响应于将系统互联配置关系写入存储组件，控制多路复用器205打开存储组件204与基板管理控制器206之间的数据交互链路，并通知基板管理控制器206系统互联配置关系写入完成。例如，识别组件控制MUX_SEL信号打开存储组件与基板管理控制器之间的数据交互链路，通过ID_READY信号通知基板管理控制器获取存储组件的系统互联配置关系。
基板管理控制器206响应于识别组件202的通知，从存储组件204获取系统互联配置关系。
在本申请实施例中，在机箱设备识别完成之前，通过多路复用器断开基板管理控制器与存储组件之间的数据交互链路，使得基板管理控制器无法在机箱设备识别完成之前读取系统互联配置关系。在机箱设备识别完成之后，通过多路复用器打开基板管理控制器与存储组件之间的数据交互链路，使得基板管理控制器能够读取完整的系统互联配置关系，保证了基板管理控制器读取的系统互联配置关系的完整性以及准确性。
图4示出了本申请实施例的服务系统的设备机箱的结构示意图。如图4所示，设备机箱的各个第二CDFP接口包括输入端口和输出端口，输入端口与第一标识组件耦合，输出端口与第二标识组件耦合。第二标识组件管理代表设备机箱类型和数量的标识信息，第一标识组件用于配置第二标识组件管理的标识信息。
IO机箱扫描多个第一CDFP接口，读取第二标识组件管理的标识信息；在存在相同标识信息的情况下，IO机箱确定相同的标识信息对应的目标设备机箱，向至少一个目标设备机箱的第一标识组件发送更改命令，更改命令用于指示第一标识组件更改其对应的第二标识组件管理的标识信息；第一标识组件对应的第二标识组件为耦合到同一个第二CDFP接口的第二标识组件。
第一标识组件响应于接收到更改命令，更改其对应的第二标识组件管理的标识信息。
IO机箱重新扫描多个第一CDFP接口，读取第二标识组件管理的标识信息，根据标识信息识别设备机箱的类型。
在本申请的一些实施例中，第一标识组件的地址为第一固定地址，第二标识组件的地址为第二固定地址。将第一标识组件和第二标识组件分别设置为固定地址，可以保证设备机箱耦合到IO机箱任一CDFP接口时，IO机箱都可以读取到标识信息。
为便于理解本申请实施例的基于融合架构的服务系统，下面结合图5A、图5B、图6图7和图8所示的例子进行说明。图5A和图5B分别示出了GPU Box与IO Box的一种耦合关系示意图。图6示出了GPU Box的全部CDFP接口耦合的标识组件所管理的标识信息的示意图。图7示出了一种基于融合架构的服务系统的示意图。图8示出了本申请实施例提供的机箱识别方法的流程示意图。
在本实施例中，IO Box作为整个服务系统的IO资源管控节点，其具体功能为：通过IO Box内包含的8个PCIe Switch芯片(高速串行计算机扩展组件)将来自多个不同CPU的PCIe资源(高速串行计算机扩展资源)进行拓展、组网、分配。其中，PCIe Switch芯片用于提供扩展或聚合能力，并允许更多的设备连接到一个PCle端口。PCIe(Peripheral Component Interconnect Express)是一种高速串行计算机扩展总线标准，用于连接外部设备。整个IO Box最终可对外提供40个CDFP接口，每个CDFP接口包含一组PCIe 5.0x16的高速IO信号。
GPU Box是专门用于承载GPU标卡的容器。每个GPU Box可满载16张PCIe标卡形态GPU。GPU Box对外提供16个CDFP接口，通过该16个CDFP接口耦合至IO Box。图5A和图5B示出了GPU Box与IO Box的两种耦合关系的示意图。图5A中，IO Box的CDFP0-0接口、CDFP0-1接口、CDFP0-2接口、CDFP0-3接口分别与GPU Box-1的CDFP0接口、CDFP1接口、CDFP2接口、CDFP3接口耦合，IO Box的CDFP4-0接口、CDFP4-1接口、CDFP4-2接口、CDFP6-0接口分别与GPU Box-0的CDFP0接口、CDFP1接口、CDFP2接口、CDFP8接口耦合。图5B中，IO Box的CDFP0-2接口、CDFP0-3接口、CDFP0-4接口、CDFP2-2接口分别与GPU Box-1的CDFP0接口、CDFP1接口、CDFP2接口、CDFP8接口耦合，IO Box的CDFP4-2接口、CDFP4-3接口、CDFP4-4接口、CDFP5-0接口分别与GPU Box-0的CDFP0接口、CDFP1接口、CDFP2接口、CDFP8接口耦合。如图5A和图5B所示，GPU Box的16个CDFP接口可对接IO Box的40个CDFP接口中的任意16个，无需指定固定的插接顺序。SSD Box是专门用于承载NVMe U.2硬盘的容器。每个SSD Box可满载24块盘，SSD Box对外提供6个CDFP接口，通过该6个CDFP接口耦合至IO Box。6个CDFP接口可对接IO Box的40个CDFP接口中的任意6个，无需指定固定的插接顺序。Memory Box是专门用于承载内存的容器，其内通过CXL Controllor芯片(CXL控制器，其中，CXL(Compute Express Link)是一种高速串行协议，它允许在计算机系统内部的不同组件之间进行快速、可靠的数据传输)将CXL信号(复用PCIe协议的物理层)转为内存信号，进而实现内存共享。每个Memory Box对外提供8个CDFP接口，可对接IO Box的40个CDFP接口中的任意8个，无需指定固定的插接顺序。
在本实施例的服务系统中，IO Box对外提供40个CDFP接口，最多可以耦合4个GPU Box。4个GPU Box可以用2位数量位进行区分。设备机箱可以包括GPU Box、Memory Box、SSD Box，可以用2位类型位进行区分。GPU Box包括的CDFP接口最多(16个CDFP接口)，可以用4位接口位进行区分。因此，标识信息可以为8位。本申请一些实施例中，设备机箱内的标识组件可以选择PCA9554芯片。例如，PCA9554的bit7和bit6是作为数量位(即Box Number)，用于相同Box的区分，这两位默认数值为00，通过这两位的数值，可区分出4台相同的Box。bit5和bit4是类型位，用于区分不同类型的Box，进而使得IO Box在一次扫描后即可识别出设备机箱的类型。在本实施例中，bit5和bit4为10，表明设备机箱的类型为GPU Box。bit5和bit4为01，表明设备机箱的类型为SSD Box。bit5和bit4为11，表明设备机箱的类型为Memory Box。bit3、bit2、bit1和bit0是接口位(即CDFP Number位)，用于区分出每个CDFP接口。作为示例，GPU Box的标识信息如下表1所示，SSD Box的标识信息如下表2所示，Memory Box的标识信息如下表3所示。
表1：
表2：
表3：
GPUBox的全部CDFP接口耦合的标识组件所管理的标识信息如图6所示，通过标识信息的第0位-第3位的数值区分不同的CDFP接口。图6中，“**100000”表示GPU Box的第0个CDFP接口CDFP-0，“**100001”表示GPU Box的第1个CDFP接口CDFP-1，“**100010”表示GPU Box的第2个CDFP接口CDFP-2。图6中其他标识信息的含义类似，为避免重复，在此不再赘述。
图7A示出了两个GPU Box耦合到IO Box的服务系统的结构示意图，图7B示出了本申请实施例提供的GPU Box 0的结构示意图，图7C示出了本申请实施例提供的GPU Box 1的结构示意图。参考图7A，以2个GPU Box为例，对多个相同设备机箱场景下的机箱识别原理进行说明，此方案亦适用于其他类型设备机箱。
在图7A中，IO Box中的CPLD为识别组件，其作为机箱识别进程的任务发起者。PCA9548为两线式串行总线扩展组件。通过PCA9548将CPLD的1路I2C拓展为多路，分别连接至不同的CDFP接口。为保证每一个CDFP接口均对应一路特定的I2C通道，整个IO Box内需多个PCA9548，进而确保了设备机箱在安装时，无论其插接在IO Box的哪个CDFP接口下、无论是否按顺序插接，均可通过某一路I2C通道被IO Box的CPLD有效识别。
在图7A中，IO Box内的CPLD与基板管理控制器(BMC)之间引入了存储组件(FRU)及多路复用器(MUX)。服务系统上电后，IO Box内CPLD负责整个机箱识别过程。在识别未完成前，多路复用器始终将FRU的I2C切给CPLD；在识别完成后，CPLD首先将完整的系统互联配置关系存入FRU，然后控制MUX_SEL信号将I2C切给基板管理控制器，最后通过ID_READY信号通知基板管理控制器可以获取存储组件的系统互联配置关系。
在图7B和图7C中，每个GPU Box的CDFP接口包括输入端口和输出端口，输入端口和输出端口分别耦合1个PCA9554，PCA9554作为标识组件管理其耦合的CDFP接口的标识信息。通过2个PCA9554与其内的CPLD搭配实现标识信息的配置和识别，此2个PCA9554挂接于CDFP对应的I2C通道下。参考图7，CDFP接口的输出端口耦合PCA9554(1-0)，输入端口耦合PCA9554(1-A)。PCA9554(1-0)用于管理标识信息，整个GPU Box内此类PCA9554的I2C地址均为固定值：0100001X。PCA9554(1-A)用于对PCA9554(1-0)管理的标识信息进行配置，例如对PCA9554(1-0)的bit7和bit6进行配置，整个GPU Box内此类PCA9554的I2C地址均为固定值：0100010X。
服务系统上电后，IO Box内CPLD依次扫描其下的多颗PCA9548下的各个I2C通道。其CDFP接口若已与GPU Box的CDFP接口互联，CPLD则可以在此I2C通道下扫描到一颗地址为0100001X的PCA9554。依次扫描完全部40个I2C通道后，便可建立一个IO CDFP<-->GPU CDFP映射关系，并存入FRU内。这样就可以确认IO BOX的哪些端口接了GPU BOX内的哪个GPU了。如果IO Box连接的都是不同类型的设备机箱，不存在类型相同的设备机箱，则根据标识信息中的类型位即可完成机箱识别过程。
当服务系统下存在两个GPU Box时，IO Box内CPLD依次扫描完各个I2C通道后发现从某两个通道下均读到了相同的8位标识信息。此时CPLD根据这些相同的标识信息无法判断其耦合的GPU具体属于哪个BOX。因此，IO BOX内CPLD将执行下一步过程：如果从某两个通道下均读到了相同的标识信息，则通过顺序靠后的I2C通道向地址为0100010X的PCA9554发送命令(例如GPU Box1的CDFP2耦合的PCA9554(1-A))，使其IO[6]输出1至GPU Box内的CPLD。GPU Box1内的CPLD检测到IO电平变化后，需将所有对应PCA9554(1-1)、PCA9554(1-2)的IO[6]全部拉高，即将PCA9554(1-1)、PCA9554(1-2)管理的标识信息中的bit6赋值1。此后，IO BOX内CPLD再次依次扫描40个I2C通道，获得更改后的标识信息，其中一组标识信息的数量位(bit7:bit6)为00，另一组标识信息的数量位(bit7:bit6)为01，从而区分出两个相同的GPU BOX了。IO Box便可建立系统配置管理关系，即IO CDFP<-->GPU Box 0CDFP、GPU Box 1CDFP映射关系。再次将信息存入存储组件内，并置位MUX_SEL、ID_READY信号，待基板管理控制器加载完成后从存储组件获取系统配置关联关系。
同理，当存在三个或四个相同机箱设备时，IO Box的识别过程类似，为避免重复，在此不再赘述。
图8示出了本申请实施例提供的机箱识别方法的流程示意图。参考图7A所示的服务系统，该机箱识别方法包括：
1)将至少一个GPU Box与IO Box的CDFP接口进行耦合，服务系统上电，IO Box内的CPLD开始进行设备机箱的识别(在本申请的一些实施例中，IO Box内的CPLD延时5S后开始识别设备机箱)。
2)IO Box内的识别组件CPLD扫描所有CDFP接口所在I2C通道，识别出所有GPU Box内地址为：0100001X的标识组件PCA9554(1-0)和PCA9554(1-1)。在识别到的PCA9554(1-0)和PCA9554(1-1)中读取其标识信息并汇总至FRU。
3)IO Box内的识别组件CPLD判断重复的标识信息的数量。
4)如果没有重复的标识信息，则表明当前IO Box CDFP–GPU BOX CDFP映射关系(即系统互联配置关系)是唯一的。
5)IO Box内的识别组件CPLD控制MUX_SEL信号将I2C切给BMC,然后通过ID_READY信号通知BMC。BMC响应于接收到通知，从FRU获取系统互联配置关系。
6)如果存在重复的标识信息，则表明当前IO Box CDFP–GPU BOX CDFP映射关系不唯一。此时需基于重复的标识信息的数量进行下一步操作。
7)若当前重复的标识信息的数量为1(即存在两个相同的标识信息)，则：任选一组存在重复的标识信息并基于I2C通道的前后进行排序，通过排序第2的通道向地址为0100010X的PCA9554发送命令，使其IO[6]输出1至GPU Box内CPLD，CPLD检测到地址为0100010X的PCA9554的IO电平变化后，将所有对应PCA9554(1-0)和PCA9554(1-1)IO[6]的信号全部拉高，即将对应PCA9554(1-0)和PCA9554(1-1)的标识信息中第6位设置为1。
8)IO BOX内CPLD再次依次扫描40个I2C通道，重新建立映射表后，再次执行步骤5)的操作。
9)若当前重复ID的数量为2(即存在三个相同的标识信息)，通过排序第2的通道向地址为0100010X的PCA9554发送命令，使其IO[6]输出1至GPU Box内CPLD，CPLD检测到地址为0100010X的PCA9554的IO电平变化后，将所有对应PCA9554(1-0)和PCA9554(1-1)IO[6]的信号全部拉高，即将对应PCA9554(1-0)和PCA9554(1-1)的标识信息中第6位设置为1，以及通过排序第3的通道向地址为0100010X的PCA9554发送命令，使其IO[7]输出1至GPU Box内CPLD，CPLD检测到地址为0100010X的PCA9554的IO电平变化后，将所有对应PCA9554(1-0)和PCA9554(1-1)IO[7]的信号全部拉高，即将对应PCA9554(1-0)和PCA9554(1-1)的标识信息中第7位设置为1。然后重复步骤8)。
10)若当前重复ID的数量为3(即存在四个相同的标识信息)，通过排序第2的通道向地址为0100010X的PCA9554发送命令，使其IO[6]输出1至GPU Box内CPLD，CPLD检测到地址为0100010X的PCA9554的IO电平变化后，将所有对应PCA9554(1-0)和PCA9554(1-1)IO[6]的信号全部拉高，即将对应PCA9554(1-0)和PCA9554(1-1)的标识信息中第6位设置为1，通过排序第3的通道向地址为0100010X的PCA9554发送命令，使其IO[7]输出1至GPU Box内CPLD，CPLD检测到地址为0100010X的PCA9554的IO电平变化后，将所有对应PCA9554(1-0)和PCA9554(1-1)IO[7]的信号全部拉高，即将对应PCA9554(1-0)和PCA9554(1-1)的标识信息中第7位设置为1，以及通过排序第4的通道向地址为0100010X的PCA9554发送命令，使其IO[6]和IO[7]输出1至GPU Box内CPLD，CPLD检测到地址为0100010X的PCA9554的IO电平变化后，将所有对应PCA9554(1-0)和PCA9554(1-1)IO[6]和IO[7]的信号全部拉高，即将对应PCA9554(1-0)和PCA9554(1-1)的标识信息中第6位和第7位设置为1。然后重复步骤8)。
本申请实施例提供的基于融合状态的服务系统，基于识别组件CPLD、标识组件PCA9554的方案设计了全新的硬件拓扑、标识信息定义方式、识别流程，解决了对物理结构完全相同的多个设备机箱的识别问题，使得数据指令能够精准发送到目标设备机箱，可以更快捷的完成多个相同设备机箱的判别并给出系统互联配置关系；而且，基板管理控制器只作为使用者读取系统互联配置关系，不参与识别过程，减轻基板管理控制器的负担，提高了系统识别速度，避免了基板管理控制器宕机情况下的系统配置识别异常问题。
图9示出了本申请实施例的电子设备的结构示意图。如图9所示，该电子设备包括：
处理器901、通信接口902、存储器903和通信总线904，其中，处理器901，通信接口902，存储器903通过通信总线904完成相互间的通信，
存储器903，用于存放计算机程序；
处理器901，用于执行存储器903上所存放的程序时，实现本申请实施例提供的机箱识别方法。
上述终端提到的通信总线可以是外设部件互连标准(Peripheral Component Interconnect，简称PCI)总线或扩展工业标准结构(Extended Industry Standard Architecture，简称EISA)总线等。该通信总线可以分为地址总线、数据总线、控制总线等。为便于表示，图中仅用一条粗线表示，但并不表示仅有一根总线或一种类型的总线。
通信接口用于上述终端与其他设备之间的通信。
存储器可以包括随机存取存储器(Random Access Memory，简称RAM)，也可以包括非易失性存储器(non-volatile memory)，例如至少一个磁盘存储器。在本申请的一些实施例中，存储器还可以是至少一个位于远离前述处理器的存储装置。
上述的处理器可以是通用处理器，包括中央处理器(Central Processing Unit，简称CPU)、网络处理器(Network Processor，简称NP)等；还可以是数字信号处理器(Digital Signal Processing，简称DSP)、专用集成电路(Application Specific Integrated Circuit，简称ASIC)、现场可编程门阵列(Field－Programmable Gate Array，简称FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件。
在本申请提供的又一实施例中，还提供了一种计算机非易失性存储介质，该计算机非易失性存储介质中存储有指令，当其在计算机上运行时，使得计算机执行上述实施例中任一的方法。
在本申请提供的又一实施例中，还提供了一种包含指令的计算机程序产品，当其在计算机上运行时，使得计算机执行上述实施例中任一的方法。
在上述实施例中，可以全部或部分地通过软件、硬件、固件或者其任意组合来实现。当使用软件实现时，可以全部或部分地以计算机程序产品的形式实现。计算机程序产品包括一个或多个计算机指令。在计算机上加载和执行计算机程序指令时，全部或部分地产生按照本申请实施例的流程或功能。计算机可以是通用计算机、专用计算机、计算机网络、或者其他可编程装置。计算机指令可以存储在计算机非易失性存储介质中，或者从一个计算机非易失性存储介质向另一个计算机非易失性存储介质传输，例如，计算机指令可以从一个网站站点、计算机、服务器或数据中心通过有线(例如同轴电缆、光纤、数字用户线(DSL))或无线(例如红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。计算机非易失性存储介质可以是计算机能够存取的任何可用介质或者是包含一个或多个可用介质集成的服务器、数据中心等数据存储设备。可用介质可以是磁性介质，(例如，软盘、硬盘、磁带)、光介质(例如，DVD)、或者半导体介质(例如固态硬盘Solid State Disk(SSD))等。
需要说明的是，在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括要素的过程、方法、物品或者设备中还存在另外的相同要素。
以上仅为本申请的较佳实施例而已，并非用于限定本申请的保护范围。凡在本申请的精神和原则之内所作的任何修改、等同替换、改进等，均包含在本申请的保护范围内。

Claims (20)

  1. 一种服务系统，其特征在于，所述服务系统包括输入输出机箱和至少一个设备机箱，所述输入输出机箱包括多个第一可插拔连接器，所述设备机箱包括多个第二可插拔连接器，至少一个所述第二可插拔连接器与至少一个所述第一可插拔连接器耦合；
    所述设备机箱还包括多个标识组件，所述标识组件与所述第二可插拔连接器耦合，所述标识组件被配置为管理其耦合的第二可插拔连接器的标识信息，所述标识信息被配置为指示所述设备机箱的类型和数量；
    所述输入输出机箱扫描所述多个第一可插拔连接器，读取各个所述第一可插拔连接器耦合的所述第二可插拔连接器下的所述标识组件管理的标识信息，根据所述标识信息识别所述设备机箱的类型和数量。
  2. 根据权利要求1所述的服务系统，其特征在于，所述输入输出机箱响应于读取到所述标识信息，判断是否存在相同的标识信息；
    所述输入输出机箱响应于确定存在相同的标识信息，确定所述相同的标识信息对应的目标设备机箱，向至少一个所述目标设备机箱发送更改命令，所述更改命令指示至少一个所述目标设备机箱更改其所包括的标识组件管理的标识信息；
    所述目标设备机箱响应于接收到所述更改命令，更改其所包括的标识组件管理的标识信息；
    所述输入输出机箱重新扫描所述多个第一可插拔连接器，以读取更改后的标识信息，根据更改后的标识信息识别相同类型的设备机箱的数量。
  3. 根据权利要求2所述的服务系统，其特征在于，所述标识信息的数据宽度为N位，其中，所述标识信息的第k位至第m位为类型位，所述类型位被配置为指示所述设备机箱的类型；所述N为大于1的正整数，1<k<m<N，且所述k和所述m为整数；
    所述输入输出机箱根据所述标识信息的所述类型位的数值，识别所述设备机箱的类型。
  4. 根据权利要求3所述的服务系统，其特征在于，所述标识信息的第(m+1)位至第(N-1)位为数量位，所述数量位被配置为区分类型相同的设备机箱。
  5. 根据权利要求4所述的服务系统，其特征在于，所述输入输出机箱根据相同标识信息的数量，生成更改命令，所述更改命令指示更改所述数量位中指定位的数值。
  6. 根据权利要求5所述的服务系统，其特征在于，所述输入输出机箱响应于确定相同标识信息的数量为2，生成第一更改命令，所述第一更改命令指示更改所述数量位中第一指定位的数值；所述输入输出机箱确定具有所述相同标识信息的2个目标设备机箱中的第一目标设备机箱和第二目标设备机箱，向所述第一目标设备机箱发送所述第一更改命令；
    或者，
    所述输入输出机箱响应于确定相同标识信息的数量为3，生成所述第一更改命令和第二更改命令，所述第二更改命令指示更改所述数量位中第二指定位的数值；所述输入输出机箱确定具有所述相同标识信息的3个目标设备机箱中的第一目标设备机箱、第二目标设备机箱和第三目标设备机箱，向所述第一目标设备机箱发送所述第一更改命令以及向所述第二目标设备机箱发送所述第二更改命令；
    或者，
    所述输入输出机箱响应于确定相同标识信息的数量为4，生成所述第一更改命令、所述第二更改命令和第三更改命令，所述第三更改命令指示同时更改所述数量位中所述第一指定位和第二指定位的数值；所述输入输出机箱确定具有所述相同标识信息的4个目标设备机箱中的第一目标设备机箱、第二目标设备机箱、第三目标设备机箱和第四目标设备机箱，向所述第一目标设备机箱发送所述第一更改命令、向所述第二目标设备机箱发送所述第二更改命令以及向所述第三目标设备机箱发送所述第三更改命令。
  7. 根据权利要求4所述的服务系统，其特征在于，所述标识信息的第0位至第(k-1)位为接口位，所述接口位被配置为指示所述第二可插拔连接器的编号。
  8. 根据权利要求1所述的服务系统，其特征在于，所述输入输出机箱还包括识别组件和两线式串行总线扩展组件，所述识别组件与所述两线式串行总线扩展组件耦合，所述两线式串行总线扩展组件分别与所述识别组件、所述多个第一可插拔连接器耦合；所述两线式串行总线扩展组件将所述识别组件的一路I2C通道扩展为多路I2C通道，并将所述多路I2C通道与所述多个第一可插拔连接器耦合；
    所述识别组件扫描其I2C通道，读取各个所述第一可插拔连接器耦合的所述第二可插拔连接器下的所述标识组件管理的标识信息，根据所述标识信息识别所述设备机箱的类型和数量。
  9. 根据权利要求8所述的服务系统，其特征在于，所述输入输出机箱还包括存储组件和多路复用器；所述存储组件与所述多路复用器耦合，所述多路复用器与所述识别组件和所述输入输出机箱的基板管理控制器耦合；
    所述识别组件在所述设备机箱的类型识别完成之前，控制所述多路复用器关闭所述存储组件与所述基板管理控制器之间的数据交互链路，打开所述识别组件与所述存储组件之间的数据交互链路；所述识别组件响应于所述设备机箱的类型识别完成，生成系统互联配置关系，并将所述系统互联配置关系写入所述存储组件；
    所述识别组件响应于将所述系统互联配置关系写入所述存储组件，控制所述多路复用器打开所述存储组件与所述基板管理控制器之间的数据交互链路，并通知所述基板管理控制器所述系统互联配置关系写入完成；
    所述基板管理控制器响应于所述识别组件的通知，从所述存储组件获取所述系统互联配置关系。
  10. 根据权利要求9所述的服务系统，其特征在于，所述系统互联配置关系表示与所述输入输出机箱耦合的所述设备机箱的类型和数量，以及所述第一可插拔连接器与所述第二可插拔连接器之间的耦合关系。
  11. 根据权利要求2-10任一项所述的服务系统，其特征在于，各个所述第二可插拔连接器包括输入端口和输出端口，所述标识组件包括第一标识组件和第二标识组件，所述输入端口与所述第一标识组件耦合，所述输出端口与所述第二标识组件耦合；
    所述输入输出机箱扫描所述多个第一可插拔连接器，读取所述第二标识组件管理的标识信息；在存在相同的标识信息的情况下，确定所述相同的标识信息对应的目标设备机箱，向至少一个所述目标设备机箱的第一标识组件发送更改命令，所述更改命令被配置为指示所述第一标识组件更改其对应的所述第二标识组件管理的标识信息；所述第一标识组件对应的第二标识组件为耦合到同一个第二可插拔连接器的第二标识组件；
    所述第一标识组件响应于接收到所述更改命令，更改其对应的所述第二标识组件管理的标识信息；
    所述输入输出机箱重新扫描所述多个第一可插拔连接器，以读取更改后的标识信息，根据更改后的标识信息识别相同类型的设备机箱的数量。
  12. 根据权利要求11所述的服务系统，其特征在于，所述第一标识组件的地址为第一固定地址，所述第二标识组件的地址为第二固定地址。
  13. 根据权利要求1所述的服务系统，其特征在于，所述标识组件包括引脚，所述标识组件通过所述引脚输出的电平管理标识信息，所述标识组件的数量与所述第二可插拔连接器的数量相同，并且所述标识组件与所述第二可插拔连接器对应。
  14. 根据权利要求1所述的服务系统，其特征在于，所述输入输出机箱包括多个高速串行计算机扩展组件，所述输入输出机箱通过所述高速串行计算机扩展组件对来自多个不同中央处理器的高速串行计算机扩展资源进行拓展、组网和分配。
  15. 一种输入输出机箱，其特征在于，所述输入输出机箱与至少一个设备机箱耦合，所述输入输出机箱包括多个第一可插拔连接器，所述设备机箱包括多个第二可插拔连接器，至少一个所述第二可插拔连接器与至少一个所述第一可插拔连接器耦合；所述设备机箱还包括多个标识组件，所述标识组件与所述第二可插拔连接器耦合，所述标识组件被配置为管理其耦合的第二可插拔连接器的标识信息，所述标识信息被配置为指示所述设备机箱的类型和数量；
    所述输入输出机箱扫描所述多个第一可插拔连接器，读取各个所述第一可插拔连接器耦合的所述第二可插拔连接器下的所述标识组件管理的标识信息，根据所述标识信息识别所述设备机箱的类型和数量。
  16. 一种设备机箱，其特征在于，所述设备机箱与输入输出机箱耦合；所述输入输出机箱包括多个第一可插拔连接器，所述设备机箱包括多个第二可插拔连接器，至少一个所述第二可插拔连接器与至少一个所述第一可插拔连接器耦合；
    所述设备机箱还包括多个标识组件，所述标识组件与所述第二可插拔连接器耦合，所述标识组件被配置为管理其耦合的第二可插拔连接器的标识信息，所述标识信息被配置为指示所述设备机箱的类型和数量。
  17. 一种机箱识别方法，其特征在于，所述方法应被配置为权利要求1-14任一项所述的服务系统，所述服务系统包括输入输出机箱和至少一个设备机箱，所述输入输出机箱包括多个第一可插拔连接器，所述设备机箱包括多个第二可插拔连接器和多个标识组件；至少一个所述第二可插拔连接器与至少一个所述第一可插拔连接器耦合，所述标识组件与所述第二可插拔连接器耦合，
    所述方法包括：
    响应于所述服务系统上电，扫描所述多个第一可插拔连接器，读取各个所述第一可插拔连接器耦合的所述第二可插拔连接器下的所述标识组件管理的标识信息，根据所述标识信息识别所述设备机箱的类型和数量。
  18. 一种计算机程序产品，包括计算机程序，其特征在于，所述计算机程序被处理器执行时实现权利要求17所述方法的步骤。
  19. 一种电子设备，其特征在于，包括处理器、通信接口、存储器和通信总线，其中，处理器，通信接口，存储器通过通信总线完成相互间的通信；
    存储器，被配置为存放计算机程序；
    处理器，被配置为执行存储器上所存放的程序时，实现如权利要求17所述方法的步骤。
  20. 一种计算机非易失性存储介质，其上存储有计算机程序，其特征在于，所述计算机程序被处理器执行时实现如权利要求17所述方法的步骤。
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CN117978811A (zh) * 2024-03-29 2024-05-03 苏州元脑智能科技有限公司 映射关系的确定方法及系统、存储介质及电子装置
CN118467434A (zh) * 2024-07-10 2024-08-09 苏州元脑智能科技有限公司 服务系统、输入输出机箱、设备机箱以及机箱识别方法

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