WO2026001065A1 - 存储芯片的控制方法、存储控制器和存储系统 - Google Patents

存储芯片的控制方法、存储控制器和存储系统

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Publication number
WO2026001065A1
WO2026001065A1 PCT/CN2025/080567 CN2025080567W WO2026001065A1 WO 2026001065 A1 WO2026001065 A1 WO 2026001065A1 CN 2025080567 W CN2025080567 W CN 2025080567W WO 2026001065 A1 WO2026001065 A1 WO 2026001065A1
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WO
WIPO (PCT)
Prior art keywords
storage
read
cells
interference
memory
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Pending
Application number
PCT/CN2025/080567
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English (en)
French (fr)
Inventor
欧阳建
陈一峰
王成旭
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Publication of WO2026001065A1 publication Critical patent/WO2026001065A1/zh
Pending legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention

Definitions

  • This application relates to the field of storage technology, and in particular to a control method for a storage chip, a storage controller, and a storage system.
  • Read interference and write interference are important factors affecting the stability of data stored in memory chips.
  • Read interference refers to the impact of the conduction current inside the memory cell on the storage state of the cell itself when frequent read operations are performed.
  • Write interference refers to the impact of the temperature rise of the memory cell itself on the storage state of itself and surrounding memory cells when frequent write operations are performed.
  • read interference mainly causes the memory cell to change from a low-resistance state to a high-resistance state
  • write interference mainly causes the memory cell to change from a high-resistance state to a low-resistance state.
  • This application provides a control method, a memory controller, and a memory system for a memory chip, which can improve the stability of data stored in the memory chip.
  • the corresponding technical solution is as follows:
  • a method for controlling a memory chip comprising: applying a read voltage to a plurality of first memory cells corresponding to a first address; and refreshing data stored in a plurality of second memory cells in response to a failure rate of the plurality of first memory cells being greater than a first threshold, wherein the first threshold is less than a second threshold for triggering a UCE (Unified Entity Encryption) of the memory chip, the plurality of second memory cells are memory cells affected by read interference or write interference, and the plurality of second memory cells are a plurality of first memory cells, or the second memory cells are a plurality of first memory cells and memory cells adjacent to the plurality of first memory cells.
  • UCE Unified Entity Encryption
  • the failure rate of the read result of the first memory cell is determined to be greater than a first threshold, it is considered that the first memory cell may have been affected by read interference or write interference. Then, the data stored in multiple second memory cells (including the first memory cells) that may be affected by read interference or write interference can be refreshed to restore the threshold voltage of the affected memory cells to a state unaffected by read interference or write interference.
  • the solution presented in this application can eliminate the impact of read interference or write interference on the memory cells before triggering the UCE, thereby improving the stability of the data stored in the memory chip and reducing the probability of triggering the UCE.
  • refreshing the data stored in a plurality of second storage units includes: determining an interference type corresponding to the plurality of first storage units, wherein the interference type is read interference or write interference, in response to the failure rate of the plurality of first storage units being greater than the first threshold; if the interference type is determined to be read interference, then determining the plurality of first storage units as a plurality of second storage units, and refreshing the data stored in the second storage units; if the interference type is determined to be read interference, then determining the plurality of first storage units and the storage units adjacent to the plurality of first storage units as second storage units, and refreshing the data stored in the second storage units.
  • the first storage cell is primarily affected by read interference or write interference, and to selectively refresh the storage cell based on the type of interference.
  • read interference only the data in the first storage cell is refreshed, reducing the number of storage cells to be refreshed and lowering the power consumption of the storage chip.
  • write interference the data in the first storage cell and adjacent storage cells can be refreshed to ensure that all storage cells affected by write interference are refreshed, thereby improving the stability of data storage in the storage chip.
  • determining the interference type corresponding to multiple first memory cells includes: determining the proportion of the number of failed low-resistivity first memory cells to the total number of failed first memory cells. If the proportion is greater than a third threshold, the interference type is determined to be read interference; if the proportion is less than or equal to the third threshold, the interference type is determined to be write interference.
  • the interference type corresponding to multiple first memory cells can be determined based on the number of failed low-resistivity first memory cells or the proportion of failed high-resistivity first memory cells in the total number of failures.
  • applying a read voltage to a plurality of first memory cells corresponding to a first address includes: applying multiple levels of read voltage to the plurality of first memory cells corresponding to the first address, wherein the read voltage levels increase sequentially.
  • Refreshing the data stored in a plurality of second memory cells in response to a failure rate greater than a first threshold includes: refreshing the data stored in the plurality of second memory cells in response to a failure rate greater than the first threshold obtained by applying read voltage levels to the plurality of first memory cells.
  • the method further includes: performing error correction processing on the target read data to obtain error-corrected read data, wherein the target read data is the set of read data with the lowest failure rate among the multiple sets of read data obtained by applying the multiple levels of read voltage.
  • Refreshing the data stored in the multiple second storage cells includes: writing the error-corrected read data into the first storage cell included in the multiple second storage cells.
  • the target read data with the lowest failure rate when refreshing the data of the first storage unit, the target read data with the lowest failure rate can be selected for error correction, and the corrected data can be rewritten into the first storage unit.
  • error correction of the target read data with the lowest failure rate can improve the accuracy of error correction of the target read data, thereby improving the accuracy of the data stored in the first storage unit after refresh.
  • the memory cells adjacent to the plurality of first memory cells include third memory cells that are on the same bit line or word line and adjacent to the plurality of first memory cells.
  • the method further includes: determining a fourth memory cell that is on the same bit line or word line and adjacent to the third memory cell as a second memory cell.
  • experimental data shows that a third threshold between one-half and four-fifths provides a high degree of accuracy in distinguishing between read and write interference.
  • the aforementioned memory chip is a phase-change memory chip
  • the memory cells included in the phase-change memory chip are phase-change memory cells.
  • a storage controller which is connected to a storage chip.
  • the storage controller is used for:
  • a read voltage is applied to multiple first memory cells corresponding to a first address in the memory chip.
  • the data stored in multiple second memory cells is refreshed, wherein the first threshold is less than a second threshold that triggers an uncorrectable error (UCE) in the memory chip, the multiple second memory cells are memory cells affected by read interference or write interference, the multiple second memory cells are multiple first memory cells, or the second memory cells are multiple first memory cells and memory cells adjacent to the multiple first memory cells.
  • UCE uncorrectable error
  • the storage controller is configured to: in response to a failure rate greater than a first threshold, determine an interference type corresponding to the plurality of first storage cells, wherein the interference type is read interference or write interference. If the interference type is determined to be read interference, the plurality of first storage cells are designated as plurality of second storage cells, and the data stored in the second storage cells is refreshed. If the interference type is determined to be read interference, the plurality of first storage cells and adjacent storage cells are designated as second storage cells, and the data stored in the second storage cells is refreshed.
  • the storage controller is configured to: determine, among a plurality of first storage cells, the proportion of the number of failed low-resistivity first storage cells to the total number of failed first storage cells. If the proportion is greater than the third threshold, the interference type is determined to be read interference; if the proportion is less than or equal to the third threshold, the interference type is determined to be write interference.
  • a storage controller is configured to: apply multiple read voltage levels to multiple first storage cells corresponding to a first address, wherein the read voltage levels increase sequentially. In response to a failure rate greater than a first threshold obtained by applying each read voltage level to the multiple first storage cells, the data stored in the multiple second storage cells is refreshed.
  • the storage controller is further configured to: perform error correction processing on the target read data to obtain error-corrected read data, wherein the target read data is the set of read data with the lowest corresponding failure rate among multiple sets of read data obtained by applying multiple levels of read voltage; and write the error-corrected read data into a first storage cell included in a plurality of second storage cells.
  • the memory cell adjacent to the plurality of first memory cells includes a third memory cell that is on the same bit line or word line and adjacent to the plurality of first memory cells.
  • the memory controller is further configured to: determine a fourth memory cell that is on the same bit line or word line and adjacent to the third memory cell as a second memory cell.
  • the third threshold is between one-half and four-fifths.
  • the first storage unit is a phase-change storage unit.
  • a storage system comprising a storage controller as described in the second aspect above, and at least one storage chip connected to the storage controller.
  • an electronic device comprising a processor and a storage system as described in the third aspect above, wherein the processor is configured to send read/write instructions to the storage system to enable the storage system to perform read/write operations.
  • Figure 1 is a schematic diagram of the structure of a memory chip provided in an embodiment of this application.
  • FIG. 2 is a schematic diagram of a control circuit provided in an embodiment of this application.
  • Figure 3 is a schematic diagram of the structure of a storage system provided in an embodiment of this application.
  • Figure 4 is a threshold voltage distribution diagram of a memory cell provided in an embodiment of this application.
  • Figure 5 is a schematic diagram illustrating the effects of write interference and read interference on a storage unit provided in an embodiment of this application;
  • FIG. 6 is a flowchart of a control method for a memory chip provided in an embodiment of this application.
  • Figure 7 is a threshold voltage distribution diagram of a memory cell provided in an embodiment of this application.
  • FIG. 8 is a flowchart of a control method for a memory chip provided in an embodiment of this application.
  • Figure 9 is a schematic diagram of an electronic device provided in an embodiment of this application.
  • Resistive memory It uses changes in resistance to store or retrieve data. For example, a resistive memory can store "0" in high configuration and "1" in low configuration.
  • Phase Change Memory A novel non-volatile semiconductor memory based on chalcogenide compounds, belonging to the resistive memory category. It utilizes the difference in resistance between the crystalline and amorphous states of the phase change material that makes up the PCM to store "0" and "1". Specifically, when the phase change material is in an amorphous state, it is in a high-resistance state, defined as the RESET(0) state; when the phase change material is in a crystalline state, it is in a low-resistance state, defined as the SET(1) state.
  • Ovonic Threshold Switch A novel bidirectional gating device based on chalcogenide compounds.
  • Ovonic Threshold Switch A novel bidirectional gating device based on chalcogenide compounds.
  • 1S1R memory cell A memory cell consisting of an OTS and a PCM.
  • the 1S1R memory cell when the PCM in the 1S1R memory cell is in the RESET(0) state, the 1S1R memory cell stores "0", and at this time, the 1S1R memory cell has a higher threshold voltage Vthr.
  • the 1S1R memory cell When the PCM in the 1S1R memory cell is in the SET(1) state, the 1S1R memory cell stores "1", and at this time, the 1S1R memory cell has a lower threshold voltage Vths.
  • Vthr is equal to the threshold voltage of the OTS plus the threshold voltage corresponding to the PCM in the RESET(0) state
  • Vths is equal to the threshold voltage of the OTS plus the threshold voltage corresponding to the PCM in the SET(1) state.
  • Erasure operation This is achieved by applying a high-amplitude, narrow-width electrical pulse to the 1S1R memory cell.
  • the amplitude of this electrical pulse is higher than the threshold voltage of the OTS.
  • the temperature of the PCM in the 1S1R memory cell is rapidly raised above the melting temperature and then quenched. Since the microscopic atoms do not have enough time to crystallize, they remain in a high-resistivity amorphous state, thus achieving the storage of "0".
  • the amplitude of this electrical pulse is higher than the threshold voltage of the OTS.
  • the temperature of the PCM in the 1S1R memory cell is raised to above the crystallization temperature but below the melting temperature.
  • the PCM can be transformed into a low-resistance state through a thermal crystallization process, thus achieving the storage of "1".
  • Word line The signal line required to select a 1S1R memory cell in a memory array. It works together with the bit line to complete the selection of a 1S1R memory cell.
  • Bit lines Signal lines used to select a specific column in a memory array. Working together with word lines, they enable the selection of a 1S1R memory cell. By applying appropriate electrical pulses to the word lines and bit lines, write, erase, or read operations can be performed on the selected 1S1R memory cell.
  • Figure 1 is a schematic diagram of a memory chip structure provided in an embodiment of this application.
  • the memory chip 100 includes a control circuit 110 and at least one storage bank 120, each bank 120 including multiple storage arrays 121.
  • the multiple storage arrays 121 included in the multiple banks 120 can generally be laid flat on the same plane or stacked in three-dimensional space.
  • Each storage array 121 includes storage cells distributed in rows and columns.
  • one storage cell can be selected in each storage array 121 to perform read and write operations on multiple selected storage cells. In this way, the storage capacity and storage performance of the memory chip can be improved without increasing the area occupied by the memory chip.
  • FIG. 2 is a schematic diagram of a control circuit provided in an embodiment of this application.
  • the control circuit 110 includes a logic control circuit 1101, an address register 1102, a bank selection circuit 1103, a row address multiplexing circuit 1104, a column address multiplexing circuit 1105, and a row decoder 1106, a column decoder 1107, a driving circuit 1108, and a sensing circuit (SA) 1109 corresponding to each memory array, wherein:
  • the logic control circuit 1101 can be used to receive read, write, and other operation requests sent from the outside, and control the timing of the read, write, and other operations. For example, it can send the address of the memory cell to be read or written to the address register 1102, and send the operation type to be performed, such as write operation or read operation, to the driver circuit.
  • Address register 1102 can receive and store the addresses of memory cells to be read, written, or otherwise executed by the logic control circuit 1101. These addresses include the row address, column address, and bank address of the memory cell.
  • the Bank selection circuit 1103 can select the Bank containing the memory cell to be read or written from multiple Banks based on the Bank address corresponding to the memory cell to be read or written.
  • the row address multiplexing circuit 1104 can send the row address corresponding to the memory cell to be read, written, or otherwise operated to the row decoder 1106 corresponding to each memory array 121 included in the selected Bank.
  • the column address multiplexing circuit 1105 can send the column address corresponding to the memory cell to be read, written, or otherwise operated to the column decoder 1107 corresponding to each memory array 121 included in the selected Bank.
  • each row decoder 1106 can decode the row address to select the row containing the memory cell to be read, written, or otherwise operated on.
  • each column decoder 1107 can decode the column address to select the column containing the memory cell to be read, written, or otherwise operated on.
  • the memory cell selected by both the row decoder 1106 and the column decoder 1107 is the memory cell to be read, written, or otherwise operated on.
  • each drive circuit 1108 included in the selected Bank can apply an operating voltage to the selected memory cell in the corresponding memory array 121 according to the received operation type to complete the corresponding operation.
  • each sensing circuit 1109 can determine the data stored in the memory cell by detecting the magnitude of the current or voltage after the drive circuit 1108 completes the application of the read operation voltage to the memory cell.
  • FIG. 3 is a schematic diagram of a storage system provided in an embodiment of this application. As shown in Figure 3, the storage system 300 includes a storage controller 200 and one or more storage chips 100 as shown in Figure 1. Wherein:
  • the storage controller 200 is a hardware device used to control the storage chip 100 to perform read and write operations.
  • the storage controller 200 can send operation requests corresponding to read, write, or erase operations to the storage chip 100, causing the control circuit 110 in the storage chip 100 to select the storage cell via word lines and bit lines, and apply read, write, or erase voltages to the selected storage cell, thereby executing the read, write, or erase operation.
  • the storage controller 200 also includes an error correction algorithm, such as an Error Correction Code (ECC). This error correction algorithm can verify and correct the read results of the storage chip to avoid or reduce erroneous data reads.
  • ECC Error Correction Code
  • OTS threshold voltage drift The characteristic of OTS threshold voltage to change due to the influence of voltage applied to OTS and ambient temperature during the time from the last time it was turned on to the current time it was turned on is called OTS threshold voltage drift.
  • the OTS Overcurrent Switch
  • the OTS exhibits significant current conduction capability under applied voltages exceeding its threshold voltage. This is due to the transition of low-energy, non-conductive electrons to a high-energy, non-conductive state under high voltage.
  • the applied voltage is removed from the OTS, the high-energy non-equilibrium carriers do not instantly return to equilibrium; instead, they gradually return to the low-energy, non-conductive state with a certain probability. Therefore, after each operation on a 1S1R memory cell, the threshold voltage of the OTS in the 1S1R memory cell suddenly decreases and then gradually increases over time.
  • the higher the applied voltage the greater the drop in the OTS threshold voltage.
  • the higher the ambient temperature of the OTS the faster its threshold voltage drifts upward. Additionally, when the OTS is left unused for an extended period, its threshold voltage will also drift to a higher level.
  • Figure 4 is a threshold voltage distribution diagram provided in an embodiment of this application.
  • the threshold voltage drift mainly causes the threshold voltage to increase, and the shape of its threshold voltage distribution curve remains basically unchanged.
  • Read interference and write interference are mainly caused by electrical and thermal interference to the memory cells. This process affects the OTS and PCM as a whole, increasing the threshold voltage on the one hand and widening the threshold voltage distribution curve on the other, which in turn causes the distribution curves of "0" and "1" of the memory cells to overlap.
  • write interference refers to the interference (mainly thermal interference) that occurs when a memory cell at a certain address is frequently written to, affecting neighboring, second-nearest, and second-nearest neighbor memory cells. This causes the high-resistivity "0" state of neighboring cells to be thermally crystallized into a low-resistivity "1" state.
  • the memory cells that may be affected are also called PVs (potential-victims), and the closer the distance, the greater the impact.
  • write interference mainly broadens the curve shape of the threshold voltage of the high-resistivity "0” state, causing the threshold voltage of some high-resistivity "0” states to overlap with the threshold voltage of the low-resistivity "1" state.
  • read interference occurs because frequent read operations on a memory cell at a certain address can cause the cumulative effect of factors such as current fluctuations during read operations on the memory state (mainly current interference), leading to the misinterpretation of a low-resistance "1" state as a "0" state.
  • write interference mainly broadens the curve of the threshold voltage of the low-resistance "1” state, causing the threshold voltage of some low-resistance "1" states to overlap with the threshold voltage of the high-resistance "0" state.
  • FIG. 5 is a schematic diagram illustrating the effects of write interference and read interference on a storage cell according to an embodiment of this application.
  • the target storage cell a and multiple storage cells (PVs) adjacent to the target storage cell a may be affected by the high temperature of the target storage cell, resulting in a change in storage state.
  • storage cells storing a high-resistance state "0" are interfered with and become storage cells storing a low-resistance state "1".
  • the multiple storage cells adjacent to the target storage cell a may include storage cells b, c, d, e, etc.
  • the target storage cell n will be frequently turned on.
  • the conduction current will continuously affect the storage state of the target storage cell n, leading to a change in storage state. Specifically, storage cells storing a low-resistance state "1" are interfered with and become storage cells storing a high-resistance state "0".
  • This application provides a control method for a memory chip.
  • the reason for the high failure rate of the memory cell at that address can be further determined, including whether it is affected by write interference or read interference.
  • a refresh operation is performed on the corresponding memory cells to refresh the storage state of the memory cells to the storage state before the interference, thereby improving the stability of the data stored in the memory chip and avoiding uncorrectable errors caused by write or read interference.
  • FIG. 6 is a flowchart of a control method for a memory chip according to an embodiment of this application. This method can be executed by the memory controller described above. Referring to Figure 6, the method includes:
  • Step 601 The storage controller applies a read voltage to the plurality of first storage cells corresponding to the first address.
  • the storage controller can receive read requests sent by the host. Upon receiving a read request, the storage controller can send the first address corresponding to the read request to the control circuit in the storage chip. Then, the control circuit of the storage chip applies a read voltage to multiple first storage cells corresponding to the first address to perform a read operation on the multiple first storage cells.
  • the process of the control circuit applying the read voltage to the multiple first storage cells can be referred to the embodiment corresponding to Figure 2 above, and will not be repeated here.
  • the storage chip involved can be a phase-change storage chip, and the storage cells included are phase-change storage cells, such as 1S1R storage cells.
  • Step 602 In response to the failure rate of multiple first storage cells being greater than a first threshold, refresh the data stored in multiple second storage cells.
  • the first threshold is less than a second threshold that triggers an uncorrectable error (UCE) in the storage chip.
  • the multiple second storage cells are storage cells affected by read or write interference.
  • the multiple second storage cells are multiple first storage cells, or the second storage cells are multiple first storage cells plus storage cells adjacent to the multiple first storage cells.
  • the reading results corresponding to the multiple first memory cells can be obtained through the sensing circuit included in the control circuit, and the reading result of each first memory cell can be stored in the register included in the control circuit.
  • the reading result of a first memory cell is either "1" or "0". In one example, a reading result of "1" indicates that the storage state of the first memory cell is low-impedance, and a reading result of "0" indicates that the storage state of the first memory cell is high-impedance.
  • the memory controller can read the read results stored in the registers and then determine the failure rate corresponding to the read results using error correction algorithms, such as Error Correction Code (ECC).
  • ECC Error Correction Code
  • the failure rate can be represented by the number of memory cells with failed data in multiple first memory cells.
  • the failure rate can be the number of error bits (FBC) or the percentage of memory cells with failed data in multiple first memory cells.
  • the second storage unit is the storage unit that may be affected by read or write interference.
  • the failure rate of multiple first storage units exceeds a first threshold, it indicates that these units may be affected by read or write interference, leading to a high failure rate. Therefore, at least multiple first storage units can be identified as second storage units to be refreshed, and the data stored in these units can be refreshed to eliminate the impact of read or write interference on the storage state of the units and ensure the accuracy of the stored data.
  • the first threshold is less than the second threshold that triggers the UCE (Unified Error Correction) of the storage chip. This ensures that after determining that the failure rate of multiple first storage units exceeds the first threshold, the error correction algorithm can correct errors by reading the results from these units, thereby refreshing the data stored in the first storage units.
  • the first threshold is between 0.5 and 0.99 times the second threshold.
  • the first storage cell When the first storage cell is subjected to write interference, its surrounding storage cells may also be affected. As shown in Figure 5, when frequent write operations are performed on storage cell a, in addition to storage cell a being affected by write interference, the high temperature generated by storage cell a will also be transferred to storage cells b, c, d, and e through some media, making storage cells b, c, d, and e potentially affected by write interference. Therefore, when it is determined that the first storage cell may be affected by write interference, even if it cannot be directly determined whether the first storage cell is the storage cell that frequently performs write operations, it can be determined that the storage cells adjacent to the first storage cell may also be affected by write interference.
  • the first storage cell and the storage cells adjacent to the first storage cell can be identified as second storage cells to be refreshed, and the data stored in multiple second storage cells can be refreshed to eliminate the impact of read interference or write interference on the storage state of the storage cell and ensure the accuracy of the data stored in the storage cell.
  • refreshing the data stored in the second storage unit involves correcting the read results corresponding to the second storage unit and then rewriting the corrected data into the second storage unit. Since the data rewritten to the second storage unit is corrected data, the accuracy of the data stored in the second storage unit can be guaranteed. Furthermore, after rewriting data to the second storage unit, the threshold voltage of the second storage unit is refreshed to the threshold voltage before being affected by read interference, write interference, threshold voltage drift, etc., thereby avoiding the problem that the read voltage cannot distinguish the storage state of the storage unit and improving the accuracy of the data stored in the storage unit.
  • Figure 7 is a threshold voltage distribution diagram provided in an embodiment of this application. As shown in Figure 7, after multiple second storage cells are subjected to read or write interference, the threshold voltage distribution curves of the first storage cell storing "1" and the second storage cell storing “0" may overlap, causing the read voltage (Vread) to be unable to distinguish the storage state of some second storage cells. Continuing to refer to Figure 7, after refreshing the data stored in the second storage cell, the threshold voltage of the second storage cell is refreshed. The threshold voltage distribution curves of the first storage cell storing "1" and the second storage cell storing "0” will both become “narrower,” and the read voltage (Vread) can accurately distinguish the storage state of the second storage cell.
  • the range of storage cells for data refresh can be selected. The method for determining the type of interference experienced by the first storage cells is described below:
  • Read interference primarily disrupts the memory cell from a low-resistance state to a high-resistance state, essentially causing memory cells storing "1"s to store "0".
  • Write interference primarily disrupts the memory cell from a high-resistance state to a low-resistance state, essentially causing memory cells storing "0"s to store "1". Therefore, in this embodiment, the number of failures in both the low-resistance and high-resistance states of the memory cells can be used to determine whether a memory cell is primarily affected by read interference or write interference.
  • the storage controller uses an error correction algorithm to determine the number of failed first storage cells among multiple first storage cells. It can also determine a first number of first storage cells that failed from storage "1" to storage "0", and a second number of first storage cells that failed from storage "0" to storage "1". The sum of the first and second numbers represents the total number of failed storage cells among the multiple first storage cells.
  • the first number is greater than the second number, that is, when the first proportion of the first memory cells that failed from storage “1" to storage "0" in the total number of failed first memory cells is greater than 50% (or the second proportion of the first memory cells that failed from storage "0" to storage "1” in the total number of failed first memory cells is less than 50%), it can be determined that the multiple first memory cells corresponding to the first address are mainly affected by read interference.
  • the first number is less than the second number, that is, when the second proportion of the first memory cells that failed from storage “0" to storage “1” in the total number of failed first memory cells is greater than 50% (or the first proportion of the first memory cells that failed from storage "1" to storage "0” in the total number of failed first memory cells is less than 50%), it can be determined that the multiple first memory cells corresponding to the first address are mainly affected by write interference.
  • a threshold (third threshold) can be set for the aforementioned first or second percentage. Based on the relationship between the first or second percentage and the set third threshold, it can be determined whether the memory cell is primarily affected by read interference or write interference. For example, when the first percentage is greater than the third threshold (i.e., the second percentage is less than the third threshold), it can be determined that multiple first memory cells corresponding to the first address are primarily affected by read interference. When the first percentage is greater than the third threshold (i.e., the second percentage is less than the third threshold), it can be determined that multiple first memory cells corresponding to the first address are primarily affected by write interference.
  • the specific value of the third threshold can be preset by technicians. Experimental data shows that setting the third threshold between one-half and four-fifths yields the highest accuracy in identifying read and write interference.
  • the interference type affecting multiple first storage units when the interference type affecting multiple first storage units is determined to be read interference, the data stored in the determined first storage units can be refreshed, thereby avoiding the impact of read interference on the storage units.
  • the interference type affecting multiple first storage units is determined to be write interference
  • the multiple first storage units and the storage units adjacent to the multiple first storage units can be designated as second storage units, and the data stored in the designated second storage units can be refreshed. This avoids the impact of write interference on the first storage units and the surrounding storage units.
  • the second storage cells to be refreshed may also include third storage cells that are on the same word line and adjacent to the first storage cells, as well as third storage cells that are on the same bit line and adjacent to the first storage cells.
  • the first storage cell is a
  • the third storage cells that are on the same word line and adjacent to the first storage cell include storage cells b, c, d, and e.
  • the high temperature of the third storage cell may also be transmitted through the word line and bit line to the fourth storage cell adjacent to the third storage cell, causing the fourth storage cell to also be affected by write interference.
  • data refresh can also be performed on the fourth storage cells that are on the same bit line or the same word line and adjacent to the third storage cell.
  • the third storage cell includes storage cells b, c, d, and e
  • the corresponding fourth storage cell includes storage cells f, g, h, i, j, k, l, and m.
  • the address correspondence between each first storage unit and the third and fourth storage units can be pre-stored. After it is determined that the first storage unit is subject to write interference, the data stored in the third and fourth storage units can be refreshed according to the address relationship.
  • the interference type affecting multiple first storage units when the interference type affecting multiple first storage units is determined to be read interference, it means that the failure of multiple first storage units is mainly due to read interference, but the possibility of the first storage units also being affected by write interference cannot be ruled out.
  • the interference type affecting multiple first storage units when the interference type affecting multiple first storage units is determined to be write interference, it means that the failure of multiple first storage units is mainly due to write interference, but the possibility of the first storage units also being affected by read interference cannot be ruled out.
  • the second storage unit performing data refresh always includes the first storage units, which can avoid read interference or write interference affecting the first storage units, solve the problem of high failure rate of the first storage units, and improve the accuracy of data stored by the storage chip.
  • the read voltage applied in step 601 is a multi-level read voltage, with the multi-level read voltage increasing sequentially.
  • the read voltage applied to the first memory cell includes multiple levels, with the read voltage increasing sequentially across the multiple levels.
  • the lowest level of read voltage can be applied to the multiple first memory cells first. If the failure rate of the obtained read result does not trigger the UCE of the memory chip, the read result is corrected using an error correction algorithm to obtain an accurate read result. If the failure rate of the obtained read result triggers the UCE of the memory chip, the level of read voltage can be increased, applying a higher level of read voltage to the multiple first memory cells to obtain a new read result.
  • a smaller first threshold is set compared to the second threshold that triggers the UCE of the memory chip.
  • a higher read voltage level can be applied to the multiple first memory cells again. If a read result with a failure rate less than the first threshold appears among the applied read voltage levels, an error correction algorithm can be used to correct the read result, resulting in an error-corrected read result. If the failure rate of the read result corresponding to the applied read voltage levels is greater than the first threshold, it indicates that the multiple first memory cells are severely affected by read interference or write interference, which may trigger the UCE of the memory chip.
  • step 602 above which refreshes the data stored in the multiple second memory cells, is executed first to ensure data accuracy.
  • step 602 above which refreshes the data stored in the multiple second memory cells, is executed first to ensure data accuracy.
  • step 602 above which refreshes the data stored in the multiple second memory cells.
  • the first storage cell included in the second storage cell can be refreshed by performing error correction processing on the target read data to obtain error-corrected read data, and then writing the error-corrected read data into the first storage cell.
  • the target read data is the set of read data with the lowest failure rate among multiple sets of read data obtained by applying multiple levels of read voltage to multiple first storage cells.
  • FIG 8 is a flowchart of a control method for a memory chip provided in an embodiment of this application. As shown in Figure 8, the method includes:
  • Step 801 Start the read process.
  • the lowest level of read voltage is applied to multiple first memory cells corresponding to the first address to obtain the read result.
  • Step 802 Determine whether the FBC corresponding to the read result is greater than the set FBC threshold.
  • FBC is determined to be greater than the set FBC threshold, proceed to step 803. If the FBC is determined not to be greater than the set FBC threshold, perform normal error correction on the read result and return the corrected read result.
  • the set FBC threshold is less than the FBC threshold that triggers the UCE of the memory chip.
  • Step 803 Use different voltage levels to perform read retry and find the lowest FBC.
  • Step 804 Determine whether the lowest FBC is greater than the set FBC threshold.
  • Step 805 Determine whether the failure rate of "0 ⁇ 1" exceeds 50%.
  • step 806 If the percentage of memory cells that failed in the "0 ⁇ 1" state (i.e., memory cells that failed in the high-resistivity state) exceeds 50%, it indicates that the first memory cell is mainly affected by write disturbance, and step 806 can be executed. If the percentage of memory cells that failed in the "0 ⁇ 1" state does not exceed 50%, it indicates that the memory cell is mainly affected by read disturbance, and step 807 can be executed.
  • Step 806 Perform a refresh process on the current storage cell and its neighboring storage cells.
  • Step 807 Perform a refresh process on the current storage unit.
  • the effects of read interference and write interference on the storage unit can be distinguished, and different refresh processes can be performed for read interference and write interference respectively, which can improve the stability of data stored in the storage chip and reduce the power consumption of refresh processing.
  • FIG. 9 is a schematic diagram of an electronic device provided in an embodiment of this application.
  • the storage system includes a host, a storage controller, and a storage chip.
  • the host, storage controller, and storage chip are connected via an interface.
  • the storage controller is equipped with an algorithm module, including a Disturbance Resolution module, an ECC module, and a Read Retry module.
  • the Disturbance Resolution module, ECC module, and Read Retry module can be used to implement the control method provided in this embodiment of the application to improve the stability of data stored in the storage chip.
  • the ECC module can send the FBC to the Disturb resolution module.
  • the Disturb resolution module After receiving the FBC corresponding to the read result, the Disturb resolution module determines whether multiple read retry operations (i.e., performing read operations on the first memory cells using multiple higher read voltage levels) are required for multiple first memory cells. If the Disturb resolution module determines that read retry is required, it can send a read retry command to the Read retry module.
  • the read retry module After receiving the read retry instruction, the read retry module can sequentially read voltages at multiple higher voltage levels from multiple first memory cells and send the read results obtained each time to the ECC module.
  • the ECC module When the ECC module receives the reading result corresponding to the higher-level reading voltage, it can determine the FBC corresponding to the reading result of the higher-level reading voltage and send the corresponding FBC to the Disturb resolution module.
  • the Disturb resolution module determines whether a data refresh is needed based on the FBC corresponding to the reading results of the higher-level reading voltage, and if a data refresh is needed, it determines the type of disturbance.
  • the Disturb resolution module can obtain the error-corrected data corresponding to multiple first storage units from the ECC module, and write the error-corrected data into multiple first storage units to refresh the data in the first storage units, thus solving the impact of read disturbance on the storage units.
  • the Disturbance Resolution module can send the addresses of the third and fourth memory units to be read to the Read Retry module.
  • the Read Retry module can then read the results from the third and fourth memory units based on their addresses and provide them to the ECC module for error correction.
  • the Disturbance Resolution module can obtain the corrected data corresponding to multiple first, third, and fourth memory units from the ECC module and write the corrected data into these memory units, thus resolving the impact of write interference on the memory units.
  • the main interference experienced by the memory cell can be distinguished based on the specific failure status of the memory cell. Specifically, if the first number of failed memory cells in the low-resistance state is greater than the second number of failed memory cells in the high-resistance state, it indicates that the memory cell at the first address is mainly affected by read interference. Therefore, a write refresh can be performed on the memory cell at the first address to ensure the stability of the data stored therein. If the second number of failed memory cells in the high-resistance state is greater than the first number of failed memory cells in the low-resistance state, it indicates that the memory cell at the first address is mainly affected by write interference.
  • write interference is influenced by surrounding memory cells
  • a write refresh can be performed on the memory cell at the first address and the memory cells surrounding it to ensure the stability of the data stored therein. Therefore, this application can distinguish between read interference and write interference affecting the memory cell and provides different write refresh methods for each type of interference, thereby improving the stability of data stored in the memory chip.
  • this application also provides a storage controller, which is included in the storage system shown in FIG3.
  • this storage controller can implement the storage chip control method provided in the above embodiments to determine whether read interference or write interference exists based on the failure rate of multiple first storage cells corresponding to a first address in the storage chip, and perform data refresh on the second storage cells affected by the read interference or write interference to eliminate the impact of the read interference or write interference.
  • the process by which the storage controller implements the storage chip control method can be referred to the above method embodiments, and will not be repeated here.
  • the storage system shown in Figure 3 includes a storage controller and one or more storage chips.
  • the storage controller can implement the control method for the storage chip provided in the above embodiments. This method determines whether read interference or write interference exists based on the failure rate of multiple first storage cells corresponding to a first address in the storage chip, and performs data refresh on the second storage cells affected by the read interference or write interference to eliminate its impact.
  • the process by which the storage controller implements the control method for the storage chip can be referred to the above method embodiments, and will not be repeated here.
  • first, second, etc. are used to distinguish identical or similar items with substantially the same function. It should be understood that there is no logical or temporal dependency between “first” and “second,” nor does it limit the quantity or order of execution. It should also be understood that although the following description uses the terms “first,” “second,” etc., to describe various elements, these elements should not be limited by the terms. These terms are merely used to distinguish one element from another. In this application, the term “at least one" means one or more, and the term “multiple” means two or more.

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Abstract

一种存储芯片的控制方法、存储控制器和存储系统。该控制方法包括：对第一地址对应的多个第一存储单元施加读电压；响应于多个第一存储单元的失效率大于第一阈值，对多个第二存储单元中存储的数据进行刷新，其中，第一阈值小于触发存储芯片UCE的第二阈值，多个第二存储单元是受到读干扰或写干扰影响的存储单元，多个第二存储单元为多个第一存储单元，或，多个第二存储单元为多个第一存储单元以及与多个第一存储单元相邻的存储单元。该控制方法可以提高存储芯片存储数据的稳定性。

Description

存储芯片的控制方法、存储控制器和存储系统
本申请要求于2024年06月27日提交的申请号为202410851268.X、发明名称为“存储芯片的控制方法、存储控制器和存储系统”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及存储技术领域，特别涉及一种存储芯片的控制方法、存储控制器和存储系统。
背景技术
随着存储技术的发展，存储芯片的存储性能也越来越高，存储芯片存储数据的稳定性也越来越重要。
读干扰和写干扰是影响存储芯片存储数据稳定性的重要因素。读干扰是指对存储单元频繁的执行读操作时，存储单元内部的导通电流对存储单元本身存储状态的影响。写干扰是指对存储单元频繁的执行写操作时，存储单元本身的温度升高对本身以及周围的存储单元存储状态的影响。其中，读干扰主要是将存储单元从低阻态干扰为高阻态，写干扰主要是将存储单元从高阻态干扰为低阻态。
目前存储芯片中没有针对读干扰和写干扰进行优化的方案，导致存储芯片存储数据的稳定性较低。
发明内容
本申请实施例提供了一种存储芯片的控制方法、存储控制器和存储系统，能够提高存储芯片存储数据的稳定性，相应的技术方案如下：
第一方面，提供了一种存储芯片的控制方法，包括：对第一地址对应的多个第一存储单元施加读电压。响应于多个第一存储单元的失效率大于第一阈值，对多个第二存储单元中存储的数据进行刷新，其中，第一阈值小于触发存储芯片UCE的第二阈值，多个第二存储单元是受到读干扰或写干扰影响的存储单元，多个第二存储单元为多个第一存储单元，或，第二存储单元为多个第一存储单元以及与多个第一存储单元相邻的存储单元。
在本申请所示的方案中，对第一地址的多个第一存储单元执行读操作后，如果确定第一存储单元读取结果的失效率大于第一阈值，则认为第一存储单元可能受到了读干扰或写干扰的影响。然后可以对可能受到读干扰或写干扰影响的多个第二存储单元(多个第二存储单元中包括第一存储单元)存储的数据进行刷新，以使受到读干扰或写干扰影响的存储单元的阈值电压恢复至未受到读干扰或写干扰的影响的状态。由于第一阈值小于触发存储芯片UCE的第二阈值，所以本申请所示的方案可以实现在触发存储芯片UCE之前，对存储单元受到读干扰或写干扰的影响进行消除，进而可以提高存储芯片存储数据的稳定性，降低触发存储芯片UCE的概率。
在一种可实现的方式中，响应于多个第一存储单元的失效率大于第一阈值，对多个第二存储单元中存储的数据进行刷新，包括：响应于多个第一存储单元的失效率大于第一阈值，确定多个第一存储单元对应的干扰类型，干扰类型为读干扰或写干扰。在确定干扰类型为读干扰的情况下，确定多个第一存储单元为多个第二存储单元，对第二存储单元中存储的数据进行刷新。在确定干扰类型为读干扰的情况下，确定多个第一存储单元以及与多个第一存储单元相邻的存储单元为第二存储单元，对第二存储单元中存储的数据进行刷新。
在本申请所示的方案中，能够区分第一存储单元是主要是受到读干扰影响还是受到写干扰影响，并且可以根据第一存储单元是受到干扰类型的不同，选择性的对存储单元进行刷新。在受到读干扰影响的情况下，仅对第一存储单元的数据进行刷新，以减少刷新的存储单元的数量，降低存储芯片的功耗。在受到写干扰影响的情况下，可以对第一存储单元以及与第一存储单元相邻的存储单元的数据进行刷新，以确保对受到写干扰影响的存储单元均执行数据刷新，进而提高存储芯片存储数据的稳定性。
在一种可实现的方式中，确定多个第一存储单元对应的干扰类型，包括：在多个第一存储单元中，确定失效的低阻态第一存储单元的个数在失效的第一存储单元总数中的占比。在占比大于第三阈值的情况下，确定干扰类型为读干扰，在占比小于或等于第三阈值的情况下，确定干扰类型为写干扰。
在本申请所示的方案中，可以根据失效的低阻态第一存储单元的数量，或失效的高阻态第一存储单元的数量在总失效数量中的占比，确定多个第一存储单元对应的干扰类型。如此通过区分第一存储单元对应的干扰类型，可准确的确定受到读干扰或写干扰的第二存储单元的范围，避免对受到干扰的存储单元漏刷，或者对未受到干扰的存储单元误刷，进而可以降低存储芯片的功耗，提高存储芯片存储数据的稳定性。
在一种可实现的方式中，对第一地址对应的多个第一存储单元施加读电压，包括：对第一地址对应的多个第一存储单元施加多个档位的读电压，多个档位的读电压依次增大。响应于多个第一存储单元的失效率大于第一阈值，对多个第二存储单元中存储的数据进行刷新，包括：响应于对多个第一存储单元施加每个档位的读电压得到的失效率均大于第一阈值，对多个第二存储单元中存储的数据进行刷新。
在本申请所示的方案中，对第一存储单元施加的多个档位的读电压得到的失效率均大于第一阈值时，触发对存储单元中存储的数据进行刷新，如此可以在临近触发第一存储单元读取失败之前，消除第一存储单元受到读干扰或写干扰的影响，进而可以在保证存储芯片存储数据稳定性的前提下，降低对存储单元刷新的刷新次数，可以降低存储芯片的功耗。
在一种可实现的方式中，对第一地址对应的多个第一存储单元施加多个档位的读电压之后，还包括：对目标读取数据进行纠错处理，得到纠错处理后的读取数据，目标读取数据为施加多个档位的读电压分别得到的多组读取数据中对应失效率最低的一组读取数据。对多个第二存储单元中存储的数据进行刷新，包括：将纠错处理后的读取数据写入多个第二存储单元中包括的第一存储单元。
在本申请所示的方案中，在对第一存储单元的数据进行刷新时，可以选择对应失效率最低的目标读取数据进行纠错，并对纠错后的数据重新写入第一存储单元，这样对失效率最低的目标读取数据进行纠错，可以提高对目标读取数据进行纠错的准确率，进而提高刷新后第一存储单元存储数据的准确性。
在一种可实现的方式中，与多个第一存储单元相邻的存储单元包括与多个第一存储单元在同一位线或字线且相邻的第三存储单元，方法还包括：确定与第三存储单元在同一位线或同一字线且相邻的第四存储单元为第二存储单元。如此，扩大第二存储单元的范围，可以保证对受到写干扰影响的存储单元均得到刷新，进而可以提高存储芯片存储数据的稳定性。
在一种可实现的方式中，通过实验数据可以得到，第三阈值在二分之一到五分之四之间，对读干扰和写干扰的区分准确性较高。
在一种可实现的方式中，上述存储芯片为相变存储芯片，相变存储芯片包括的存储单元为相变存储单元。
第二方面，提供了一种存储控制器，存储控制器与存储芯片连接，存储控制器，用于：
对存储芯片中第一地址对应的多个第一存储单元施加读电压。响应于多个第一存储单元的失效率大于第一阈值，对多个第二存储单元中存储的数据进行刷新，其中，第一阈值小于触发存储芯片不可纠正错误UCE的第二阈值，多个第二存储单元是受到读干扰或写干扰影响的存储单元，多个第二存储单元为多个第一存储单元，或，第二存储单元为多个第一存储单元以及与多个第一存储单元相邻的存储单元。
在一种可实现的方式中，存储控制器，用于：响应于多个第一存储单元的失效率大于第一阈值，确定多个第一存储单元对应的干扰类型，干扰类型为读干扰或写干扰。在确定干扰类型为读干扰的情况下，确定多个第一存储单元为多个第二存储单元，对第二存储单元中存储的数据进行刷新。在确定干扰类型为读干扰的情况下，确定多个第一存储单元以及与多个第一存储单元相邻的存储单元为第二存储单元，对第二存储单元中存储的数据进行刷新。
在一种可实现的方式中，存储控制器，用于：在多个第一存储单元中，确定失效的低阻态第一存储单元的个数在失效的第一存储单元总数中的占比。在占比大于第三阈值的情况下，确定干扰类型为读干扰，在占比小于或等于第三阈值的情况下，确定干扰类型为写干扰。
在一种可实现的方式中，存储控制器，用于：对第一地址对应的多个第一存储单元施加多个档位的读电压，多个档位的读电压依次增大。响应于对多个第一存储单元施加每个档位的读电压得到的失效率均大于第一阈值，对多个第二存储单元中存储的数据进行刷新。
在一种可实现的方式中，存储控制器，还用于：对目标读取数据进行纠错处理，得到纠错处理后的读取数据，目标读取数据为施加多个档位的读电压分别得到的多组读取数据中对应失效率最低的一组读取数据。将纠错处理后的读取数据写入多个第二存储单元中包括的第一存储单元。
在一种可实现的方式中，与多个第一存储单元相邻的存储单元包括与多个第一存储单元在同一位线或字线且相邻的第三存储单元，存储控制器，还用于：确定与第三存储单元在同一位线或同一字线且相邻的第四存储单元为第二存储单元。
在一种可实现的方式中，第三阈值在二分之一到五分之四之间。
在一种可实现的方式中，第一存储单元为相变存储单元。
第三方面，提供了一种存储系统，存储系统包括如上述第二方面所述的存储控制器，以及与存储控制器连接的至少一个存储芯片。
第四方面，提供了一种电子设备，该电子设备包括处理器以及如上第三方面提供的存储系统，其中，处理器用于向存储系统发送读写指令，以使存储系统实现读写操作。
附图说明
图1是本申请实施例提供的一种存储芯片的结构示意图；
图2是本申请实施例提供的一种控制电路的结构示意图；
图3是本申请实施例提供的一种存储系统的结构示意图；
图4是本申请实施例提供的一种存储单元的阈值电压分布图；
图5是本申请实施例提供的一种存储单元受到写干扰和读干扰的影响的示意图；
图6是本申请实施例提供的一种存储芯片的控制方法流程图；
图7是本申请实施例提供的一种存储单元的阈值电压分布图；
图8是本申请实施例提供的一种存储芯片的控制方法流程图；
图9是本申请实施例提供的一种电子设备的示意图。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请实施方式作进一步地详细描述。
下面对本申请实施例中涉及的一些名词进行解释：
电阻式存储器：利用电阻的变化来存储或读取数据，例如电阻式存储器在高组态时，可实现“0”的存储，在低组态时，可实现“1”的存储。
相变存储器(Phase Change Memory，PCM)：一种基于硫系化合物的新型非易失性半导体存储器，属于电阻式存储器中的一种，可以利用组成相变存储器的相变材料晶态和非晶态时所具有电阻不同，实现对“0”和“1”的存储。其中，当相变材料处于非晶态时，相变材料处于高阻状态，即具有较高的阻值，被定义为RESET(0)态；当相变材料处于晶态时，相变材料处于低阻状态，即具有较低的阻值，被定义为SET(1)态。
双向阈值开关(Ovonic Threshold Switch，OTS)：一种基于硫系化合物的新型双向选通器件。对双向阈值开关施加一个任意正反方向且低于双向阈值开关对应的阈值电压的电脉冲，该双向阈值开关上的响应电流较小，呈现出高阻非导通的状态。对双向阈值开关施加一个任意正反方向且高于双向阈值开关对应的阈值电压的电脉冲，该双向阈值开关上的响应电流较大，呈现出低阻导通的状态。
1S1R存储单元：由一个OTS和一个PCM组成的存储单元。在一种可实现的方式中，当1S1R存储单元中的PCM处于RESET(0)态时，1S1R存储单元中存储“0”，此时，1S1R存储单元具有较高的阈值电压Vthr。当1S1R存储单元中的PCM处于SET(1)态时，1S1R存储单元中存储“1”，此时，1S1R存储单元具有较低的阈值电压Vths。其中，Vthr等于OTS的阈值电压加上RESET(0)态的PCM对应的阈值电压，Vths等于OTS的阈值电压加上SET(1)态的PCM对应的阈值电压。
基于上述特性可知，当1S1R存储单元中存储“0”时，1S1R器件单元在特定读电压Vread(大于Vths，小于Vthr)下响应电流较小；当1S1R存储单元中存储“1”时，1S1R器件单元在特定读电压Vread下响应电流较大。如此，可以通过施加读电压Vread，读取1S1R存储单元中存储的数据。
擦除操作：通过对1S1R存储单元施加一个高幅度窄宽度的电脉冲实现。该电脉冲的幅值高于OTS的阈值电压，在该电脉冲的作用下，1S1R存储单元中的PCM的温度被迅速提升至融化温度以上然后骤冷，由于微观原子没有充分的时间结晶，因而保持在了高阻的非晶状态，即实现“0”的存储。
写操作：通过对1S1R存储单元施加一个幅度相对写操作较低但是持续时间相对较长的电脉冲实现。该电脉冲的幅值高于OTS的阈值电压，在该电脉冲作用下，1S1R存储单元中的PCM的温度被提升至结晶温度之上熔化温度之下，PCM可以通过热致结晶过程转变成低阻的状态，即实现“1”的存储。
读操作：可以通过在1S1R存储单元两端施加一个固定读电压Vread，根据1S1R存储单元的响应电流，实现对1S1R存储单元中存储数据的读取。
字线：存储阵列中选中某一行1S1R存储单元所需的信号线，与位线共同作用可以完成一个1S1R存储单元的选中。
位线：存储阵列中选中某一列所需的信号线，与字线共同作用可以完成一个1S1R存储单元的选中。通过在字线和位线施加相应的电脉冲，可以实现对选中的1S1R存储单元执行上述写操作、擦除操作或读操作。
图1是本申请实施例提供的一种存储芯片的结构示意图。如图1所示，存储芯片100中包括控制电路110和至少一个存储库120(Bank120)，每个Bank120中包括多个存储阵列121。多个Bank120包括的多个存储阵列121一般可以在平铺在同一平面上，或者可以在三维空间中堆叠。其中，每个存储阵列121中包括按照行列分布的存储单元，在对存储芯片100的存储单元进行读写等操作时，可以在每个存储阵列121中选中一个存储单元，以对选中的多个存储单元进行读写等操作。如此可以实现在不增加存储芯片所占面积的情况下，提升存储芯片的存储容量和存储性能。
图2是本申请实施例提供的一种控制电路的示意图。如图2所示，控制电路110包括逻辑控制电路1101、地址寄存器1102、Bank选择电路1103、行地址复用电路1104、列地址复用电路1105，以及对应每个存储阵列的行解码器1106、列解码器1107、驱动电路1108以及感测电路(SA)1109，其中：
逻辑控制电路1101可用于接收外部发送的读、写等操作请求，控制执行读、写等操作的时序等。如向地址寄存器1102发送待执行读、写操作的存储单元的地址，向驱动电路发送所执行操作的操作类型，如写操作、读操作等。
地址寄存器1102可以接收并存储逻辑控制电路1101发送的待执行读、写等操作的存储单元对应的地址。其中，该地址中包括存储单元所在的行地址、列地址以及所在的Bank地址。
Bank选择电路1103可根据待执行读、写等操作的存储单元对应的Bank地址，在多个Bank中选中待执行读、写等操作的存储单元所在的Bank。
行地址复用电路1104可以将待执行读、写等操作的存储单元对应的行地址发送至被选中的Bank包括的各个存储阵列121所对应的行解码器1106。列地址复用电路1105可以将待执行读、写等操作的存储单元对应的列地址发送至被选中的Bank包括的各个存储阵列121所对应的列解码器1107。
对于接收到行地址的各个行解码器1106，每个行解码器1106可以对行地址进行解码，以选中待执行读、写等操作的存储单元所在的行。对于接收到行地址的各个列解码器1107，每个列解码器1107可以对列地址进行解码，以选中待执行读、写等操作的存储单元所在的列。其中，被行解码器1106和被列解码器1107同时选中的存储单元即为待执行读、写等操作的存储单元。
对于被选中的Bank中包括的各个驱动电路1108，每个驱动电路1108可以根据接收到的操作类型，向对应的存储阵列121中被选中的存储单元施加操作电压，以完成对应的操作。
对于被选中的Bank中包括的各个感测电路1109，每个感测电路1109可以在驱动电路1108完成对存储单元施加读操作电压后，通过检测到的电流大小或电压大小，确定存储单元中存储的数据。
图3是本申请实施例提供一种存储系统的示意图。如图3所示，存储系统300包括存储控制器200以及一个或多个如图1所示的存储芯片100。其中：
存储控制器200是用于控制存储芯片100进行读写等操作的硬件装置。存储控制器200可以向存储芯片100发送读操作、写操作或擦除操作对应的操作请求，以使存储芯片100中的控制电路110通过字线和位线对存储单元进行选中，并对选中的存储单元施加读电压、写电压或者擦除电压，进而实现读操作、写操作或擦除操作的执行。为了应对存储单元的读取出错，存储控制器200中还设置有纠错算法，如纠正算法(Error Correction Code，ECC)。该纠错算法可以对存储芯片的读取结果进行校验、纠错，以避免或减少读取出错的数据。
1S1R存储单元在写入或读取操作过程中可能会受到某些因素干扰，使得1S1R存储单元整体的物理状态发生改变，继而引起其Vth的变化，从而导致该单元的读取异常。这些干扰因素包括读干扰(read disturb)、写干扰(write disturb)以及长时间放置产生的阈值电压漂移(drift)等。
OTS的阈值电压漂移：OTS的阈值电压受上一次开启到本次开启的时间内施加在OTS上的电压、环境温度等影响进而产生变化的特性，被称为OTS的阈值电压漂移。
OTS在施加的大于阈值电压的电压作用下具有较大的电流导通能力，是原本处于低能量态的平衡非导电电子在高压作用下跃迁至高能量态的非平衡导电状态导致的。当施加在OTS的电压撤除后，OTS中处于高能量非平衡载流子不会在瞬间全部回到平衡态，而是按照一定概率逐步回到低能量的平衡非导电状态。因此，在每次对1S1R存储单元执行操作后，1S1R存储单元中的OTS的阈值电压会突然降低，然后随着时间逐渐增加。其中，施加在OTS上的电压越大，OTS的阈值电压下降的就越多，之后当OTS所处的环境温度越高，其阈值电压向上漂移的速度越快。另外，当OTS放置的时间长时，其阈值电压也会漂移至一个较高的状态。
图4是本申请实施例提供的阈值电压分布图，参见图4，与OTS的阈值电压漂移不同，阈值电压漂移主要引起阈值电压变大，其阈值电压分布的曲线形状基本维持不变。而读干扰和写干扰主要是由于存储单元受到电、热干扰导致，这个过程影响到OTS和PCM整体，一方面使阈值电压变大，另一方面使得阈值电压分布的曲线展宽，进而导致存储单元“0”和“1”的分布曲线会发生重叠。
在一示例中，写干扰是指某个地址的存储单元在频繁写入时，对邻近、次邻近、次次邻近的存储单元产生干扰(主要是热干扰)，导致临近单元的高阻“0”态被热结晶至低阻“1”态，可能受到影响的存储单元也被称为PV(potential-victim)，距离越近受到的影响越大。如图4所示，写干扰主要是将高阻“0”态的阈值电压的曲线形状展宽，使得部分高阻“0”态的阈值电压与低阻“1”态的阈值电压重叠。
在一示例中，读干扰是因为某地址的存储单元在频繁读打开的时候可能由于出现的自身读取时的电流浮动等因素的累积影响对存储状态的影响(主要是电流干扰)，导致自身存储的低阻“1”态被误判成“0”态。如图4所示，写干扰主要是将低阻“1”态的阈值电压的曲线形状展宽，使得部分低阻“1”态的阈值电压与高阻“0”态的阈值电压重叠。
图5是本申请实施例提供的一种存储单元分别受到写干扰和读干扰的影响的示意图。如图5所示，在对频繁对目标存储单元a执行写操作时，目标存储单元a、与目标存储单元a临近的多个存储单元(PV)均可能受到目标存储单元高温的影响，而导致存储状态改变，且其中主要是存储高阻态“0”的存储单元被干扰为存储低阻态“1”的存储单元。其中目标存储单元a临近的多个存储单元可以包括存储单元b、c、d、e等。在对频繁对目标存储单元n执行读操作时，目标存储单元n会频繁的导通，导通电流会对目标存储单元n的存储状态持续产生影响，进而导致存储状态改变，且其中主要是将存储低阻态“1”存储单元干扰为存储高阻态“0”的存储单元。
本申请实施例提供了一种存储芯片的控制方法，在对存储芯片正常读取的过程中，如果确定某个地址的存储单元对应的失效率大于设定的失效率阈值，则可以进一步确定该地址的存储单元失效率较高的原因，包括是受到写干扰的影响还是受到读干扰的影响。根据存储单元失效率较高的原因不同，以及读写操作对存储芯片中存储单元的干扰的特点，对相应的存储单元执行的刷新操作，以将存储单元中的存储状态刷新至未受到干扰前的存储状态，进而可以提高存储芯片存储数据的稳定性，避免存储芯片由于受到写干扰或读干扰导致出现的不可纠错问题。
图6是本申请实施例提供了一种存储芯片的控制方法流程图，该可以由上述存储控制器执行，参见图6，该方法包括：
步骤601、存储控制器对第一地址对应的多个第一存储单元施加读电压。
在实施中，存储控制器可以接收主机发送的读取请求。存储控制器在接收到读取请求后，可以将读取请求对应的第一地址发送至存储芯片中的控制电路，然后由存储芯片的控制电路对第一地址对应的多个第一存储单元施加读电压，以对多个第一存储单元执行读操作。对于控制电路对多个第一存储单元施加读电压的过程可参照上述图2对应的实施例内容，此处不再赘述。其中，本申请实施例中涉及的存储芯片可以为相变存储芯片，包括的存储单元为相变存储单元，如1S1R存储单元。
步骤602、响应于多个第一存储单元的失效率大于第一阈值，对多个第二存储单元中存储的数据进行刷新。其中，第一阈值小于触发存储芯片不可纠正错误(Uncorrectable Error，UCE)的第二阈值，多个第二存储单元是受到读干扰或写干扰影响的存储单元，多个第二存储单元为多个第一存储单元，或，第二存储单元为多个第一存储单元以及与多个第一存储单元相邻的存储单元。
在对多个第一存储单元执行读操作后，可以通过控制电路中包括的感测电路得到多个第一存储单元对应的读取结果，并可以将每个第一存储单元的读取结果存储至控制电路中包括的寄存器中。其中，第一存储单元读取结果为“1”或“0”。在一示例中，在读取结果为“1”时，可表示第一存储单元的存储状态为低阻态，在读取结果为“0”时，可表示第一存储单元的存储状态为高阻态。
存储控制器可以读取寄存器中存储的读取结果，然后通过纠错算法，如纠正算法(Error Correction Code，ECC)，确定读取结果对应的失效率。其中失效率可以通过多个第一存储单元中数据失效的存储单元的个数表示，如该失效率可以是错误比特数(Fail bit count，FBC)，也可以是数据失效的存储单元的个数在多个第一存储单元中的占比。
第二存储单元即为可能受到读干扰或写干扰影响的存储单元，即PV。在多个第一存储单元的失效率大于第一阈值时，说明多个第一存储单元可能受到读干扰或写干扰的影响，导致失效率较高。因此至少可以将多个第一存储单元确定为待进行数据刷新的第二存储单元，并对多个第二存储单元中存储的数据进行刷新，以消除读干扰或写干扰对存储单元的存储状态的影响，保证存储单元存储数据的准确性。其中，第一阈值小于触发存储芯片UCE的第二阈值，以保证在确定多个第一存储单元的失效率大于第一阈值后，纠错算法能够通过对多个第一存储单元的读取结果进行纠错，进而实现对第一存储单元存储输数的刷新。在一示例中，第一阈值在第二阈值的0.5～0.99倍之间。
由于第一存储单元在受到写干扰时，其周围的存储单元也可能受到写干扰。如图5中，在对存储单元a频繁执行写操作时，除了存储单元a会受到写干扰的影响外，存储单元a产生的高温也会通过一些介质传递到存储单元b、c、d、e，使得存储单元b、c、d、e均可能受到写干扰的影响。所以在确定第一存储单元可能受到写干扰的影响时，即使不能直接确定第一存储单元是否为频繁执行写操作的存储单元，但也能确定与第一存储单元相邻的存储单元也可能受到写干扰的影响。因此在本申请实施例中，为了进一步消除写干扰对存储单元存储状态的影响，在确定第一存储单元受到写干扰影响时，可以对第一存储单元以及与第一存储单元相邻的存储单元确定为待进行数据刷新的第二存储单元，并对多个第二存储单元中存储的数据进行刷新，以消除读干扰或写干扰对存储单元的存储状态的影响，保证存储单元存储数据的准确性。
在本申请实施例中，对第二存储单元存储的数据进行刷新就是对第二存储单元对应的读取结果进行纠错处理后，将纠错处理后的数据再次写入第二存储单元。这样，由于再次写入第二存储单元的数据是经过纠错处理后的数据，所以可以保证第二存储单元存储数据的准确性，并且再次向第二存储单元写入数据后，第二存储单元的阈值电压被刷新为未受到读干扰、写干扰、阈值电压漂移等因素影响前的阈值电压，进而可以避免读取电压无法区分存储单元的存储状态的问题，能够提高存储单元存储数据的准确性。
图7是本申请实施例提供的一种阈值电压分布图。如图7所示，在多个第二存储单元在受到读干扰或写干扰后，存储“1”的第一存储单元阈值电压分布曲线和存储“0”的第二存储单元阈值电压分布曲线可能存在交叠，导致读电压(Vread)无法对部分第二存储单元的存储状态进行区分。继续参照图7，在对第二存储单元存储的数据进行刷新后，第二存储单元的阈值电压得到的刷新，存储“1”的第一存储单元阈值电压分布曲线和存储“0”的第二存储单元阈值电压分布曲线均会变“窄”，读电压(Vread)可以准确的区分第二存储单元的存储状态。
在一示例中，在确定多个第一存储单元的失效率大于第一阈值后，可以确定所述多个第一存储单元受到的干扰类型为读干扰还是写干扰。然后可以根据第一存储单元受到的干扰类型，选择进行数据刷新的存储单元的范围。下面对确定第一存储单元受到的干扰类型的方式进行介绍：
读干扰主要是将存储单元从低阻态干扰为高组态，也就是主要将存储“1”的存储单元干扰为存储“0”的存储单元。而写干扰主要是将存储单元从高阻态干扰为低组态，也就是主要将存储“0”的存储单元干扰为存储“1”的存储单元。因此在本申请实施例中，可以根据多个存储单元中，低阻态的存储单元的失效个数以及高阻态的存储单元的失效个数，确定存储单元主要是受读干扰的影响还是受写干扰的影响。
在实施中，存储控制器通过纠错算法，可以确定多个第一存储单元中失效的第一存储单元的数量，还可以确定失效的第一存储单元中，从存储“1”失效为存储“0”的第一存储单元的第一数量、以及从存储“0”失效为存储“1”的第一存储单元的第二数量。其中，第一数量和第二数量之和为多个第一存储单元中失效的存储单元的总数。
在一示例中，在第一数量大于第二数量时，也就是从存储“1”失效为存储“0”的第一存储单元在总失效的第一存储单元中的第一占比大于50％(或者从存储“0”失效为存储“1”的第一存储单元在总失效的第一存储单元中的第二占比小于50％)时，可以确定第一地址对应的多个第一存储单元主要受到读干扰的影响。在第一数量小于第二数量时，也就是从存储“0”失效为存储“1”的第一存储单元在总失效的第一存储单元中的第二占比大于50％(或者从存储“1”失效为存储“0”的第一存储单元在总失效的第一存储单元中的第一占比小于50％)时，可以确定第一地址对应的多个第一存储单元主要受到写干扰的影响。
在另一示例中，可以通过对上述第一占比或第二占比设置阈值(第三阈值)，根据第一占比或第二占比与设置的第三阈值的关系，确定存储单元主要是受读干扰的影响还是受写干扰的影响。例如，在第一占比大于第三阈值(也就是第二占比小于第三阈值)时，可以确定第一地址对应的多个第一存储单元主要受到读干扰的影响。在第一占比大于第三阈值(也就是第二占比小于第三阈值)时，可以确定第一地址对应的多个第一存储单元主要受到写干扰的影响。其中，第三阈值的具体数值可由技术人员预先设置，通过实验数据可以得到，第三阈值可设置在二分之一到五分之四之间时，对于读干扰和写干扰的准确率最高。
在本申请实施例中，在确定多个第一存储单元受到的干扰类型为读干扰时，可以对确定的第一存储单元中存储的数据进行刷新，进而避免读干扰对存储单元的影响。在确定多个第一存储单元受到的干扰类型为写干扰时，可以将多个第一存储单元以及与多个第一存储单元相邻的存储单元确定为第二存储单元，并对确定的第二存储单元中存储的数据进行刷新。这样，可以避免写干扰对第一存储单元以及第一存储单元的周围的存储单元的影响。
在一示例中，在确定多个第一存储单元受到的干扰类型为写干扰时，待进行数据刷新的第二存储单元除了包括第一存储单元的之外，还可以包括与第一存储单元在同一字线且相邻的第三存储单元以及与第一存储单元在同一位线且相邻的第三存储单元。如图5所示，第一存储单元为a，与第一存储单元在同一字线且相邻的第三存储单元包括存储单元b、c、d、e。另外，第三存储单元的高温还可能通过字线和位线传递至与第三存储单元相邻的第四存储单元，使得第四存储单元也受到写干扰的影响。因此为了保证存储单元存储数据的准确性，还可以对与第三存储单元在同一位线或同一字线且相邻的第四存储单元执行数据刷新。如图5所示，第三存储单元包括存储单元b、c、d、e，对应的第四存储单元包括存储单元f、g、h、i、j、k、l、m。在实施中，可以预先存储每个第一存储单元与第三存储单元、第四存储单元的地址对应关系，在确定第一存储单元受到写干扰操作后，可根据该地址关系，对第三存储单元和第四存储单元存储的数据进行刷新。
需要说明的是，在本申请实施例中，在确定多个第一存储单元受到的干扰类型为读干扰时，是指多个第一存储单元失效的原因主要受到读干扰的影响，不排除第一存储单元同时受到写干扰的影响。同样，在确定多个第一存储单元受到的干扰类型为写干扰时，是指多个第一存储单元失效的原因主要受到写干扰的影响，不排除第一存储单元同时受到读干扰的影响。但无论多个第一存储单元受到的干扰类型为读干扰还是写干扰，执行数据刷新的第二存储单元中均包括第一存储单元，均可以避免第一存储单元受到的读干扰或写干扰，可以解决第一存储单元失效率较高的问题，可以提高存储芯片存储数据的准确性。
在一种可实现的方式中，上述步骤601中施加的读电压为多个档位的读电压，多个档位的读电压依次增大。在一些实施例中，在对第一存储单元施加的读电压包括多个档位，在多个档位的读电压依次增大。在需要对多个第一存储单元执行读操作时，可以先对多个第一存储单元施加最低档位的读电压，如果得到的读取结果的失效率未触发存储芯片的UCE，则通过纠错算法对读取结果进行纠错，得到准确的读取结果。如果得到的读取结果的失效率触发存储芯片的UCE，则可以增加读电压的档位，将更高档位的读电压施加在多个第一存储单元，得到新的读取结果，然后再次判断读取结果对应的失效率是否触发存储芯片的UCE，并执行相同的操作，直到得到纠错后的读取结果。如果对第一存储单元分别施加多个档位的读电压，均触发UCE，则读取失败。这样，通过施加不同档位的读电压可以解决阈值电压漂移对存储单元阈值电压的影响。
在本申请实施例提供的实施例中，相对于触发存储芯片的UCE的第二阈值，设置了数值更小的第一阈值，在将读电压施加在多个第一存储单元后，如果得到的读取结果的失效率大于第一阈值，则可以使用更高档位的读电压再次施加在多个第一存储单元上。如果施加的多个档位的读电压中出现对应的失效率小于第一阈值的读取结果，则可以通过纠错算法对读取结果进行纠错，得到纠错后的读取结果。如果施加的多个档位的读电压对应读取结果的失效率均大于第一阈值，则说明多个第一存储单元受到读干扰或写干扰的影响比较严重，可能会触发存储芯片的UCE，进而先执行上述步骤602中，对多个第二存储单元中存储的数据进行刷新的处理，以保证数据的准确性。如此，通过对多个档位读电压得到的读取结果的失效率进行验证，可以减少对第一存储单元执行数据刷新操作的次数，还可以保证在第一存储单元读取失败(也就是严重受到读、写干扰影响)之前，对受到读、写干扰影响的存储单元执行数据刷新，进而可以降低存储芯片功耗、提高存储芯片存储数据的准确性。
在一示例中，在本申请示例中，如果在施加多个档位的读电压后需要对第二存储单元进行刷新，则对于第二存储单元中包括的第一存储单元，可以通过对目标读取数据进行纠错处理，得到纠错处理后的读取数据，然后将将纠错处理后的读取数据写入第一存储单元，以实现对第一存储单元的数据刷新。其中，目标读取数据为施加对多个第一存储单元多个档位的读电压分别得到的多组读取数据中对应失效率最低的一组读取数据。这样，通过对失效率最低的读取数据进行纠错，能够降低对读取数据进行纠错的准确性，进而保证第一存储单元刷新后的数据的准确性。
图8是本申请实施例提供的一种存储芯片的控制方法流程图，如图8所示，该方法包括：
步骤801、启动读流程。
对第一地址对应的多个第一存储单元施加最低档位的读电压，得到读取结果。
步骤802、确定读取结果对应的FBC是否大于设置的FBC阈值。
如果确定FBC大于设置的FBC阈值，则执行步骤803。如果确定FBC不大于设置的FBC阈值，则正常对读取结果纠错，并返回纠错后的读取结果。其中，设置的FBC阈值小于触发存储芯片UCE的FBC阈值。
步骤803、采用不同档位读电压进行read retry，找到最低的FBC。
步骤804、确定最低的FBC是否大于设置的FBC阈值。
如果确定FBC大于设置的FBC阈值，则执行步骤805。如果确定FBC不大于设置的FBC阈值，则正常对读取结果纠错，并返回纠错后的读取结果。
步骤805、确定“0→1”失效占比是否超过50％。
如果“0→1”失效的存储单元(也就是高阻态失效的存储单元)失效占比超过50％，则说明第一存储单元主要受到write disturb影响，可执行步骤806。如果“0→1”失效的存储单元占比未超过50％，则说明存储单元主要受到readdisturb影响，可执行步骤807。
步骤806、对当前存储单元及周围临近的存储单元执行刷新处理。
步骤807、对当前存储单元执行刷新处理。
如此在本申请实施例中，可以对存储单元受到读干扰和写干扰的影响进行区分，并针对读干扰和写干扰分别执行不同的刷新处理，可以提高存储芯片存储数据的稳定性，还可以降低刷新处理的功耗。
图9是本申请实施例提供的一种电子设备的示意图。在存储系统中包括主机(host)、存储控制器(Controller)以及存储芯片。其中，主机、存储控制器和存储芯片之间可通过接口连接。存储控制器设置有算法模块，其中包括Disturb解决模块、ECC模块和Read retry模块等。Disturb解决模块、ECC模块和Read retry模块可用于实现本申请实施例提供的控制方法，以提高存储芯片存储数据的稳定性。其中：
ECC模块在每次得到多个第一存储单元的读取结果对应的FBC后，可以将FBC发送至Disturb解决模块。
Disturb解决模块接收到读取结果对应的FBC后，确定是否需要对多个第一存储单元进行多次read retry(即通过多个更高档位的读电压对第一存储单元执行读操作)。如果Disturb解决模块判断需要进行read retry，则可以向Read retry模块发送read retry指令。
Read retry模块接收到read retry指令后，可以对多个第一存储单元依次多个更高档位的读电压，并将每次得到的读取结果发送至ECC模块。
ECC模块在接收到更高档位的读电压对应的读取结果，可以确定更高档位的读电压对应的读取结果分别对应的FBC，并将对应的FBC发送至Disturb解决模块。
Disturb解决模块根据更高档位的读电压对应的读取结果分别对应的FBC，确定是否需要执行数据刷新，并在需要执行数据刷新的情况下，判断disturb类型。
在disturb类型为读干扰的情况下，Disturb解决模块可以从ECC模块获取多个第一存储单元对应的纠错后的数据，将纠错后的数据写入多个第一存储单元实现对第一存储单元数据的刷新，解决了读干扰对存储单元的影响。
在disturb类型为读干扰的情况下，Disturb解决模块可以向Read retry模块发送需要读取的第三存储单元、第四存储单元的地址。Read retry模块可以根据第三存储单元、第四存储单元的地址，读取据第三存储单元、第四存储单元的读取结果，并提供给ECC模块进行纠错。Disturb解决模块可以从ECC模块获取多个第一存储单元、第三存储单元以及第四存储单元对应的纠错后的数据，将纠错后的数据写入多个第一存储单元、第三存储单元以及第四存储单元，解决了写干扰对存储单元的影响。
在本申请实施例中，在确定第一地址的存储单元失效率较高时，可根据存储单元的具体失效情况，区分存储单元主要受到的干扰。其中，在低阻态的存储单元失效的第一数目大于高阻态的存储单元失效的第二数目时，说明第一地址的存储单元主要受到读干扰的影响，因此可以对第一地址的存储单元进行写刷新，以保证第一地址的存储单元存储数据的稳定性。在高阻态的存储单元失效的第二数目大于低阻态的存储单元失效的第一数目时，说明第一地址的存储单元主要受到写干扰的影响，由于写干扰是受到周围存储单元影响，因此可以对第一地址的存储单元以及第一地址的存储单元周围的存储单元进行写刷新，以保证第一地址的存储单元以及周围的存储单元存储数据的稳定性。可见，在本申请中可以对存储单元受到读干扰和写干扰的影响进行区分，并针对读干扰和写干扰分别提供了不同的写刷新方式，能够提高存储芯片存储数据的稳定性。
基于相同的发明构思，本申请实施例还提供了一种存储控制器，该存储控制器图3所示的存储系统中包括的存储控制器。该存储控制器在对存储芯片进行读操作的过程中，可实现上述实施例提供的对存储芯片的控制方法，以根据存储芯片中第一地址对应的多个第一存储单元的失效率，确定是否存在读干扰或写干扰，并对读干扰或写干扰影响的第二存储单元执行数据刷新，以消除读干扰或写干扰的影响。其中，存储控制器实现存储芯片的控制方法的过程可参照上述方法实施例，此处不再进行赘述。
基于相同的发明构思，本申请实施例还提供了一种存储系统，该存储控制器图3所示的存储系统，包括存储控制器和一个或多个存储芯片。其中，存储控制器在对存储芯片进行读操作的过程中，可实现上述实施例提供的对存储芯片的控制方法，以根据存储芯片中第一地址对应的多个第一存储单元的失效率，确定是否存在读干扰或写干扰，并对读干扰或写干扰影响的第二存储单元执行数据刷新，以消除读干扰或写干扰的影响。其中，存储控制器实现存储芯片的控制方法的过程可参照上述方法实施例，此处不再进行赘述。
本申请中术语“第一”“第二”等字样用于对作用和功能基本相同的相同项或相似项进行区分，应理解，“第一”、“第二”之间不具有逻辑或时序上的依赖关系，也不对数量和执行顺序进行限定。还应理解，尽管以下描述使用术语第一、第二等来描述各种元素，但这些元素不应受术语的限制。这些术语只是用于将一元素与另一元素区别分开。本申请中术语“至少一个”的含义是指一个或多个，本申请中术语“多个”的含义是指两个或两个以上。
以上描述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到各种等效的修改或替换，这些修改或替换都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以权利要求的保护范围为准。

Claims (18)

  1. 一种存储芯片的控制方法，其特征在于，所述方法包括：
    对第一地址对应的多个第一存储单元施加读电压；
    响应于所述多个第一存储单元的失效率大于第一阈值，对多个第二存储单元中存储的数据进行刷新，其中，所述第一阈值小于触发所述存储芯片不可纠正错误UCE的第二阈值，所述多个第二存储单元是受到读干扰或写干扰影响的存储单元，所述多个第二存储单元为多个第一存储单元，或，所述第二存储单元为所述多个第一存储单元以及与所述多个第一存储单元相邻的存储单元。
  2. 根据权利要求1所述的方法，其特征在于，所述响应于所述多个第一存储单元的失效率大于第一阈值，对多个第二存储单元中存储的数据进行刷新，包括：
    响应于所述多个第一存储单元的失效率大于第一阈值，确定所述多个第一存储单元对应的干扰类型，所述干扰类型为读干扰或写干扰；
    在确定所述干扰类型为读干扰的情况下，确定所述多个第一存储单元为多个第二存储单元，对所述第二存储单元中存储的数据进行刷新；
    在确定所述干扰类型为读干扰的情况下，确定所述多个第一存储单元以及与所述多个第一存储单元相邻的存储单元为第二存储单元，对所述第二存储单元中存储的数据进行刷新。
  3. 根据权利要求2所述的方法，其特征在于，所述确定所述多个第一存储单元对应的干扰类型，包括：
    在所述多个第一存储单元中，确定失效的低阻态第一存储单元的个数在失效的第一存储单元总数中的占比；
    在所述占比大于第三阈值的情况下，确定所述干扰类型为读干扰，在所述占比小于或等于所述第三阈值的情况下，确定所述干扰类型为写干扰。
  4. 根据权利要求1至3任一项所述的方法，其特征在于，所述对第一地址对应的多个第一存储单元施加读电压，包括：
    对第一地址对应的多个第一存储单元施加多个档位的读电压，所述多个档位的读电压依次增大；
    所述响应于所述多个第一存储单元的失效率大于第一阈值，对多个第二存储单元中存储的数据进行刷新，包括：
    响应于对所述多个第一存储单元施加每个档位的读电压得到的失效率均大于所述第一阈值，对多个第二存储单元中存储的数据进行刷新。
  5. 根据权利要求4所述的方法，其特征在于，所述对第一地址对应的多个第一存储单元施加多个档位的读电压之后，还包括：
    对目标读取数据进行纠错处理，得到纠错处理后的读取数据，所述目标读取数据为施加多个档位的读电压分别得到的多组读取数据中对应失效率最低的一组读取数据；
    所述对所述多个第二存储单元中存储的数据进行刷新，包括：
    将所述纠错处理后的读取数据写入所述多个第二存储单元中包括的第一存储单元。
  6. 根据权利要求2所述的方法，其特征在于，与所述多个第一存储单元相邻的存储单元包括与所述多个第一存储单元在同一位线或字线且相邻的第三存储单元，所述方法还包括：
    确定与所述第三存储单元在同一位线或同一字线且相邻的第四存储单元为第二存储单元。
  7. 根据权利要求3所述的方法，其特征在于，所述第三阈值在二分之一到五分之四之间。
  8. 根据权利要求1至7任一项所述的方法，其特征在于，所述第一存储单元为相变存储单元。
  9. 一种存储控制器，其特征在于，所述存储控制器与存储芯片连接，所述存储控制器，用于：
    对所述存储芯片中第一地址对应的多个第一存储单元施加读电压；
    响应于所述多个第一存储单元的失效率大于第一阈值，对多个第二存储单元中存储的数据进行刷新，其中，所述第一阈值小于触发所述存储芯片不可纠正错误UCE的第二阈值，所述多个第二存储单元是受到读干扰或写干扰影响的存储单元，所述多个第二存储单元为多个第一存储单元，或，所述第二存储单元为所述多个第一存储单元以及与所述多个第一存储单元相邻的存储单元。
  10. 根据权利要求9所述的存储控制器，其特征在于，所述存储控制器，用于：
    响应于所述多个第一存储单元的失效率大于第一阈值，确定所述多个第一存储单元对应的干扰类型，所述干扰类型为读干扰或写干扰；
    在确定所述干扰类型为读干扰的情况下，确定所述多个第一存储单元为多个第二存储单元，对所述第二存储单元中存储的数据进行刷新；
    在确定所述干扰类型为读干扰的情况下，确定所述多个第一存储单元以及与所述多个第一存储单元相邻的存储单元为第二存储单元，对所述第二存储单元中存储的数据进行刷新。
  11. 根据权利要求10所述的存储控制器，其特征在于，所述存储控制器，用于：
    在所述多个第一存储单元中，确定失效的低阻态第一存储单元的个数在失效的第一存储单元总数中的占比；
    在所述占比大于第三阈值的情况下，确定所述干扰类型为读干扰，在所述占比小于或等于所述第三阈值的情况下，确定所述干扰类型为写干扰。
  12. 根据权利要求9至11任一项所述的存储控制器，其特征在于，所述存储控制器，用于：
    对第一地址对应的多个第一存储单元施加多个档位的读电压，所述多个档位的读电压依次增大；
    响应于对所述多个第一存储单元施加每个档位的读电压得到的失效率均大于所述第一阈值，对多个第二存储单元中存储的数据进行刷新。
  13. 根据权利要求12所述的存储控制器，其特征在于，所述存储控制器，还用于：
    对目标读取数据进行纠错处理，得到纠错处理后的读取数据，所述目标读取数据为施加多个档位的读电压分别得到的多组读取数据中对应失效率最低的一组读取数据；
    将所述纠错处理后的读取数据写入所述多个第二存储单元中包括的第一存储单元。
  14. 根据权利要求10所述的存储控制器，其特征在于，与所述多个第一存储单元相邻的存储单元包括与所述多个第一存储单元在同一位线或字线且相邻的第三存储单元，所述存储控制器，还用于：
    确定与所述第三存储单元在同一位线或同一字线且相邻的第四存储单元为第二存储单元。
  15. 根据权利要求11所述的存储控制器，其特征在于，所述第三阈值在二分之一到五分之四之间。
  16. 根据权利要求9至15任一项所述的存储控制器，其特征在于，所述第一存储单元为相变存储单元。
  17. 一种存储系统，其特征在于，所述存储系统包括如权利要求9至16任一项所述的存储控制器，以及与所述存储控制器连接的至少一个存储芯片。
  18. 一种电子设备，其特征在于，所述电子设备包括处理器以及如权利要求17所述的存储系统；
    所述处理器用于向所述存储系统发送读写指令，以使所述存储系统实现读写操作。
PCT/CN2025/080567 2024-06-27 2025-03-04 存储芯片的控制方法、存储控制器和存储系统 Pending WO2026001065A1 (zh)

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