WO2025256359A1 - 显示面板及其制备方法、显示装置 - Google Patents

显示面板及其制备方法、显示装置

Info

Publication number
WO2025256359A1
WO2025256359A1 PCT/CN2025/095933 CN2025095933W WO2025256359A1 WO 2025256359 A1 WO2025256359 A1 WO 2025256359A1 CN 2025095933 W CN2025095933 W CN 2025095933W WO 2025256359 A1 WO2025256359 A1 WO 2025256359A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
pixel
barrier
substrate
dam
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/CN2025/095933
Other languages
English (en)
French (fr)
Inventor
万晨星
何传友
苟结
郝瑞
黄强
卢嘉铭
潘明希
滕毅
魏来蕴
张冬梅
张永胜
张忠忠
朱留东
张鹏
程旭辉
刘爽
张萍娱
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Chengdu BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Publication of WO2025256359A1 publication Critical patent/WO2025256359A1/zh
Pending legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/873—Encapsulations
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • G09F9/335—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes being organic light emitting diodes [OLED]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/871—Self-supporting sealing arrangements
    • H10K59/8722—Peripheral sealing arrangements, e.g. adhesives, sealants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass

Definitions

  • This application relates to, but is not limited to, the field of display technology, specifically to a display panel and its manufacturing method, and a display device.
  • a barrier dam is typically installed on one side of the edge area of the display panel to prevent material from the organic encapsulation layer from spilling out to the outside of the barrier dam.
  • an open vapor deposition mask is not used during the formation of the light-emitting layer; instead, an etching process is used to pattern the light-emitting layer.
  • the height of the barrier dam is reduced, decreasing its ability to block the organic encapsulation layer. Material from the organic encapsulation layer at the edge area can easily overflow to the side of the barrier dam away from the display area, allowing moisture to easily penetrate the organic encapsulation layer and enter the display area, leading to encapsulation failure.
  • An embodiment of this application provides a display panel, comprising: a substrate, the substrate including a display area and an edge area surrounding the display area; a pixel defining layer located on one side of the display area of the substrate; a first barrier dam located on one side of the edge area of the substrate; a second barrier dam located on one side of the substrate between the pixel defining layer and the first barrier dam, the material of the second barrier dam being different from the material of the pixel defining layer; and an encapsulation layer, the encapsulation layer comprising: an organic encapsulation layer located on the side of the pixel defining layer opposite to the substrate and extending to cover the second barrier dam; wherein the first barrier dam surrounds the organic encapsulation layer.
  • Embodiments of this application also provide a method for manufacturing a display panel, comprising: providing a substrate, the substrate including a display area and an edge area surrounding the display area; forming a pixel defining layer on one side of the display area of the substrate; forming a first barrier dam on one side of the edge area of the substrate; forming a second barrier dam located on one side of the substrate between the pixel defining layer and the first barrier dam, the second barrier dam being made of a different material than the pixel defining layer; and forming an encapsulation layer, comprising: forming an organic encapsulation layer on the side of the pixel defining layer and the second barrier dam facing away from the substrate; wherein the first barrier dam surrounds the organic encapsulation layer.
  • Embodiments of this application also provide a display device, including the display panel described above in the embodiments of this application.
  • Figure 1 is a schematic diagram of the structure of a display panel provided in one embodiment
  • Figure 2 is a schematic diagram of the structure of a display panel provided in another embodiment
  • Figure 3 is a partial schematic diagram of Figure 2;
  • Figure 4 is a schematic diagram of the structure of a display panel according to an embodiment of this application.
  • Figure 5 is a structural schematic diagram of a second barrier dam according to an embodiment of this application.
  • Figure 6 is a structural schematic diagram of the second barrier dam according to another embodiment of this application.
  • Figure 7 is a structural schematic diagram of the second barrier dam according to another embodiment of this application.
  • Figure 8 is a structural schematic diagram of the second barrier dam according to another embodiment of this application.
  • Figure 9 is a partial structural diagram of the display area according to an embodiment of this application.
  • Figure 10 is a schematic diagram of the structure of a display panel according to another embodiment of this application.
  • Figure 11 is a flowchart of a method for manufacturing a display panel according to an embodiment of this application.
  • FIGS 12 and 13 are schematic diagrams of the display panel manufacturing process in one embodiment of this application.
  • a display panel provided in one embodiment, referring to FIG1, includes: a substrate 10, the substrate 10 including a display area and an edge area surrounding the display area; a barrier dam B0 located on one side of the edge area of the substrate 10; a pixel defining layer (not shown) located on the display area side of the substrate 10, the pixel defining layer having a pixel opening; a light-emitting layer (not shown) located in the pixel opening; a support pillar (not shown) located on the side of the pixel defining layer opposite to the substrate 10; and an encapsulation layer (not shown) including: an organic encapsulation layer (not shown); wherein the barrier dam B0 surrounds the organic encapsulation layer.
  • the support pillar is used to support the vapor deposition mask during the vapor deposition of the light-emitting layer.
  • a portion of the retaining dams B0 comprises a first retaining layer 11, a second retaining layer 12, a third retaining layer 13, and a fourth retaining layer 14, wherein the material of the fourth retaining layer 14 is the same as the material of the supporting columns.
  • a portion of the retaining dams B0 comprises a first retaining layer, a second retaining layer, and a third retaining layer, wherein the material of the third retaining layer is the same as the material of the supporting columns.
  • FIG2 Another embodiment of the display panel, referring to FIG2, includes: a substrate 100, the substrate 100 including a display area and an edge area surrounding the display area; a barrier dam B1 located on one side of the edge area of the substrate 100; a pixel defining layer 103 located on one side of the display area of the substrate 100, the pixel defining layer 103 having a pixel opening; a light-emitting layer (not shown) located in the pixel opening; and an encapsulation layer (not shown), the encapsulation layer including: an organic encapsulation layer 101; wherein the barrier dam B1 is used to surround the organic encapsulation layer 101.
  • the steps for forming the light-emitting layer include: forming an initial light-emitting layer; etching the initial light-emitting layer to form the light-emitting layer. Since a vapor deposition mask is not required during the formation of the light-emitting layer, the support pillars are eliminated.
  • the barrier dam B1 does not contain a film layer of the same material as the support pillars.
  • a portion of the barrier dams B1 include a stacked first barrier layer 11, a second barrier layer 12, and a third barrier layer 13, with the third barrier layer 13 made of the same material as the pixel defining layer 103.
  • a portion of the barrier dams B1 also include a stacked first barrier layer and a second barrier layer, with the second barrier layer made of the same material as the pixel defining layer 103. Because the barrier dam B1 does not contain a film layer of the same material as the support pillars, the height of the barrier dam B1 is reduced, and its ability to block the organic encapsulation layer 101 is weakened. Material from the organic encapsulation layer 101 on the edge area easily overflows to the side of the barrier dam B1 facing away from the display area, allowing moisture to easily enter the display area through the organic encapsulation layer 101, leading to encapsulation failure.
  • embodiments of this application provide a display panel and its manufacturing method, as well as a display device, which improves packaging reliability.
  • the terms “center,” “upper,” “lower,” “left,” “right,” “vertical,” “horizontal,” “inner,” and “outer,” etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. In addition, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
  • connection should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection.
  • connection can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection.
  • a display panel comprising: a substrate 200, the substrate 200 including a display area A1 and an edge area A2 surrounding the display area A1; a pixel defining layer 240 located on one side of the display area A1 of the substrate 200; a first barrier dam B2 located on one side of the edge area A2 of the substrate 200; a second barrier dam C located on one side of the substrate 200 between the pixel defining layer 240 and the first barrier dam B2, the material of the second barrier dam C being different from the material of the pixel defining layer 240; and an encapsulation layer comprising: an organic encapsulation layer 201 located on the side of the pixel defining layer 240 away from the substrate 200 and extending to cover the second barrier dam C; wherein the first barrier dam B2 surrounds the organic encapsulation layer 201.
  • a second barrier dam C is provided, and the material of the second barrier dam C is different from the material of the pixel defining layer 240.
  • the second barrier dam C and the first barrier dam B2 are used to jointly block the flow of the organic encapsulation layer 201 during the formation of the organic encapsulation layer 201, preventing the material of the organic encapsulation layer 201 on the edge area A2 from overflowing to the side of the first barrier dam B2 away from the display area A1, thereby avoiding and reducing the probability of encapsulation failure.
  • the display panel is a flexible display panel, such as an organic light-emitting diode display (OLED display panel).
  • the display panel is a rigid display panel, such as a liquid crystal display panel.
  • substrate 200 is a driving substrate, and substrate 200 includes driving transistors.
  • the display panel further includes: pixel structures located in the pixel defining layer 240, wherein multiple pixel structures have multiple pixel colors; and a first inorganic encapsulation layer located on the surface of the pixel structures facing away from the substrate.
  • the pixel structures include an anode layer (not shown), a light-emitting layer 300, and a cathode layer 230, wherein the light-emitting layer 300 is located between the anode layer and the cathode layer 230, and the cathode layer 230 is located on the side of the anode layer facing away from the substrate 200.
  • a portion of the pixel structures have red (R) pixel colors, and the corresponding light-emitting layer 300 emits red light.
  • a portion of the pixel structures have green (G) pixel colors, and the corresponding light-emitting layer 300 emits green light.
  • a portion of the pixel structures have blue (B) pixel colors, and the corresponding light-emitting layer 300 emits blue light.
  • the cathode layers 230 in different pixel structures are spaced apart.
  • the cathode layers 230 in each pixel structure are spaced apart.
  • the display panel further includes: conductive isolation pillars (not shown), located on the side of the pixel defining layer 240 facing away from the substrate 200 between adjacent pixel structures; wherein the cathode layers 230 are connected to the conductive isolation pillars.
  • the conductive isolation pillars can electrically connect the cathode layers 230 in different pixel structures.
  • the conductive isolation pillars can also isolate light emitted by adjacent pixel structures, avoiding optical crosstalk between adjacent pixel structures.
  • the material of the conductive isolation pillars is a light-shielding conductive material.
  • the display panel further includes a first inorganic encapsulation layer located on the side surface of the pixel structure facing away from the substrate 200.
  • a portion of the pixel structures of pixel colors have the first inorganic encapsulation layer 203b disposed on the side surface facing away from the substrate 200.
  • Another portion of the pixel structures of pixel colors have the first inorganic encapsulation layer 203a disposed on the side surface facing away from the substrate 200.
  • Yet another portion of the pixel structures of pixel colors have the first inorganic encapsulation layer 203 disposed on the side surface facing away from the substrate 200.
  • the first inorganic encapsulation layers 203b, 203a, and 203 are made of the same material or at least partially different materials.
  • FIG9 illustrates the first inorganic encapsulation layers corresponding to three different pixel structures.
  • the pixel colors are not limited to three, and the first inorganic encapsulation layer is disposed on the side surface facing away from the substrate 200 for each pixel structure of different pixel colors.
  • the organic encapsulation layer 201 is located on the side of the first inorganic encapsulation layer opposite to the substrate 200.
  • the organic encapsulation layer 201 covers the first inorganic encapsulation layer, and exemplarily, the organic encapsulation layer 201 covers the first inorganic encapsulation layer 203, the first inorganic encapsulation layer 203a, and the first inorganic encapsulation layer 203b.
  • the second barrier dam C comprises one or more stacked second sub-barrier dams; the material of one layer of the second sub-barrier dam is the same as the material of the first inorganic encapsulation layer on the surface of the pixel structure of a pixel color.
  • the multiple pixel structures have M pixel colors; M is an integer greater than or equal to 2.
  • the second barrier dam C includes a first layer of second sub-barrier dams to an Nth layer of second sub-barrier dams stacked sequentially, where N is an integer greater than or equal to 1 and less than or equal to M.
  • the materials of the first layer of second sub-barrier dams to the Nth layer of second sub-barrier dams correspond one-to-one with the materials of the first inorganic encapsulation layer on the surface of the pixel structures with N different pixel colors.
  • the first layer second sub-barrier is located between the Nth layer second sub-barrier and the substrate 200.
  • the second barrier dam C includes a first-layer second sub-barrier dam 221, a second-layer second sub-barrier dam 222, and a third-layer second sub-barrier dam 223.
  • the first-layer second sub-barrier dam 221 is made of the same material as the first inorganic encapsulation layer 203b on the surface of the red pixel structure.
  • the second-layer second sub-barrier dam 222 is made of the same material as the first inorganic encapsulation layer 203a on the surface of the green pixel structure.
  • the third-layer second sub-barrier dam 223 is made of the same material as the first inorganic encapsulation layer 203 on the surface of the blue pixel structure.
  • the second barrier dam C includes a first second sub-barrier dam 221 and a second second sub-barrier dam 222.
  • the first second sub-barrier dam 221 is made of the same material as the first inorganic encapsulation layer 203a on the surface of the green pixel structure.
  • the second second sub-barrier dam 222 is made of the same material as the first inorganic encapsulation layer 203 on the surface of the blue pixel structure.
  • the Nth layer of second sub-barriers in each second barrier dam C are connected together, and the interval between any n’th layer of second sub-barriers in each second barrier dam C is an integer greater than or equal to 1 and less than N. Because the Nth layer of second sub-barriers in each second barrier dam C are connected together, the moisture blocking capability of the edge region A2 is improved.
  • the second barrier dam C includes a first layer of second sub-barrier dam 221, a second layer of second sub-barrier dam 222, and a third layer of second sub-barrier dam 223.
  • the third layer of second sub-barrier dam 223 of each second barrier dam C is connected together, the first layer of second sub-barrier dam 221 of each second barrier dam C is spaced apart, and the second layer of second sub-barrier dam 222 of each second barrier dam C is spaced apart.
  • the second barrier dam C includes a first layer of second sub-barrier dams 221 and a second layer of second sub-barrier dams 222.
  • the second layers of second sub-barrier dams 222 of each second barrier dam C are connected together.
  • the first layers of second sub-barrier dams 221 of each second barrier dam C are spaced apart.
  • a portion of the second barrier dams C includes a first-layer second sub-barrier dam 221, a second-layer second sub-barrier dam 222, and a third-layer second sub-barrier dam 223, while another portion of the second barrier dams C includes a first-layer second sub-barrier dam 221 and a second-layer second sub-barrier dam 222.
  • the third-layer second sub-barrier dam 223 of the portion of the second barrier dams C and the second-layer second sub-barrier dam 222 of the other portion of the second barrier dams C are connected together.
  • the first-layer second sub-barrier dam 221 and the second-layer second sub-barrier dam 222 of the portion of the second barrier dams C are both spaced apart from the first-layer second sub-barrier dam 221 of the other portion of the second barrier dams C.
  • the membrane layers in different second barrier dams C may be spaced apart.
  • the height of the second barrier dam C along the direction perpendicular to the surface of the substrate 200 can be set to approximately 3 micrometers to 4 micrometers.
  • the second barrier dam C is formed during the formation of the first inorganic encapsulation layer.
  • the height setting of the second barrier dam C is related to the number of pixel colors in the multiple pixel structures. The more pixel colors in the multiple pixel structures, the higher the upper limit of the number of film layers in the second barrier dam C, and the higher the upper limit of the height of the second barrier dam C.
  • the height dimension of the second barrier dam C in the direction perpendicular to the surface of the substrate 200 is smaller than the height dimension of the first barrier dam B2 in the direction perpendicular to the surface of the substrate 200.
  • the height dimension of the second barrier dam C in the direction perpendicular to the surface of the substrate 200 is not limited.
  • the width of the second barrier dam C in the direction from the display area A1 to the edge area A2 can be set to approximately 10-20 micrometers, for example, 10 micrometers, 15 micrometers, or 20 micrometers. This can improve the positional stability of the second barrier dam C and prevent it from tipping over during the process.
  • the width of the second barrier dam C is not limited.
  • the second barrier dam C has an annular structure surrounding the pixel defining layer 240.
  • the second barrier dam C provides some degree of obstruction to the organic encapsulation layer 201 at any position in the circumferential direction.
  • the number of second blocking dams C is one in the direction from the display area A1 to the edge area A2.
  • the number of second blocking dams is not limited.
  • the number of second blocking dams C should also take into account the space constraints between the pixel limiting layer 240 and the first blocking dam B2, and a reasonable number of second blocking dams C can be set according to actual conditions.
  • the plurality of second barrier dams C have the same number of membrane layers. Referring to Figures 4 and 6, each second barrier dam C has three membrane layers. Referring to Figure 8, each second barrier dam C has two membrane layers.
  • At least two second barrier dams C have different numbers of membrane layers.
  • some of the second barrier dams C have two membrane layers, and some of the second barrier dams C have three membrane layers.
  • the display panel further includes a planarization layer located between the pixel defining layer 240 and the substrate 200.
  • the planarization layer extends to one side of a portion of the edge region A2 and is spaced from the first barrier dam B2. Specifically, along the direction from the display region A1 to the edge region A2, the distance between the pixel defining layer 240 and the first barrier dam B2 is greater than the distance between the planarization layer and the first barrier dam B2.
  • the planarization layer has a multi-layer structure.
  • the planarization layer includes a first planarization layer 251 and a second planarization layer 252, with the first planarization layer 251 located between the second planarization layer 252 and the substrate 200.
  • the planarization layer may be a single-layer structure.
  • the second barrier dam C is located on the side of the planarization layer between the pixel defining layer 240 and the first barrier dam B2 facing away from the substrate 200.
  • the second barrier dam C is located between the planarization layer and the first barrier dam B2.
  • a portion of the second barrier dams are located on the side of the planarization layer between the pixel defining layer 240 and the first barrier dam B2 facing away from the substrate 200, and another portion of the second barrier dams are located between the planarization layer and the first barrier dam B2.
  • the display panel further includes a cathode lead-out layer 280 located on one side of the substrate 200 between the planarization layer and the first barrier dam B2, and extending to the side of the planarization layer opposite to the substrate 200.
  • a cathode layer 230 in a portion of the pixel structure extends to overlap with the cathode lead-out layer 280 on the planarization layer side.
  • the cathode lead-out layer 280 is used to provide a ground level to the cathode layer 230.
  • the cathode lead-out layer 280 is made of the same material as the anode layer. In other embodiments, the cathode lead-out layer 280 is made of a different material than the anode layer.
  • a second barrier dam C located between the flat layer and the first barrier dam B2 covers the cathode lead-out layer 280.
  • a second barrier dam C located on one side of the flat layer between the pixel defining layer 240 and the first barrier dam B2 covers the cathode layer 230.
  • the first barrier dam B2 includes a first portion 274 and a second portion 273 located between the first portion 274 and the substrate 200.
  • the material of the second portion 273 is the same as the material of the pixel defining layer 240.
  • the first portion 274 includes one or more stacked first sublayers, the material of which is the same as the material of a first inorganic encapsulation layer on the surface of a pixel structure of a pixel color.
  • Figures 4 and 10 illustrate a first portion 274 comprising a first sublayer, the material of which is the same as that of the first inorganic encapsulation layer 203.
  • the first portion 274 comprises multiple first sublayers, each of which is made of the same material as the first inorganic encapsulation layer on the surface of a pixel structure of a pixel color.
  • the first barrier dam B2 further includes a third portion located between the second portion 273 and the substrate 200.
  • the material of the third portion is the same as that of the planarization layer.
  • the third portion in a portion of the first barrier dams B2, is a multilayer structure.
  • the third portion includes a first third sublayer 271 and a second third sublayer 272.
  • the material of the first third sublayer 271 is the same as that of the first planarization layer 251, and the material of the second third sublayer 272 is the same as that of the second planarization layer 252.
  • the second third sublayer 272 is located between the first third sublayer 271 and the second portion 273.
  • the third portion is a single-layer structure, i.e., the third portion of the first barrier dam B2 includes one third sublayer. This application does not limit the number of film layers in the third portion.
  • the encapsulation layer further includes a second inorganic encapsulation layer 202, located on the side of the organic encapsulation layer 201 facing away from the substrate 200.
  • the display panel further includes a carrier layer 260, which comprises a first carrier layer and a second carrier layer.
  • the carrier layer 260 is located between the cathode layer 230 and the pixel defining layer 240, and between the cathode layer 230 and the anode layer.
  • the first carrier layer between the cathode layer 230 and the anode layer is located between the cathode layer 230 and the light-emitting layer 300
  • the second carrier layer between the cathode layer 230 and the anode layer is located between the anode layer and the light-emitting layer 300.
  • the first carrier layer includes an electron transport layer, a hole blocking layer, and an electron injection layer.
  • the second carrier layer includes a hole transport layer, an electron blocking layer, and a hole injection layer.
  • the carrier layer 260 shown in Figures 4 and 10 extends to the side of the pixel defining layer 240 opposite to the substrate 200.
  • step S1 providing a substrate, the substrate including a display area and an edge area surrounding the display area; step S2: forming a pixel defining layer on one side of the display area of the substrate; step S3: forming a first barrier dam on one side of the edge area of the substrate; step S4: forming a second barrier dam, the second barrier dam being located on one side of the substrate between the pixel defining layer and the first barrier dam, the material of the second barrier dam being different from the material of the pixel defining layer; and step S5: forming an encapsulation layer, including: forming an organic encapsulation layer on the side of the pixel defining layer and the second barrier dam facing away from the substrate; wherein, the first barrier dam surrounds the organic encapsulation layer.
  • FIGS 12 and 13 are schematic diagrams of the display panel manufacturing process in another embodiment of this application.
  • a substrate 200 is provided, the substrate 200 including a display area A1 and an edge area A2 surrounding the display area A1; a pixel defining layer 240 is formed on one side of the display area A1 of the substrate 200; a first blocking dam B2 is formed on one side of the edge area A2 of the substrate 200; a second blocking dam C is formed, the second blocking dam C is located on one side of the substrate 200 between the pixel defining layer 240 and the first blocking dam B2, and the material of the second blocking dam B2 is different from the material of the pixel defining layer 240.
  • substrate 200 is a driving substrate, and substrate 200 includes driving transistors.
  • the method for manufacturing a display panel further includes: before forming the pixel defining layer 240, forming a planarization layer on the display area A1 side of the substrate 200, the planarization layer being spaced apart from the first barrier dam B2.
  • the pixel defining layer 240 is located on the side of the planarization layer facing away from the substrate 200.
  • the planarization layer is a multi-layer structure.
  • the step of forming the planarization layer includes: forming a first planarization layer 251 on one side of the display area A1 of the substrate 200; and forming a second planarization layer 252 on the side of the first planarization layer 251 opposite to the substrate 200.
  • the planarization layer is a single-layer structure.
  • the planarization layer further extends to one side of a portion of the edge region A2. Specifically, along the direction from the display region A1 to the edge region A2, the spacing between the pixel defining layer 240 and the first barrier dam B2 is greater than the spacing between the planarization layer and the first barrier dam B2.
  • the display panel fabrication method further includes: forming a plurality of pixel structures in a pixel defining layer 240, the plurality of pixel structures having a plurality of pixel colors.
  • the plurality of pixel structures have M pixel colors; M is an integer greater than or equal to 2.
  • the pixel structure includes an anode layer (not shown), a light-emitting layer 300, and a cathode layer 230, the light-emitting layer 300 being located between the anode layer and the cathode layer 230, and the cathode layer 230 being located on the side of the anode layer facing away from the substrate 200.
  • a portion of the pixel structures have red (R) pixel colors, and the corresponding light-emitting layer 300 is used to emit red light.
  • a portion of the pixel structures have green (G) pixel colors, and the corresponding light-emitting layer 300 is used to emit green light.
  • a portion of the pixel structures have blue (B) pixel colors, and the corresponding light-emitting layer 300 is used to emit blue light.
  • the cathode layers 230 in different pixel structures are spaced apart.
  • pixel structures of different pixel colors are formed sequentially.
  • the steps of forming a pixel structure of any pixel color include: forming an anode layer, forming an initial light-emitting layer and an initial cathode layer, etching the initial light-emitting layer and the initial cathode layer to form a light-emitting layer 300 and an initial cathode layer 230.
  • the step of forming the anode layer of a pixel structure of any pixel color includes: forming an initial anode layer before forming an initial light-emitting layer, etching the initial anode layer during the etching process of the initial light-emitting layer and the initial cathode layer, so that the initial anode layer forms an anode layer.
  • the anode layers of pixel structures with different pixel colors can be formed in the same process.
  • the step of forming a pixel structure of any pixel color further includes: forming a second initial carrier layer before forming an initial light-emitting layer; forming a first initial carrier layer on the side of the initial light-emitting layer away from the substrate 200 before forming an initial cathode layer; and etching the second initial carrier layer and the first initial carrier layer during the etching process of the initial light-emitting layer and the initial cathode layer, so that the second initial carrier layer forms a second carrier layer and the first initial carrier layer forms a first carrier layer.
  • carrier layer 260 in a portion of the pixel structure extends to the side of pixel defining layer 240 away from substrate 200.
  • a first inorganic encapsulation layer is formed during the formation of the pixel structure; wherein, the first inorganic encapsulation layers on one side of the pixel structure for different pixel colors are formed sequentially.
  • the step of forming the first inorganic encapsulation layer on one side of the pixel structure for any pixel color includes: before etching the initial light-emitting layer and the initial cathode layer, forming an initial first inorganic encapsulation layer on the side of the initial cathode layer facing away from the substrate 200; during the etching of the initial light-emitting layer and the initial cathode layer, etching the initial first inorganic encapsulation layer to form the first inorganic encapsulation layer.
  • the first inorganic encapsulation layer, formed during the formation of the pixel structure protects the pixel structure and reduces etching damage to the pixel structure.
  • Forming the second barrier dam C includes forming one or more stacked second sub-barrier dams, and forming a first inorganic encapsulation layer on the pixel structure surface of a pixel color during the formation of a second sub-barrier dam.
  • the cathode layer 230 is spaced apart in each pixel structure.
  • the light-emitting layer is spaced apart in each pixel structure.
  • the carrier layer 260 is spaced apart in each pixel structure.
  • the multiple pixel structures have M pixel colors; M is an integer greater than or equal to 2.
  • the second barrier dam C includes a first layer of second sub-barrier dams to an Nth layer of second sub-barrier dams stacked sequentially, where N is an integer greater than or equal to 1 and less than or equal to M.
  • the materials of the first layer of second sub-barrier dams to the Nth layer of second sub-barrier dams correspond one-to-one with the materials of the first inorganic encapsulation layer on the surface of the pixel structures with N different pixel colors.
  • a first inorganic encapsulation layer 203b is formed on the surface of a pixel structure of a certain pixel color facing away from the substrate 200.
  • a first inorganic encapsulation layer 203a is formed on the surface of a pixel structure of another pixel color facing away from the substrate 200.
  • Yet another portion of the pixel structure of a pixel color forms a first inorganic encapsulation layer 203 on the surface of a pixel structure facing away from the substrate 200.
  • the materials of the first inorganic encapsulation layers 203b, 203a, and 203 are the same or at least partially different.
  • Figure 9 illustrates the first inorganic encapsulation layers corresponding to pixel structures of three different pixel colors. In other embodiments, the pixel colors are not limited to three; the first inorganic encapsulation layer is formed on the surface of the pixel structure of different pixel colors facing away from the substrate 200.
  • the second blocking dam C includes a first-layer second sub-blocking dam 221, a second-layer second sub-blocking dam 222, and a third-layer second sub-blocking dam 223.
  • the first-layer second sub-blocking dam 221 is made of the same material as the first inorganic encapsulation layer 203b on the surface of the red pixel structure.
  • the second-layer second sub-blocking dam 222 is made of the same material as the first inorganic encapsulation layer 203a on the surface of the green pixel structure.
  • the third-layer second sub-blocking dam 223 is made of the same material as the first inorganic encapsulation layer 203 on the surface of the blue pixel structure.
  • N is less than M
  • the materials of the first layer second sub-barrier dam to the Nth layer second sub-barrier dam correspond one-to-one with the materials of the first inorganic encapsulation layer on the surface of the pixel structure of N different pixel colors.
  • the Nth layer of second sub-barriers in each second barrier dam C are connected together, and the interval between any n’th layer of second sub-barriers in each second barrier dam C is an integer greater than or equal to 1 and less than N.
  • the membrane layers in different second barrier dams C may be spaced apart.
  • the height dimension of the second barrier dam C along the direction perpendicular to the surface of the substrate 200 can be set to 3 micrometers to 4 micrometers.
  • the height of the second barrier dam C in the direction perpendicular to the surface of the substrate 200 can be set to be less than the height of the first barrier dam B2 in the direction perpendicular to the surface of the substrate 200. In other embodiments, the height of the second barrier dam C in the direction perpendicular to the surface of the substrate 200 is not limited.
  • the width of the second barrier dam C in the direction from the display area A1 to the edge area A2 can be set to approximately 10 micrometers to 20 micrometers. In other embodiments, the width of the second barrier dam C is not limited.
  • the second barrier dam C is a ring-shaped structure surrounding the pixel defining layer 240.
  • the number of second blocking dams C is one in the direction from the display area A1 to the edge area A2.
  • the number of second blocking dams C is multiple, extending from the display area A1 to the edge area A2.
  • the number of membrane layers of the plurality of second barrier dams C is the same. In another embodiment, the number of membrane layers of at least two second barrier dams C is different.
  • the display panel fabrication method further includes: forming conductive isolation pillars (not shown), the conductive isolation pillars being located on the side of the pixel defining layer 240 between adjacent pixel structures facing away from the substrate 200; wherein the cathode layer 230 is connected to the conductive isolation pillars.
  • the conductive isolation pillars can electrically connect the cathode layers 230 in different pixel structures.
  • the conductive isolation pillars can also isolate light emitted by adjacent pixel structures, avoiding optical crosstalk between adjacent pixel structures.
  • the material of the conductive isolation pillars is a light-shielding conductive material.
  • conductive isolation pillars are formed on the side of the pixel defining layer facing away from the substrate 200. After the pixel structure is formed, the conductive isolation pillars are located on the side of the pixel defining layer 240 facing away from the substrate 200 between adjacent pixel structures.
  • the display panel fabrication method further includes: before forming an initial cathode layer, forming a cathode lead-out layer 280, the cathode lead-out layer 280 being located on one side of the substrate 200 between the planarization layer and the first barrier dam B2, and extending to the side of the planarization layer opposite to the substrate 200.
  • the cathode layer 230 in a portion of the pixel structure extends to overlap with the cathode lead-out layer 280 on the planarization layer side.
  • a cathode lead-out layer 280 is formed during the formation of the anode layer, and the cathode lead-out layer 280 is made of the same material as the anode layer. In other embodiments, the anode layer and the cathode lead-out layer 280 may be formed sequentially in different steps.
  • the second barrier dam C is located between the flat layer and the first barrier dam B2.
  • the second barrier dam is located on the side of the planar layer between the pixel defining layer 240 and the first barrier dam B2 that faces away from the substrate 200.
  • a portion of the second blocking dams are located on the side of the planarization layer between the pixel defining layer 240 and the first blocking dam B2 away from the substrate 200, and another portion of the second blocking dams are located between the planarization layer and the first blocking dam B2.
  • a second barrier dam C located between the flat layer and the first barrier dam B2 covers the cathode lead-out layer 280.
  • a second barrier dam located on one side of the flat layer between the pixel defining layer 240 and the first barrier dam B2 covers the cathode layer 230.
  • the step of forming a first barrier dam B2 on one side of the edge region of the substrate includes forming a first portion 274, a second portion 273 and a third portion.
  • the second portion 273 is formed on the side of the third portion away from the substrate 200
  • the first portion 274 is formed on the side of the second portion 273 away from the substrate 200.
  • a second portion 273 is formed during the formation of the pixel defining layer 240, and the material of the second portion 273 is the same as that of the pixel defining layer 240.
  • a third portion is formed during the formation of the planarization layer, and the material of the third portion is the same as that of the planarization layer.
  • the third portion of a portion of the first barrier dam B2 has a multi-layered structure.
  • the flattening layer has a multi-layered structure.
  • the third portion includes a first third sublayer 271 and a second third sublayer 272.
  • the first third sublayer 271 is formed during the formation of the first flattening layer 251, and the second third sublayer 272 is formed during the formation of the second flattening layer 252.
  • the material of the first third sublayer 271 is the same as that of the first flattening layer 251, and the material of the second third sublayer 272 is the same as that of the second flattening layer 252.
  • the second third sublayer 272 is located between the first third sublayer 271 and the second portion 273.
  • the third part of another portion of the first barrier dam B2 is a single-layer structure, and the third part of the first barrier dam B2 includes a third sub-layer.
  • a third sub-layer is formed during the formation of the first flattening layer 251, or during the formation of the second flattening layer 252.
  • the first portion 274 includes one or more stacked first sublayers, which are formed during the formation of a first inorganic encapsulation layer on the pixel structure surface of different pixel colors.
  • the material of one first sublayer is the same as the material of the first inorganic encapsulation layer on the pixel structure surface of one pixel color.
  • Figure 12 illustrates a first portion 274 comprising a first sublayer, the material of which is the same as that of the first inorganic encapsulation layer 203.
  • the first portion 274 comprises multiple first sublayers, each of which is made of the same material as the first inorganic encapsulation layer on the surface of a pixel structure of a pixel color.
  • forming an encapsulation layer includes: forming an organic encapsulation layer 201 on the side of the pixel defining layer 240 and the second barrier dam C opposite to the substrate 200; wherein, the first barrier dam B2 surrounds the organic encapsulation layer 201.
  • the step of forming the encapsulation layer further includes forming a second inorganic encapsulation layer 202 on the side of the organic encapsulation layer 201 facing away from the substrate 200.
  • Another embodiment of this application provides a display device, including the display panel of the above embodiment.
  • this display device can refer to the implementation of the aforementioned display panel, and repeated details will not be repeated.
  • This display device can be any product or component with display functionality, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. Other essential components of this display device are understood by those skilled in the art and will not be described in detail here, nor should they be construed as limiting this application.

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Abstract

一种显示面板，包括：基板(200)，基板(200)包括显示区(A1)和包围显示区(A1)的边缘区(A2)；像素限定层(240)，位于基板(200)的显示区(A1)的一侧；第一阻挡坝(B2)，位于基板(200)的边缘区(A2)的一侧；第二阻挡坝(C)，位于像素限定层(240)和第一阻挡坝(B2)之间的基板(200)的一侧，第二阻挡坝(C)的材料和像素限定层(240)的材料不同；以及封装层，包括：有机封装层(201)，有机封装层(201)位于像素限定层(240)背离基板(200)的一侧且延伸至覆盖第二阻挡坝(C)；其中，第一阻挡坝(B2)包围有机封装层(201)。

Description

显示面板及其制备方法、显示装置
本申请要求于2024年06月13日提交的、申请号为202410764465.8、发明名称为“显示面板及其制备方法、显示装置”的中国专利申请的优先权，其内容应理解为通过引用的方式并入本申请中。
技术领域
本申请实施例涉及但不限于显示技术领域，具体涉及一种显示面板及其制备方法、显示装置。
背景技术
显示面板中的边缘区一侧通常设置阻挡坝，阻挡坝用于阻挡有机封装层的材料溢出至阻挡坝的外围。
在一种显示面板的制备方法中，形成发光层的过程中不使用具有开口的蒸镀掩膜版，形成发光层使用刻蚀工艺进行图形化。采用该方法形成的显示面板中，相应的阻挡坝的高度降低，阻挡坝对有机封装层的阻挡能力降低，边缘区上的有机封装层的材料容易溢出至阻挡坝背离显示区的一侧，水汽容易通过有机封装层进入显示区，导致封装失效。
发明内容
以下是对本文详细描述的主题的概述，本概述并非是为了限制权利要求的保护范围。
本申请的实施例提供一种显示面板，包括：基板，所述基板包括显示区和包围所述显示区的边缘区；像素限定层，位于所述基板的所述显示区的一侧；第一阻挡坝，位于所述基板的所述边缘区的一侧；第二阻挡坝，位于所述像素限定层和所述第一阻挡坝之间的所述基板的一侧，所述第二阻挡坝的材料和所述像素限定层的材料不同；以及封装层，所述封装层包括：有机封装层，有机封装层位于所述像素限定层背离所述基板的一侧且延伸至覆盖所述第二阻挡坝；其中，所述第一阻挡坝包围所述有机封装层。
本申请的实施例还提供一种显示面板的制备方法，包括：提供基板，所述基板包括显示区和包围所述显示区的边缘区；在所述基板的所述显示区的一侧形成像素限定层；在所述基板的所述边缘区的一侧形成第一阻挡坝；形成第二阻挡坝，所述第二阻挡坝位于所述像素限定层和所述第一阻挡坝之间的所述基板的一侧，所述第二阻挡坝的材料和所述像素限定层的材料不同；以及形成封装层，包括：在所述像素限定层和所述第二阻挡坝背离所述基板的一侧形成有机封装层；其中，所述第一阻挡坝包围所述有机封装层。
本申请的实施例还提供一种显示装置，包括本申请实施例上述的显示面板。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图概述
为了更清楚地说明本申请具体实施方式或现有技术中的技术方案，下面将对具体实施方式或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施方式，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为一种实施例提供的显示面板的结构示意图；
图2为另一种实施例提供的显示面板的结构示意图；
图3为图2的局部示意图；
图4为本申请一实施例的显示面板的结构示意图；
图5为本申请一实施例的第二阻挡坝的结构示意图；
图6为本申请另一实施例的第二阻挡坝的结构示意图；
图7为本申请又一实施例的第二阻挡坝的结构示意图；
图8为本申请又一实施例的第二阻挡坝的结构示意图；
图9为本申请一实施例的显示区上的部分结构示意图；
图10为本申请另一实施例的显示面板的结构示意图；
图11为本申请一实施例中的显示面板的制备方法的流程图；
图12至图13为本申请一实施例中显示面板制备过程的结构示意图。
详述
一种实施例提供的显示面板，参考图1，包括：基板10，基板10包括显示区和包围显示区的边缘区；阻挡坝B0，位于基板10的边缘区的一侧；位于基板10的显示区一侧的像素限定层(未图示)，像素限定层中具有像素开口；位于像素开口中的发光层(未图示)；支撑柱(未图示)，位于像素限定层背离基板10的一侧；封装层(未图示)包括：有机封装层(未图示)；其中，阻挡坝B0包围有机封装层。其中，支撑柱用于在蒸镀发光层的过程中支撑蒸镀掩膜版。
部分数量的阻挡坝B0包括层叠的第一阻挡层11、第二阻挡层12、第三阻挡层13以及第四阻挡层14，第四阻挡层14的材料和支撑柱的材料相同。部分数量的阻挡坝B0包括层叠的第一阻挡层、第二阻挡层和第三阻挡层，第三阻挡层的材料和支撑柱的材料相同。
另一种实施例提供的显示面板，参考图2，包括：基板100，基板100包括显示区和包围显示区的边缘区；阻挡坝B1，位于基板100的边缘区的一侧；位于基板100的显示区一侧的像素限定层103，像素限定层103中具有像素开口；位于像素开口中的发光层(未图示)；封装层(未图示)，封装层包括：有机封装层101；其中，阻挡坝B1用于包围有机封装层101。
图2中的显示面板中，发光层的形成步骤包括：形成初始发光层；对初始发光层进行刻蚀，形成发光层。由于形成发光层的过程中不需要蒸镀掩膜版，因此取消了支撑柱。相应的，阻挡坝B1中没有和支撑柱的材料相同的膜层。参考图3，部分数量的阻挡坝B1包括层叠的第一阻挡层11、第二阻挡层12和第三阻挡层13，第三阻挡层13的材料和像素限定层103的材料相同。部分数量的阻挡坝B1包括层叠的第一阻挡层和第二阻挡层，第二阻挡层的材料和像素限定层103的材料相同。由于阻挡坝B1中没有和支撑柱的材料相同的膜层，因此阻挡坝B1的高度降低，阻挡坝B1对有机封装层101的阻挡能力降低，边缘区上的有机封装层101的材料容易溢出至阻挡坝B1背离显示区的一侧，水汽容易通过有机封装层101进入显示区，导致封装失效。
在此基础上，本申请的实施例提供一种显示面板及其制备方法、显示装置，提高了封装可靠性。
下面将结合附图对本申请的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”、“第三”仅用于描述目的，而不能理解为指示或暗示相对重要性。
本公开中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
在本申请的描述中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，还可以是两个元件内部的连通，可以是无线连接，也可以是有线连接。对于本领域的普通技术人员而言，可以根据情况理解上述术语在本申请中的含义。
此外，下面所描述的本申请不同实施方式中所涉及的技术特征只要彼此之间未构成冲突就可以相互结合。
本申请一实施例提出一种显示面板，参考图4，包括：基板200，基板200包括显示区A1和包围显示区A1的边缘区A2；像素限定层240，位于基板200的显示区A1的一侧；第一阻挡坝B2，位于基板200的边缘区A2的一侧；第二阻挡坝C，位于像素限定层240和第一阻挡坝B2之间的基板200的一侧，第二阻挡坝C的材料和像素限定层240的材料不同；以及封装层，封装层包括：有机封装层201，有机封装层201位于像素限定层240背离基板200的一侧且延伸至覆盖第二阻挡坝C；其中，第一阻挡坝B2包围有机封装层201。
本实施例中，设置第二阻挡坝C，第二阻挡坝C的材料和像素限定层240的材料不同。第二阻挡坝C和第一阻挡坝B2用于在形成有机封装层201的过程中共同阻挡有机封装层201的流动，避免边缘区A2上的有机封装层201的材料溢出至第一阻挡坝B2背离显示区A1的一侧，从而避免降低封装失效的概率。
在一个实施例中，显示面板为柔性显示面板，柔性显示面板例如为有机发光二极管显示屏(OLED显示面板)。在其他实施例中，显示面板为硬质显示面板，例如液晶显示面板。
在一个实施例中，基板200为驱动基板，基板200包括驱动晶体管。
在一个实施例中，参考图9，显示面板还包括：位于像素限定层240中的像素结构，多个像素结构具有多种像素颜色；位于像素结构背离基板一侧表面的第一无机封装层。像素结构包括阳极层(未图示)、发光层300和阴极层230，发光层300位于阳极层和阴极层230之间，阴极层230位于阳极层背离基板200的一侧。部分数量的像素结构的像素颜色为红色(R)，对应的发光层300用于发红光。部分数量的像素结构的像素颜色为绿色(G)，对应的发光层300用于发绿光。部分数量的像素结构的像素颜色为蓝色(B),对应的发光层300用于发蓝光。不同像素结构中的阴极层230间隔设置。
在一个实施例中，参考图9，每个像素结构中的阴极层230间隔设置。显示面板还包括：导电隔离柱(未图示)，位于相邻像素结构之间的像素限定层240背离基板200的一侧；其中，阴极层230与导电隔离柱连接。导电隔离柱能将不同像素结构中的阴极层230电学连接。导电隔离柱还能隔离相邻像素结构发出的光，避免相邻像素结构之间的光学串扰。在一个实施例中，导电隔离柱的材料为遮光导电材料。
在一个实施例中，参考图9，显示面板还包括：位于像素结构背离基板200的一侧表面的第一无机封装层。一部分像素颜色的像素结构背离基板200的一侧表面设置第一无机封装层203b。另一部分像素颜色的像素结构背离基板200的一侧表面设置第一无机封装层203a。又一部分像素颜色的像素结构背离基板200的一侧表面设置第一无机封装层203。第一无机封装层203b、第一无机封装层203a和第一无机封装层203的材料相同或至少部分不同。图9示意出三种不同像素颜色的像素结构对应的第一无机封装层。在其他实施例中，像素颜色不限于三种，不同的像素颜色的像素结构背离基板200的一侧表面均设置第一无机封装层。
在一个实施例中，参考图4，有机封装层201位于第一无机封装层背离基板200的一侧。换言之，有机封装层201覆盖第一无机封装层，示例性地，有机封装层201覆盖第一无机封装层203、第一无机封装层203a和第一无机封装层203b。
在一个实施例中，第二阻挡坝C包括一层或多层层叠的第二子阻挡坝；一层第二子阻挡坝的材料与一种像素颜色的像素结构表面的第一无机封装层的材料相同。
在一个实施例中，多个像素结构具有M种像素颜色；M为大于或等于2的整数。第二阻挡坝C包括依次层叠的第一层第二子阻挡坝至第N层第二子阻挡坝，N为大于或等于1且小于或等于M的整数。第一层第二子阻挡坝至第N层第二子阻挡坝的材料分别与N种不同像素颜色的像素结构表面的第一无机封装层的材料一一对应相同。
在一个实施例中，第一层第二子阻挡坝位于第N层第二子阻挡坝和基板200之间。
示例性的，结合参考图4和图9，M＝3，多个像素结构具有三种像素颜色。N＝3，第二阻挡坝C包括第一层第二子阻挡坝221、第二层第二子阻挡坝222和第三层第二子阻挡坝223。第一层第二子阻挡坝221与红色像素颜色的像素结构表面的第一无机封装层203b的材料相同。第二层第二子阻挡坝222与绿色像素颜色的像素结构表面的第一无机封装层203a的材料相同。第三层第二子阻挡坝223与蓝色像素颜色的像素结构表面的第一无机封装层203的材料相同。
示例性的，结合参考图8和图9，M＝3，多个像素结构具有三种像素颜色。N＝2，第二阻挡坝C包括第一层第二子阻挡坝221和第二层第二子阻挡坝222。第一层第二子阻挡坝221与绿色像素颜色的像素结构表面的第一无机封装层203a的材料相同。第二层第二子阻挡坝222与蓝色像素颜色的像素结构表面的第一无机封装层203的材料相同。
在一个实施例中，每个第二阻挡坝C中的第N层第二子阻挡坝连接在一起，每个第二阻挡坝C中的任意的第n’层第二子阻挡坝之间间隔，n’为大于或等于1且小于N的整数。由于每个第二阻挡坝C中的第N层第二子阻挡坝连接在一起，因此对边缘区A2的水汽阻隔能力提高。
示例性的，参考图4和图6，第二阻挡坝C包括第一层第二子阻挡坝221、第二层第二子阻挡坝222和第三层第二子阻挡坝223。每个第二阻挡坝C的第三层第二子阻挡坝223连接在一起，每个第二阻挡坝C的第一层第二子阻挡坝221间隔，每个第二阻挡坝C的第二层第二子阻挡坝222间隔。
示例性的，参考图8，第二阻挡坝C包括第一层第二子阻挡坝221和第二层第二子阻挡坝222。每个第二阻挡坝C的第二层第二子阻挡坝222连接在一起。每个第二阻挡坝C的第一层第二子阻挡坝221间隔。
示例性的，参考图7，一部分数量的第二阻挡坝C包括第一层第二子阻挡坝221、第二层第二子阻挡坝222和第三层第二子阻挡坝223，另一部分数量的第二阻挡坝C包括第一层第二子阻挡坝221和第二层第二子阻挡坝222。一部分数量的第二阻挡坝C的第三层第二子阻挡坝223和另一部分数量的第二阻挡坝C的第二层第二子阻挡坝222连接在一起。一部分数量的第二阻挡坝C的第一层第二子阻挡坝221和第二层第二子阻挡坝222均与另一部分数量的第二阻挡坝C的第一层第二子阻挡坝221间隔。
在其他实施例中，不同第二阻挡坝C中的膜层之间可以是间隔设置。
在一个实施例中，第二阻挡坝C沿垂直于基板200表面的方向上的高度尺寸可设置为约3微米-4微米。第二阻挡坝C在第一无机封装层形成过程中形成，第二阻挡坝C的高度设置和多个像素结构的像素颜色种类相关，多个像素结构的像素颜色种类越多，第二阻挡坝C中的膜层数量的上限越多，第二阻挡坝C的高度上限越高。
在一个实施例中，第二阻挡坝C沿垂直于基板200表面的方向上的高度尺寸小于第一阻挡坝B2沿垂直于基板200表面的方向上的高度尺寸。
在其他实施例中，对第二阻挡坝C沿垂直于基板200表面的方向上的高度尺寸不做限制。
在一个实施例中，自显示区A1至边缘区A2的方向上，第二阻挡坝C的宽度尺寸可设置为约10微米-20微米，例如10微米、15微米或20微米。可以提高第二阻挡坝C的位置稳定性，避免第二阻挡坝C在工艺过程中倾倒。
在其他实施例中，对第二阻挡坝C的宽度尺寸不做限制。
在一个实施例中，第二阻挡坝C呈包围像素限定层240的环状结构。第二阻挡坝C在第二阻挡坝C的周向方向上的任何位置处均对有机封装层201具有一定的阻挡作用。
在一个实施例中，自显示区A1至边缘区A2的方向上，第二阻挡坝C的数量为一个。
在一个实施例中，参考图4、图6、图7和图8，自显示区A1至边缘区A2的方向上，第二阻挡坝C的数量为多个。第二阻挡坝C的数量越多，多个第二阻挡坝C对有机封装层201的阻挡作用越强。
参考图5，多个第二阻挡坝包括第一个第二阻挡坝C1至第W个第二阻挡坝CW，W为大于或等于2的整数。进一步的，W＝3，多个第二阻挡坝包括第一个第二阻挡坝C1、第二个第二阻挡坝C2和第三个第二阻挡坝C3。多个第二阻挡坝对有机封装层201的阻挡作用增强。
在其他实施例中，对第二阻挡坝的数量不进行限制。第二阻挡坝C的数量设置也需要考虑到像素限定层240和第一阻挡坝B2之间的空间的限制，可以根据实际条件设置合理数量的第二阻挡坝C。
在一个实施例中，参考图4、图6和图8，多个第二阻挡坝C的膜层数量相同。参考图4和图6，每个第二阻挡坝C的膜层数量为三层。参考图8，每个第二阻挡坝C的膜层数量为两层。
在另一个实施例中，参考图7，至少两个第二阻挡坝C的膜层数量不同。示例性的，部分数量的第二阻挡坝C的膜层数量为两层，部分数量的第二阻挡坝C的膜层数量为三层。
在一个实施例中，参考图4和图10，显示面板还包括：平坦层，位于像素限定层240和基板200之间，进一步的，平坦层延伸至部分边缘区A2的一侧，平坦层与第一阻挡坝B2间隔。其中，沿显示区A1至边缘区A2的方向，像素限定层240至第一阻挡坝B2的间隔距离大于平坦层至第一阻挡坝B2的间隔距离。图4和图10中，平坦层为多层结构，示例性的，平坦层包括第一平坦层251和第二平坦层252，第一平坦层251位于第二平坦层252和基板200之间。
在其他实施例中，平坦层可以为单层结构。
在一个实施例中，参考图10，第二阻挡坝C位于像素限定层240和第一阻挡坝B2之间的平坦层背离基板200的一侧。或者，参考图4，第二阻挡坝C位于平坦层和第一阻挡坝B2之间。或者，一部分数量的第二阻挡坝位于像素限定层240和第一阻挡坝B2之间的平坦层背离基板200的一侧，另一部分数量的第二阻挡坝位于平坦层和第一阻挡坝B2之间。
在一个实施例中，参考图4和图10，显示面板还包括：阴极引出层280，位于平坦层和第一阻挡坝B2之间的基板200的一侧、且延伸至部分平坦层背离基板200的一侧。部分像素结构中的阴极层230延伸至与平坦层一侧的阴极引出层280搭接。阴极引出层280用于给阴极层230提供接地电平。
在一个实施例中，阴极引出层280的材料与阳极层的材料相同。在其他实施例中，阴极引出层280的材料与阳极层的材料不同。
在一个实施例中，参考图4，位于平坦层和第一阻挡坝B2之间的第二阻挡坝C覆盖阴极引出层280。
在一个实施例中，参考图10，位于像素限定层240和第一阻挡坝B2之间的平坦层一侧的第二阻挡坝C覆盖阴极层230。
在一个实施例中，参考图4和图10，第一阻挡坝B2包括第一部分274以及位于第一部分274和基板200之间的第二部分273。第二部分273的材料和像素限定层240的材料相同。第一部分274包括一层或多层层叠的第一子层，一层第一子层的材料与一种像素颜色的像素结构表面的第一无机封装层的材料相同。
图4和图10以第一部分274包括一层第一子层作为示例，第一子层的材料与第一无机封装层203的材料相同。在其他实施例中。第一部分274包括多层第一子层，一层第一子层的材料与一种像素颜色的像素结构表面的第一无机封装层的材料相同。
参考图4和图10，第一阻挡坝B2还包括：第三部分，位于第二部分273和基板200之间，第三部分的材料和平坦层的材料相同。参考图4和图10中，一部分数量的第一阻挡坝B2中的第三部分为多层结构，示例性的，第三部分包括第一层第三子层271和第二层第三子层272，第一层第三子层271的材料和第一平坦层251的材料相同，第二层第三子层272的材料和第二平坦层252的材料相同，第二层第三子层272位于第一层第三子层271和第二部分273之间。另一部分数量的第一阻挡坝B2的第三部分为单层结构，即，第一阻挡坝B2的第三部分包括一层第三子层。本申请对第三部分中的膜层数量不做限制。
参考图4和图10，封装层还包括：第二无机封装层202，位于有机封装层201背离基板200的一侧。
参考图4和图10，显示面板还包括：载流子层260，载流子层包括第一载流子层和第二载流子层，载流子层260位于阴极层230和像素限定层240之间以及阴极层230和阳极层之间。其中，阴极层230和阳极层之间的第一载流子层位于阴极层230和发光层300之间，阴极层230和阳极层之间的第二载流子层位于阳极层和发光层300之间。第一载流子层包括电子传输层、空穴阻挡层和电子注入层。第二载流子层包括空穴传输层、电子阻挡层和空穴注入层。图4和图10中示出的载流子层260为：一部分像素结构中的载流子层260延伸至像素限定层240背离基板200的一侧。
本申请另一实施例还提供一种显示面板的制备方法，参考图11，包括：步骤S1：提供基板，基板包括显示区和包围显示区的边缘区；步骤S2：在基板的显示区的一侧形成像素限定层；步骤S3：在基板的边缘区的一侧形成第一阻挡坝；步骤S4：形成第二阻挡坝，第二阻挡坝位于像素限定层和第一阻挡坝之间的基板的一侧，第二阻挡坝的材料和像素限定层的材料不同；以及步骤S5：形成封装层，包括：在像素限定层和所述第二阻挡坝背离所述基板的一侧形成有机封装层；其中，第一阻挡坝包围所述有机封装层。
图12至图13为本申请另一实施例中的显示面板制备过程的示意图。
参考图12，提供基板200，基板200包括显示区A1和包围显示区A1的边缘区A2；在基板200的显示区A1的一侧形成像素限定层240；在基板200的边缘区A2的一侧形成第一阻挡坝B2；形成第二阻挡坝C，第二阻挡坝C位于像素限定层240和第一阻挡坝B2之间的基板200的一侧，第二阻挡坝B2的材料和像素限定层240的材料不同。
在一个实施例中，基板200为驱动基板，基板200包括驱动晶体管。
显示面板制备方法还包括：在形成像素限定层240之前，在基板200的显示区A1一侧形成平坦层，平坦层与第一阻挡坝B2间隔。像素限定层240位于平坦层背离基板200的一侧。
在一个实施例中，平坦层为多层结构，示例性的，形成平坦层的步骤包括：在基板200的显示区A1一侧形成第一平坦层251；在第一平坦层251背离基板200的一侧形成第二平坦层252。在其他实施例中，平坦层为单层结构。
在一个实施例中，平坦层还延伸至部分边缘区A2的一侧。其中，沿显示区A1至边缘区A2的方向，像素限定层240至第一阻挡坝B2的间隔距离大于平坦层至第一阻挡坝B2的间隔距离。
在一个实施例中，显示面板制备方法还包括：在像素限定层240中形成多个像素结构，多个像素结构具有多种像素颜色。多个像素结构具有M种像素颜色；M为大于或等于2的整数。参考图9，像素结构包括阳极层(未图示)、发光层300和阴极层230，发光层300位于阳极层和阴极层230之间，阴极层230位于阳极层背离基板200的一侧。部分数量的像素结构的像素颜色为红色(R)，对应的发光层300用于发红光。部分数量的像素结构的像素颜色为绿色(G)，对应的发光层300用于发绿光。部分数量的像素结构的像素颜色为蓝色(B)，对应的发光层300用于发蓝光。不同像素结构中的阴极层230间隔设置。
在一个实施例中，不同像素颜色的像素结构先后依次形成。形成任意一种像素颜色的像素结构的步骤包括：形成阳极层、形成初始发光层和初始阴极层，对初始发光层和初始阴极层进行刻蚀，使初始发光层形成发光层300，使初始阴极层形成阴极层230。
在一个实施例中，任意一种像素颜色的像素结构的阳极层的形成步骤包括：在形成初始发光层之前形成初始阳极层，在对初始发光层和初始阴极层进行刻蚀的过程中刻蚀初始阳极层，使初始阳极层形成阳极层。
在另一个实施例中，不同的像素颜色的像素结构的阳极层可以在同一道工艺中形成。
在一个实施例中，形成任意一种像素颜色的像素结构的步骤还包括：在形成初始发光层之前，形成第二初始载流子层；在形成初始阴极层之前，在初始发光层背离基板200的一侧形成第一初始载流子层；在对初始发光层和初始阴极层进行刻蚀的过程中，对第二初始载流子层和第一初始载流子层进行刻蚀，使第二初始载流子层形成第二载流子层，使第一初始载流子层形成第一载流子层。
第二载流子层和第一载流子层构成载流子层260。图12中示出的载流子层260为：一部分像素结构中的载流子层260延伸至像素限定层240背离基板200的一侧。
本实施例中，在形成像素结构的过程中形成第一无机封装层；其中，不同像素颜色的像素结构一侧的第一无机封装层先后依次形成。形成任意的像素颜色的像素结构一侧的第一无机封装层的步骤包括：在对初始发光层和初始阴极层进行刻蚀之前，在初始阴极层背离基板200的一侧形成初始第一无机封装层；在对初始发光层和初始阴极层进行刻蚀的过程中，对初始第一无机封装层进行刻蚀，使初始第一无机封装层形成第一无机封装层。在形成像素结构的过程中形成第一无机封装层，第一无机封装层能保护像素结构，降低像素结构受到的刻蚀损伤。
形成第二阻挡坝C包括形成一层或多层层叠的第二子阻挡坝，在形成一层第二子阻挡坝的过程中形成一种像素颜色的像素结构表面的第一无机封装层。
每个像素结构中的阴极层230间隔设置。每个像素结构中的发光层间隔设置。每个像素结构中的载流子层260间隔设置。
在一个实施例中，多个像素结构具有M种像素颜色；M为大于或等于2的整数。第二阻挡坝C包括依次层叠的第一层第二子阻挡坝至第N层第二子阻挡坝，N为大于或等于1且小于或等于M的整数。第一层第二子阻挡坝至第N层第二子阻挡坝的材料分别与N种不同像素颜色的像素结构表面的第一无机封装层的材料一一对应相同。
参考图9，一部分像素颜色的像素结构背离基板200一侧表面形成第一无机封装层203b。另一部分像素颜色的像素结构背离基板200一侧表面形成第一无机封装层203a。又一部分像素颜色的像素结构背离基板200一侧表面形成第一无机封装层203。第一无机封装层203b、第一无机封装层203a和第一无机封装层203的材料相同或至少部分不同。图9示意出三种不同像素颜色的像素结构对应的第一无机封装层。在其他实施例中，像素颜色不限于三种，不同的像素颜色的像素结构背离基板200一侧表面均形成第一无机封装层。
示例性的，参考图12，M＝3，多个像素结构具有三种像素颜色。N＝3，第二阻挡坝C包括第一层第二子阻挡坝221、第二层第二子阻挡坝222和第三层第二子阻挡坝223。第一层第二子阻挡坝221与红色像素颜色的像素结构表面的第一无机封装层203b的材料相同。第二层第二子阻挡坝222与绿色像素颜色的像素结构表面的第一无机封装层203a的材料相同。第三层第二子阻挡坝223与蓝色像素颜色的像素结构表面的第一无机封装层203的材料相同。
在其他实施例中，N小于M，第一层第二子阻挡坝至第N层第二子阻挡坝的材料分别与N种不同像素颜色的像素结构表面的第一无机封装层的材料一一对应相同。
在一个实施例中，每个第二阻挡坝C中的第N层第二子阻挡坝连接在一起，每个第二阻挡坝C中的任意的第n’层第二子阻挡坝之间间隔，n’为大于或等于1且小于N的整数。
在其他实施例中，不同第二阻挡坝C中的膜层之间可以是间隔设置。
在一个实施例中，第二阻挡坝C沿垂直于基板200表面的方向上的高度尺寸可设置为3微米～4微米。
在一个实施例中，第二阻挡坝C沿垂直于基板200表面的方向上的高度尺寸可设置为小于第一阻挡坝B2沿垂直于基板200表面的方向上的高度尺寸。在其他实施例中，对第二阻挡坝C沿垂直于基板200表面的方向上的高度尺寸不做限制。
在一个实施例中，自显示区A1至边缘区A2的方向上，第二阻挡坝C的宽度尺寸可设置为约10微米-20微米。在其他实施例中，对第二阻挡坝C的宽度尺寸不做限制。
在一个实施例中，第二阻挡坝C呈包围像素限定层240的环状结构。
在一个实施例中，自显示区A1至边缘区A2的方向上，第二阻挡坝C的数量为一个。
在一个实施例中，自显示区A1至边缘区A2的方向上，第二阻挡坝C的数量为多个。
在一个实施例中，多个第二阻挡坝C的膜层数量相同。在另一个实施例中，至少两个第二阻挡坝C的膜层数量不同。
在一个实施例中，显示面板制备方法还包括：形成导电隔离柱(未图示)，导电隔离柱位于相邻像素结构之间的像素限定层240背离基板200的一侧；其中，阴极层230与导电隔离柱连接。导电隔离柱能将不同像素结构中的阴极层230电学连接。导电隔离柱还能隔离相邻像素结构发出的光，避免相邻像素结构之间的光学串扰。在一个实施例中，导电隔离柱的材料为遮光导电材料。
在一个实施例中，在形成第二初始载流子层之前，在部分像素限定层背离基板200的一侧形成导电隔离柱。形成像素结构之后，导电隔离柱位于相邻像素结构之间的像素限定层240背离基板200的一侧。
在一个实施例中，显示面板制备方法还包括：在形成初始阴极层之前，形成阴极引出层280，阴极引出层280位于平坦层和第一阻挡坝B2之间的基板200的一侧、且延伸至部分平坦层背离基板200的一侧。形成阴极层之后，部分像素结构中的阴极层230延伸至与平坦层一侧的阴极引出层280搭接。
在一个实施例中，在形成阳极层的过程中形成阴极引出层280，阴极引出层280的材料和阳极层的材料相同。在其他实施例中，阳极层和阴极引出层280可以先后在不同的步骤中形成。
在一个实施例中，参考图12，第二阻挡坝C位于平坦层和第一阻挡坝B2之间。
在另一个实施例中，第二阻挡坝位于像素限定层240和第一阻挡坝B2之间的平坦层背离基板200的一侧。
在另一个实施例中，一部分数量的第二阻挡坝位于像素限定层240和第一阻挡坝B2之间的平坦层背离基板200的一侧，另一部分数量的第二阻挡坝位于平坦层和第一阻挡坝B2之间。
在一个实施例中，位于平坦层和第一阻挡坝B2之间的第二阻挡坝C覆盖阴极引出层280。
在一个实施例中，位于像素限定层240和第一阻挡坝B2之间的平坦层一侧的第二阻挡坝覆盖阴极层230。
在一个实施例中，参考图12，在基板的边缘区的一侧形成第一阻挡坝B2的步骤包括：形成第一部分274、第二部分273和第三部分，示例性地，在第三部分背离基板200的一侧形成第二部分273，在第二部分273背离基板200的一侧形成第一部分274。
在一个实施例中，在形成像素限定层240的过程中形成第二部分273，第二部分273的材料和像素限定层240的材料相同。
在一个实施例中，在形成平坦层的过程中形成第三部分，第三部分的材料和平坦层的材料相同。
参考图12，一部分数量的第一阻挡坝B2中的第三部分为多层结构。平坦层为多层结构。示例性的，第三部分包括第一层第三子层271和第二层第三子层272，在形成第一平坦层251的过程中形成第一层第三子层271，在形成第二平坦层252的过程中形成第二层第三子层272，第一层第三子层271的材料和第一平坦层251的材料相同，第二层第三子层272的材料和第二平坦层252的材料相同，第二层第三子层272位于第一层第三子层271和第二部分273之间。
参考图12，另一部分数量的第一阻挡坝B2中的第三部分为单层结构，第一阻挡坝B2中的第三部分包括一层第三子层。在形成第一平坦层251的过程中形成一层第三子层，或者，在形成第二平坦层252的过程中形成一层第三子层。
本申请对第三部分中的膜层数量不做限制。
参考图12，第一部分274包括一层或多层层叠的第一子层，在形成不同像素颜色的像素结构表面的第一无机封装层的过程中形成第一部分274。一层第一子层的材料与一种像素颜色的像素结构表面的第一无机封装层的材料相同。
图12以第一部分274包括一层第一子层作为示例，第一子层的材料与第一无机封装层203的材料相同。在其他实施例中。第一部分274包括多层第一子层，一层第一子层的材料与一种像素颜色的像素结构表面的第一无机封装层的材料相同。
参考图13，形成封装层，包括：在像素限定层240和第二阻挡坝C背离基板200的一侧形成有机封装层201；其中，第一阻挡坝B2包围有机封装层201。
形成封装层的步骤还包括：在有机封装层201背离基板200的一侧形成第二无机封装层202。
本申请另一实施例还提供一种显示装置，包括上述实施例的显示面板。
由于该显示装置解决问题的原理与前述显示面板相似，因此该显示装置中的显示面板的实施可以参见前述显示面板的实施，重复之处不再赘述。该显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本申请的限制。
显然，上述实施例仅仅是为清楚地说明所作的举例，而并非对实施方式的限定。对于所属领域的普通技术人员来说，在上述说明的基础上还可以做出其它不同形式的变化或变动。这里无需也无法对所有的实施方式予以穷举。而由此所引伸出的显而易见的变化或变动仍处于本申请创造的保护范围之中。

Claims (20)

  1. 一种显示面板，包括：
    基板，包括显示区和包围所述显示区的边缘区；
    像素限定层，位于所述基板的所述显示区的一侧；
    第一阻挡坝，位于所述基板的所述边缘区的一侧；
    第二阻挡坝，位于所述像素限定层和所述第一阻挡坝之间的所述基板的一侧，所述第二阻挡坝的材料和所述像素限定层的材料不同；以及
    封装层，包括有机封装层，所述有机封装层位于所述像素限定层背离所述基板的一侧且延伸至覆盖所述第二阻挡坝；其中，所述第一阻挡坝包围所述有机封装层。
  2. 根据权利要求1所述的显示面板，其中，所述第二阻挡坝沿垂直于所述基板表面的方向上的高度尺寸为3微米-4微米。
  3. 根据权利要求1所述的显示面板，其中，所述第二阻挡坝沿垂直于所述基板表面的方向上的高度尺寸小于所述第一阻挡坝沿垂直于所述基板表面的方向上的高度尺寸。
  4. 根据权利要求1或2或3所述的显示面板，其中，自所述显示区至所述边缘区的方向上，所述第二阻挡坝的宽度尺寸为10微米-20微米。
  5. 根据权利要求1或4所述的显示面板，其中，所述第二阻挡坝呈包围所述像素限定层的环状结构。
  6. 根据权利要求1-5中任一项所述的显示面板，其中，自所述显示区至所述边缘区的方向上，所述第二阻挡坝的数量为一个。
  7. 根据权利要求1-5中任一项所述的显示面板，其中，自所述显示区至所述边缘区的方向上，所述第二阻挡坝的数量为多个。
  8. 根据权利要求7所述的显示面板，其中，多个所述第二阻挡坝的膜层数量相同。
  9. 根据权利要求7所述的显示面板，其中，至少两个所述第二阻挡坝的膜层数量不同。
  10. 根据权利要求1至9任意一项所述的显示面板，还包括：位于所述像素限定层中的像素结构，多个所述像素结构具有多种像素颜色；位于所述像素结构背离所述基板一侧表面的第一无机封装层；其中，所述有机封装层位于所述第一无机封装层背离所述基板的一侧；
    其中，所述第二阻挡坝包括一层或多层层叠的第二子阻挡坝；一层所述第二子阻挡坝的材料与一种像素颜色的所述像素结构表面的所述第一无机封装层的材料相同。
  11. 根据权利要求10所述的显示面板，其中，多个所述像素结构具有M种像素颜色；M为大于或等于2的整数；
    其中，所述第二阻挡坝包括依次层叠的第一层第二子阻挡坝至第N层第二子阻挡坝，N为大于或等于1且小于或等于M的整数；第一层第二子阻挡坝至第N层第二子阻挡坝的材料分别与N种不同像素颜色的所述像素结构表面的所述第一无机封装层的材料一一对应相同。
  12. 根据权利要求11所述的显示面板，其中，第一层第二子阻挡坝位于第N层第二子阻挡坝和所述基板之间；
    其中，每个所述第二阻挡坝中的第N层第二子阻挡坝连接在一起，每个所述第二阻挡坝中的任意的第n’层第二子阻挡坝之间间隔，n’为大于或等于1且小于N的整数。
  13. 根据权利要求10所述的显示面板，还包括：平坦层，位于所述像素限定层和所述基板之间且延伸至部分所述边缘区的一侧，所述平坦层与所述第一阻挡坝间隔；
    其中，沿所述显示区至所述边缘区的方向，所述像素限定层至所述第一阻挡坝的间隔距离大于所述平坦层至所述第一阻挡坝的间隔距离；
    其中，所述第二阻挡坝位于所述像素限定层和所述第一阻挡坝之间的所述平坦层背离所述基板的一侧或者位于所述平坦层和所述第一阻挡坝之间；或者，一部分数量的所述第二阻挡坝位于所述像素限定层和所述第一阻挡坝之间的所述平坦层背离所述基板的一侧，另一部分数量的所述第二阻挡坝位于所述平坦层和所述第一阻挡坝之间。
  14. 根据权利要求13所述的显示面板，还包括：阴极引出层，位于所述平坦层和所述第一阻挡坝之间的所述基板的一侧、且延伸至部分所述平坦层背离所述基板的一侧；
    其中，所述像素结构包括阴极层，部分所述像素结构中的所述阴极层延伸至与所述平坦层一侧的所述阴极引出层搭接；
    其中，位于所述像素限定层和所述第一阻挡坝之间的所述平坦层一侧的所述第二阻挡坝覆盖所述阴极层；位于所述平坦层和所述第一阻挡坝之间的所述第二阻挡坝覆盖所述阴极引出层。
  15. 根据权利要求10所述的显示面板，其中，所述像素结构包括阴极层；每个像素结构中的所述阴极层间隔设置；
    所述显示面板还包括：导电隔离柱，位于相邻所述像素结构之间的所述像素限定层背离所述基板的一侧；
    其中，所述阴极层与所述导电隔离柱连接。
  16. 根据权利要求10所述的显示面板，其中，所述第一阻挡坝包括第一部分和位于所述第一部分和所述基板之间的第二部分；
    其中，所述第二部分的材料和所述像素限定层的材料相同；所述第一部分包括一层或多层层叠的第一子层，一层所述第一子层的材料与一种像素颜色的所述像素结构表面的所述第一无机封装层的材料相同。
  17. 根据权利要求16所述的显示面板，还包括：平坦层，位于所述像素限定层和所述基板之间，所述平坦层与所述第一阻挡坝间隔；
    其中，所述第一阻挡坝还包括：第三部分，位于所述第二部分和所述基板之间，所述第三部分的材料和所述平坦层的材料相同。
  18. 一种显示面板的制备方法，包括：
    提供基板，所述基板包括显示区和包围所述显示区的边缘区；
    在所述基板的所述显示区的一侧形成像素限定层；
    在所述基板的所述边缘区的一侧形成第一阻挡坝；
    形成第二阻挡坝，所述第二阻挡坝位于所述像素限定层和所述第一阻挡坝之间的所述基板的一侧，所述第二阻挡坝的材料和所述像素限定层的材料不同；以及
    形成封装层，包括：在所述像素限定层和所述第二阻挡坝背离所述基板的一侧形成有机封装层；其中，所述第一阻挡坝包围所述有机封装层。
  19. 根据权利要求18所述的显示面板的制备方法，还包括：
    在所述像素限定层中形成多个像素结构，多个所述像素结构具有多种像素颜色；在形成所述像素结构的过程中形成第一无机封装层；
    其中，不同像素颜色的所述像素结构先后依次形成；不同像素颜色的所述像素结构一侧的所述第一无机封装层先后依次形成；
    其中，所述形成所述第二阻挡坝包括：形成一层或多层层叠的第二子阻挡坝，在形成一层所述第二子阻挡坝的过程中形成一种像素颜色的所述像素结构表面的所述第一无机封装层。
  20. 一种显示装置，包括权利要求1-17中任意一项所述的显示面板。
PCT/CN2025/095933 2024-06-13 2025-05-20 显示面板及其制备方法、显示装置 Pending WO2025256359A1 (zh)

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CN208271949U (zh) * 2018-05-11 2018-12-21 云谷（固安）科技有限公司 显示面板母板
CN112018159A (zh) * 2020-08-27 2020-12-01 京东方科技集团股份有限公司 触控显示面板
US20220263046A1 (en) * 2021-02-16 2022-08-18 Samsung Display Co., Ltd. Display apparatus
CN220155097U (zh) * 2023-04-20 2023-12-08 华为技术有限公司 显示面板及显示装置
CN118695751A (zh) * 2024-06-13 2024-09-24 京东方科技集团股份有限公司 显示面板及其制备方法、显示装置

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CN208271949U (zh) * 2018-05-11 2018-12-21 云谷（固安）科技有限公司 显示面板母板
CN112018159A (zh) * 2020-08-27 2020-12-01 京东方科技集团股份有限公司 触控显示面板
US20220263046A1 (en) * 2021-02-16 2022-08-18 Samsung Display Co., Ltd. Display apparatus
CN220155097U (zh) * 2023-04-20 2023-12-08 华为技术有限公司 显示面板及显示装置
CN118695751A (zh) * 2024-06-13 2024-09-24 京东方科技集团股份有限公司 显示面板及其制备方法、显示装置

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